Deep trench isolation structure, preparation method thereof and semiconductor device

Abstract

The embodiment of the invention relates to a deep trench isolation structure, a preparation method thereof and a semiconductor device. The preparation method comprises the following steps: forming a deep trench in a semiconductor structure; wherein a to-be-led-out part is formed in the semiconductor structure, and the deep groove extends from the top surface of the semiconductor structure to the to-be-led-out part, so that the to-be-led-out part is located at the bottom of the deep groove; ion doping is carried out on the semiconductor structure to at least form a first doped region in the semiconductor structure on the side wall of the deep groove, and the first doped region is conductively connected with the to-be-led-out part; and filling an insulating layer in the deep trench. Therefore, the process compatibility, the device miniaturization and the production efficiency are considered while the deep trench isolation conductive lead-out is realized.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a deep trench isolation structure, its fabrication method, and semiconductor devices. Background Technology

[0002] Deep trench isolation (DTI) is a key technology for creating electrical isolation in three-dimensional semiconductor devices. Specifically, it involves etching deep trenches within the semiconductor structure and filling them with insulating material to achieve isolation between adjacent devices or cells, thereby preventing current leakage and signal crosstalk.

[0003] To further achieve conductive lead-out, the art typically involves directly leading the electrical signal from the bottom of the deep trench to the surface of the semiconductor structure based on the DTI structure (commonly known as DTI PICK UP). Specifically, the semiconductor structure is first etched to form a deep trench exposing the lead-out portion. Then, an insulating material is deposited to cover the deep trench. The insulating material covering the bottom wall of the deep trench is removed to expose the lead-out portion. Finally, polysilicon is grown within the deep trench as the conductive lead-out structure. Understandably, to achieve conductive lead-out, dopant ions are typically introduced during the growth of the polysilicon, resulting in a heavily doped polysilicon structure.

[0004] However, in furnace tube processes, dopant ions from heavily doped polysilicon can escape and contaminate other wafers within the furnace tube. Separately controlling the furnace tube process would increase manufacturing cycles, reduce capacity, and raise costs. Furthermore, to ensure complete filling of the polysilicon within the deep trenches and prevent voids from breaking conductive paths, the deep trenches typically require a large width, which to some extent sacrifices device size. Summary of the Invention

[0005] In view of this, the present application provides a deep trench isolation structure, its fabrication method, and a semiconductor device to solve at least one problem existing in the background art.

[0006] In a first aspect, embodiments of this application provide a method for preparing a deep trench isolation structure, the method comprising: A deep trench is formed within a semiconductor structure; wherein a portion to be led out is formed within the semiconductor structure, and the deep trench extends from the top surface of the semiconductor structure toward the portion to be led out, such that the portion to be led out is located at the bottom of the deep trench; The semiconductor structure is ion-doped to form a first doped region within the semiconductor structure at least on the sidewall of the deep trench, and the first doped region is electrically connected to the lead-out portion. An insulating layer is filled into the deep trench.

[0007] In conjunction with the first aspect of this application, in an optional embodiment, the bottom wall of the deep trench is spaced apart from the lead-out portion along the thickness direction of the semiconductor structure; The semiconductor structure is ion-doped, and a second doped region is formed in the semiconductor structure at the bottom of the deep trench. The second doped region is in conductive contact with the part to be led out, and the first doped region and the second doped region are connected.

[0008] In conjunction with the first aspect of this application, in an optional embodiment, the distance between the bottom wall of the deep trench and the lead-out portion along the thickness direction of the semiconductor structure ranges from 0.1 μm to 0.4 μm.

[0009] In conjunction with the first aspect of this application, in an optional embodiment, the process for ion doping the semiconductor structure includes a plasma doping process.

[0010] In conjunction with the first aspect of this application, in an alternative embodiment, The semiconductor structure is ion-doped to form a first doped region at least within the semiconductor structure on the sidewalls of the deep trench; an insulating layer is filled within the deep trench, comprising: The semiconductor structure is ion-doped to form at least a first doped region and a third doped region connected together; wherein the first doped region is located within the semiconductor structure on the sidewall of the deep trench, and the third doped region is located on the top surface side of the semiconductor structure. An insulating material is deposited, which fills the deep trench and covers the top surface of the semiconductor structure; The portion of the insulating material covering the top surface of the semiconductor structure, and the portion of the semiconductor structure in which the third doped region is formed, are removed sequentially.

[0011] Secondly, embodiments of this application provide a deep trench isolation structure, including: A deep trench is located within a semiconductor structure; wherein a portion to be led out is formed within the semiconductor structure, and the deep trench extends from the top surface of the semiconductor structure toward the portion to be led out, such that the portion to be led out is located at the bottom of the deep trench; The first doped region is located within the semiconductor structure of the sidewall of the deep trench, and the first doped region is electrically connected to the part to be led out. An insulating layer is filled into the deep trench.

[0012] In conjunction with a second aspect of this application, in an optional embodiment, the bottom wall of the deep trench is spaced apart from the lead-out portion along the thickness direction of the semiconductor structure; It also includes: a second doped region located within the semiconductor structure at the bottom of the deep trench, the second doped region being in conductive contact with the part to be led out, and the first doped region and the second doped region being connected.

[0013] In conjunction with a second aspect of this application, in an optional embodiment, the distance between the bottom wall of the deep trench and the lead-out portion along the thickness direction of the semiconductor structure ranges from 0.1 μm to 0.4 μm.

[0014] In conjunction with a second aspect of this application, in an optional embodiment, the first doped region is obtained by plasma doping.

[0015] Thirdly, embodiments of this application provide a semiconductor device, including: a deep trench isolation structure prepared by the method for preparing a deep trench isolation structure as described in the first aspect, or including a deep trench isolation structure as described in the second aspect; A conductive connection structure is located on the top surface of the semiconductor structure and is conductively connected to the first doped region.

[0016] The deep trench isolation structure, its fabrication method, and semiconductor device provided in this application embodiment use a first doped region within the semiconductor structure of the deep trench sidewall as the conductive lead-out structure, and an insulating layer filling the deep trench as the isolation structure. Compared to heavily doped polycrystalline silicon in related technologies, the first doped region formed by ion doping has a lower doping concentration, which can ensure conductivity while avoiding contamination of other wafers in furnace tube processes, thereby avoiding production capacity loss and cost increases, and providing better process compatibility. The formation of the first doped region is not limited by the width of the deep trench, which is more conducive to device miniaturization. Furthermore, the conductive connection between the first doped region and the lead-out portion is not affected by the insulating layer, eliminating the need for additional etching steps and effectively saving processes. During the fabrication process, the deep trench is etched first and then ion doping is performed, ensuring that the first doped region has sufficient depth to conductively connect with the lead-out portion. Thus, while achieving deep trench isolation and conductive lead-out, process compatibility, device miniaturization, and production efficiency are also considered.

[0017] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figures 1 to 2 This is a schematic cross-sectional view of the deep trench isolation structure during its fabrication process in the prior art. Figure 3 A schematic flowchart illustrating the fabrication method of the deep trench isolation structure provided in this application embodiment; Figures 4 to 8 A cross-sectional structural diagram of the deep trench isolation structure provided in the embodiments of this application during the fabrication process; Figure 9 A schematic cross-sectional view of a semiconductor device provided as an optional specific embodiment; Figure 10 A cross-sectional structural schematic diagram of a semiconductor device provided for another optional specific embodiment. Detailed Implementation

[0019] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0020] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0021] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0022] When an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. Although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0023] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship of one element or feature shown in the figure to other elements or features. In addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0025] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0026] Figure 1 and Figure 2 A cross-sectional schematic diagram of the fabrication process of a deep trench isolation structure in the related art is shown. First, a semiconductor structure 100 is etched to form a deep trench 200 exposing the lead-out portion 110. Then, an insulating material 301 is deposited, covering at least the sidewalls and bottom wall of the deep trench 200. At least the insulating material 301 covering the bottom wall of the deep trench 200 is removed to expose the lead-out portion 110, forming an insulating layer 300. Finally, polycrystalline silicon is grown within the deep trench 200 and doped with dopant ions to form a polycrystalline silicon structure 400. By simultaneously doping with dopant ions, such as boron (B) ions or phosphorus (P) ions, during the growth of the polycrystalline silicon, the polycrystalline silicon becomes conductive, enabling conductive lead-out of the lead-out portion 110. The final polycrystalline silicon structure 400 is heavily doped.

[0027] When the semiconductor structure 100 is placed in a furnace tube, dopant ions from the heavily doped polysilicon structure 400 escape under the high-temperature environment of the furnace tube, contaminating other wafers inside the furnace tube, especially the lightly doped wafers. If the furnace tube process is controlled separately, it will lead to increased manufacturing cycles, reduced capacity, and higher costs. Furthermore, to ensure the structural integrity of the polysilicon structure 400, the deep trench 200 is typically required to have a large width to avoid voids during polysilicon filling, which to some extent sacrifices device size.

[0028] Based on this, this application provides a method for fabricating a deep trench isolation structure. Please refer to [link / reference]. Figure 3 The preparation methods include: Step S1: Form a deep trench within a semiconductor structure; wherein, a portion to be led out is formed within the semiconductor structure, and the deep trench extends from the top surface of the semiconductor structure toward the portion to be led out, such that the portion to be led out is located at the bottom of the deep trench; Step S2: Ion doping is performed on the semiconductor structure to form a first doped region at least within the semiconductor structure on the sidewalls of the deep trench, and the first doped region is electrically connected to the lead-out portion. Step S3: Fill the deep trench with an insulating layer.

[0029] This application uses a first doped region within the semiconductor structure on the sidewall of a deep trench as the conductive lead-out structure, and an insulating layer filling the deep trench as the isolation structure. Compared to heavily doped polycrystalline silicon in related technologies, the first doped region formed by ion doping has a lower doping concentration, which can ensure conductivity while avoiding contamination of other wafers in furnace tube processes, thereby avoiding production capacity loss and cost increases, and providing better process compatibility. The formation of the first doped region is not limited by the width of the deep trench, which is more conducive to device miniaturization. Furthermore, the conductive connection between the first doped region and the lead-out portion is not affected by the insulating layer, eliminating the need for additional etching steps and effectively saving processes. During the fabrication process, the deep trench is etched first and then ion doping is performed, ensuring that the first doped region has sufficient depth to conduct to the lead-out portion. Thus, while achieving deep trench isolation conductive lead-out, process compatibility, device miniaturization, and production efficiency are all taken into account.

[0030] First, please refer to Figure 4 and Figure 5 Step S1 is executed to form a deep trench 200 in the semiconductor structure 100; wherein, a lead-out portion 110 is formed in the semiconductor structure 100, and the deep trench 200 extends from the top surface of the semiconductor structure 100 to the lead-out portion 110, so that the lead-out portion 110 is located at the bottom of the deep trench 200.

[0031] In some embodiments, the semiconductor structure 100 includes a lead-out portion 110 and a semiconductor material layer 120 stacked along the thickness direction; a deep trench 200 extends at least into the interior of the semiconductor material layer from the side of the semiconductor material layer away from the lead-out portion 110. In this embodiment, the lead-out portion 110 is another semiconductor material layer. In some other embodiments, the lead-out portion 110 can be a doped region within the semiconductor structure 100. This application does not limit this aspect.

[0032] Next, please refer to Figure 8 Step S2 is executed to ion-dope the semiconductor structure 100 to form a first doped region 510 within the semiconductor structure 100 on the sidewall of the deep trench 200. The first doped region 510 is electrically connected to the lead-out portion 110. In this embodiment, the first doped region 510 serves as a conductive lead-out structure, leading the electrical signal of the lead-out portion 110 to the top surface of the semiconductor structure 100.

[0033] Understandably, if semiconductors are directly ion-doped, the resulting doped region is shallow, making it difficult to achieve the required depth of the deep trench 200. Therefore, in this embodiment, the deep trench 200 is formed by etching first, followed by ion doping, ensuring that the first doped region 510 has sufficient vertical depth to allow the conductive lead-out portion 110 to be brought out. Compared to heavily doped polysilicon in related technologies, the first doped region 510 formed by ion doping has a lower doping concentration, which can ensure conductivity while avoiding contamination of other wafers in the furnace tube process, thereby avoiding production capacity loss and cost increases, and providing better process compatibility. In practical applications, the doping depth, doping concentration, and aspect ratio of the deep trench 200 can also be adaptively adjusted to regulate the doping effect, for example, achieving an effective doping depth of 0.1 μm; it can also be used to adapt to different voltages.

[0034] In some embodiments, along the thickness direction of the semiconductor structure 100, the bottom wall of the deep trench 200 is spaced apart from the lead-out portion 110; the semiconductor structure 100 is ion-doped, and a second doped region 520 is formed in the semiconductor structure 100 at the bottom of the deep trench 200, the second doped region 520 being in conductive contact with the lead-out portion 110, and the first doped region 510 and the second doped region 520 being connected. In related technologies, such as Figure 1 and Figure 2 As shown, to ensure that the polysilicon structure 400 can be electrically connected to the lead-out portion 110, the lead-out portion 110 needs to be exposed during the etching of the deep trench 200 and after the deposition of the insulating material 301. This places high demands on the precision of the etching process, as over-etching can easily cause damage or insufficient etching can lead to connection failure. In contrast, the second doped region 520 formed by ion doping in this embodiment has a certain vertical depth. The doped ions diffuse from the bottom wall of the deep trench 200 toward the lead-out portion 110, achieving a conductive connection with the lead-out portion 110. Therefore, in this embodiment, the deep trench 200 does not expose the lead-out portion 110, which can reduce the requirements for the precision of the etching process. Of course, this application does not exclude the possibility that the deep trench 200 extends into the lead-out portion 110, or even into the interior of the lead-out portion 110. In this case, the second doped region 520 is specifically formed inside the lead-out portion 110.

[0035] Optionally, along the thickness direction of the semiconductor structure, the distance between the bottom wall of the deep trench 200 and the lead-out portion 110 ranges from 0.1 μm to 0.4 μm. If the distance is too large, the diffusion time of doped ions is prolonged, affecting production efficiency. Furthermore, the greater the distance, the fewer doped ions diffuse to the doped region, affecting the conductivity of the doped region. Therefore, within this range, not only can the requirements for etching process precision be reduced, but the conductive connection between the doped region and the lead-out portion 110 can also be guaranteed.

[0036] In some embodiments, the linewidth at the top of the deep trench 200 is less than or equal to 1.5 μm. Understandably, in related technologies, to ensure the filling effect of polysilicon, the linewidth at the top of the deep trench 200 is typically above 3 μm. However, in this application, the formation of the first doped region 510 is not constrained by the width of the deep trench 200, and the area of ​​the DTI CD (Critical Dimension) can be reduced by more than 10%. Here, DTI CD typically refers to the linewidth at the top of the deep trench 200.

[0037] Optionally, the process for ion doping the semiconductor structure 100 includes plasma doping. In the plasma doping (PLAD) process, the semiconductor structure 100 is placed in a reaction chamber, a gas containing dopant elements is introduced, and the gas is ionized by a radio frequency power supply to form a plasma containing the desired dopant ions. A bias voltage is applied to the semiconductor structure 100 to form an electric field, under which the dopant ions are accelerated and injected into the surface of the semiconductor structure 100. In this application, since a deep trench 200 is formed first, the dopant ions can enter the semiconductor structure 100 along the sidewalls and bottom wall of the deep trench 200, thereby forming a continuous first doped region 510 and a second doped region 520. In this embodiment, the process for ion doping the semiconductor structure 100 is specifically a plasma doping process.

[0038] In one example, along the thickness direction of the semiconductor structure 100, the projected area of ​​the top of the deep trench 200 is smaller than the projected area of ​​the bottom wall of the deep trench 200. Specifically, the cross-sectional shape of the deep trench 200 is a trapezoid. Here, the cross-section is the plane along the thickness direction of the semiconductor structure 100. Understandably, in plasma doping processes, dopant ions move under the influence of an electric field, and any surface exposed to the electric field will be implanted with dopant ions, regardless of the morphology of the deep trench.

[0039] Finally, please refer to Figure 8 Step S3 is executed, filling the deep trench 200 with an insulating layer 300. Thus, the insulating layer 300 filled within the deep trench 200 serves as an isolation structure, achieving electrical isolation. In this embodiment, before filling with the insulating layer 300, the first doped region 510 and the lead-out portion 110 have already formed a conductive connection and are unaffected by the insulating layer 300. Compared to related technologies, this application can save the step of removing the insulating material 301 covering the bottom wall of the deep trench 200, improving production efficiency and reducing costs.

[0040] The insulating layer 300 can be made of any suitable insulating material, and this application does not limit it. In this embodiment, the insulating layer 300 is specifically made of an oxide material.

[0041] In some embodiments, please refer to Figures 6 to 8 The semiconductor structure 100 is ion-doped to form a first doped region 510 within the semiconductor structure 100 at least on the sidewalls of the deep trench 200; filling the deep trench 200 with an insulating layer 300 may include: The semiconductor structure 100 is ion-doped to form at least a first doped region 510 and a third doped region 530 connected to each other; wherein the first doped region 510 is located within the semiconductor structure 100 on the sidewall of the deep trench 200, and the third doped region 530 is located on the top surface side of the semiconductor structure 100. An insulating material 301 is deposited, which fills the deep trench 200 and covers the top surface of the semiconductor structure 100. The portion of the insulating material 301 covering the top surface of the semiconductor structure 100 and the portion of the semiconductor structure 100 in which the third doped region 530 is formed are removed sequentially.

[0042] Understandably, when performing ion doping on semiconductor structure 100, in addition to forming the first doped region 510, a third doped region 530 is also formed on the top surface of semiconductor structure 100. This creates unnecessary conductive paths in semiconductor structure 100, which in turn affects the electrical isolation effect of the deep trench isolation structure. Furthermore, the portion of insulating material 301 covering the top surface of semiconductor structure 100 will affect subsequent processes performed on semiconductor structure 100.

[0043] In some embodiments, a chemical mechanical polishing (CMP) process is used to remove the portion of the insulating material 301 covering the top surface of the semiconductor structure 100, as well as the portion of the semiconductor structure 100 in which the third doped region 530 is formed. This avoids complex steps such as photolithography and etching, simplifying the process; and the CMP process creates a flat surface morphology, which is beneficial for subsequent processing of the semiconductor structure 100.

[0044] This application also provides a deep trench isolation structure, please refer to... Figure 8 The deep trench isolation structure includes: A deep trench 200 is located within a semiconductor structure 100; wherein a lead-out portion 110 is formed within the semiconductor structure 100, and the deep trench 200 extends from the top surface of the semiconductor structure 100 toward the lead-out portion 110, such that the lead-out portion 110 is located at the bottom of the deep trench 200. The first doped region 510 is located within the semiconductor structure 100 on the sidewall of the deep trench 200, and the first doped region 510 is electrically connected to the lead-out portion 110. An insulating layer 300 is filled within a deep trench 200.

[0045] In this embodiment, a first doped region 510 within the semiconductor structure 100 on the sidewall of the deep trench 200 serves as the conductive lead-out structure, and an insulating layer 300 filling the deep trench 200 serves as the isolation structure. Compared to heavily doped polycrystalline silicon in related technologies, the first doped region 510 formed by ion doping has a lower doping concentration, which can ensure conductivity while avoiding contamination of other wafers in furnace tube processes, thereby avoiding capacity loss and cost increases, and providing better process compatibility. The formation of the first doped region 510 is not limited by the width of the deep trench 200, which is more conducive to device miniaturization. Thus, while achieving deep trench isolation and conductive lead-out, process compatibility, device miniaturization, and production efficiency are all taken into account.

[0046] In some embodiments, along the thickness direction of the semiconductor structure 100, the bottom wall of the deep trench 200 is spaced apart from the lead-out portion 110; it also includes: a second doped region 520 located in the semiconductor structure 100 at the bottom of the deep trench 200, the second doped region 520 being in conductive contact with the lead-out portion 110, and the first doped region 510 and the second doped region 520 being connected.

[0047] In some embodiments, the first doped region 510 and the second doped region 520 are formed by the same ion doping process.

[0048] In some embodiments, the distance between the bottom wall of the deep trench 200 and the lead-out portion 110 along the thickness direction of the semiconductor structure ranges from 0.1 μm to 0.4 μm.

[0049] In some embodiments, the first doped region 510 is obtained by plasma doping.

[0050] Correspondingly, embodiments of this application also provide a semiconductor device, please refer to... Figure 9 The semiconductor device includes: a deep trench isolation structure prepared by the method for preparing a deep trench isolation structure as provided in the above embodiments, or a deep trench isolation structure as provided in the above embodiments; and a conductive connection structure 600 located on the top surface of the semiconductor structure 100 and conductively connected to the first doped region 510.

[0051] In one example, the conductive connection structure 600 is a contact hole (CT). The material of the conductive connection structure 600 includes metallic materials.

[0052] In some embodiments, please refer to Figure 9 and Figure 10 The semiconductor device may also include an ohmic contact located on the top surface of the semiconductor structure 100, through which the conductive connection structure 600 is electrically connected to the first doped region 510. This reduces contact resistance through the ohmic contact.

[0053] In one optional embodiment, the semiconductor structure 100 is made of silicon; the ohmic contact is made of metal silicide 710.

[0054] In another optional embodiment, the ohmic contact is a heavily doped region 720, and the conductivity type of the heavily doped region 720 is the same as that of the first doped region 510.

[0055] It should be noted that the deep trench isolation structure embodiments and the deep trench isolation structure preparation method embodiments provided in this application belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict. However, it should be further noted that the combination of technical features of the deep trench isolation structure provided in the embodiments of this application can already solve the technical problem to be solved by this application; therefore, the deep trench isolation structure provided in the embodiments of this application is not limited to the preparation method of the deep trench isolation structure provided in the embodiments of this application, and any deep trench isolation structure prepared by the preparation method of the deep trench isolation structure provided in the embodiments of this application is within the scope of protection of this application.

[0056] It should be understood that the above embodiments are exemplary and are not intended to encompass all possible implementations included in the claims. Various modifications and changes can be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.

Claims

1. A method for preparing a deep trench isolation structure, characterized in that, The method includes: A deep trench is formed within a semiconductor structure; wherein a portion to be led out is formed within the semiconductor structure, and the deep trench extends from the top surface of the semiconductor structure toward the portion to be led out, such that the portion to be led out is located at the bottom of the deep trench; The semiconductor structure is ion-doped to form a first doped region within the semiconductor structure at least on the sidewall of the deep trench, and the first doped region is electrically connected to the lead-out portion. An insulating layer is filled into the deep trench.

2. The method for preparing the deep trench isolation structure according to claim 1, characterized in that, Along the thickness direction of the semiconductor structure, the bottom wall of the deep trench is spaced apart from the lead-out portion; The semiconductor structure is ion-doped, and a second doped region is formed in the semiconductor structure at the bottom of the deep trench. The second doped region is in conductive contact with the part to be led out, and the first doped region and the second doped region are connected.

3. The method for preparing the deep trench isolation structure according to claim 2, characterized in that, Along the thickness direction of the semiconductor structure, the distance between the bottom wall of the deep trench and the part to be led out ranges from 0.1 μm to 0.4 μm.

4. The method for preparing the deep trench isolation structure according to claim 1, characterized in that, The process of ion doping the semiconductor structure includes plasma doping.

5. The method for preparing the deep trench isolation structure according to claim 1, characterized in that, The semiconductor structure is ion-doped to form a first doped region within the semiconductor structure at least on the sidewalls of the deep trench. The deep trench is filled with an insulating layer, including: The semiconductor structure is ion-doped to form at least a first doped region and a third doped region connected together; wherein the first doped region is located within the semiconductor structure on the sidewall of the deep trench, and the third doped region is located on the top surface side of the semiconductor structure. An insulating material is deposited, which fills the deep trench and covers the top surface of the semiconductor structure; The portion of the insulating material covering the top surface of the semiconductor structure, and the portion of the semiconductor structure in which the third doped region is formed, are removed sequentially.

6. A deep trench isolation structure, characterized in that, include: A deep trench is located within a semiconductor structure; wherein a portion to be led out is formed within the semiconductor structure, and the deep trench extends from the top surface of the semiconductor structure toward the portion to be led out, such that the portion to be led out is located at the bottom of the deep trench; The first doped region is located within the semiconductor structure of the sidewall of the deep trench, and the first doped region is electrically connected to the part to be led out. An insulating layer is filled into the deep trench.

7. The deep trench isolation structure according to claim 6, characterized in that, Along the thickness direction of the semiconductor structure, the bottom wall of the deep trench is spaced apart from the lead-out portion; It also includes: a second doped region located within the semiconductor structure at the bottom of the deep trench, the second doped region being in conductive contact with the part to be led out, and the first doped region and the second doped region being connected.

8. The deep trench isolation structure according to claim 7, characterized in that, Along the thickness direction of the semiconductor structure, the distance between the bottom wall of the deep trench and the part to be led out ranges from 0.1 μm to 0.4 μm.

9. The deep trench isolation structure according to claim 6, characterized in that, The first doped region was obtained by plasma doping.

10. A semiconductor device, characterized in that, include: The deep trench isolation structure prepared by the method for preparing the deep trench isolation structure as described in any one of claims 1 to 5, or the deep trench isolation structure as described in any one of claims 6 to 9; A conductive connection structure is located on the top surface of the semiconductor structure and is conductively connected to the first doped region.

Images