Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: forming a substrate; forming a shallow trench isolation structure and an active region in the substrate, wherein the active region is adjacent to the shallow trench isolation structure; etching the shallow trench isolation structure to expose part of the top and the side wall of the active region close to the shallow trench isolation structure; and performing round corner processing on the exposed active region so as to form a round corner between the top and the side wall of the active region close to the shallow trench isolation structure. According to the forming method, after the shallow trench isolation structure is formed, the rounding process is carried out on the specific area, the problem of stress concentration caused by a sharp corner of an active area in part of the area is solved, meanwhile, the influence on the area where the rounding process does not need to be carried out is reduced, the forming process of the shallow trench isolation structure is kept unchanged, and the yield of the shallow trench isolation structure is improved. According to the scheme, the process effect can be greatly improved without greatly changing the process flow.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] As semiconductor process nodes advance towards deep submicron and advanced processes, shallow trench isolation (STI) technology is gradually replacing traditional local oxide of silicon (LOCOS) isolation as the mainstream.

[0003] STI, as a core isolation technology in semiconductor manufacturing, has several key advantages over traditional LOCOS, adapting to process evolution and device performance requirements: First, strong integration adaptability. STI achieves isolation by etching trenches to fill insulating media, eliminating the "bird's beak effect" inherent in LOCOS and preventing intrusion into active regions. This significantly reduces device spacing, meeting the high integration requirements of deep submicron and nanometer-scale processes, enabling the integration of more transistors per unit chip area. Second, excellent and stable isolation performance. The trench depth can be flexibly adjusted, achieving more thorough electrical isolation and effectively blocking leakage and crosstalk between devices. It is particularly suitable for the isolation requirements of high-voltage devices and high-density logic chips, and its isolation performance is less affected by process fluctuations, exhibiting outstanding stability. Third, broad process compatibility. It is compatible with advanced processes such as FinFET and BCD, as well as high and low voltage integration solutions. It can meet the fine isolation requirements of low-voltage devices and adapt to high-voltage power devices through deep trench (DTI) variants. It is also compatible with subsequent metallization, annealing, and other processes without requiring significant additional process adjustments. Fourth, superior structure and performance. Trench structures can reduce the adverse effects on substrate stress. Combined with optimizations such as rounded corner etching, they can alleviate electric field concentration problems, balance device reliability and electrical performance, and provide support for low-power, high-speed operation of chips.

[0004] In semiconductor device integration processes, the sharp corner problem at the boundary between the active region and the isolation region (AA Corner) is a typical challenge in the application of STI isolation technology. Due to the differences in operating voltage, performance requirements and reliability requirements, the requirements for sharp corner rounding of high voltage devices and medium and low voltage devices are significantly different.

[0005] However, the current process for rounding the sharp corners of the active region in high-voltage devices still needs improvement. Summary of the Invention

[0006] The problem addressed by this invention is how to improve the rounding process of sharp corners in the active region to solve the problems of electric field concentration and stress concentration in high-voltage devices.

[0007] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure, comprising: forming a substrate; forming a shallow trench isolation structure and an active region within the substrate, wherein the active region is adjacent to the shallow trench isolation structure; etching the shallow trench isolation structure to expose a portion of the top and sidewalls of the active region near the shallow trench isolation structure; and rounding the exposed active region to form a rounded corner between the top and sidewalls of the active region near the shallow trench isolation structure.

[0008] Optionally, after rounding the exposed active region, a first gate oxide layer is formed on the active region.

[0009] Optionally, in the step of forming a substrate, the substrate includes: a first region and a second region; the step of etching the shallow trench isolation structure to expose a portion of the top and sidewalls of the active region near the shallow trench isolation structure includes: etching the shallow trench isolation structure in the substrate of the first region; the step of rounding the exposed active region to form a rounded corner between the top and sidewalls of the active region near the shallow trench isolation structure includes: rounding the active region in the exposed substrate of the first region to form a rounded corner between the top and sidewalls of the active region near the shallow trench isolation structure; forming a first gate oxide layer on the active region of the substrate of the first region; the method of forming the semiconductor structure further includes: after rounding the exposed active region, forming a second gate oxide layer on the active region of the substrate of the second region, wherein the thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer.

[0010] Optionally, in the step of forming the first gate oxide layer on the active region, a high-temperature furnace tube process is used to form the first gate oxide layer.

[0011] Optionally, the step of etching the shallow trench isolation structure to expose a portion of the top and sidewalls of the active region near the shallow trench isolation structure includes: etching the shallow trench isolation structure by wet etching to expose a portion of the top and sidewalls of the active region near the shallow trench isolation structure.

[0012] Optionally, in the step of etching the shallow trench isolation structure by wet etching to expose a portion of the top and sidewalls of the active region near the shallow trench isolation structure, hydrofluoric acid is used as the etching solution.

[0013] Optionally, the method further includes: after forming the shallow trench isolation structure and the active region in the substrate, before etching the shallow trench isolation structure, forming a protective layer on the shallow trench isolation structure and the substrate; the method of forming the semiconductor structure further includes: after etching the shallow trench isolation structure, before rounding the exposed active region, removing part of the protective layer to expose part of the top and sidewalls of the active region near the shallow trench isolation structure.

[0014] Optionally, a portion of the protective layer may be removed by wet etching.

[0015] Optionally, in the step of removing part of the protective layer by wet etching, phosphoric acid is used as the etching solution.

[0016] Optionally, the step of rounding the exposed active area includes: oxidizing the exposed active area to form a sacrificial oxide layer on the exposed active area.

[0017] Optionally, the step of rounding the exposed active area further includes removing the sacrificial oxide layer after it has been formed.

[0018] Optionally, the rounding process further includes: forming a linear oxide layer on the exposed active region before oxidizing the exposed active region and forming a sacrificial oxide layer on the exposed active region.

[0019] Optionally, in the step of oxidizing the exposed active region to form a sacrificial oxide layer on the exposed active region, a high-temperature furnace tube process is used to form the sacrificial oxide layer.

[0020] Accordingly, the present invention also provides a semiconductor structure, which is formed by the semiconductor structure forming method described in the present invention.

[0021] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0022] In the semiconductor structure formation method of the present invention, after forming a shallow trench isolation structure, a portion of the shallow trench isolation structure on the substrate is etched to expose the top and sidewalls of the active region near the shallow trench isolation structure. The exposed active region is then rounded. The remaining areas of the shallow trench isolation structure on the substrate are not etched to expose the active region, nor are the active regions rounded. This method, by performing a rounding process on specific areas after forming the shallow trench isolation structure, solves the problem of stress concentration caused by sharp corners of the active region in some areas, while reducing the impact on areas that do not require rounding. Furthermore, the solution maintains the shallow trench isolation structure formation process unchanged, and the solution achieves significant improvements in process performance without requiring major modifications to the process flow.

[0023] In an optional embodiment of the present invention, in the step of forming a substrate, the substrate includes: a first region and a second region; the step of etching the shallow trench isolation structure to expose a portion of the top and sidewalls of the active region near the shallow trench isolation structure includes: etching the shallow trench isolation structure in the substrate of the first region; the step of rounding the exposed active region to form a rounded corner between the top and sidewalls of the active region near the shallow trench isolation structure includes: rounding the active region in the exposed substrate of the first region to form a rounded corner between the top and sidewalls of the active region near the shallow trench isolation structure; forming a first gate oxide layer on the active region of the substrate of the first region; the method of forming the semiconductor structure further includes: after rounding the exposed active region, forming a second gate oxide layer on the active region of the substrate of the second region, wherein the thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer. The first gate oxide layer is suitable for forming high-voltage devices, and the second gate oxide layer is suitable for forming medium- and low-voltage devices. After forming the shallow trench isolation structure, the top and sidewalls of the active region suitable for forming high-voltage devices are rounded, while the top and sidewalls of the active region suitable for forming medium- and low-voltage devices are not rounded. This improves the stress concentration between the top and sidewalls of the active region suitable for forming high-voltage devices, while avoiding the impact on the region suitable for forming medium- and low-voltage devices. Attached Figure Description

[0024] Figure 1 This is a schematic cross-sectional view of a semiconductor structure.

[0025] Figures 2 to 9 This is a cross-sectional structural schematic diagram of each step in the formation process of the semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0026] As can be seen from the background technology, the existing process for rounding the sharp corners of the active region of high-voltage devices still has shortcomings. The reasons for these problems will now be analyzed in conjunction with the attached figures.

[0027] With the continuous advancement of semiconductor process nodes, shallow trench isolation structures have replaced traditional local silicon oxidation as the mainstream device isolation technology due to their excellent isolation effect.

[0028] Please refer to Figure 1 A semiconductor structure includes: a substrate 100; a shallow trench isolation structure 1001 and an active region 1002, wherein the shallow trench isolation structure 1001 and the active region 1002 are located within the substrate 100, and the active region 1002 and the shallow trench isolation structure 1001 are adjacent to each other.

[0029] The shallow trench isolation structure 1001 is prone to forming a sharp corner at the adjacent position A of the active region 1002 and the shallow trench isolation structure 1001, which causes electric field concentration and stress concentration, thereby affecting the electrical performance and reliability of the device.

[0030] According to current semiconductor process development trends, the smaller the chip device size, the less effort is made to round the sharp corners at the junction of the active region 1002 and the shallow trench isolation structure 1001 in the shallow trench isolation structure process. This results in the sharp corners not being smooth enough during the subsequent growth of the high-voltage gate oxide layer. These non-rounded sharp corners can cause local stress concentration, leading to lattice defects such as dislocations in the silicon substrate, ultimately severely affecting the electrical performance and long-term reliability of the high-voltage device.

[0031] To address the aforementioned technical problem, the present invention provides a method for forming a semiconductor structure, comprising: forming a substrate; forming a shallow trench isolation structure and an active region within the substrate, wherein the active region is adjacent to the shallow trench isolation structure; etching the shallow trench isolation structure to expose a portion of the top and sidewalls of the active region near the shallow trench isolation structure; and rounding the exposed active region to form a rounded corner between the top and sidewalls of the active region near the shallow trench isolation structure.

[0032] In the semiconductor structure formation method of the present invention, after forming a shallow trench isolation structure, a portion of the shallow trench isolation structure on the substrate is etched to expose the top and sidewalls of the active region near the shallow trench isolation structure. The exposed active region is then rounded. The remaining areas of the shallow trench isolation structure on the substrate are not etched to expose the active region, nor are the active regions rounded. This method, by performing a rounding process on specific areas after forming the shallow trench isolation structure, solves the problem of stress concentration caused by sharp corners of the active region in some areas, while reducing the impact on areas that do not require rounding. Furthermore, the solution maintains the shallow trench isolation structure formation process unchanged, and the solution achieves significant improvements in process performance without requiring major modifications to the process flow.

[0033] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0034] Please refer to Figure 2 The method for forming the semiconductor structure includes: forming a substrate 200; forming a shallow trench isolation structure 2001 and an active region 2002 in the substrate 200, wherein the active region 2002 is adjacent to the shallow trench isolation structure 2001.

[0035] The active region 2002 is adjacent to the shallow trench isolation structure 2001, that is, the edge of the active region 2002 is in direct contact with the sidewall of the shallow trench isolation structure 2001.

[0036] Specifically, the steps of forming the shallow trench isolation structure 2001 and the active region 2002 within the substrate 200 include:

[0037] A mask layer is formed on the substrate 200, wherein the substrate 200 includes an active region 2002 and an isolation region, and the mask layer exposes the surface of the isolation region of the substrate 200;

[0038] Using the mask layer as a mask, the substrate 200 is etched to form isolation trenches in the isolation region;

[0039] The shallow trench isolation structure 2001 is formed within the isolation trench.

[0040] Specifically, in some embodiments of the present invention, in the step of forming substrate 200, substrate 200 includes: a first region I and a second region (not shown).

[0041] Specifically, in some embodiments of the present invention, the first region I is suitable for forming high-voltage devices, and the second region (not shown) is suitable for forming medium- and low-voltage devices.

[0042] Specifically, the steps of forming a shallow trench isolation structure 2001 and an active region 2002 in the substrate 200 include: forming a shallow trench isolation structure 2001 and an active region 2002 in both the first region I and the second region (not shown).

[0043] The substrate 200 is made of materials including silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, indium gallium arsenide, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Specifically, in some embodiments of the present invention, the substrate 200 is made of silicon.

[0044] Specifically, in some embodiments of the present invention, the material of the shallow trench isolation structure 2001 includes silicon oxide.

[0045] Please refer to Figures 3 to 4 The method for forming the semiconductor structure includes: etching the shallow trench isolation structure 2001 to expose a portion of the top and sidewalls of the active region 2002 near the shallow trench isolation structure 2001.

[0046] like Figure 3As shown, the method for forming the semiconductor structure includes: after forming a shallow trench isolation structure 2001 and an active region 2002 in the substrate 200, before etching the shallow trench isolation structure 2001, forming a protective layer 201 on the shallow trench isolation structure 2001 and the substrate 200; etching the protective layer 201 to expose the top surface of the shallow trench isolation structure 2001 near the active region 2002.

[0047] like Figure 4 As shown, the step of etching the shallow trench isolation structure 2001 to expose a portion of the top and sidewalls of the active region 2002 near the shallow trench isolation structure 2001 includes: etching the shallow trench isolation structure 2001 within the substrate 200 of the first region I.

[0048] exist Figure 3 In this process, the protective layer 201 is adapted to protect the shallow trench isolation structure 2001 and prevent excessive loss of the shallow trench isolation structure 2001 that is not adjacent to the active region 2002 and the shallow trench isolation structure 2001 during the etching of the shallow trench isolation structure 2001 to expose the top and sidewall of the active region 2002 near the shallow trench isolation structure 2001.

[0049] Specifically, in some embodiments of the present invention, the material of the protective layer 201 includes silicon nitride.

[0050] exist Figure 4 The step of etching the shallow trench isolation structure 2001 to expose a portion of the top and sidewalls of the active region 2002 near the shallow trench isolation structure 2001 includes:

[0051] The shallow trench isolation structure 2001 is etched by wet etching to expose part of the top and sidewall of the active region 2002 near the shallow trench isolation structure 2001.

[0052] Specifically, in some embodiments of the present invention, in the step of etching the shallow trench isolation structure 2001 by wet etching to expose part of the top and sidewall of the active region 2002 near the shallow trench isolation structure 2001, hydrofluoric acid is used as the etching solution for etching.

[0053] The core advantages of hydrofluoric acid in removing silicon oxide lie in its high reactivity, excellent process selectivity, and strong controllability. It can spontaneously complex with silicon oxide to generate water-soluble fluorosilicic acid, resulting in thorough etching without solid residue, and cleaning can be completed simply by washing with water. At the same time, hydrofluoric acid has an extremely low etching rate on single-crystal silicon and silicon nitride. When etching silicon oxide, it can effectively protect the substrate 200 and the silicon nitride protective layer 201 from damage. Moreover, the etching rate can be flexibly controlled by concentration and temperature to achieve nanometer-level fine thickness control. It can react efficiently at room temperature and is easy to operate.

[0054] Please refer to Figure 5 The method for forming the semiconductor structure includes: after etching the shallow trench isolation structure 2001, removing a portion of the protective layer 201 to expose a portion of the top and sidewalls of the active region 2002 near the shallow trench isolation structure 2001.

[0055] Removing part of the protective layer 201 to expose part of the top and sidewalls of the active region 2002 near the shallow trench isolation structure 2001 is achieved by precisely isotropically etching back the protective layer 201 at the adjacent position B of the active region 2002 and the shallow trench isolation structure 2001, which exposes more of the top and sidewalls of the active region 2002 near the shallow trench isolation structure 2001.

[0056] In the step of removing part of the protective layer 201 to expose part of the top and sidewalls of the active region 2002 near the shallow trench isolation structure 2001, part of the protective layer 201 is removed by wet etching.

[0057] Specifically, in some embodiments of the present invention, in the step of removing part of the protective layer 201 by wet etching, phosphoric acid is used as the etching solution for etching.

[0058] Phosphoric acid is the preferred reagent for removing silicon nitride. Its core advantages are its ultra-high etching selectivity and good process safety and controllability. Silicon nitride is chemically stable, and approximately 85% concentrated phosphoric acid can react with it at high temperatures of 160~180℃ to generate soluble silica phosphate and ammonia gas, leaving no solid residue after etching. Under these process conditions, phosphoric acid has an extremely low etching rate for silicon oxide and monocrystalline silicon, with an etching ratio of over 1000:1. When removing silicon nitride, it can reduce the loss of the shallow trench isolation structure 2001. Compared with other silicon nitride etching reagents, high-temperature concentrated phosphoric acid has no strong oxidizing properties, no volatile toxic gases, and a mild reaction. The etching rate can be precisely controlled by adjusting the temperature and time, and it has strong process compatibility.

[0059] Please refer to Figures 6 to 7 The exposed active area 2002 is rounded to form a rounded corner between the top and sidewall of the active area 2002 near the shallow trench isolation structure 2001.

[0060] After forming the shallow trench isolation structure 2001, a portion of the shallow trench isolation structure 2001 on the substrate 200 is etched to expose a portion of the top and sidewalls of the active region 2002 near the shallow trench isolation structure 2001. The exposed active region 2002 is then rounded. However, the remaining areas of the shallow trench isolation structure 2001 on the substrate 200 are not etched to expose the active region 2002, nor are the active region 2002 rounded. This method performs a rounding process on specific areas after forming the shallow trench isolation structure 2001. This solves the problem of stress concentration in some areas caused by the sharp corners of the active region 2002, while reducing the impact on areas that do not require rounding. Furthermore, this solution maintains the same forming process for the shallow trench isolation structure 2001, and can achieve significant improvements in process performance without major modifications to the process flow.

[0061] Specifically, in some embodiments of the present invention, the step of rounding the exposed active region 2002 to form a rounded corner between the top and sidewall of the active region 2002 near the shallow trench isolation structure 2001 includes: rounding the active region 2002 in the exposed substrate 200 of the first region I to form a rounded corner between the top and sidewall of the active region 2002 near the shallow trench isolation structure 2001.

[0062] The active region 2002 of the exposed first region I is rounded, while the second region (not shown) is not rounded. The first region I is suitable for forming high-voltage devices, while the second region (not shown) is suitable for forming medium- and low-voltage devices. Medium- and low-voltage devices are sensitive to the rounding of the sharp corners of the active region 2002. Excessive rounding will directly reduce the effective size of the active region 2002, disrupt the uniformity of the gate oxide interface, and cause unbalanced strain stress distribution, leading to a decrease in device drive current, threshold voltage drift, and reduced carrier mobility. It will also cause poor parameter consistency among devices in the same batch, significantly reducing chip yield and operational stability. Only slight micro-rounding is needed to alleviate basic stress, without the need for the large curvature rounding effect required for high-voltage devices. This method solves the stress concentration problem caused by the sharp corners of the active region 2002 of high-voltage devices while reducing the impact on medium- and low-voltage devices. Furthermore, the solution maintains the same forming process for the shallow trench isolation structure 2001, achieving significant improvements in process performance without major modifications to the process flow.

[0063] like Figure 7 As shown, the step of rounding the exposed active region 2002 includes: oxidizing the exposed active region 2002 to form a sacrificial oxide layer 202 on the exposed active region 2002.

[0064] In the step of oxidizing the exposed active region 2002 and forming a sacrificial oxide layer 202 on the exposed active region 2002, the sacrificial oxide layer 202 is formed using a high-temperature furnace tube process.

[0065] During the thermal oxidation process of the high-temperature furnace tube, oxygen atoms diffuse uniformly along the surface of the silicon substrate 200 at the sharp corner of the active region 2002 and react with silicon. The lateral growth effect of oxidation gradually consumes silicon atoms at the sharp corner, slowly smoothing the originally sharp corner into a smooth rounded corner. At the same time, the thermal oxidation reaction under the high temperature environment of the furnace tube is mild and isotropic, which allows the sacrificial oxide layer 202 at the sharp corner to grow uniformly, avoiding the aggravation of the sharpness of the morphology due to uneven oxidation at the sharp corner. This achieves the rounding of the sharp corner at the junction of the active region 2002 and the shallow trench isolation structure 2001, weakening stress and electric field concentration.

[0066] Please refer to Figure 6 The rounding process further includes: before oxidizing the exposed active region 2002 and forming a sacrificial oxide layer 202 on the exposed active region 2002, forming a linear oxide layer 203 on the exposed active region 2002.

[0067] The linear oxide layer 203 is grown uniformly on the surface of the sharp corner adjacent to the active region 2002 and the shallow trench isolation structure 2001 by thermal oxidation. Utilizing the lateral etching and uniform diffusion characteristics of oxygen atoms during the oxidation process, the sharp corner adjacent to the active region 2002 and the shallow trench isolation structure 2001 is rounded into a smooth, small-curvature rounded corner, achieving initial gentle rounding of the sharp corner and weakening the electric field and stress concentration of the sharp corner in subsequent processes from the source. At the same time, the dense linear oxide layer 203 can wrap the sharp corner, optimize the interface transition between the active region 2002 and the shallow trench isolation structure 2001, further alleviate the stress concentration between the shallow trench isolation structure 2001 and the silicon substrate 200, and improve the gate oxide withstand voltage and structural reliability of the device, especially the high-voltage device.

[0068] Please refer to Figure 8 The method for forming the semiconductor structure further includes: after forming the sacrificial oxide layer 202, removing the sacrificial oxide layer 202 (e.g., ...). Figure 7 (As shown).

[0069] The sacrificial oxide layer 202 contains many impurities. Directly growing the gate oxide layer of the high-voltage device on the sacrificial oxide layer 202 will affect the quality of the gate oxide layer of the high-voltage device, and thus affect the performance of the high-voltage device. Removing the sacrificial oxide layer 202 provides a structural basis for the subsequent formation of the gate oxide layer of the high-voltage device, thereby improving the performance of the subsequently formed high-voltage device.

[0070] Specifically, in an embodiment of the present invention, the process of removing the sacrificial oxide layer 202 further includes: removing the protective layer 201 exposed during the rounding process.

[0071] The protective layer 201 exposed during the rounding process is removed to prevent the residual protective layer 201 from obstructing the growth of the gate oxide layer of the subsequent high-voltage device, resulting in incomplete gate oxide coverage or uneven thickness. This ensures that the gate oxide layer of the high-voltage device is uniformly formed on the active region 200 of the first region I. Furthermore, after peeling off the protective layer 201, a clean and flat surface of the silicon substrate 200 is exposed, providing a high-quality silicon oxide interface for the high-temperature thermal oxidation growth of the gate oxide layer of the subsequent high-voltage device. This avoids the introduction of silicon nitride impurities into the gate oxide defects and improves the gate oxide density and withstand voltage.

[0072] Please refer to Figure 9 The method for forming the semiconductor structure further includes: after rounding the corners of the exposed active region 2002, forming a first gate oxide layer 204 on the active region 2002.

[0073] Specifically, in some embodiments of the present invention, please refer to Figure 9 A first gate oxide layer 204 is formed on the active region 2002 of the substrate 200 in the first region I.

[0074] Specifically, in some embodiments of the present invention, in the step of forming the first gate oxide layer 204 on the active region 2002, the first gate oxide layer 204 is formed by a high-temperature furnace tube process.

[0075] The high-temperature furnace tube process, with high-temperature thermal oxidation as its core, allows oxygen atoms to react uniformly and slowly with the silicon substrate 200 under high-temperature conditions. This results in a first gate oxide layer 204 with extremely high density and good film thickness uniformity, and a smooth interface transition with the silicon substrate 200, exhibiting extremely low interface state density. High density prevents localized breakdown caused by micropores and impurities within the oxide layer, while low interface state density suppresses interface leakage and hot carrier injection. The uniform thick film ensures a uniform electric field distribution within the gate oxide layer, preventing gate oxide breakdown caused by localized electric field concentration. Furthermore, the furnace tube process's batch processing characteristics are well-suited for mass production, and the strong adhesion between the thermally oxidized first gate oxide layer 204 and the silicon substrate 200 alleviates stress concentration and reduces the risk of gate oxide cracking and interlayer delamination. Compared to low-temperature processes such as plasma oxidation, the gate oxide prepared by high-temperature furnace tube thermal oxidation better meets the long-term operational requirements of high-voltage devices in terms of voltage withstand capability, stability, and reliability.

[0076] The method for forming the semiconductor structure further includes: after rounding the exposed active region 2002, forming a second gate oxide layer on the active region 2002 of the substrate 200 in the second region (not shown), wherein the thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer 204.

[0077] The thickness of the first gate oxide layer 204 is greater than that of the second gate oxide layer. The thicker first gate oxide layer 204 can directly reduce the electric field strength inside the gate oxide, avoiding failures such as avalanche breakdown and tunneling breakdown under high voltage, and significantly improving the breakdown voltage and withstand voltage limit of the device. At the same time, the thicker first gate oxide layer 204 can alleviate the problem of local electric field concentration caused by the sharp corner of the adjacent position of the active region 2002 and the isolation structure 2001, reduce local leakage current of the gate oxide caused by electric field distortion, and improve the stability of device operation. In addition, the thicker first gate oxide layer 204 has a more stable physical structure, which can effectively suppress reliability failure mechanisms such as hot carrier injection and time-dependent dielectric breakdown, and extend the service life of high-voltage devices under long-term high-voltage operation. For medium and low voltage devices, due to their low operating voltage, the thinner second gate oxide layer is more suitable for the requirements of low power consumption and high switching speed.

[0078] Accordingly, embodiments of the present invention also provide a semiconductor structure, please refer to... Figure 9 The system includes: a substrate, the substrate comprising a first region and a second region; a shallow trench isolation structure and an active region, the shallow trench isolation structure and the active region being located within the substrate and adjacent to each other, wherein the curvature of the angle between the top and sidewall of the active region of the first region near the shallow trench isolation structure is less than the curvature of the angle between the top and sidewall of the active region of the second region near the shallow trench isolation structure.

[0079] Please refer to Figure 9 The semiconductor structure includes a substrate 200, which includes a first region I and a second region (not shown).

[0080] Specifically, in some embodiments of the present invention, the first region I is suitable for forming high-voltage devices, and the second region (not shown) is suitable for forming medium- and low-voltage devices.

[0081] Please refer to Figure 9 The semiconductor structure includes a shallow trench isolation structure 2001 and an active region 2002, wherein the shallow trench isolation structure 2001 and the active region 2002 are located within the substrate 200 and are adjacent to each other. The curvature of the angle between the top and sidewall of the active region 2002 near the shallow trench isolation structure 2001 in the first region I is less than the curvature of the angle between the top and sidewall of the active region 2002 near the shallow trench isolation structure 2001 in the second region (not shown).

[0082] The curvature of the angle between the top and sidewall of the active region 2002 near the shallow trench isolation structure 2001 in the first region I is less than that in the second region (not shown) near the active region 2002 near the shallow trench isolation structure 2001. The angle between the top and sidewall of the active region 2002 near the shallow trench isolation structure 2001 in the first region I is more rounded, which can effectively weaken the local electric field and stress concentration in the first region I, avoid defects such as uneven gate oxide thickness and lattice dislocations caused by sharp corners during high-voltage gate oxide growth, and improve the voltage withstand capability and structural stability of the gate oxide in the first region I. At the same time, the more rounded angle shape can reduce the failure risk of hot carrier injection, dielectric breakdown, etc., and ensure the electrical performance and long-term reliability of the first region I under high voltage operation.

[0083] In summary, in the semiconductor structure formation method of the present invention, after forming the shallow trench isolation structure, a portion of the shallow trench isolation structure on the substrate is etched to expose the top and sidewalls of the active region near the shallow trench isolation structure, and the exposed active region is rounded. The remaining portion of the shallow trench isolation structure on the substrate is not etched to expose the active region, nor is the active region rounded. This method, by performing a rounding process on specific areas after forming the shallow trench isolation structure, solves the problem of stress concentration caused by sharp corners of the active region in some areas, while reducing the need for rounding processes in areas where they are not required. The solution mitigates the impact on the region, and maintains the shallow trench isolation structure formation process unchanged. The solution achieves significant improvements in process performance without major modifications to the process flow. Specifically, the substrate includes a first region suitable for forming high-voltage devices and a second region suitable for forming medium- and low-voltage devices. The semiconductor structure formation method includes: after rounding the exposed active region, forming a first gate oxide layer on the active region of the substrate in the first region; and forming a second gate oxide layer on the active region of the substrate in the second region, wherein the thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer. After forming the shallow trench isolation structure, the top and sidewalls of the active region suitable for forming high-voltage devices are rounded, while the top and sidewalls of the active region suitable for forming medium- and low-voltage devices are not rounded. This improves stress concentration between the top and sidewalls of the active region suitable for forming high-voltage devices, while avoiding impact on the region suitable for forming medium- and low-voltage devices.

[0084] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Forming a substrate; A shallow trench isolation structure and an active region are formed within the substrate, wherein the active region is adjacent to the shallow trench isolation structure; The shallow trench isolation structure is etched to expose a portion of the top and sidewalls of the active region near the shallow trench isolation structure. The exposed active area is rounded to create a rounded corner between the top and sidewall of the active area near the shallow trench isolation structure.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: After rounding the exposed active region, a first gate oxide layer is formed on the active region.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, In the step of forming a substrate, the substrate includes: a first region and a second region; The step of etching the shallow trench isolation structure to expose a portion of the top and sidewalls of the active region near the shallow trench isolation structure includes: etching the shallow trench isolation structure within the substrate of the first region; The step of rounding the exposed active region to form a rounded corner between the top and sidewall of the active region near the shallow trench isolation structure includes: rounding the active region within the substrate of the exposed first region to form a rounded corner between the top and sidewall of the active region near the shallow trench isolation structure. A first gate oxide layer is formed on the active region of the substrate in the first region; The method for forming the semiconductor structure further includes: after rounding the exposed active region, forming a second gate oxide layer on the active region of the substrate in the second region, wherein the thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, In the step of forming the first gate oxide layer on the active region, the first gate oxide layer is formed using a high-temperature furnace tube process.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of etching the shallow trench isolation structure to expose a portion of the top and sidewalls of the active region near the shallow trench isolation structure includes: The shallow trench isolation structure is etched by wet etching to expose part of the top and sidewalls of the active region near the shallow trench isolation structure.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, In the step of etching the shallow trench isolation structure by wet etching to expose the top and sidewalls of the active region near the shallow trench isolation structure, hydrofluoric acid is used as the etching solution.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: After forming a shallow trench isolation structure and an active region in the substrate, a protective layer is formed on the shallow trench isolation structure and the substrate before etching the shallow trench isolation structure. The method for forming the semiconductor structure further includes: after etching the shallow trench isolation structure, and before rounding the exposed active region, removing part of the protective layer to expose part of the top and sidewalls of the active region near the shallow trench isolation structure.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, Part of the protective layer is removed by wet etching.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of removing part of the protective layer by wet etching, phosphoric acid is used as the etching solution.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The steps for rounding the exposed active area include: oxidizing the exposed active area to form a sacrificial oxide layer on the exposed active area.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The step of rounding the exposed active area further includes removing the sacrificial oxide layer after it has been formed.

12. The method for forming a semiconductor structure as described in claim 10, characterized in that, The rounding process further includes: forming a linear oxide layer on the exposed active region before oxidizing the exposed active region and forming a sacrificial oxide layer on the exposed active region.

13. The method for forming a semiconductor structure as described in claim 10, characterized in that, In the step of oxidizing the exposed active region to form a sacrificial oxide layer on the exposed active region, the sacrificial oxide layer is formed using a high-temperature furnace tube process.

14. A semiconductor structure, characterized in that, The semiconductor structure is formed by the semiconductor structure forming method according to any one of claims 1 to 13 above.

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