Formation method of semiconductor structure

Abstract

A semiconductor structure forming method comprises the steps that a substrate is provided, the substrate comprises a first device area and a second device area, the first device area comprises a first area and a second area, the second device area comprises the second area and a third area, the first device area and the second device area share the second area, and an insulating layer is formed on the top of the substrate; forming a first opening in the insulating layer of the first region, and forming an alignment mark in the insulating layer of the second region; and after the first opening and the alignment mark are formed, a second opening is formed in the insulating layer of the third region. In the process of forming the second opening, a photomask is used and an exposure and development process is carried out, the alignment mark can improve the alignment precision of the photomask and the second region, the risk of deviation between patterns formed in the second region subsequently is reduced, and meanwhile, the first device region and the second device region share the second region, so that the production efficiency is improved. The interconnection path between the first device region and the second device region is shortened, so that the path loss between the first device region and the second device region is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] High-bandwidth memory (HBM) is an emerging solution to address the shortage of discrete dynamic random-access memory (DRAM) chips in artificial intelligence (AI) applications. HBM is typically connected to a system-on-a-chip (SoC) using 2.5D packaging technology.

[0003] However, the area of ​​the CoWoS (Chip on Wafer on Substrate) interposer is limited by photolithography technology, with a maximum scanning field area of ​​25.52mm*32.52mm. To overcome this limitation, a mask photolithography splicing method was adopted.

[0004] However, the mask lithography stitching method faces the problem of alignment between different mask patterns. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to further improve the performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first device region and a second device region, the first device region including a first region and a second region, the second device region including a second region and a third region, and the first device region and the second device region sharing the second region, an insulating layer being formed on the top of the substrate; forming a first opening in the insulating layer of the first region and forming an alignment mark in the insulating layer of the second region; and after forming the first opening and the alignment mark, forming a second opening in the insulating layer of the third region.

[0007] Optionally, the steps of forming the first opening and the alignment mark include: forming a first mask layer covering the insulating layer on top of the substrate; patterning the first mask layer of the first device region to form a first mask opening in the first mask layer of the first region and a second mask opening in the first mask layer of the second region; using the remaining first mask layer as a mask, patterning the insulating layers of the first region and the second region along the first mask opening and the second mask opening to form a first opening in the insulating layer of the first region and a first groove in the insulating layer of the second region, and using the first groove as the alignment mark.

[0008] Optionally, the first mask layer includes a first organic material layer and a first photoresist layer located above the first organic material layer.

[0009] Optionally, the step of patterning the first mask layer of the first device region includes: providing a first photomask, the first photomask including a first intermediate region and first boundary regions located on both sides of the first intermediate region, the first intermediate region having a first connection pattern, and the first boundary regions having a first alignment mark pattern; disposing the first photomask above the first mask layer of the first device region; and using the first photomask to perform exposure and development processing on the first mask layer of the first device region, forming a first mask opening in the first mask layer of the first region that corresponds to the first connection pattern, and forming a second mask opening in the first mask layer of the second region that corresponds to the first alignment mark pattern.

[0010] Optionally, the process for patterning the first mask layer of the first device region includes a dry etching process.

[0011] Optionally, after forming the first opening and the alignment mark, and before forming the second opening, the forming method further includes: removing the first mask layer; the step of forming the second opening includes: forming a second mask layer covering the insulating layer, the first opening, and the alignment mark on top of the substrate; providing a second photomask, the second photomask including a second intermediate region and second boundary regions located on both sides of the second intermediate region, the second intermediate region having a second connection pattern, and the second boundary regions having a second alignment mark pattern; aligning the second alignment mark pattern with the alignment mark; using the second photomask, exposing and developing the second mask layer of the second device region, forming a third mask opening in the second mask layer of the third region that corresponds to the second connection pattern, and forming a fourth mask opening in the second mask layer of the second region that corresponds to the second alignment mark pattern; using the remaining second mask layer as a mask, patterning the insulating layers of the second region and the third region along the third mask opening and the fourth mask opening, forming a second opening in the insulating layer of the third region, forming a second groove in the insulating layer of the second region, and using the second groove as the alignment mark.

[0012] Optionally, the second mask layer includes a second organic material layer and a second photoresist layer located above the second organic material layer.

[0013] Optionally, the process for removing the first mask layer includes a wet etching process or an ashing process.

[0014] Optionally, the first alignment mark pattern in the first boundary region is symmetrical to the second mark pattern in the second boundary region.

[0015] Optionally, during the process of forming the first opening and the alignment mark, the process further includes forming a first opening located on the side of the alignment mark in the insulating layer of the second region; during the process of forming the second opening, the process further includes forming a second opening located on the side of the alignment mark in the insulating layer of the second region, wherein the first opening and the second opening are longitudinally connected.

[0016] Optionally, during the formation of the first opening and the alignment mark, the first opening and the alignment mark are located within a portion of the thickness of the insulating layer; during the formation of the second opening, the second opening is located within a portion of the thickness of the insulating layer.

[0017] Optionally, after forming the second opening, the method for forming the semiconductor structure further includes: using the first opening and the second opening as masks, patterning the remaining insulating layer to form a third opening that communicates with the first opening, and forming a fourth opening that communicates with the second opening; forming conductive material in the first opening, the second opening, the third opening and the fourth opening, and using the conductive material located in the first opening, the second opening, the third opening and the fourth opening as the interconnect via structure.

[0018] Optionally, in the step of providing the substrate, the substrate includes a dielectric layer and one or more redistribution layers located in the dielectric layer; in the step of forming the interconnect via structure, the interconnect via structure is electrically connected to the redistribution layer.

[0019] Optionally, after forming the interconnect via structure, the method for forming the semiconductor structure further includes: forming a device chip and a memory on top of the insulating layer and the interconnect via structure, wherein the device chip and the memory are electrically connected to the interconnect via structure.

[0020] Optionally, the material of the interconnect via structure includes one or both of copper and aluminum.

[0021] Optionally, the insulating layer may be made of one or more of the following: fluorinated silicate, fluorinated silicate glass, tetraethoxysilane, siloxane, methylsilsesquioxane, hydrosilsesquioxane, and porous organosilicon.

[0022] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0023] This invention provides a method for forming a semiconductor structure, including a substrate comprising a first device region and a second device region. The first device region includes a first area and a second area, and the second device region includes a second area and a third area, with the first and second device regions sharing the second area. An insulating layer is formed on the top of the substrate. A first opening is formed in the insulating layer of the first area, and an alignment mark is formed in the insulating layer of the second area. After forming the first opening and the alignment mark, a second opening is formed in the insulating layer of the third area. Since the alignment mark is provided in the second area shared by the first and second device regions, after forming the first opening, a photomask is used and an exposure and development process is performed in the subsequent process of forming the second opening. The alignment mark can improve the alignment accuracy between the photomask and the second area, reducing the risk of misalignment between the patterns subsequently formed in the second area. At the same time, the sharing of the second area by the first and second device regions also shortens the interconnection path between the first and second device regions, thereby reducing the path loss between the first and second device regions, increasing the electrical signal transmission rate between the first and second device regions, and thus improving the performance of the semiconductor structure. Attached Figure Description

[0024] Figures 1 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0025] As can be seen from the background, the current mask lithography splicing method faces the problem of alignment between different mask patterns.

[0026] To address the technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first device region and a second device region, the first device region including a first region and a second region, the second device region including a second region and a third region, and the first device region and the second device region sharing the second region, an insulating layer being formed on the top of the substrate; forming a first opening in the insulating layer of the first region and forming an alignment mark in the insulating layer of the second region; and after forming the first opening and the alignment mark, forming a second opening in the insulating layer of the third region.

[0027] This invention provides a method for forming a semiconductor structure, including a substrate comprising a first device region and a second device region. The first device region includes a first area and a second area, and the second device region includes a second area and a third area, with the first and second device regions sharing the second area. An insulating layer is formed on the top of the substrate. A first opening is formed in the insulating layer of the first area, and an alignment mark is formed in the insulating layer of the second area. After forming the first opening and the alignment mark, a second opening is formed in the insulating layer of the third area. Since the alignment mark is provided in the second area shared by the first and second device regions, after forming the first opening, a photomask is used and an exposure and development process is performed in the subsequent process of forming the second opening. The alignment mark can improve the alignment accuracy between the photomask and the second area, reducing the risk of misalignment between the patterns subsequently formed in the second area. At the same time, the sharing of the second area by the first and second device regions also shortens the interconnection path between the first and second device regions, thereby reducing the path loss between the first and second device regions, increasing the electrical signal transmission rate between the first and second device regions, and thus improving the performance of the semiconductor structure.

[0028] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0029] Figures 1 to 14 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0030] refer to Figure 1 A substrate 100 is provided, the substrate 100 including a first device region 100A and a second device region 100B, the first device region 100A including a first region 100a and a second region 100C, the second device region 100B including a second region 100C and a third region 100b, and the first device region 100A and the second device region 100B share the second region 100C, and an insulating layer 101 is formed on the top of the substrate 100.

[0031] Specifically, substrate 100 provides a process platform for the formation of semiconductor structures.

[0032] It should be noted that both the first device region 100A and the second device region 100B are used as areas for setting device chips. The first device region 100A and the second device region 100B share the second region 100C, which shortens the interconnection path between the first device region 100A and the second device region 100B, thereby reducing the path loss between the first device region 100A and the second device region 100B, improving the electrical signal transmission rate between the first device region 100A and the second device region 100B, and thus improving the performance of the semiconductor structure.

[0033] In this embodiment, during the step of providing the substrate 100, the substrate 100 includes a dielectric layer and one or more rewiring layers located within the dielectric layer.

[0034] Specifically, the dielectric layer is used to provide electrical isolation to the redistribution layer.

[0035] As an example, the material of the dielectric layer includes one or more of silicon oxide, silicon nitride, silicon carbide, and silicon oxynitride.

[0036] It should be noted that the redistribution layer is used for electrical connection with the subsequently formed interconnect via structures, which are used for electrical connection with the subsequently formed device chips and memory, thereby enabling the device chips and memory to be electrically connected to external circuit structures (such as circuit boards) through the redistribution layer.

[0037] In this embodiment, the material of the redistribution layer includes one or both of copper and aluminum.

[0038] As an example, when there are multiple redistribution layers, electrical connections between adjacent redistribution layers are achieved through vias.

[0039] It should be noted that the insulating layer 101 provides the process basis for the subsequent formation of the first opening, the second opening and the alignment mark. At the same time, the insulating layer 101 also provides electrical isolation for the subsequent interconnect via structure.

[0040] In this embodiment, the material of the insulating layer 101 includes one or more of the following: silicon oxyfluoride (SIOF), fluorinated silicon glass (FSG), tetraethyl orthosilicate (TEOS), silicon oxycarbide (SiOC), methylsilsesquioxane (MSQ), hydrosilsesquioxane (HSQ), and porous organosilicate (POR).

[0041] Specifically, fluorinated silicate ions, fluorinated silicate glass, tetraethoxysilane, siloxycarbide, methylsilsesquioxane, hydrosilsesquioxane, and porous organosilicon materials are all low dielectric constant materials with good insulation properties. At the same time, they can reduce the probability of signal crosstalk between the first device region 100A and the second device, and improve the electrical signal transmission speed between the first device region 100A and the second device, thereby improving the performance of the semiconductor structure.

[0042] refer to Figures 2 to 5 ,in, Figure 3 It is a top view. Figures 4 to 5 Tie Figure 3 A cross-sectional view along the AA direction shows a first opening 120 formed in the insulating layer 101 of the first region 100a and an alignment mark 198 formed in the insulating layer 101 of the second region 100c.

[0043] It should be noted that since the second region 100C, which is shared by the first device region 100A and the second device region 100B, is provided with an alignment mark 198, after the first opening 120 is formed, a photomask will be used and an exposure and development process will be performed in the subsequent process of forming the second opening. The alignment mark 198 can improve the alignment accuracy between the photomask and the second region 100C, reduce the risk of misalignment between the patterns formed in the second region 100C. At the same time, the fact that the first device region 100A and the second device region 100B share the second region 100C also shortens the interconnection path between the first device region 100A and the second device region 100B, thereby reducing the path loss between the first device region 100A and the second device region 100B, improving the electrical signal transmission rate between the first device region 100A and the second device region 100B, and thus improving the performance of the semiconductor structure.

[0044] It should also be noted that the first opening 120 provides space for the subsequent formation of interconnect via structures.

[0045] In this embodiment, the steps of forming the first opening 120 and the alignment mark 198 include: forming a first mask layer 104 covering the insulating layer 101 on the top of the substrate 100; patterning the first mask layer 104 of the first device region 100A to form a first mask opening 117 in the first mask layer 104 of the first region 100a and a second mask opening 199 in the first mask layer 104 of the second region 100C; using the remaining first mask layer 104 as a mask, patterning the insulating layer 101 of the first region 100a and the second region 100C along the first mask opening 117 and the second mask opening 199 to form a first opening 120 in the insulating layer 101 of the first region 100a and a first groove in the insulating layer 101 of the second region 100C, and using the first groove as the alignment mark 198.

[0046] In this embodiment, the first mask layer 104 includes a first organic material layer 102 (SOC) and a first photoresist layer 103 (PR) located above the first organic material layer 102.

[0047] In this embodiment, the step of patterning the first mask layer 104 of the first device region 100A includes: providing a first photomask 112, the first photomask 112 including a first intermediate region 111 and first boundary regions 110 located on both sides of the first intermediate region 111, the first intermediate region 111 having a first connection pattern 115, and the first boundary regions 110 having alignment marks 198 and first alignment mark patterns 114; disposing the first photomask 112 above the first mask layer 104 of the first device region 100A; and using the first photomask 112, performing exposure and development processing on the first mask layer 104 of the first device region 100A, forming a first mask opening 117 in the first mask layer 104 of the first region 100a that corresponds to the first connection pattern 115, and forming a second mask opening 199 in the first mask layer 104 of the second region 100C that corresponds to the alignment marks 198 and first alignment mark patterns 114.

[0048] Specifically, such as Figure 3 As shown, for ease of illustration, the extension direction of the first connecting pattern 115 is all along the same direction. In other embodiments, the extension direction of the first connecting pattern is not limited.

[0049] It should be noted that the first photomask 112 is used for exposure and development of the first zone 100a and the second zone 100C.

[0050] In this embodiment, the process of patterning the first mask layer 104 of the first device region 100A includes a dry etching process.

[0051] Specifically, the dry etching process is an anisotropic dry etching process. Anisotropic dry etching processes have high pattern transfer accuracy and better sidewall morphology quality. By selecting anisotropic dry etching processes to pattern the first mask layer 104 of the first device region 100A, the sidewall morphology of the first mask opening 117 and the second mask opening 199 can be improved, resulting in high sidewall morphology quality for the subsequently formed first opening 120 and alignment mark 198.

[0052] In this embodiment, during the process of forming the first opening 120 and the alignment mark 198, the first opening 120 located on the side of the alignment mark 198 is also formed in the insulating layer 101 of the second region 100C.

[0053] It should be noted that the first opening 120 in the second region 100C extends perpendicularly to the first opening 120 in the first region 100a. In other embodiments, the first opening in the second region may extend in the same direction as the first opening in the first region.

[0054] Specifically, a first opening 120 is formed in the insulating layer 101 of the second region 100C, located on the side of the alignment mark 198. After an interconnect via structure is subsequently formed in the first opening 120, the first device region 100A and the second device region 100B can be electrically connected through the interconnect via structure in the second region 100C.

[0055] In this embodiment, during the formation of the first opening 120 and the alignment mark 198, the first opening 120 and the alignment mark 198 are located in the insulating layer 101 of a certain thickness.

[0056] It should be noted that the first opening 120 and the alignment mark 198 are located in the insulating layer 101 of a certain thickness, which makes the depth-to-width ratio of the first opening 120 and the alignment mark 198 small. In the subsequent process of forming the second opening, the process difficulty of filling the first opening 120 and the alignment mark 198 with the second mask layer is reduced. At the same time, the process difficulty of removing the second mask layer is also reduced, and the probability of the second mask layer remaining in the first opening 120 and the alignment mark 198 is reduced.

[0057] refer to Figure 6 After forming the first opening 120 and alignment mark 198, the first mask layer 104 is removed.

[0058] Specifically, removing the first mask layer 104 can reduce the aspect ratio of the first opening 120 and the alignment mark 198, which is beneficial for depositing the second mask layer in the first opening 120 and the alignment mark 198 during the subsequent formation of the second opening, thus reducing the deposition difficulty.

[0059] In this embodiment, the process for removing the first mask layer 104 includes a wet etching process or an ashing process.

[0060] Specifically, wet etching or ashing processes are commonly used to remove masks, which can reduce the probability of residual first mask layer 104.

[0061] refer to Figures 7 to 11 ,in, Figure 8 It is a top view. Figures 9 to 11 Tie Figure 8 In a cross-sectional view along the AA direction, after the first opening 120 and alignment mark 198 are formed, a second opening 146 is formed in the insulating layer 101 of the third region 100b.

[0062] It should be noted that the second opening 146 provides space for the subsequent formation of interconnecting via structures.

[0063] In this embodiment, the step of forming the second opening 146 includes: forming a second mask layer 124 covering the insulating layer 101, the first opening 120, and the alignment mark 198 on the top of the substrate 100; providing a second photomask 134, the second photomask 134 including a second intermediate region 132 and second boundary regions 133 located on both sides of the second intermediate region 132, the second intermediate region 132 having a second connection pattern 131, and the second boundary regions 133 having a second alignment mark pattern 130; aligning the second alignment mark pattern 130 with the alignment mark 198; and using the second photomask 134 to expose and develop the second mask layer 124 of the second device region 100B. A third mask opening 140, corresponding to the second connection pattern 131, is formed in the second mask layer 124 of the third region 100b, and a fourth mask opening 197, corresponding to the second alignment mark pattern 130, is formed in the second mask layer 124 of the second region 100c. Using the remaining second mask layer 124 as a mask, the insulating layers 101 of the second region 100c and the third region 100b are patterned along the third mask opening 140 and the fourth mask opening 197. A second opening 146 is formed in the insulating layer 101 of the third region 100b, and a second groove is formed in the insulating layer 101 of the second region 100c. The second groove is used as the alignment mark 198.

[0064] It should be noted that during the exposure and development of the second mask layer 124 of the second device region 100B using the second photomask 134, the second boundary region 133 and the first boundary region 110 are exposure overlap regions. That is to say, the second region 100C is exposed and developed by the first photomask 112 and the second photomask 134 in sequence.

[0065] It should also be noted that the second photomask 134 exposes and develops the second zone 100C and the third zone 100b.

[0066] Specifically, such as Figure 8 As shown, for ease of illustration, the extension direction of the second connecting pattern 131 is all along the same direction. In other embodiments, the extension direction of the second connecting pattern is not limited.

[0067] In this embodiment, the second mask layer 124 includes a second organic material layer (SOC) and a second photoresist layer (PR) located above the second organic material layer.

[0068] In this embodiment, the first alignment mark pattern 114 in the first boundary region 110 and the second alignment mark pattern 130 in the second boundary region 133 are symmetrical to each other.

[0069] Specifically, the first alignment mark pattern 114 in the first boundary region 110 and the second alignment mark pattern 130 in the second boundary region 133 are symmetrical to each other, so that during the formation of the second opening 146, the second alignment mark pattern 130 in the second boundary region 133 can be aligned with the alignment mark 198, thereby improving the alignment accuracy between the second photomask 134 and the second region 100C and reducing the risk of misalignment between the patterns subsequently formed in the second region 100C (i.e., the first opening 120 and the second opening 146 subsequently formed in the second region 100C).

[0070] It should be noted that, since the second alignment mark pattern 130 is aligned with the alignment mark 198, during the process of forming the second opening 146, the insulating layer 101 exposed at the bottom of the first groove will be patterned, thereby forming a second groove in the insulating layer 101 of the second region 100C, and the second groove is connected to the first groove.

[0071] In this embodiment, during the process of forming the second opening 146, the second opening 146 located on the side of the alignment mark 198 is also formed in the insulating layer 101 of the second region 100C, and the first opening 120 and the second opening 146 are longitudinally connected.

[0072] It should be noted that a second opening 146 is formed in the insulating layer 101 of the second region 100C, located on the side of the alignment mark 198. The first opening 120 and the second opening 146 are longitudinally connected. After an interconnecting via structure is formed in the first opening 120 and the second opening 146, the first device region 100A and the second device region 100B can be electrically connected through the interconnecting via structure in the second region 100C.

[0073] Specifically, the second opening 146 located in the second region 100C is perpendicular to the extending direction of the second opening 146 in the first region 100a. In other embodiments, the extending direction of the second opening in the second region may be the same as that of the second opening in the first region.

[0074] It should be noted that the first opening 120 and the second opening 146 are vertically connected. Therefore, the first boundary region 110 of the first photomask 112 has a first connecting pattern 115, and the second boundary region 133 of the second photomask 134 has a second connecting pattern 131. The first connecting pattern 115 in the first boundary region 110 and the second connecting pattern 131 in the second boundary region 133 are symmetrical.

[0075] In this embodiment, during the formation of the second opening 146, the second opening 146 is located in the insulating layer 101 of a certain thickness.

[0076] Specifically, the second opening 146 is located in the insulating layer 101 of a certain thickness, so that the second opening 146 does not expose the top of the substrate 100. Accordingly, the third and fourth openings can be formed in a subsequent etching process step, thereby reducing the probability of the top surface of the substrate 100 in the first region 100a and the third region 100b being etched and damaged.

[0077] It should be noted that, as Figure 11 As shown, after forming the second opening 146, the process also includes removing the second mask layer 124.

[0078] refer to Figures 12 to 13 After forming the second opening 146, the method for forming the semiconductor structure further includes: using the first opening 120 and the second opening 146 as masks, performing patterning processing on the remaining insulating layer 101 to form a third opening 150 that communicates with the first opening 120 and a fourth opening 155 that communicates with the second opening 146; forming conductive material in the first opening 120, the second opening 146, the third opening 150 and the fourth opening 155, and using the conductive material located in the first opening 120, the second opening 146, the third opening 150 and the fourth opening 155 as the interconnect via structure 180.

[0079] Specifically, the third opening 150 and the fourth opening 155 provide spatial locations for forming the interconnecting via structure 180.

[0080] In this embodiment, the process for forming the third opening 150 and the fourth opening 155 includes a dry etching process.

[0081] It should be noted that the interconnect via structure 180 is used for electrical connection with the subsequently formed device chip and memory, thereby enabling the device chip and memory to be electrically connected to external circuit structures (e.g., circuit boards) through the interconnect via structure 180.

[0082] In this embodiment, the step of forming the interconnect via structure 180 includes: forming conductive material in the first opening 120, the second opening 146, the third opening 150 and the fourth opening 155, and on the top of the insulating layer 101; taking the top of the insulating layer 101 as the stop position, performing planarization processing on the conductive material above the top of the insulating layer 101, and using the conductive material located in the first opening 120, the second opening 146, the third opening 150 and the fourth opening 155 as the interconnect via structure 180.

[0083] It should be noted that during the formation of the interconnect via structure 180, conductive material is also filled in the first and second grooves corresponding to the alignment mark 198. Accordingly, after planarization, the conductive material located in the alignment mark 198 is also used as the interconnect via structure 180.

[0084] Specifically, the process for planarizing the conductive material above the top of the insulating layer 101 includes a chemical mechanical polishing process.

[0085] In this embodiment, during the step of forming the interconnect via structure 180, the interconnect via structure 180 is electrically connected to the redistribution layer.

[0086] Specifically, the interconnect via structure 180 is electrically connected to the redistribution layer and is used to electrically connect to the subsequently formed device chip and memory, thereby enabling the device chip and memory to be electrically connected to external circuit structures (e.g., circuit boards) through the interconnect via structure 180.

[0087] In this embodiment, the material of the interconnect via structure 180 includes one or both of copper and aluminum.

[0088] refer to Figure 14 After forming the interconnect via structure 180, the method for forming the semiconductor structure further includes forming a device chip 190 and a memory 191 on top of the insulating layer 101 and the interconnect via structure 180, wherein the device chip 190 and the memory 191 are electrically connected to the interconnect via structure 180.

[0089] Specifically, the device chip 190 includes a system-on-a-chip (SoC), which has multiple functions to meet different application scenarios.

[0090] The memory 191 includes a high-bandwidth memory 191 (HBM) for storing large amounts of data and using the stored data for system-on-a-chip processing.

[0091] In this embodiment, the device chip 190 and the memory 191 are electrically connected to the interconnect via structure 180, enabling the device chip 190 and the memory 191 to be electrically connected to an external circuit structure (e.g., a circuit board) through the interconnect via structure 180.

[0092] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, include: A substrate is provided, the substrate including a first device region and a second device region, the first device region including a first region and a second region, the second device region including a second region and a third region, and the first device region and the second device region sharing the second region, and an insulating layer is formed on the top of the substrate; A first opening is formed in the insulating layer of the first region, and an alignment mark is formed in the insulating layer of the second region; After the first opening and alignment mark are formed, a second opening is formed in the insulating layer of the third region.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The steps of forming the first opening and alignment mark include: forming a first mask layer covering the insulating layer on top of the substrate; patterning the first mask layer of the first device region to form a first mask opening in the first mask layer of the first region and a second mask opening in the first mask layer of the second region; using the remaining first mask layer as a mask, patterning the insulating layers of the first region and the second region along the first mask opening and the second mask opening to form a first opening in the insulating layer of the first region and a first groove in the insulating layer of the second region, and using the first groove as the alignment mark.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The first mask layer includes a first organic material layer and a first photoresist layer located above the first organic material layer.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, The step of patterning the first mask layer of the first device region includes: providing a first photomask, the first photomask including a first intermediate region and first boundary regions located on both sides of the first intermediate region, the first intermediate region having a first connection pattern, and the first boundary regions having a first alignment mark pattern; disposing the first photomask above the first mask layer of the first device region; and using the first photomask to perform exposure and development processing on the first mask layer of the first device region, forming a first mask opening in the first mask layer of the first region that corresponds to the first connection pattern, and forming a second mask opening in the first mask layer of the second region that corresponds to the first alignment mark pattern.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The process for patterning the first mask layer of the first device region includes a dry etching process.

6. The method for forming a semiconductor structure as described in claim 4, characterized in that, After forming the first opening and the alignment mark and before forming the second opening, the forming method further includes: removing the first mask layer; The step of forming the second opening includes: forming a second mask layer on top of the substrate that covers the insulating layer, the first opening, and the alignment mark; A second photomask is provided, the second photomask including a second intermediate region and second boundary regions located on both sides of the second intermediate region, the second intermediate region having a second connection pattern, and the second boundary regions having a second alignment mark pattern; Align the second alignment mark graphic with the alignment mark; Using the second photomask, the second mask layer of the second device region is exposed and developed, and a third mask opening that corresponds to the second connection pattern is formed in the second mask layer of the third region, and a fourth mask opening that corresponds to the second alignment mark pattern is formed in the second mask layer of the second region. Using the remaining second mask layer as a mask, the insulating layers of the second and third regions are patterned along the third and fourth mask openings, forming a second opening in the insulating layer of the third region and a second groove in the insulating layer of the second region, and using the second groove as the alignment mark.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The second mask layer includes a second organic material layer and a second photoresist layer located above the second organic material layer.

8. The method for forming a semiconductor structure as described in claim 6, characterized in that, The process for removing the first mask layer includes wet etching or ashing.

9. The method for forming a semiconductor structure as described in claim 6, characterized in that, The first alignment mark pattern in the first boundary region is symmetrical to the second mark pattern in the second boundary region.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process of forming the first opening and the alignment mark also includes forming the first opening located on the side of the alignment mark in the insulating layer of the second region; The process of forming the second opening also includes forming a second opening located on the side of the alignment mark in the insulating layer of the second region, wherein the first opening and the second opening are longitudinally connected.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, During the formation of the first opening and alignment mark, the first opening and alignment mark are located within a portion of the thickness of the insulating layer; During the formation of the second opening, the second opening is located within a portion of the thickness of the insulating layer.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming the second opening, the method for forming the semiconductor structure further includes: using the first opening and the second opening as masks, patterning the remaining insulating layer to form a third opening that communicates with the first opening, and forming a fourth opening that communicates with the second opening; forming conductive material in the first opening, the second opening, the third opening and the fourth opening, and using the conductive material in the first opening, the second opening, the third opening and the fourth opening as an interconnect via structure.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, In the step of providing the substrate, the substrate includes a dielectric layer and one or more redistribution layers located in the dielectric layer; In the step of forming the interconnect via structure, the interconnect via structure is electrically connected to the redistribution layer.

14. The method for forming a semiconductor structure as described in claim 12, characterized in that, After forming the interconnect via structure, the method for forming the semiconductor structure further includes: forming a device chip and a memory on top of the insulating layer and the interconnect via structure, wherein the device chip and the memory are electrically connected to the interconnect via structure.

15. The method for forming a semiconductor structure as described in claim 12, characterized in that, The material of the interconnect via structure includes one or both of copper and aluminum.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, The insulating layer is made of one or more of the following materials: fluorinated silicate, fluorinated silicate glass, tetraethoxysilane, siloxycarbide, methylsilsesquioxane, hydrosilsesquioxane, and porous organosilicon.

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