Three-layer coreless packaging substrate manufacturing method and three-layer coreless packaging substrate

Abstract

The invention discloses a three-layer coreless packaging substrate manufacturing method and a three-layer coreless packaging substrate, and relates to the technical field of packaging. The method comprises the following steps: performing pretreatment, circuit manufacturing and cleaning on a strippable core board, and then forming same inner layer circuits on first copper foil layers on two surfaces of the strippable core board; pressing a second prepreg and a second copper foil layer on the strippable core plate to obtain a first semi-finished substrate, and performing circuit manufacturing to form a same middle-layer circuit; laminating a third prepreg and a third copper foil layer on the surface on which the middle-layer circuit is formed to obtain a second semi-finished substrate; the residual copper rate of the first copper foil layer is greater than that of the third copper foil layer; cutting the second semi-finished product substrate, and applying force along a target direction to separate the second semi-finished product substrate to obtain two three-layer coreless packaging semi-finished product substrates; and performing circuit manufacturing on the three-layer coreless packaging semi-finished product substrate to form an outer layer circuit on the surface, and performing post-processing to obtain the three-layer coreless packaging substrate. And the deformation and warping degree of the three-layer coreless packaging substrate can be effectively reduced.

Description

Technical Field

[0001] This application relates to the field of packaging technology, and in particular to a method for manufacturing a three-layer coreless packaging substrate and the three-layer coreless packaging substrate. Background Technology

[0002] As integrated circuits continue to evolve towards smaller, thinner, and more highly integrated designs, the market demands increasingly stringent requirements for the thickness and tolerances of three-layer packaging substrates. Currently, the thickness of ultra-thin coreless packaging substrates produced is 120±20µm. This total thickness tolerance is no longer sufficient to meet the needs of downstream manufacturers. Because ultra-thin coreless packaging substrates lack a core board, their strength is significantly lower than that of cored substrates, failing to provide adequate support during packaging. This makes them prone to deformation and warping during production, leading to board breakage, low yield, and further risks of substrate deformation and warping during downstream packaging. Therefore, how to manufacture thinner three-layer coreless packaging substrates while reducing the risk of deformation and warping is a pressing technical problem that needs to be solved. Summary of the Invention

[0003] This application aims to at least solve one of the technical problems existing in the prior art. To this end, this application proposes a method for manufacturing a three-layer coreless packaging substrate and a three-layer coreless packaging substrate, which can effectively reduce the deformation and warping of the three-layer coreless packaging substrate.

[0004] In a first aspect, embodiments of this application provide a method for fabricating a three-layer coreless packaging substrate, including: Prepare a peelable core board; wherein the peelable core board includes: a core substrate and a first copper foil layer formed on the surface of the core substrate; After pretreatment, first circuit fabrication, and cleaning of the peelable core board, the same inner layer circuit is formed on the first copper foil layer on both sides of the peelable core board. A second prepreg and a second copper foil layer are pressed onto the surface of the peelable core board to form the inner layer circuitry to obtain a first semi-finished substrate. The first semi-finished substrate is subjected to a second circuit fabrication process, and the same middle layer circuit is formed on the second copper foil layer on both sides of the first semi-finished substrate. A second semi-finished substrate is obtained by laminating a third prepreg and a third copper foil layer onto the surface of the first semi-finished substrate on which the middle layer circuit is formed; wherein, the residual copper content of the first copper foil layer is greater than that of the third copper foil layer. The second semi-finished substrate is cut by a board-splitting machine and separated by applying force along a target direction to obtain two three-layer coreless encapsulation semi-finished substrates; the target direction is the protrusion direction of the three-layer coreless encapsulation semi-finished substrates. The three-layer coreless packaging semi-finished substrate is subjected to a third circuit fabrication process to form an outer layer circuit on the surface, and then post-processed to obtain the three-layer coreless packaging substrate.

[0005] According to some embodiments of this application, the preparation of the peelable core board includes: Prepare the cored substrate; The peelable core board is formed by plating copper on both surfaces of the core substrate.

[0006] According to some embodiments of this application, the pretreatment of the peelable core board includes: Drill a positioning hole with a diameter of 0.2 mm at each of the four corners of the peelable core board edge; After fixing using the positioning holes, the peelable core board is subjected to a film pressing process to attach the photosensitive film to the peelable core board. The peelable core board with the photosensitive film attached is exposed and developed to remove the unhardened photosensitive film covering the non-effective area of ​​the process edge. The ineffective area of ​​the process edge is etched to obtain the peelable core board with the ineffective area of ​​the process edge etched away.

[0007] According to some embodiments of this application, before laminating a third prepreg and a third copper foil layer onto the surface of the first semi-finished substrate where the intermediate layer circuit is formed to obtain a second semi-finished substrate, the method further includes: The first semi-finished substrate undergoes a second circuit fabrication process, forming identical intermediate layer circuits on the second copper foil layers on both surfaces of the first semi-finished substrate, including: After the first semi-finished substrate is subjected to target reaming, acid washing, lamination, exposure and development, circuit patterns are formed on the second copper foil layer on both surfaces of the first semi-finished substrate. After electroplating, organic film removal and rapid etching are performed on the first semi-finished substrate that forms the circuit pattern, the middle layer circuit is formed. The first semi-finished substrate forming the middle layer circuit is subjected to AOI optical inspection. If the middle layer circuit meets the circuit requirements, the second copper foil layer forming the middle layer circuit is subjected to copper surface browning treatment to obtain the browned first semi-finished substrate.

[0008] According to some embodiments of this application, the third circuit fabrication process on the three-layer coreless packaged semi-finished substrate to form an outer layer circuit on the surface includes: The three-layer coreless packaging semi-finished substrate is subjected to the following steps in sequence: target edge trimming, laser blind hole operation, blind hole PTH treatment, circuit positive film, dry film lamination, circuit exposure and development, and dry film organic peeling to obtain the three-layer coreless packaging semi-finished substrate after film removal. The three-layer coreless encapsulation semi-finished substrate after film removal is subjected to baking and etching processes to form the outer layer circuitry. The three-layer coreless packaged semi-finished substrate forming the outer layer circuitry is subjected to AOI optical inspection. If the outer layer circuitry is confirmed to meet the circuitry requirements, the post-processing is then performed.

[0009] According to some embodiments of this application, the baking process for the three-layer coreless encapsulation semi-finished substrate after film removal includes: The three-layer coreless encapsulation semi-finished substrate after film removal is baked at a baking temperature of 150 degrees Celsius. After baking for a preset time, the baking plate processing is completed to stabilize the size of the three-layer coreless encapsulation semi-finished substrate.

[0010] According to some embodiments of this application, the post-processing includes: The three-layer coreless encapsulation semi-finished substrate after AOI optical inspection is subjected to pre-soldering treatment, vacuum pressing and flattening treatment using SR1 solder resist dry film, exposure treatment, and static treatment to obtain the exposed three-layer coreless encapsulation semi-finished substrate. After exposure, the double-sided PET protective film of the three-layer coreless packaging semi-finished substrate is removed, the SR1 solder resist dry film is developed, the SR1 solder resist dry film is photocured, the board is baked and the edges are trimmed, the surface is electroplated, and the molding process is performed to obtain the finished three-layer coreless packaging substrate; the surface electroplating process is a soft gold process for the front side and an OSP anti-oxidation process for the back side.

[0011] According to some embodiments of this application, both the first copper foil layer and the second copper foil layer include: a first sub-copper layer located in the inner layer and a second sub-copper layer located in the outer layer; the thickness of the first sub-copper layer and the second sub-copper layer is 12 μm.

[0012] According to some embodiments of this application, the thickness of the first curing sheet and the second curing sheet is 15 μm.

[0013] Secondly, embodiments of this application provide a three-layer coreless packaging substrate, which is prepared by the three-layer coreless packaging substrate manufacturing method as described in any one of the embodiments of the first aspect.

[0014] The embodiments of this application include: First, a peelable core board is prepared; wherein the peelable core board includes: a core substrate and a first copper foil layer formed on the surface of the core substrate; second, after pretreatment, first circuit fabrication treatment, and cleaning treatment of the peelable core board, identical inner layer circuits are formed on the first copper foil layer on both sides of the peelable core board; then, a second prepreg and a second copper foil layer are laminated onto the surface of the peelable core board where the inner layer circuits are formed to obtain a first semi-finished substrate; next, a second circuit fabrication treatment is performed on the first semi-finished substrate to form identical middle layer circuits on the second copper foil layer on both sides of the first semi-finished substrate; then, a third prepreg and a third copper foil layer are laminated onto the surface of the first semi-finished substrate where the middle layer circuits are formed to obtain a second semi-finished substrate; wherein, the residual copper ratio of the first copper foil layer is greater than the residual copper ratio of the third copper foil layer. The process involves bending the subsequent three-layer coreless encapsulation semi-finished substrate towards the direction of the third copper foil layer and bulging towards the direction of the first copper foil layer. Then, the second semi-finished substrate is cut using a board-splitting machine, and force is applied along the target direction to separate it into two three-layer coreless encapsulation semi-finished substrates. The target direction is the bulging direction of the three-layer coreless encapsulation semi-finished substrate. This helps to flatten the substrate during the board-splitting process, reducing the deformation and warping of the three-layer coreless encapsulation semi-finished substrate. Finally, the three-layer coreless encapsulation semi-finished substrate undergoes a third circuit fabrication process to form an outer layer circuit on its surface, followed by post-processing to obtain the three-layer coreless encapsulation substrate. During post-processing, processes such as lamination are performed to further reduce the deformation and warping of the three-layer coreless encapsulation semi-finished substrate. In other words, the embodiments of this application can effectively reduce the deformation and warping of the three-layer coreless encapsulation substrate.

[0015] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the description and the accompanying drawings. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a system architecture for performing a method for fabricating a three-layer coreless packaging substrate according to an embodiment of this application; Figure 2 This is a schematic diagram of the side curling of a common three-layer coreless packaging substrate; Figure 3 This is a schematic diagram of the side curling of a three-layer coreless packaging substrate provided in one embodiment of this application; Figure 4 This is a schematic diagram of the separation of a second semi-finished substrate provided in one embodiment of this application. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments.

[0018] It should be understood that in the description of this application, the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0019] It should be noted that although a logical order is shown in the flowcharts in this application, in some cases, the steps shown or described may be performed in a different order than that shown in the flowcharts. In the description of this application, "several" means one or more, and "more" means two or more. The terms "first" and "second" are used only to distinguish technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of technical features indicated, or implicitly indicating the order in which the technical features are indicated.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0021] This application provides a method for fabricating a three-layer coreless packaging substrate and the three-layer coreless packaging substrate, relating to the field of packaging technology. The method includes: pre-processing a peelable core board, fabricating circuitry, and cleaning; forming identical inner layer circuitry on the first copper foil layers on both sides of the peelable core board; laminating a second prepreg and a second copper foil layer onto the peelable core board to obtain a first semi-finished substrate, and then fabricating circuitry to form identical middle layer circuitry; laminating a third prepreg and a third copper foil layer onto the surface where the middle layer circuitry is formed to obtain a second semi-finished substrate; the residual copper ratio of the first copper foil layer is greater than that of the third copper foil layer; cutting the second semi-finished substrate and separating it along a target direction to obtain two three-layer coreless packaging semi-finished substrates; fabricating circuitry on the three-layer coreless packaging semi-finished substrates to form outer layer circuitry on their surfaces, and performing post-processing to obtain the three-layer coreless packaging substrate. This method can effectively reduce the deformation and warping of the three-layer coreless packaging substrate.

[0022] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0023] Firstly, such as Figure 1 As shown, Figure 1This is a schematic flowchart of a method for manufacturing a three-layer coreless packaging substrate according to an embodiment of this application. The method for manufacturing a three-layer coreless packaging substrate may include, but is not limited to, steps S100 to S700.

[0024] Step S100: Prepare a peelable core board; wherein the peelable core board includes: a core substrate and a first copper foil layer formed on the surface of the core substrate.

[0025] Step S200: After pre-processing, first circuit fabrication and cleaning of the peelable core board, the same inner layer circuit is formed on the first copper foil layer on both sides of the peelable core board.

[0026] Step S300: Press the second prepreg and the second copper foil layer onto the surface of the peelable core board to form the inner layer circuitry to obtain the first semi-finished substrate.

[0027] Step S400: Perform a second circuit fabrication process on the first semi-finished substrate, forming the same middle layer circuit on the second copper foil layer on both sides of the first semi-finished substrate.

[0028] Step S500: A third prepreg and a third copper foil layer are laminated onto the surface of the intermediate layer circuit of the first semi-finished substrate to obtain a second semi-finished substrate; wherein, the residual copper content of the first copper foil layer is greater than that of the third copper foil layer.

[0029] Step S600: The second semi-finished substrate is cut by a board splitting machine and separated by applying force along the target direction to obtain two three-layer coreless encapsulation semi-finished substrates; the target direction is the convex direction of the three-layer coreless encapsulation semi-finished substrates.

[0030] Step S700: Perform a third circuit fabrication process on the three-layer coreless packaging semi-finished substrate to form an outer layer circuit on the surface, and perform post-processing to obtain the three-layer coreless packaging substrate.

[0031] According to some embodiments of this application, step S100 is further described. Step S100: preparing a peelable core board includes, but is not limited to, steps S110 to S120.

[0032] Step S110: Prepare a core substrate.

[0033] Step S120: Copper plating is performed on both surfaces of the core substrate to form a peelable core board.

[0034] It should be noted that this application mainly focuses on the design, lamination, and copper plating production process of ultra-thin three-layer packaging substrates, employing inner and outer layer mSAP technology. A flame-retardant halogen-free copper-clad laminate with a Cl content ≤0.09%, Br content ≤0.09%, and total halogen content ≤0.15% is used. The structure of the peelable core board is as follows: a B / Boz (2 / 2um) copper foil is added to the outer top and bottom layers of an H / Hoz (18 / 18um) core substrate to form the peelable core board. Previously, the core material underwent a baking process after cutting to relieve stress and improve expansion, contraction, and warping. However, the peelable core board does not require baking after cutting, and the core material is removed after subsequent lamination. Baking only increases the risk of delamination of the peelable core board. This application does not perform a baking process in step S100 to ensure that the peelable core board does not delamination before core board removal.

[0035] Steps S110 to S120 prepare the peelable core board to provide material preparation for the subsequent fabrication of the three-layer coreless packaging substrate and provide a working basis.

[0036] According to some embodiments of this application, step S200 is further described, wherein the pretreatment of the peelable core board includes, but is not limited to, steps S210 to S240.

[0037] Step S210: Drill a positioning hole with a diameter of 0.2 mm at each of the four corners of the peelable core board edge.

[0038] Step S220: After fixing using the positioning holes, the peelable core board is pressed to attach the photosensitive film to the peelable core board.

[0039] Step S230: Expose and develop the peelable core board with the photosensitive film attached, and remove the uncured photosensitive film covering the non-effective area of ​​the process edge.

[0040] Step S240: Etch the ineffective area of ​​the process edge to obtain a peelable core board with the ineffective area of ​​the process edge etched away.

[0041] From step S210 to step S240, four 0.2mm positioning holes are drilled at the four corners of the peelable core board. Then, the first pressing, exposure, development, and etching operations are performed. The purpose is to etch the copper skin on the board edge. The etched part is the non-effective area of ​​the process edge. The subsequent board fabrication is carried out to prepare materials and provide a basis for the operation.

[0042] Further explanation of step S200: After pretreatment, first circuit fabrication, and cleaning of the peelable core board, identical inner layer circuits are formed on the first copper foil layers on both sides of the peelable core board. It can be understood that the B / B copper foil of the peelable core board is used for the inner and outer layer circuits of subsequent three-layer coreless structure products. Specifically, during the first circuit fabrication process, the peelable core board is first machine-drilled and edge-sealed. Then, holes are drilled and edge-sealed in the non-effective area of ​​the process board. During subsequent lamination of the prepreg, the resin of the prepreg flows into the holes to seal them. After circuit alignment, 1.5mm positioning holes are drilled on the board edge using internal mechanical drilling as positioning points. Then, the surface of the peelable core board is laminated, the circuit is exposed to positive film, developed, electroplated with copper, stripped, and baked, forming inner layer circuits on both surfaces. After completing the first circuit fabrication, no pre-treatment of the copper surface for browning is required; after cleaning, the pre-stacked boards are directly laminated.

[0043] Further explanation of step S300: A second prepreg and a second copper foil layer are laminated onto the surface of the peelable core board forming the inner layer circuit to obtain a first semi-finished substrate. Specifically, a second prepreg and a second copper foil layer are placed sequentially on the surface of the peelable core board forming the inner layer circuit, and the second prepreg and the second copper foil layer are laminated at high temperature to obtain the first semi-finished substrate.

[0044] According to some embodiments of this application, the first copper foil layer includes: a first sub-copper layer located in the inner layer and a second sub-copper layer located in the outer layer; the thickness of the first sub-copper layer and the second sub-copper layer is 12 μm.

[0045] According to some embodiments of this application, the thickness of the first cured sheet is 15 μm.

[0046] In step S300, the thinnest 15um thick PP is used in combination with T / T (12 / 12um) copper foil to press together a 4-layer structure semi-finished substrate (i.e., the first semi-finished substrate).

[0047] According to some embodiments of this application, step S400 is further described. Step S400: a second circuit fabrication process is performed on the first semi-finished substrate to form the same middle layer circuit on the second copper foil layer on both surfaces of the first semi-finished substrate, including but not limited to steps S410 to S430.

[0048] Step S410: After the first semi-finished substrate is subjected to target reaming, acid washing, lamination, exposure and development, circuit patterns are formed on the second copper foil layer on both surfaces of the first semi-finished substrate.

[0049] Step S420: After electroplating, organic film removal and rapid etching of the first semi-finished substrate with the circuit pattern, the middle layer circuit is formed.

[0050] Step S430: Perform AOI optical inspection on the first semi-finished substrate forming the middle layer circuit. If the middle layer circuit meets the circuit requirements, perform copper browning treatment on the second copper foil layer forming the middle layer circuit to obtain the browned first semi-finished substrate.

[0051] Specifically, AOI optical inspection is used to inspect circuit defects. By performing AOI optical inspection on the first semi-finished substrate that forms the middle layer circuit, circuit defects are inspected to ensure that the manufactured circuits meet the circuit requirements, resulting in a high circuit yield when leaving the factory.

[0052] Through steps S410 to S430, the fabrication of the middle layer circuitry is completed, resulting in the first semi-finished substrate after browning, which facilitates subsequent lamination to fabricate the next layer of circuitry.

[0053] Further explanation of step S500: A third prepreg and a third copper foil layer are laminated onto the surface of the intermediate layer circuit of the first semi-finished substrate to obtain a second semi-finished substrate; wherein, the residual copper content of the first copper foil layer is greater than that of the third copper foil layer.

[0054] According to some embodiments of this application, the second copper foil layer includes: a first sub-copper layer located in the inner layer and a second sub-copper layer located in the outer layer; the thickness of the first sub-copper layer and the second sub-copper layer is 12 μm.

[0055] According to some embodiments of this application, the thickness of the second cured sheet is 15 μm.

[0056] In step S500, the thinnest 15um thick PP is used in combination with T / T (12 / 12um) copper foil to press together a 6-layer structure semi-finished substrate (i.e., the second semi-finished substrate).

[0057] It should be noted that currently manufactured three-layer coreless packaging substrates lack a core layer, relying entirely on stacked copper foil and dielectric layers, making them inherently prone to warping. Furthermore, the residual copper content differs between the innermost and outermost layers; specifically, the residual copper content of the outermost layer is greater than that of the innermost layer. This creates a "bimetallic effect" on the upper and lower surfaces, leading to uneven tensile forces during temperature changes, which can easily cause warping, i.e., the three-layer coreless packaging substrate bulges downwards. Figure 2 As shown, the edges curl upwards. Figure 2 This is a schematic diagram of the common side curling of a three-layer coreless packaging substrate. However, the embodiments of this application, by changing the interlayer structure, make the residual copper ratio of the first copper foil layer (the innermost copper layer) greater than that of the third copper foil layer (the outermost copper layer), thus altering the curling of the three-layer coreless packaging substrate and causing it to bulge upwards. Figure 2 As shown, the edges curl downwards. Figure 3This is a schematic diagram showing the side curling of a three-layer coreless packaging substrate according to an embodiment of this application. This application changes the curling direction of the three-layer coreless packaging substrate to facilitate subsequent flattening of the curled three-layer coreless packaging substrate using a series of processes.

[0058] Step S600: The second semi-finished substrate is cut by a board splitting machine and separated by applying force along the target direction to obtain two three-layer coreless encapsulation semi-finished substrates; the target direction is the convex direction of the three-layer coreless encapsulation semi-finished substrates.

[0059] Understandably, after the second semi-finished substrate is produced, it is cut and separated by applying force along the target direction to obtain two three-layer coreless packaging semi-finished substrates, such as... Figure 4 As shown, Figure 4 This is a schematic diagram of the separation of the second semi-finished substrate provided in one embodiment of this application. It can be understood that, by changing the processing method, the layer structure of the three-layer coreless encapsulation semi-finished substrate formed in this application is: core + first layer with a large residual copper ratio + second layer + third layer with a large residual copper ratio, so that the thin plate bulges upward. After separation, the edge of the plate is pulled upward, which is equivalent to flattening the thin plate. Subsequently, this Ayong SR1 dry film press-dry film replaces the drying step to further flatten the thin plate. During subsequent board making, gravity is used to continue pressing the plate to reduce the curvature of the thin plate.

[0060] It should be noted that, in the two three-layer coreless packaging semi-finished substrates, such as Figure 4 As shown, the protrusion of the three-layer coreless packaging semi-finished substrate located above the dividing line is upward; the protrusion of the three-layer coreless packaging semi-finished substrate located above the dividing line is downward; both three-layer coreless packaging semi-finished substrates protrude in the direction of the third copper foil layer.

[0061] Specifically, this application uses step S600 to peel off the outer copper foil of the 6-layer semi-finished substrate and split it into two to form two identical three-layer coreless packaging substrates. When peeling off the copper foil and splitting the board, force is applied in the target direction to prevent serious warping problems in the product after the board is split.

[0062] According to some embodiments of this application, step S700 is further described. Step S700: The three-layer coreless packaging semi-finished substrate is subjected to a third circuit fabrication process to form an outer layer circuit on the surface, including but not limited to steps S710 to S730.

[0063] Step S710: The three-layer coreless packaging semi-finished substrate is subjected to the following steps in sequence: target edge trimming, laser blind via operation, blind via PTH treatment, circuit positive film, dry film lamination, circuit exposure and development, and organic stripping of dry film to obtain the three-layer coreless packaging semi-finished substrate after film removal.

[0064] Step S720: The three-layer coreless encapsulation semi-finished substrate after film removal is subjected to baking and etching processes to form the outer layer circuitry.

[0065] Step S730: Perform AOI optical inspection on the three-layer coreless packaged semi-finished substrate that forms the outer layer circuit. If the outer layer circuit meets the circuit requirements, perform post-processing.

[0066] According to some embodiments of this application, step S720 is further described. Step S720 is a baking process for the three-layer coreless encapsulation semi-finished substrate after the film is removed, including but not limited to steps S721 to S722.

[0067] Step S721: Bake the three-layer coreless encapsulation semi-finished substrate after film removal at a baking temperature of 150 degrees Celsius.

[0068] Step S722: After baking for a preset time, the baking plate is processed to stabilize the size of the three-layer coreless encapsulation semi-finished substrate.

[0069] It is understandable that the baking plate treatment in steps S721 to S722 is used to stabilize the material and prevent dimensional expansion and contraction.

[0070] According to some embodiments of this application, step S730 is further described, wherein the post-processing includes, but is not limited to, steps S731 to S732.

[0071] Step S731: Perform pre-soldering treatment on the three-layer coreless packaging semi-finished substrate after AOI optical inspection, use SR1 solder resist dry film for vacuum lamination and flattening, exposure treatment, and static treatment to obtain the exposed three-layer coreless packaging semi-finished substrate.

[0072] Step S732: Remove the double-sided PET protective film from the exposed three-layer coreless packaging semi-finished substrate, develop the SR1 solder resist dry film, light-cur the SR1 solder resist dry film, bake the board and trim the edges, perform surface electroplating, and shape the substrate to obtain the finished three-layer coreless packaging substrate; the surface electroplating is performed by using a soft gold process on the front side and an OSP anti-oxidation process on the back side.

[0073] Through steps S731 to S732, a finished three-layer coreless packaging substrate is produced.

[0074] Understandably, through steps S710 to S730, specifically, the final targeting operation is performed on the three-layer coreless packaging semi-finished substrate after board separation; laser blind via operation is performed on the three-layer coreless packaging semi-finished substrate; mSAP process is performed on the outer layer; PTH treatment is performed on the forked vias (PTH treatment refers to: using PTH solution to form an organic conductive film on the wall of the via on the substrate after laser blind via, so that the 1-3 layers of copper foil are connected through the conductive film in this via, providing a base adhesion for subsequent via filling); positive film is used for the circuit; RD-1225 anti-plating dry film is used for lamination; outer layer circuit exposure is performed; and the areas where the circuit pattern needs to be formed are not exposed and developed. The areas requiring etching of the line spacing are covered with dry film and not developed. After developing the outer layer lines, the three-layer coreless packaging substrate is filled with holes to form an electroplated copper layer with the surface copper. The copper thickness of the plated surface copper is less than 18um. The package substrate after hole filling is subjected to dry film organic stripping. The film is removed cleanly using a high-pressure stripping line. The package substrate after stripping is then baked at 150℃ for 1 hour to stabilize the expansion and contraction dimensions of the three-layer coreless packaging semi-finished substrate. Then, the outer layer lines are rapidly etched, flash etching the B / B (2 / 2um) bottom copper foil. The top and bottom lines form the outer layer pattern of the lines, and AOI optical inspection is performed to check for defects and abnormalities in the lines. For the copper surface of the three-layer coreless encapsulation semi-finished substrate after AOI optical scanning, the solder resist process uses SR1 dry film ink for vacuum lamination and airbag flattening, resulting in a total board thickness of 0.985-0.115 (0.10±0.015) mm after flattening. After exposure and standing for 30 minutes, the double-sided PET protective film is first peeled off, and then the solder resist dry film is developed to expose the windowed area. The solder resist dry film is first UV cured to ensure the hardening degree of the product, and then baked. After baking, the edge shaping is performed; before the cover line. The copper surface is cleaned, then vacuum-pressed, exposed, and developed. Areas requiring electroplating are exposed by opening windows. The areas where leads are etched back are covered with an anti-electroplating dry film. A soft gold plating process is then performed. The exposed areas are coated with the required thick gold-nickel layer for encapsulation, soldering, bonding, and wire bonding. The dry film is then removed, and wire bonding is repeated. The BGA copper surface to be treated with OSP is covered with dry film, and the exposed areas are subjected to alkaline etching. After alkaline etching, the film is removed again. After removal, CCD is used to drill the vias of the three-layer coreless encapsulation semi-finished substrate. After drilling, 2D coding and board forming are performed before molding to ensure the dimensions of the formed board are within tolerance requirements. The molded three-layer coreless encapsulation substrate is cleaned, and a flying probe is used for short-circuiting. If no abnormalities are found, OSP processing is performed on the BGA copper surface to form a 0.3+ / -0.1um anti-oxidation film. Finally, final quality inspection, packaging, and warehousing are performed.

[0075] According to some embodiments of this application, both the first copper foil layer and the second copper foil layer include: a first sub-copper layer located in the inner layer and a second sub-copper layer located in the outer layer; the thickness of the first sub-copper layer and the second sub-copper layer is 12 μm. According to some embodiments of this application, the thickness of the first curing wafer and the second curing wafer is 15 μm. By using thinner first and second copper foil layers, first curing wafers and second curing wafers, it is beneficial to reduce the thickness of the three-layer coreless packaging substrate.

[0076] Through steps S100 to S700, firstly, a peelable core board is prepared; wherein, the peelable core board includes: a core substrate and a first copper foil layer formed on the surface of the core substrate; secondly, after pretreatment, first circuit fabrication treatment, and cleaning treatment of the peelable core board, identical inner layer circuits are formed on the first copper foil layers on both sides of the peelable core board; then, a second prepreg and a second copper foil layer are laminated onto the surface of the peelable core board where the inner layer circuits are formed to obtain a first semi-finished substrate; next, a second circuit fabrication treatment is performed on the first semi-finished substrate to form identical middle layer circuits on the second copper foil layers on both sides of the first semi-finished substrate; then, a third prepreg and a third copper foil layer are laminated onto the surface of the first semi-finished substrate where the middle layer circuits are formed to obtain a second semi-finished substrate; wherein, the residual copper rate of the first copper foil layer is greater than the residual copper rate of the third copper foil layer; so that... The resulting three-layer coreless encapsulation semi-finished substrate is bent towards the direction of the third copper foil layer and bulges towards the direction of the first copper foil layer. Then, the second semi-finished substrate is cut by a board-splitting machine and separated by applying force along the target direction to obtain two three-layer coreless encapsulation semi-finished substrates. The target direction is the bulging direction of the three-layer coreless encapsulation semi-finished substrate. This can reduce the deformation and warping of the three-layer coreless encapsulation semi-finished substrate by flattening it during the board-splitting process. Finally, the three-layer coreless encapsulation semi-finished substrate is processed to form an outer layer circuit on the surface, and then post-processed to obtain the three-layer coreless encapsulation substrate. During the post-processing, processes such as lamination are performed to further reduce the deformation and warping of the three-layer coreless encapsulation semi-finished substrate. That is to say, the embodiments of this application can effectively reduce the deformation and warping of the three-layer coreless encapsulation substrate.

[0077] Secondly, embodiments of this application provide a three-layer coreless packaging substrate, which is prepared by the three-layer coreless packaging substrate manufacturing method as described in any one of the embodiments of the first aspect.

[0078] In summary, the three-layer coreless packaging substrate fabrication method of this application improves the total thickness of the original coreless three-layer board (120+ / -20um) to 100+ / -15um; the through-hole plating of the ultra-thin three-layer packaging substrate is controlled to achieve a minimum thickness of 4um; the quality and yield of the ultra-thin three-layer coreless packaging substrate are improved, meeting the reliability and quality requirements for the ultra-thin three-layer packaging substrate.

[0079] This application employs inner and outer layer mSAP technology, using a peelable core board, and involves a total of two lamination processes. The product surface treatment is lamination + copper plating, resulting in a three-layer laser blind via filling product. After the second lamination, when forming a six-layer semi-finished substrate, the outer copper foil is peeled off and the board is split in two to form two identical ultra-thin three-layer packaging substrates. This ensures that the product is free of delamination and bubbles after lamination. SR1 dry film ink is used to cover the surface of the circuit after the circuit is applied to ensure the uniformity of the thickness of the ultra-thin three-layer packaging substrate.

[0080] The above provides a detailed description of the preferred embodiments of this application. However, this application is not limited to the above-described embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application. All such equivalent modifications or substitutions are included within the scope defined by this application.

Claims

1. A method for manufacturing a three-layer coreless package substrate, characterized by, include: Prepare a peelable core board; wherein the peelable core board includes: a core substrate and a first copper foil layer formed on the surface of the core substrate; After pretreatment, first circuit fabrication, and cleaning of the peelable core board, the same inner layer circuit is formed on the first copper foil layer on both sides of the peelable core board. A second prepreg and a second copper foil layer are pressed onto the surface of the peelable core board to form the inner layer circuitry to obtain a first semi-finished substrate. The first semi-finished substrate is subjected to a second circuit fabrication process, and the same middle layer circuit is formed on the second copper foil layer on both sides of the first semi-finished substrate. A second semi-finished substrate is obtained by laminating a third prepreg and a third copper foil layer onto the surface of the first semi-finished substrate on which the middle layer circuit is formed; wherein, the residual copper content of the first copper foil layer is greater than that of the third copper foil layer. The second semi-finished substrate is cut by a board-splitting machine and separated by applying force along a target direction to obtain two three-layer coreless encapsulation semi-finished substrates; the target direction is the protrusion direction of the three-layer coreless encapsulation semi-finished substrates. The three-layer coreless packaging semi-finished substrate is subjected to a third circuit fabrication process to form an outer layer circuit on the surface, and then post-processed to obtain the three-layer coreless packaging substrate.

2. The method of claim 1, wherein The preparation of the peelable core board includes: Prepare the cored substrate; The peelable core board is formed by plating copper on both surfaces of the core substrate.

3. The method for fabricating a three-layer coreless packaging substrate according to claim 1, characterized in that, Pre-treatment of the peelable core board includes: Drill a positioning hole with a diameter of 0.2 mm at each of the four corners of the peelable core board edge; After fixing using the positioning holes, the peelable core board is subjected to a film pressing process to attach the photosensitive film to the peelable core board. The peelable core board with the photosensitive film attached is exposed and developed to remove the unhardened photosensitive film covering the non-effective area of ​​the process edge. The ineffective area of ​​the process edge is etched to obtain the peelable core board with the ineffective area of ​​the process edge etched away.

4. The method for fabricating a three-layer coreless packaging substrate according to claim 1, characterized in that, The first semi-finished substrate undergoes a second circuit fabrication process, forming identical intermediate layer circuits on the second copper foil layers on both surfaces of the first semi-finished substrate, including: After the first semi-finished substrate is subjected to target reaming, acid washing, lamination, exposure and development, circuit patterns are formed on the second copper foil layer on both surfaces of the first semi-finished substrate. After electroplating, organic film removal and rapid etching are performed on the first semi-finished substrate that forms the circuit pattern, the middle layer circuit is formed. The first semi-finished substrate forming the middle layer circuit is subjected to AOI optical inspection. If the middle layer circuit meets the circuit requirements, the second copper foil layer forming the middle layer circuit is subjected to copper surface browning treatment to obtain the first semi-finished substrate after browning.

5. The method for fabricating a three-layer coreless packaging substrate according to claim 1, characterized in that, The process of performing a third circuit fabrication on the three-layer coreless packaging semi-finished substrate to form an outer layer circuit on the surface includes: The three-layer coreless packaging semi-finished substrate is subjected to the following steps in sequence: target edge trimming, laser blind hole operation, blind hole PTH treatment, circuit positive film, dry film lamination, circuit exposure and development, and dry film organic peeling to obtain the three-layer coreless packaging semi-finished substrate after film removal. The three-layer coreless encapsulation semi-finished substrate after film removal is subjected to baking and etching processes to form the outer layer circuitry. The three-layer coreless packaged semi-finished substrate forming the outer layer circuitry is subjected to AOI optical inspection. If the outer layer circuitry is confirmed to meet the circuitry requirements, the post-processing is then performed.

6. The method for fabricating a three-layer coreless packaging substrate according to claim 5, characterized in that, The baking process for the three-layer coreless encapsulation semi-finished substrate after film removal includes: The three-layer coreless encapsulation semi-finished substrate after film removal is baked at a baking temperature of 150 degrees Celsius. After baking for a preset time, the baking plate processing is completed to stabilize the size of the three-layer coreless encapsulation semi-finished substrate.

7. The method for fabricating a three-layer coreless packaging substrate according to claim 1 or 5, characterized in that, The post-processing includes: The three-layer coreless encapsulation semi-finished substrate after AOI optical inspection is subjected to pre-soldering treatment, vacuum pressing and flattening treatment using SR1 solder resist dry film, exposure treatment, and static treatment to obtain the exposed three-layer coreless encapsulation semi-finished substrate. After exposure, the double-sided PET protective film of the three-layer coreless packaging semi-finished substrate is removed, the SR1 solder resist dry film is developed, the SR1 solder resist dry film is photocured, the board is baked and the edges are trimmed, the surface is electroplated, and the molding process is performed to obtain the finished three-layer coreless packaging substrate; the surface electroplating process is a soft gold process for the front side and an OSP anti-oxidation process for the back side.

8. The method for fabricating a three-layer coreless packaging substrate according to claim 1, characterized in that, Both the first copper foil layer and the second copper foil layer include: a first sub-copper layer located in the inner layer and a second sub-copper layer located in the outer layer; the thickness of the first sub-copper layer and the second sub-copper layer is 12um.

9. The method for fabricating a three-layer coreless packaging substrate according to claim 1, characterized in that, The thickness of the first and second cured sheets is 15µm.

10. A three-layer coreless packaging substrate, characterized in that, It is prepared by the three-layer coreless packaging substrate fabrication method according to any one of claims 1 to 9.

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