Fan-out wafer level packaging unit

Abstract

The invention discloses a fan-out type wafer level packaging unit, which comprises a carrier plate, a first dielectric layer, a plurality of first conductive connection lines, at least one first die, a second dielectric layer, at least one conductive column, a plurality of second conductive connection lines, a third dielectric layer, a plurality of third conductive connection lines and at least one second die, wherein each first die and each second die can be electrically connected with each other through each first welding pad around the wafer area on the second surface of each first die; wherein each first conductive connection line, each second conductive connection line and each third conductive connection line are manufactured by using a technology of filling metal paste into the grooves and then grinding and forming the conductive connection lines, so that the problems that the manufacturing cost is high and environmental protection is not facilitated when each conductive connection line is manufactured by using the existing fan-out packaging technology are solved.

Description

Technical Field

[0001] This invention relates to a packaging unit, and more particularly to a fan-out wafer-level packaging unit. Background Technology

[0002] In advanced FOWLP packaging, the redistribution layer (RDL) is the most critical component. This is because the conductors in the RDL enable multiple pads on the die to achieve XY-planar electrical extension and interconnection, allowing for the formation of more dispersed solder pads around the die. This effectively improves the design space and reliability of each conductor. However, the fabrication of each conductor in the RDL is crucial in ensuring that it maintains or achieves a certain degree of thinness and compactness while achieving XY-planar electrical extension and interconnection.

[0003] However, the existing FOWLP packaging technology uses RDL technology to form the conductors by chemical plating or electroplating. This results in relatively high material and manufacturing costs, and the existing process does not meet or is detrimental to environmental protection requirements.

[0004] Furthermore, when the FOWLP package unit needs to increase performance or computing power, it is necessary to increase the number of bare dies. How to make electrical connections between the bare dies inside the package unit and the external bare dies, or between them, is also an important problem that needs to be solved. Summary of the Invention

[0005] The main objective of this invention is to provide a fan-out wafer-level packaging unit, comprising a carrier board, a first dielectric layer, multiple first conductive lines, at least one first die, a second dielectric layer, at least one conductive post, multiple second conductive lines, a third dielectric layer, multiple third conductive lines, and at least one second die; wherein each first die and each second die can be electrically connected to the external circuit via first bonding pads around the wafer region on the second surface of each first die; wherein each first conductive line, each second conductive line, and each third conductive line is manufactured using a technique of first filling the grooves with metal paste and then grinding to form the conductive lines, effectively solving the problem that existing fan-out packaging technology in modules easily generates high manufacturing costs and is detrimental to the environment when manufacturing each conductive line.

[0006] To achieve the above objectives, the present invention provides a fan-out wafer-level packaging unit, which includes a carrier substrate, a first dielectric layer, multiple first conductive lines, at least one first die, a second dielectric layer, at least one conductive post, multiple second conductive lines, a third dielectric layer, multiple third conductive lines, and at least one second die; wherein the carrier substrate has a first surface and an opposite second surface, wherein a carrier substrate dielectric layer is disposed on the second surface of the carrier substrate; wherein the first dielectric layer is disposed on the carrier substrate dielectric layer, and the first dielectric layer has at least one first groove formed extending horizontally; wherein each of the first conductive lines The path is formed by filling each of the first grooves with metal paste; each of the first dies is diced from a wafer, each of the first dies has a first surface and an opposite second surface, the first surface of each of the first dies has a plurality of first wafer pads, the vertical wafer region of the second surface of each of the first dies defines a wafer region, each of the first dies has at least one wafer conductive post penetrating the first surface and the second surface of the first die, such that the first surface of each of the first dies can be electrically connected to the second surface of the first die through the wafer conductive post, wherein each of the first dies is formed using a flip-chip technique. The first surface of the bare die is covered on the first conductive line, such that each pad of each first bare die is electrically connected to each first conductive line; wherein the second dielectric layer is disposed on the first dielectric layer and covers each first bare die, the second dielectric layer has at least one second groove and at least one through hole formed in a horizontal direction, each second groove communicates with each through hole, and each through hole communicates with each first groove; wherein each conductive post is formed in each through hole and exposed to the outside through each through hole, wherein each conductive post is electrically connected to each first conductive line; wherein each second conductive line is filled in each The second groove is formed by metal paste, wherein each of the second conductive lines is electrically connected to each of the conductive pillars; wherein the third dielectric layer is disposed on the second dielectric layer and each of the second conductive lines, the third dielectric layer having at least one opening formed in a horizontal direction; wherein each of the third conductive lines is formed by filling the opening with metal paste, wherein at least one opening is located around the wafer region on the second surface of each of the first bare dies, wherein each of the third conductive lines is exposed to the outside by each opening and a first solder pad is formed in the opening, wherein each of the third conductive lines is electrically connected to each of the second conductive lines;Each of the second dies is diced from a wafer. Each second die has a first surface and an opposite second surface. The first surface of each second die has multiple die pads. Each second die has at least one conductive post penetrating both the first and second surfaces, allowing the first surface of each second die to be electrically connected to the second surface via the conductive post. Each second die is fabricated using a flip-chip technique, whereby the first surface of the second die is overlaid onto the third conductive line, such that each die pad of each second die is connected to... Each of the third conductive lines is electrically connected; wherein each of the second bare dies can be electrically connected to the first bare die in sequence via each of the die pads, each of the third conductive lines, each of the second conductive lines, each of the conductive pillars, each of the first conductive lines, and each of the die pads of the first bare die; wherein each of the second bare dies can be electrically connected to the outside via each of the die pads, each of the third conductive lines, each of the second conductive lines, each of the third conductive lines, and each of the first bonding pads located around the wafer region on the second surface of the first bare die. Connection; wherein each of the first bare dies can be electrically connected to the external environment sequentially via each of the die pads, each of the first conductive lines, each of the conductive pillars, each of the second conductive lines, each of the third conductive lines, and each of the first bonding pads surrounding the wafer region on the second surface of the first bare die, thereby forming the fan-out wafer-level package unit; wherein the manufacturing method of the fan-out wafer-level package unit includes the following steps: Step S1: providing a carrier board, wherein the carrier board has a first surface and an opposing second surface, wherein a carrier board dielectric is provided on the second surface of the carrier board. Layer; Step S2: Using the technique of first filling the grooves with metal paste and then grinding to form conductive lines, multiple first conductive lines are formed on the dielectric layer of the substrate. First, a first dielectric layer is laid on the second surface of the substrate. Then, multiple first grooves are formed horizontally on the first dielectric layer. After that, metal paste is filled into each of the first grooves, and the thickness of the metal paste is higher than the surface of the first dielectric layer. Finally, the metal paste that is higher than the surface of the first dielectric layer is ground so that the surface of the metal paste is flush with the surface of the first dielectric layer to form multiple first conductive lines.Step S3: A plurality of first dies, diced from at least one wafer, are spaced apart and disposed on the second surface of the carrier substrate. Each first die has a first surface and an opposite second surface. The first surface of each first die has a plurality of first wafer pads. The vertical wafer region of the second surface of each first die defines a wafer region. Each first die has at least one wafer conductive pillar penetrating the first surface and the second surface of the first die. Each first die is fabricated by flip-chip technology, whereby the first surface of the first die is deposited on each first conductive pillar. On the circuit, each pad of each first bare die is electrically connected to each first conductive line; Step S4: Using the technique of first filling the grooves with metal paste and then grinding to form conductive lines, multiple second conductive lines are formed on the second surface of each first bare die. First, a second dielectric layer is laid on the second surface of the substrate and on each first bare die, and the second dielectric layer covers the first bare die. Then, multiple second grooves and multiple through holes penetrating the second dielectric layer are formed horizontally on the second dielectric layer, so that each pad of each first bare die can be connected by each second groove. The groove is exposed to the outside, and each of the perforations is connected to each of the first grooves and each of the second grooves. Then, a conductive post is formed in each of the connected perforations, and then metal paste is filled into each of the second grooves, with the thickness of the metal paste being higher than the surface of the second dielectric layer. Finally, the metal paste that is higher than the surface of the second dielectric layer is ground so that the surface of the metal paste is flush with the surface of the second dielectric layer to form multiple second conductive lines; Step S5: Using the technique of filling the grooves with metal paste first and then grinding to form conductive lines, multiple third conductive lines are formed on the second dielectric layer: First in A third dielectric layer is laid on the second dielectric layer. Then, multiple openings are formed horizontally on the third dielectric layer. Metal paste is then filled into each opening, and the thickness of the metal paste is higher than the surface of the third dielectric layer. Finally, the metal paste that is higher than the surface of the third dielectric layer is polished so that the surface of the metal paste is flush with the surface of the third dielectric layer to form multiple third conductive lines. At least one of the openings is located around the wafer area on the second surface of each first bare die. Each third conductive line is exposed to the outside by each opening and a first solder pad is formed in each opening.Step S6: A plurality of second dies, diced from at least one wafer, are spaced apart on each of the third conductive lines. Each second die has a first surface and an opposing second surface. The first surface of each second die has a plurality of die pads. Each second die has at least one conductive post penetrating both the first and second surfaces. Each second die is flip-chip mounted on the first surface of each third conductive line using a flip-chip technique, such that each die pad of each second die is electrically connected to each third conductive line. Step S7: A dicing operation is performed to dice and form a plurality of fan-out wafer-level packaging units.

[0007] In a preferred embodiment of the present invention, the carrier is a silicon (Si) carrier, a glass carrier, or a ceramic carrier.

[0008] In a preferred embodiment of the present invention, the metal paste constituting each of the first conductive lines comprises silver paste, nano silver paste, copper paste or nano copper paste, wherein the metal paste constituting each of the second conductive lines comprises silver paste, nano silver paste, copper paste or nano copper paste, and wherein the metal paste constituting each of the third conductive lines comprises silver paste, nano silver paste, copper paste or nano copper paste.

[0009] In a preferred embodiment of the present invention, each of the openings is further provided with a solder ball, and each solder ball can be electrically connected to each of the first solder pads in the opening.

[0010] In a preferred embodiment of the present invention, the fan-out wafer-level packaging unit can be electrically connected to a printed circuit board (PCB) using each of the solder balls.

[0011] The present invention also provides a fan-out wafer-level packaging unit, which includes a carrier substrate, a first dielectric layer, multiple first conductive lines, at least one first die, a second dielectric layer, at least one conductive post, multiple second conductive lines, a third dielectric layer, multiple third conductive lines, and at least one second die; wherein the carrier substrate has a first surface and an opposite second surface, wherein a carrier substrate dielectric layer is disposed on the second surface of the carrier substrate, and wherein the carrier substrate further has at least one carrier substrate conductive post penetrating the carrier substrate dielectric layer, the first surface, and the second surface, wherein each carrier substrate conductive post is exposed to the outside of the carrier substrate to form a second bonding pad on the carrier substrate; wherein the first dielectric layer is disposed on the carrier substrate. On the dielectric layer of the substrate, the first dielectric layer has at least one first groove formed extending horizontally; each first conductive line is formed by filling the first groove with metal paste, and each first conductive line is electrically connected to each substrate conductive post; each first die is diced from a wafer, each first die has a first surface and an opposite second surface, the first surface of each first die has a plurality of first die pads, the vertical wafer region of the second surface of each first die defines a wafer region, and each first die has at least one wafer conductive post penetrating the first surface and the second surface of the first die, such that the first surface of each first die can... Each of the conductive pillars on the wafer is electrically connected to the second side of the first bare die, wherein each of the first bare dies is fabricated using a flip-chip technique, with its first side deposited on each of the first conductive lines, such that each pad of each of the first bare dies is electrically connected to each of the first conductive lines; wherein a second dielectric layer is disposed on the first dielectric layer and covers each of the first bare dies, the second dielectric layer having at least one second groove and at least one through-hole extending horizontally, each second groove communicating with each through-hole, and each through-hole communicating with each first groove; wherein each conductive pillar is formed in each through-hole and exposed to the outside through each through-hole, and each conductive pillar is connected to each of the first conductive lines. Electrical connection; wherein each of the second conductive lines is formed by filling the metal paste disposed in each of the second grooves, wherein each of the second conductive lines is electrically connected to each of the conductive pillars; wherein the third dielectric layer is disposed on the second dielectric layer and each of the second conductive lines, the third dielectric layer having at least one opening formed in a horizontal direction; wherein each of the third conductive lines is formed by filling the metal paste disposed in each opening, wherein at least one opening is located around the wafer region on the second surface of each of the first bare dies, wherein each of the third conductive lines is exposed to the outside through each opening and a first solder pad is formed in each opening, wherein each of the third conductive lines is electrically connected to each of the second conductive lines;Each of the second dies is diced from a wafer. Each second die has a first surface and an opposite second surface. The first surface of each second die has a plurality of die pads. Each second die has at least one wafer conductive post penetrating the first surface and the second surface, so that the first surface of each second die can be electrically connected to the second surface of the second die through each wafer conductive post. Each second die is fabricated using a flip-chip technique, whereby the first surface of the second die is deposited on each of the third conductive lines, such that each die pad of each second die is connected to each of the third conductive lines. The third conductive line is electrically connected; wherein each of the second bare crystals can be electrically connected to the first bare crystal in sequence via each of the crystal pads, each of the third conductive lines, each of the second conductive lines, each of the conductive pillars, each of the first conductive lines, and each of the crystal pads of the first bare crystal; wherein each of the second bare crystals can be electrically connected to the outside via each of the crystal pads, each of the third conductive lines, each of the second conductive lines, each of the third conductive lines, and each of the first bonding pads located around the wafer area on the second surface of each first bare crystal; wherein each of the second bare crystals can be electrically connected to the outside. The crystal energy is sequentially electrically connected to the external environment via each of the crystal pads, each of the third conductive lines, each of the second conductive lines, each of the conductive pillars, each of the first conductive lines, each of the carrier conductive pillars, and each of the second solder pads of the second bare crystal. Each first bare crystal can be electrically connected to the external environment sequentially via each of the crystal pads, each of the first conductive lines, each of the carrier conductive pillars, and each of the second solder pads of the first bare crystal. Each of the first bonding pads around the wafer region on the second surface of the first bare die is electrically connected to the outside to form the fan-out wafer-level package unit; wherein the manufacturing method of the fan-out wafer-level package unit includes the following steps: Step S1: providing a carrier board; wherein the carrier board has a first surface and an opposite second surface, wherein a carrier board dielectric layer is provided on the second surface of the carrier board, wherein the carrier board further has at least one carrier board conductive post penetrating the carrier board dielectric layer, the first surface and the second surface, wherein each carrier board conductive post is exposed to the outside by the carrier board and forms a second bonding pad on the carrier board;Step S2: Multiple first conductive lines are formed on the dielectric layer of the substrate using a technique of first filling the grooves with metal paste and then grinding to form the conductive lines. First, a first dielectric layer is laid on the second surface of the substrate. Then, multiple first grooves are formed horizontally on the first dielectric layer. Next, metal paste is filled into each of the first grooves, with the thickness of the metal paste exceeding the surface of the first dielectric layer. Finally, the metal paste exceeding the surface of the first dielectric layer is ground to make the surface of the metal paste flush with the surface of the first dielectric layer, thus forming multiple first conductive lines. First conductive line; Step S3: A plurality of first dies, diced from at least one wafer, are spaced apart on the second surface of the carrier board; wherein each first die has a first surface and an opposite second surface, the first surface of each first die has a plurality of first die pads, the vertical wafer region of the second surface of each first die defines a wafer region, wherein each first die has at least one wafer conductive pillar penetrating the first surface and the second surface of the first die, wherein each first die is made using flip-chip technology. The technique involves covering the first surface of the first bare die onto each of the first conductive lines, so that each pad of each first bare die is electrically connected to each of the first conductive lines; Step S4: Using a technique of first filling the grooves with metal paste and then grinding to form the conductive lines, multiple second conductive lines are formed on the second surface of each first bare die: First, a second dielectric layer is laid on the second surface of the substrate and on each first bare die, and the second dielectric layer covers each first bare die; then, multiple second grooves are formed horizontally on the second dielectric layer. The second dielectric layer is formed by a groove and multiple through holes that penetrate downwards, allowing each pad of each first bare die to be exposed to the outside through each second groove, and making each through hole connected to each first groove and each second groove. Then, a conductive pillar is formed in each of the connected through holes, and then metal paste is filled into each second groove, with the thickness of the metal paste being higher than the surface of the second dielectric layer. Finally, the metal paste that is higher than the surface of the second dielectric layer is ground so that the surface of the metal paste is flush with the surface of the second dielectric layer to form multiple second conductive lines.Step S5: Multiple third conductive lines are fabricated on the second dielectric layer using a technique of first filling the grooves with metal paste and then grinding to form the conductive lines. First, a third dielectric layer is laid on the second dielectric layer. Then, multiple openings are formed horizontally on the third dielectric layer. Next, metal paste is filled into each opening, with the thickness of the metal paste exceeding the surface of the third dielectric layer. Finally, the metal paste exceeding the surface of the third dielectric layer is ground to make the surface of the metal paste flush with the surface of the third dielectric layer, thus forming multiple third conductive lines. At least one opening is located around the wafer region on the second surface of each first bare die, and each third conductive line is exposed to the outside through each opening. Step S6: A first pad is formed in each of the openings; Step S7: A plurality of second dies, diced from at least one wafer, are spaced apart on each of the third conductive lines, wherein each second die has a first surface and an opposite second surface, the first surface of each second die has a plurality of pads, and each second die has at least one conductive post penetrating the first surface and the second surface of the second die, wherein the first surface of each second die is flip-chip deposited on each of the third conductive lines using flip-chip technology, so that each pad of each second die is electrically connected to each of the third conductive lines; and Step S8: A dicing operation is performed to dicing and form a plurality of fan-out wafer-level packaging units.

[0012] In another preferred embodiment of the present invention, the carrier is a silicon (Si) carrier, a glass carrier, or a ceramic carrier.

[0013] In another preferred embodiment of the present invention, the metal paste constituting each of the first conductive lines is silver paste, nano silver paste, copper paste or nano copper paste, wherein the metal paste constituting each of the second conductive lines is silver paste, nano silver paste, copper paste or nano copper paste, and wherein the metal paste constituting each of the third conductive lines is silver paste, nano silver paste, copper paste or nano copper paste.

[0014] In another preferred embodiment of the present invention, each of the second solder pads is further provided with a solder ball, and each solder ball can be electrically connected to each of the second solder pads.

[0015] In another preferred embodiment of the present invention, the fan-out wafer-level packaging unit can be electrically connected to a printed circuit board (PCB) using each of the solder balls. Attached Figure Description

[0016] Figure 1 This is a side cross-sectional plan view of an application embodiment of the fan-out wafer-level packaging unit of the present invention.

[0017] Figure 2This is a side view of the cross-section of the carrier plate according to the first embodiment of the present invention.

[0018] Figure 3 Is Figure 2 A side view of the cross-section of the first dielectric layer on the carrier plate.

[0019] Figure 4 Is Figure 3 A side view of the first groove filled with metal paste.

[0020] Figure 5 It is Figure 4 A side view of the cross-section of the metal paste used to form the first conductive line.

[0021] Figure 6 Is Figure 5 A side view of the first bare crystal on the first conductor line.

[0022] Figure 7 Is Figure 6 A side view of the cross-section of the first bare die with a second dielectric layer disposed thereon.

[0023] Figure 8 Is Figure 7 A side view of the conductive post with perforations.

[0024] Figure 9 Is Figure 8 A side view of the cross-section of the second groove filled with metal paste.

[0025] Figure 10 It is Figure 9 A side view of the cross-section of the metal paste used to form the second conductive line.

[0026] Figure 11 Is Figure 10 A side view of the cross-section of the second conductor in the circuit, showing the arrangement of the third dielectric layer.

[0027] Figure 12 Is Figure 11 A side view of the cross-section of the third groove filled with metal paste.

[0028] Figure 13 It is Figure 12 A side view of the cross-section of the metal paste used to form the third conductive line.

[0029] Figure 14 Is Figure 13 A side view of the cross-section of the second bare crystal on the third conductor line.

[0030] Figure 15 Is Figure 14 A side view of the cross-section of the first solder pad with solder balls.

[0031] Figure 16 This is a side cross-sectional schematic diagram of another application embodiment of the fan-out wafer-level packaging unit of the present invention.

[0032] Figure 17 This is a side view of the cross-section of the carrier plate according to the second embodiment of the present invention.

[0033] Figure 18 Is Figure 17 A side view of the cross-section of the first dielectric layer on the carrier plate.

[0034] Figure 19 Is Figure 18 A side view of the first groove filled with metal paste.

[0035] Figure 20 It is Figure 19 A side view of the cross-section of the metal paste used to form the first conductive line.

[0036] Figure 21 Is Figure 20 A side view of the first bare crystal on the first conductor line.

[0037] Figure 22 Is Figure 21 A side view of the cross-section of the first bare die with a second dielectric layer disposed thereon.

[0038] Figure 23 Is Figure 22 A side view of the conductive post with perforations.

[0039] Figure 24 Is Figure 23 A side view of the cross-section of the second groove filled with metal paste.

[0040] Figure 25 It is Figure 24 A side view of the cross-section of the metal paste used to form the second conductive line.

[0041] Figure 26 Is Figure 25 A side view of the cross-section of the second conductor in the circuit, showing the arrangement of the third dielectric layer.

[0042] Figure 27 Is Figure 26 A side view of the cross-section of the third groove filled with metal paste.

[0043] Figure 28 It is Figure 27 A side view of the cross-section of the metal paste used to form the third conductive line.

[0044] Figure 29 Is Figure 28 A side view of the cross-section of the second bare crystal on the third conductor line.

[0045] Figure 30 Is Figure 29 A side view of the cross-section of the first solder pad with solder balls.

[0046] Figure reference numerals: 1-Fan-out wafer-level packaging unit; 1a-Wafer region; 10-Carrier substrate; 11-First side; 12-Second side; 13-Carrier substrate dielectric layer; 14-Carrier substrate conductive pillar; 15-Second solder pad; 20-First dielectric layer; 21-First groove; 30-First conductive line; 30a-Metal paste; 40-First bare die; 41-First side; 42-Second side; 43-First die pad; 44-Wafer conductive pillar ; 50-Second dielectric layer; 51-Second groove; 52-Through hole; 60-Conductive pillar; 70-Second conductive line; 70a-Metal paste; 80-Third dielectric layer; 81-Opening; 90-Third conductive line; 90a-Metal paste; 91-First solder pad; 100-Second bare die; 101-First side; 102-Second side; 103-Die pad; 104-Chip conductive pillar; 110-Solder ball; 2-Printed circuit board. Detailed Implementation

[0047] The structure and technical features of the present invention are described in detail below with reference to the illustrations. The illustrations are only used to illustrate the structural relationships and related functions of the present invention. Therefore, the dimensions of the components in the illustrations are not drawn to actual scale and are not intended to limit the present invention.

[0048] refer to Figure 1 , Figure 15 , Figure 16 and Figure 30 This invention provides a fan-out wafer-level packaging unit 1, which includes a carrier 10, a first dielectric layer 20, multiple first conductive lines 30, at least one first die 40, a second dielectric layer 50, at least one conductive post 60, multiple second conductive lines 70, a third dielectric layer 80, multiple third conductive lines 90, and at least one second die 100. Depending on the type of the carrier 10 and the method of external electrical connection of the fan-out wafer-level packaging unit 1, this invention can be further divided into a first embodiment (e.g., Figure 1 and Figure 15 (as shown) and the second embodiment (as shown) Figure 16 and Figure 30 (as shown), but not limited to, and will be explained separately below.

[0049] like Figure 1 and Figure 15 The embodiment shown is the first embodiment of the fan-out wafer-level packaging unit 1 of the present invention.

[0050] The carrier plate 10 has a first surface 11 and an opposing second surface 12, wherein a carrier plate dielectric layer 13 is provided on the second surface 12 of the carrier plate, such as... Figure 2 As shown.

[0051] The first dielectric layer 20 is disposed on the carrier dielectric layer 13 of the carrier plate 10, and the first dielectric layer 20 has at least one first groove 21 formed in a horizontal direction, such as... Figure 3 As shown.

[0052] Each first conductive line 30 is formed by filling the first groove 21 with metal paste 30a, such as Figure 5 As shown.

[0053] Each first die 40 is cleaved from a wafer. Each first die 40 has a first surface 41 and an opposite second surface 42. The first surface 41 of each first die 40 has a plurality of first wafer pads 43. The vertical wafer region of the second surface 42 of each first die 40 is defined as a wafer region 1a. Figure 6 As shown; each first die 40 has at least one conductive post 44 penetrating the first surface 41 and the second surface 42 of the first die 40, such that the first surface 41 of each first die 40 can be electrically connected to the second surface 42 of the first die 40 through the conductive post 44, as shown. Figure 6 As shown; each first bare die 40 is fabricated by flip-chip technology, where the first surface 41 of the first bare die 40 is deposited on each first conductive line 30, so that each die pad 43 of each first bare die 40 is electrically connected to each first conductive line 30, as shown. Figure 6 As shown. In Figure 6 In the embodiments shown, each first bare die 40 has two conductive pillars 44 of the wafer, but this is not intended to limit the invention.

[0054] The second dielectric layer 50 is disposed on the first dielectric layer 20 and covers each first bare die 40. The second dielectric layer 50 has at least one second groove 51 and at least one through hole 52 formed in a horizontal direction. Each second groove 51 communicates with each through hole 52, and each through hole 52 communicates with each first groove 21. Figure 7 As shown.

[0055] Each conductive post 60 is formed in each through hole 52 and exposed to the outside through each through hole 52, such as Figure 8 As shown; each conductive post 60 is electrically connected to each first conductive line 30, as... Figure 8 As shown.

[0056] Each second conductive line 70 is formed by filling the second groove 51 with metal paste 70a, such as Figure 10 As shown; each of the second conductive lines 70 is electrically connected to each conductive post 60, as... Figure 10 As shown.

[0057] The third dielectric layer 80 is disposed on the second dielectric layer 50 and each of the second conductive lines 70. The third dielectric layer 80 has at least one opening 81 formed in a horizontal direction, such as... Figure 11 As shown.

[0058] Each third conductor 90 is constructed by filling each opening 81 with metal paste 90a, such as... Figure 13 As shown; at least one of the openings 81 is located around the wafer region 1a on the second surface 42 of each first bare die 40, such as Figure 14 As shown; each third conductive line 90 is exposed to the outside through each opening 81, and a first solder pad 91 is formed within each opening 81, as shown. Figure 14 As shown; each of the third conductors 90 is electrically connected to each of the second conductors 70, as... Figure 14 As shown. In Figure 13 In the embodiment shown, the fan-out wafer-level packaging unit 1 has three of the openings 81, but this is not intended to limit the invention.

[0059] Each second bare die 100 is cleaved from a wafer. Each second bare die 100 has a first surface 101 and an opposite second surface 102. The first surface 101 of each second bare die 100 has a plurality of die pads 103, such as... Figure 14 As shown; each second die 100 has at least one wafer conductive post 104 penetrating the first surface 101 and the second surface 102 of the second die 100, such that the first surface 101 of each second die 100 can be electrically connected to the second surface 102 of the second die 100 through the wafer conductive post 104, as shown. Figure 14 As shown; each second bare die 100 is fabricated by flip-chip technology, where the first surface 101 of the second bare die 100 is deposited on each third conductive line 90, so that each pad 103 of each second bare die 100 is electrically connected to each third conductive line 90, as shown. Figure 14 As shown. In Figure 29 In the embodiments shown, each second bare die 100 has two conductive pillars 104 of the wafer, but this is not intended to limit the scope of this invention.

[0060] Each second bare die 100 can be electrically connected to the first bare die 40 sequentially via each crystal pad 103 of the second bare die 100, each third conductive line 90, each second conductive line 70, each conductive pillar 60, each first conductive line 30, and each crystal pad of the first bare die 40, such as Figure 14 As shown.

[0061] Each second bare die 100 can be electrically connected to the external circuitry via each die pad 103, each third conductive line 90, each second conductive line 70, each third conductive line 90, and each first bonding pad 91 located around the wafer region 1a on the second surface 42 of each first bare die 40, such as... Figure 14 As shown.

[0062] Each first bare die 40 can be electrically connected to the outside via each die pad, each first conductive line 30, each conductive pillar 60, each second conductive line 70, each third conductive line 90, and each first bonding pad 91 located around the wafer region 1a on the second surface 42 of the first bare die 40, thereby forming the fan-out wafer-level package unit 1, such as Figure 14 As shown.

[0063] The manufacturing method of the fan-out wafer-level packaging unit 1 includes the following steps:

[0064] Step S1: Provide a carrier board 10, such as Figure 2 As shown; wherein the carrier plate 10 has a first surface 11 and an opposite second surface 12; wherein a carrier plate dielectric layer 13 is provided on the second surface 12 of the carrier plate 10, as shown. Figure 2 As shown.

[0065] Step S2: Using a technique of first filling the grooves with metal paste and then grinding to form conductive lines, multiple first conductive lines 30 are formed on the dielectric layer 13 of the carrier board 10: First, a first dielectric layer 20 is laid on the second surface 12 of the carrier board 10, such as... Figure 3 As shown, a plurality of first grooves 21 are then formed horizontally on the first dielectric layer 20. Metal paste 30a is then filled into each of the first grooves 21, and the thickness of the metal paste 30a is higher than the surface of the first dielectric layer 20. Figure 4 As shown, the metal paste 30a, which is higher than the surface of the first dielectric layer 20, is finally polished so that the surface of the metal paste 30a is flush with the surface of the first dielectric layer 20, thus forming multiple first conductive lines 30, as shown. Figure 5 As shown.

[0066] Step S3: A plurality of first dies 40, cleaved from at least one wafer, are spaced apart and disposed on the second surface 12 of the carrier substrate 10, such as... Figure 6As shown; each first die 40 has a first surface 41 and an opposite second surface 42. The first surface 41 of each first die 40 has a plurality of first wafer pads 43. The vertical wafer region of the second surface 42 of each first die 40 is defined as a wafer region 1a, as shown. Figure 6 As shown; wherein each first bare die 40 has at least one wafer conductive post 44 penetrating the first surface 41 and the second surface 42 of the first bare die 40, as... Figure 6 As shown; each first bare die 40 is fabricated by flip-chip technology, where the first surface 41 of the first bare die 40 is deposited on each first conductive line 30, so that each die pad 43 of each first bare die 40 is electrically connected to each first conductive line 30, as shown. Figure 6 As shown.

[0067] Step S4: Using a technique of first filling the grooves with metal paste and then grinding to form conductive lines, multiple second conductive lines 70 are formed on the second surface 42 of each first bare die 40: First, a second dielectric layer 50 is laid on the second surface 12 of the carrier board 10 and on each first bare die 40, and the second dielectric layer 50 covers each first bare die 40, such as... Figure 7 As shown, then, multiple second grooves 51 and multiple through holes 52 extending downward through the second dielectric layer 50 are formed horizontally on the second dielectric layer 50, so that each pad 43 of each first bare die 40 can be exposed to the outside through each second groove 51, and each through hole 52 is connected to each first groove 21 and each second groove 51, as shown. Figure 7 As shown, a conductive post 60 is first formed in each of the connected perforations 52, then... Figure 8 As shown, metal paste 70a is then filled into each of the second grooves 51, and the thickness of the metal paste 70a is higher than the surface of the second dielectric layer 50, as shown. Figure 9 As shown, the metal paste 70a above the surface of the second dielectric layer 50 is finally polished so that the surface of the metal paste 50 is flush with the surface of the second dielectric layer 50, thus forming multiple second conductive lines 70, as shown. Figure 10 As shown.

[0068] Step S5: Using a technique of first filling the grooves with metal paste and then grinding to form the conductive lines, multiple third conductive lines 90 are formed on the second dielectric layer 50: First, a third dielectric layer 80 is laid on the second dielectric layer 50, and then multiple openings 81 are formed horizontally on the third dielectric layer 80, such as... Figure 11 As shown, metal paste 90a is then filled into each opening 81, and the thickness of metal paste 90a is higher than the surface of the third dielectric layer 80, as shown. Figure 12As shown, the metal paste 90a, which is higher than the surface of the third dielectric layer 80, is finally polished so that the surface of the metal paste 90a is flush with the surface of the third dielectric layer 80, thus forming multiple third conductive lines 90, as shown. Figure 13 As shown; at least one of the openings 81 is located around the wafer region 1a on the second surface 42 of each first bare die 40, such as Figure 14 As shown; each third conductive line 90 is exposed to the outside through each opening 81, and a first solder pad 91 is formed within each opening 81, as shown. Figure 14 As shown.

[0069] Step S6: Multiple second bare dies 100, diced from at least one wafer, are spaced apart and disposed on each third conductive line 90, such as... Figure 14 As shown; each second die 100 has a first surface 101 and an opposite second surface 102, and the first surface 101 of each second die 100 has a plurality of crystal pads 103; each second die 100 has at least one wafer conductive pillar 104 penetrating the first surface 101 and the second surface 102 of the second die 100, as shown. Figure 14 As shown; each second bare die 100 is fabricated by flip-chip technology, where the first surface 101 of the second bare die 100 is deposited on each third conductive line 90, so that each pad 103 of each second bare die 100 is electrically connected to each third conductive line 90, as shown. Figure 14 As shown.

[0070] Step S7: Perform a dicing operation to divide and form multiple fan-out wafer-level packaging units 1, such as Figure 14 As shown.

[0071] The processes S2, S4, and S5 in the manufacturing method of the aforementioned fan-out wafer-level package 1 can be considered as key steps in fabricating the redistribution layer (RDL) of the fan-out wafer-level package 1. These steps utilize a technique of first filling the grooves with metal paste and then grinding to form conductive lines to create multiple conductive lines on the dielectric layer. Since steps S2, S4, and S5 are processes that are easy to implement precisely, the process is relatively simplified. This allows each first conductive line 30, each second conductive line 70, and each third conductive line 90 in the redistribution layer (RDL) to achieve XY plane electrical extension and interconnection, while also ensuring that the completed fan-out wafer-level package 1 maintains or achieves a certain degree of thinness and compactness.

[0072] refer to Figure 2The substrate 10 may include a silicon (Si) substrate, a glass substrate, or a ceramic substrate, but is not limited thereto, in order to facilitate diversified product development applications.

[0073] refer to Figure 5 The metal paste 30a constituting each first conductive line 30 may include silver paste, nano-silver paste, copper paste, or nano-copper paste, but is not limited thereto, to facilitate diversified product development and application. The nano-silver paste material has the characteristics of low cost, high conductivity, and low-temperature sintering capability, but since nano-silver paste material is a commonly used material, it will not be described in detail here.

[0074] refer to Figure 10 The metal paste 70a constituting each second conductive line 70 may include silver paste, nano silver paste, copper paste or nano copper paste, but is not limited thereto.

[0075] refer to Figure 13 The metal paste 90a constituting each third conductive line 90 may include silver paste, nano silver paste, copper paste or nano copper paste, but is not limited thereto.

[0076] refer to Figure 15 Each opening 81 is further provided with a solder ball 110, but it is not limited that each solder ball 110 can be electrically connected to each first solder pad 91 in each opening 81.

[0077] refer to Figure 1 The fan-out wafer-level packaging unit 1 can be electrically connected on a printed circuit board (PCB) 2 using each solder ball 110, but is not limited thereto.

[0078] like Figure 16 and Figure 30 The embodiment shown is a second embodiment of the fan-out wafer-level packaging unit 1 of the present invention.

[0079] The carrier plate 10 has a first surface 11 and an opposite second surface 12, such as Figure 17 As shown; wherein a carrier dielectric layer 13 is provided on the second surface 12 of the carrier plate, as... Figure 17 As shown; wherein the carrier plate 10 further has at least one carrier plate conductive post 14 penetrating the carrier plate 10 through the carrier plate dielectric layer 13, the first surface 11 and the second surface 12, as shown. Figure 17 As shown; each conductive post 14 on the carrier plate 10 is exposed to the outside by the first surface 11 of the carrier plate 10, forming a second solder pad 15 on the carrier plate 10, as shown. Figure 29 As shown.

[0080] The first dielectric layer 20 is disposed on the carrier dielectric layer 13 of the carrier plate 10, and the first dielectric layer 20 has at least one first groove 21 formed in a horizontal direction, such as... Figure 18 As shown.

[0081] Each first conductive line 30 is formed by filling the first groove 21 with metal paste 30a, such as Figure 20 As shown; each of the first conductive lines 30 is electrically connected to each carrier plate conductive post 14, such as... Figure 20 As shown.

[0082] Each first die 40 is cleaved from a wafer. Each first die 40 has a first surface 41 and an opposite second surface 42. The first surface 41 of each first die 40 has a plurality of first wafer pads 43. The vertical wafer region of the second surface 42 of each first die 40 is defined as a wafer region 1a. Figure 21 As shown; each first die 40 has at least one conductive post 44 penetrating the first surface 41 and the second surface 42 of the first die 40, such that the first surface 41 of each first die 40 can be electrically connected to the second surface 42 of the first die 40 through the conductive post 44, as shown. Figure 21 As shown; each first bare die 40 is fabricated by flip-chip technology, where the first surface 41 of the first bare die 40 is deposited on each first conductive line 30, so that each die pad 43 of each first bare die 40 is electrically connected to each first conductive line 30, as shown. Figure 21 As shown. In Figure 21 In the illustrated embodiment, each first bare die 40 has two conductive pillars 44 of the wafer, but this is not intended to limit the scope of the invention. Figure 21 In the embodiments shown, each first bare die 40 has two conductive pillars 44 of the wafer, but this is not intended to limit the scope of this invention.

[0083] The second dielectric layer 50 is disposed on the first dielectric layer 20 and covers each first bare die 40. The second dielectric layer 50 has at least one second groove 51 and at least one through hole 52 formed in a horizontal direction. Each second groove 51 communicates with each through hole 52, and each through hole 52 communicates with each first groove 21. Figure 22 As shown.

[0084] Each conductive post 60 is formed in each through hole 52 and exposed to the outside through each through hole 52, such as Figure 23 As shown; each conductive post 60 is electrically connected to each first conductive line 30, as... Figure 23 As shown.

[0085] Each second conductive line 70 is formed by filling the second groove 51 with metal paste 70a, such as Figure 25 As shown; each of the second conductive lines 70 is electrically connected to each conductive post 60, as... Figure 25 As shown.

[0086] The third dielectric layer 80 is disposed on the second dielectric layer 50 and each of the second conductive lines 70. The third dielectric layer 80 has at least one opening 81 formed in a horizontal direction, such as... Figure 26 As shown.

[0087] Each third conductor 90 is constructed by filling each opening 81 with metal paste 90a, such as... Figure 28 As shown; at least one of the openings 81 is located around the wafer region 1a on the second surface 42 of each first bare die 40, such as Figure 29 As shown; each third conductive line 90 is exposed to the outside through each opening 81, and a first solder pad 91 is formed within each opening 81, as shown. Figure 29 As shown; each of the third conductors 90 is electrically connected to each of the second conductors 70, as... Figure 29 As shown. In Figure 28 In the embodiment shown, the fan-out wafer-level packaging unit 1 has three openings 81, but this is not intended to limit the scope of this invention.

[0088] Each second bare die 100 is cleaved from a wafer. Each second bare die 100 has a first surface 101 and an opposite second surface 102. The first surface 101 of each second bare die 100 has a plurality of die pads 103, such as... Figure 29 As shown; each second die 100 has at least one wafer conductive post 104 penetrating the first surface 101 and the second surface 102 of the second die 100, such that the first surface 101 of each second die 100 can be electrically connected to the second surface 102 of the second die 100 by each wafer conductive post 104, as shown. Figure 29 As shown; each second bare die 100 is fabricated by flip-chip technology, where the first surface 101 of the second bare die 100 is deposited on each third conductive line 90, so that each pad 103 of each second bare die 100 is electrically connected to each third conductive line 90, as shown. Figure 29 As shown. In Figure 29 In the embodiments shown, each second bare die 100 has two conductive pillars 104 of the wafer, but this is not intended to limit the scope of this invention.

[0089] Each second bare die 100 can be electrically connected to each first bare die 40 sequentially via each die pad 103 of the second bare die 100, each third conductive line 90, each second conductive line 70, each conductive pillar 60, each first conductive line 30, and each die pad 43 of each first bare die 40, such as Figure 29 As shown.

[0090] Each second bare die 100 can be electrically connected to the external circuitry via each die pad 103, each third conductive line 90, each second conductive line 70, each third conductive line 90, and each first bonding pad 91 located around the wafer region 1a on the second surface 42 of each first bare die 40, such as... Figure 29 As shown.

[0091] Each second bare die 100 can be sequentially electrically connected to the external circuit via each die pad 103, each third conductive line 90, each second conductive line 70, each conductive post 60, each first conductive line 30, each carrier board conductive post 14, and each second solder pad 15, such as... Figure 29 As shown.

[0092] Each first bare die 40 can be sequentially connected to the external power via each die pad of the first bare die 40, each first conductive line 30, each carrier conductive post 14, and each second solder pad 15, such as Figure 29 As shown.

[0093] Each first bare die 40 can be electrically connected to the outside via each die pad, each first conductive line 30, each conductive pillar 60, each second conductive line 70, each third conductive line 90, and each first bonding pad 91 located around the wafer region 1a on the second surface 42 of the first bare die 40, thereby forming the fan-out wafer-level package unit 1, such as Figure 29 As shown.

[0094] The manufacturing method of the fan-out wafer-level packaging unit 1 includes the following steps:

[0095] Step S1: Provide a carrier board 10, such as Figure 17 As shown; wherein the carrier plate 10 has a first surface 11 and an opposite second surface 12, as Figure 17 As shown; wherein a carrier dielectric layer 13 is provided on the second surface 12 of the carrier plate, as... Figure 17 As shown; wherein the carrier plate 10 further has at least one carrier plate conductive post 14 penetrating the carrier plate 10 through the carrier plate dielectric layer 13, the first surface 11 and the second surface 12, as shown. Figure 17 As shown; each conductive post 14 on the carrier plate is exposed to the outside by the carrier plate 10, and a second solder pad 15 is formed on the carrier plate 10, as shown. Figure 17 As shown.

[0096] Step S2: Using a technique of first filling the grooves with metal paste and then grinding to form conductive lines, multiple first conductive lines 30 are formed on the dielectric layer 13 of the carrier board 10: First, a first dielectric layer 20 is laid on the second surface 12 of the carrier board 10, and then multiple first grooves 21 are formed horizontally on the first dielectric layer 20, such as... Figure 18As shown, metal paste 30a is then filled into each of the first grooves 21, and the thickness of the metal paste 30a is higher than the surface of the first dielectric layer 20, as shown. Figure 19 As shown, the metal paste 30a, which is higher than the surface of the first dielectric layer 20, is finally polished so that the surface of the metal paste 30a is flush with the surface of the first dielectric layer 20, thus forming multiple first conductive lines 30, as shown. Figure 20 As shown.

[0097] Step S3: A plurality of first dies 40, cleaved from at least one wafer, are spaced apart and disposed on the second surface 12 of the carrier substrate 10, such as... Figure 21 As shown; each first die 40 has a first surface 41 and an opposite second surface 42. The first surface 41 of each first die 40 has a plurality of first wafer pads 43. The vertical wafer region of the second surface 42 of each first die 40 is defined as a wafer region 1a, as shown. Figure 21 As shown; wherein each first bare die 40 has at least one wafer conductive post 44 penetrating the first surface 41 and the second surface 42 of the first bare die 40, as... Figure 21 As shown; each first bare die 40 is fabricated by flip-chip technology, where the first surface 41 of the first bare die 40 is deposited on each first conductive line 30, so that each die pad 43 of each first bare die 40 is electrically connected to each first conductive line 30, as shown. Figure 21 As shown.

[0098] Step S4: Using a technique of first filling the grooves with metal paste and then grinding to form conductive lines, multiple second conductive lines 70 are formed on the second surface 42 of each first bare die 40: First, a second dielectric layer 50 is laid on the second surface 12 of the carrier board 10 and on each first bare die 40, and the second dielectric layer 50 covers each first bare die 40, such as... Figure 22 As shown, then, multiple second grooves 51 and multiple through holes 52 extending downward through the second dielectric layer 50 are formed horizontally on the second dielectric layer 50, so that each pad 43 of each first bare die 40 can be exposed to the outside through each second groove 51, and each through hole 52 is connected to each first groove 21 and each second groove 51, as shown. Figure 22 As shown, a conductive post 60 is first formed in each of the connected perforations 52, then... Figure 23 As shown, metal paste 70a is then filled into each of the second grooves 51, and the thickness of the metal paste 70a is higher than the surface of the second dielectric layer 50, as shown. Figure 24 As shown, the metal paste 70a above the surface of the second dielectric layer 50 is finally polished so that the surface of the metal paste 50 is flush with the surface of the second dielectric layer 50, thus forming multiple second conductive lines 70, as shown. Figure 25 As shown.

[0099] Step S5: Using a technique of first filling the grooves with metal paste and then grinding to form the conductive lines, multiple third conductive lines 90 are formed on the second dielectric layer 50: First, a third dielectric layer 80 is laid on the second dielectric layer 50, and then multiple openings 81 are formed horizontally on the third dielectric layer 80, such as... Figure 26 As shown, metal paste 90a is then filled into each opening 81, and the thickness of metal paste 90a is higher than the surface of the third dielectric layer 80, as shown. Figure 27 As shown, the metal paste 90a, which is higher than the surface of the third dielectric layer 80, is finally polished so that the surface of the metal paste 90a is flush with the surface of the third dielectric layer 80, thus forming multiple third conductive lines 90, as shown. Figure 28 As shown; at least one of the openings 81 is located around the wafer region 1a on the second surface 42 of each first bare die 40, such as Figure 29 As shown; each third conductive line 90 is exposed to the outside through each opening 81, and a first solder pad 91 is formed within each opening 81, as shown. Figure 29 As shown.

[0100] Step S6: Multiple second bare dies 100, diced from at least one wafer, are spaced apart and disposed on each third conductive line 90, such as... Figure 29 As shown; each of the second bare crystals 100 has a first surface 101 and an opposite second surface 102, and each of the second bare crystals 100 has a plurality of crystal pads 103 on the first surface 101, such as Figure 29 As shown; wherein each second bare die 100 has at least one wafer conductive post 104 penetrating the first surface 101 and the second surface 102 of each second bare die 100, as... Figure 29 As shown; each second bare die 100 is fabricated by flip-chip technology, where the first surface 101 of the second bare die 100 is deposited on each third conductive line 90, so that each pad 103 of each second bare die 100 is electrically connected to each third conductive line 90, as shown. Figure 29 As shown.

[0101] Step S7: Perform a dicing operation to divide and form multiple fan-out wafer-level packaging units 1, such as Figure 29 As shown.

[0102] The processes S2, S4, and S5 in the manufacturing method of the aforementioned fan-out wafer-level package 1 can be considered as key steps in fabricating the redistribution layer (RDL) of the fan-out wafer-level package 1. These steps utilize a technique of first filling the grooves with metal paste and then grinding to form conductive lines to create multiple conductive lines on the dielectric layer. Since steps S2, S4, and S5 are processes that are easy to implement precisely, the process is relatively simplified. This allows each first conductive line 30, each second conductive line 70, and each third conductive line 90 in the redistribution layer (RDL) to achieve XY plane electrical extension and interconnection, while also ensuring that the completed fan-out wafer-level package 1 maintains or achieves a certain degree of thinness and compactness.

[0103] refer to Figure 17 The substrate 10 may include a silicon (Si) substrate, a glass substrate, or a ceramic substrate, but is not limited thereto, in order to facilitate diversified product development applications.

[0104] refer to Figure 19 The metal paste 30a constituting each first conductive line 30 may include silver paste, nano silver paste, copper paste or nano copper paste, but is not limited to, so as to facilitate diversified product development and application.

[0105] refer to Figure 24 The metal paste 70a constituting each second conductive line 70 may include silver paste, nano silver paste, copper paste or nano copper paste, but is not limited thereto.

[0106] refer to Figure 27 The metal paste 90a constituting each third conductive line 90 may include silver paste, nano silver paste, copper paste or nano copper paste, but is not limited thereto.

[0107] refer to Figure 30 Each opening 81 is further provided with a solder ball 110, but it is not limited that each solder ball 110 can be electrically connected to each first solder pad 91 in each opening 81.

[0108] refer to Figure 16 The fan-out wafer-level packaging unit 1 can be electrically connected on a printed circuit board (PCB) 2 using each solder ball 110, but is not limited thereto.

[0109] Compared with existing fan-out wafer-level packaging technology, the fan-out wafer-level packaging unit 1 of the present invention has the following advantages:

[0110] (1) The fan-out wafer-level packaging unit 1 manufactured by the manufacturing process of steps S2, S4 and S5 in the manufacturing method of the present invention, compared with the existing related manufacturing technology of fan-out wafer-level packaging units, the fan-out wafer-level packaging unit 1 of the present invention can maintain or achieve a certain degree of thinness and small size by making each conductive line in the RDL so that each conductive line in the RDL can generate XY plane electrical extension and interconnection effect. These are all simplified and easy to implement precisely, which is especially beneficial to reduce the thickness of the packaging unit. Therefore, the process of the present invention is not only simpler and saves costs, but also effectively improves the efficiency and reliability of the fan-out wafer-level packaging unit 1.

[0111] (2) The manufacturing process of the present invention in steps S2, S4 and S5 all utilizes the technique of first filling the groove with metal paste and then grinding to form the conductive lines to form multiple conductive lines on the dielectric layer, instead of using existing chemical plating or electroplating techniques, which reduces the cost and pollution generated by the process. Therefore, the present invention can effectively solve the problem that existing fan-out packaging technology is prone to high manufacturing costs and is not conducive to environmental protection when making each conductive line.

[0112] (3) Each of the second bare crystals 100 of the present invention can be electrically connected to each of the first bare crystals 40, such as Figure 29 As shown; wherein each second die 100 can be electrically connected to the external circuit via each first pad 91 located around the wafer region 1a on the second surface 42 of each first die 40, such as Figure 29 As shown; each of the second bare dies 100 can be electrically connected to the outside via each of the second bonding pads 15, such as Figure 29 As shown; each of the first bare die 40 can be electrically connected to the outside via each of the second bonding pads 15, such as Figure 29 As shown; each first bare die 40 can be electrically connected to the outside via each first bonding pad 91 located around the wafer region 1a on the second surface 42 of the first bare die 40, thereby forming the fan-out wafer-level package unit 1, as shown. Figure 29 As shown, this enables electrical connections between the bare dies inside the packaging unit and the external bare dies, either to the outside or to the inside, thereby increasing the number of bare dies to provide products with higher performance or more functions, and increasing the product's market competitiveness.

[0113] (4) Each first die 40 of the present invention has at least one wafer conductive post 44 penetrating the first surface 41 and the second surface 42 of the first die 40, so that the first surface 41 of each first die 40 can be electrically connected to the second surface 42 of each first die 40 through the wafer conductive post 44; wherein each second die 100 has at least one wafer conductive post 104 penetrating the first surface 101 and the second surface 102 of the second die 100, so that the first surface 101 of each second die 100 can be electrically connected to the second surface 102 of each second die 100 through the wafer conductive post 104, thereby increasing the diversity of external electrical connections of the product and increasing the market competitiveness of the product.

[0114] The above are merely preferred embodiments of the present invention and are illustrative rather than restrictive. Those skilled in the art will understand that many changes, modifications, and even equivalent alterations can be made within the spirit and scope defined by the claims of the present invention, but all such changes will fall within the protection scope of the present invention.

Claims

1. A fan-out wafer-level packaging unit, characterized in that, Include: A carrier plate having a first side and an opposite second side; wherein a carrier plate dielectric layer is provided on the second side of the carrier plate; A first dielectric layer is disposed on the substrate dielectric layer of the substrate, the first dielectric layer having at least one first groove formed in a horizontal direction. Multiple first conductive lines, each of which is composed of metal paste filled in each of the first grooves; At least one first bare die, each first bare die being diced from a wafer, each first bare die having a first surface and an opposite second surface, each first bare die having a plurality of first die pads on the first surface, and the vertical wafer region of the second surface of each first bare die defining a wafer region; wherein each first bare die has at least one wafer conductive pillar penetrating the first surface and the second surface of the first bare die, such that the first surface of each first bare die can be electrically connected to the second surface of the first bare die through each wafer conductive pillar; wherein each first bare die is fabricated on each first conductive line using a flip-chip technique, such that each die pad of each first bare die is electrically connected to each first conductive line; A second dielectric layer is disposed on the first dielectric layer and covers each of the first bare crystals. The second dielectric layer has at least one second groove and at least one through hole formed in a horizontal direction. Each of the second grooves communicates with each of the through holes, and each of the through holes communicates with each of the first grooves. At least one conductive post, each of which is formed in each of the through holes and exposed to the outside through each of the through holes; wherein each of the conductive posts is electrically connected to each of the first conductive lines; Multiple second conductive lines, each of which is composed of metal paste filled in each of the second grooves; wherein each of the second conductive lines is electrically connected to each of the conductive posts; A third dielectric layer is disposed on the second dielectric layer and each of the second conductive lines, the third dielectric layer having at least one opening formed in a horizontal direction; Multiple third conductive lines, each third conductive line being formed by filling each opening with metal paste; wherein at least one opening is located around the wafer region on the second surface of each first bare die; wherein each third conductive line is exposed to the outside through each opening and a first solder pad is formed within each opening; wherein each third conductive line is electrically connected to each second conductive line; and At least one second bare die, each second bare die being diced from a wafer, each second bare die having a first side and an opposite second side, the first side of each second bare die having a plurality of die pads; wherein each second bare die has at least one wafer conductive pillar penetrating the first side and the second side of the second bare die, such that the first side of each second bare die can be electrically connected to the second side of the second bare die through each wafer conductive pillar; wherein each second bare die is fabricated on each third conductive line using a flip-chip technique, such that each die pad of each second bare die is electrically connected to each third conductive line; Each of the second bare dies can be electrically connected to the first bare die via each of the second bare die's pads, each of the third conductive lines, each of the second conductive lines, each of the conductive pillars, each of the first conductive lines, and each of the first bare die's pads in sequence: Each of the second bare dies can be electrically connected to the outside via each of the die pads, each of the third conductive lines, each of the second conductive lines, each of the third conductive lines and each of the first bonding pads located around the wafer region on the second surface of each first bare die. Each of the first bare dies can be electrically connected to the outside via each of the first die pads, each of the first conductive lines, each of the conductive pillars, each of the second conductive lines, each of the third conductive lines, and each of the first bonding pads surrounding the wafer area on the second surface of the first bare die, thereby forming the fan-out wafer-level packaging unit. The manufacturing method of this fan-out wafer-level packaging unit includes the following steps: Step S1: Provide a carrier board; wherein the carrier board has a first side and an opposite second side; wherein a carrier board dielectric layer is provided on the second side of the carrier board; Step S2: Using the technique of filling the grooves with metal paste and then grinding to form the conductive lines, multiple first conductive lines are formed on the dielectric layer of the substrate: First, a first dielectric layer is laid on the second surface of the substrate. Then, multiple first grooves are formed horizontally on the first dielectric layer. Next, metal paste is filled into each of the first grooves, and the thickness of the metal paste is higher than the surface of the first dielectric layer. Finally, the metal paste that is higher than the surface of the first dielectric layer is ground so that the surface of the metal paste is flush with the surface of the first dielectric layer to form multiple first conductive lines. Step S3: A plurality of first bare dies, cleaved from at least one wafer, are spaced apart on the second surface of the carrier; wherein each first bare die has a first surface and an opposite second surface, the first surface of each first bare die has a plurality of first die pads, and the vertical wafer region of the second surface of each first bare die is defined as a wafer region; wherein each first bare die has at least one wafer conductive pillar penetrating the first surface and the second surface of the first bare die; wherein each first bare die is fabricated on each first conductive line using a flip-chip technique, such that each die pad of each first bare die is electrically connected to each first conductive line; Step S4: Using the technique of filling the grooves with metal paste and then grinding to form conductive lines, multiple second conductive lines are formed on the second surface of each first bare die: First, a second dielectric layer is laid on the second surface of the substrate and on each first bare die, and the second dielectric layer covers each first bare die. Then, multiple second grooves and multiple through holes penetrating the second dielectric layer are formed horizontally on the second dielectric layer, so that each die pad of each first bare die can be exposed to the outside through each second groove, and each through hole is connected to each first groove and each second groove. After forming a conductive pillar in each connected through hole, metal paste is filled into each second groove, and the thickness of the metal paste is higher than the surface of the second dielectric layer. Finally, the metal paste higher than the surface of the second dielectric layer is ground so that the surface of the metal paste is flush with the surface of the second dielectric layer to form multiple second conductive lines. Step S5: Using a technique of first filling the groove with metal paste and then grinding to form the conductive lines, multiple third conductive lines are formed on the second dielectric layer: First, a third dielectric layer is laid on the second dielectric layer. Then, multiple openings are formed horizontally on the third dielectric layer. Next, metal paste is filled into each of the openings, and the thickness of the metal paste is higher than the surface of the third dielectric layer. Finally, the metal paste that is higher than the surface of the third dielectric layer is ground so that the surface of the metal paste is flush with the surface of the third dielectric layer to form multiple third conductive lines. At least one of the openings is located around the wafer area on the second surface of each first bare die. Each third conductive line is exposed to the outside by each opening, and a first bonding pad is formed in the opening. Step S6: A plurality of second bare dies, cleaved from at least one wafer, are spaced apart on each of the third conductive lines; wherein each of the second bare dies has a first surface and an opposite second surface, and the first surface of each of the second bare dies has a plurality of die pads; wherein each of the second bare dies has at least one wafer conductive pillar penetrating the first surface and the second surface of the second bare dies; wherein each of the second bare dies is flip-chip fabricated on each of the third conductive lines using a flip-chip technique, such that each die pad of each of the second bare dies is electrically connected to each of the third conductive lines; and Step S7: Perform a dicing operation to divide the wafer into multiple fan-out wafer-level packaging units.

2. The fan-out wafer-level packaging unit as described in claim 1, characterized in that, The carrier can be a silicon carrier, a glass carrier, or a ceramic carrier.

3. The fan-out wafer-level packaging unit as described in claim 1, characterized in that, The metal paste constituting each of the first conductive lines is silver paste, nano silver paste, copper paste, or nano copper paste; the metal paste constituting each of the second conductive lines is silver paste, nano silver paste, copper paste, or nano copper paste; and the metal paste constituting each of the third conductive lines is silver paste, nano silver paste, copper paste, or nano copper paste.

4. The fan-out wafer-level packaging unit as described in claim 1, characterized in that, Each opening is further provided with a solder ball, and each solder ball can be electrically connected to each of the first solder pads in each opening.

5. The fan-out wafer-level packaging unit as described in claim 4, characterized in that, The fan-out wafer-level packaging unit can be electrically connected on a printed circuit board using each of the solder balls.

6. A fan-out wafer-level packaging unit, characterized in that, Include: A carrier board has a first side and an opposite second side; wherein a carrier board dielectric layer is provided on the second side of the carrier board; wherein the carrier board also has at least one carrier board conductive post penetrating the carrier board dielectric layer, the first side and the second side; wherein each carrier board conductive post is exposed to the outside of the carrier board to form a second solder pad on the carrier board. A first dielectric layer is disposed on the substrate dielectric layer of the substrate, the first dielectric layer having at least one first groove formed in a horizontal direction. Multiple first conductive lines, each of which is composed of metal paste filled in each of the first grooves; wherein each of the first conductive lines is electrically connected to each of the conductive posts of the carrier plate. At least one first bare die, each first bare die being diced from a wafer, each first bare die having a first surface and an opposite second surface, each first bare die having a plurality of first die pads on the first surface, and the vertical wafer region of the second surface of each first bare die defining a wafer region; wherein each first bare die has at least one wafer conductive pillar penetrating the first surface and the second surface of the first bare die, such that the first surface of each first bare die can be electrically connected to the second surface of the first bare die through each wafer conductive pillar; wherein each first bare die is fabricated on each first conductive line using a flip-chip technique, such that each die pad of each first bare die is electrically connected to each first conductive line; A second dielectric layer is disposed on the first dielectric layer and covers each of the first bare crystals. The second dielectric layer has at least one second groove and at least one through hole formed in a horizontal direction. Each of the second grooves communicates with each of the through holes, and each of the through holes communicates with each of the first grooves. At least one conductive post, each of which is formed in each of the through holes and exposed to the outside through each of the through holes; wherein each of the conductive posts is electrically connected to each of the first conductive lines; Multiple second conductive lines, each of which is composed of metal paste filled in each of the second grooves; wherein each of the second conductive lines is electrically connected to each of the conductive posts; A third dielectric layer is disposed on the second dielectric layer and each of the second conductive lines, the third dielectric layer having at least one opening formed in a horizontal direction; Multiple third conductive lines, each third conductive line being formed by filling each opening with metal paste; wherein at least one opening is located around the wafer region on the second surface of each first bare die; wherein each third conductive line is exposed to the outside through each opening and a first solder pad is formed within each opening; wherein each third conductive line is electrically connected to each second conductive line; and At least one second bare die, each second bare die being diced from a wafer, each second bare die having a first side and an opposite second side, the first side of each second bare die having a plurality of die pads; wherein each second bare die has at least one wafer conductive pillar penetrating the first side and the second side of the second bare die, such that the first side of each second bare die can be electrically connected to the second side of the second bare die through each wafer conductive pillar; wherein each second bare die is fabricated on each third conductive line using a flip-chip technique, such that each die pad of each second bare die is electrically connected to each third conductive line; Each of the second bare crystals can be electrically connected to the first bare crystal via each of the second bare crystal pads, each of the third conductive lines, each of the second conductive lines, each of the conductive pillars, each of the first conductive lines, and each of the first bare crystal pads in sequence. Each of the second bare dies can be electrically connected to the outside via each of the die pads, each of the third conductive lines, each of the second conductive lines, each of the third conductive lines and each of the first bonding pads located around the wafer region on the second surface of each first bare die. Each of the second bare dies can be electrically connected to the external environment sequentially via each of the die pads, each of the third conductive lines, each of the second conductive lines, each of the conductive pillars, each of the first conductive lines, each of the carrier conductive pillars, and each of the second solder pads: Each of the first bare die can be electrically connected to the outside via each of the first bare die pads, each of the first conductive lines, each of the carrier conductive pillars and each of the second solder pads in sequence: Each of the first bare dies can be electrically connected to the outside via each of the first die pads, each of the first conductive lines, each of the conductive pillars, each of the second conductive lines, each of the third conductive lines, and each of the first bonding pads surrounding the wafer area on the second surface of the first bare die, thereby forming the fan-out wafer-level packaging unit. The manufacturing method of this fan-out wafer-level packaging unit includes the following steps: Step S1: Provide a carrier board; wherein the carrier board has a first side and an opposite second side; wherein a carrier board dielectric layer is provided on the second side of the carrier board; wherein the carrier board also has at least one carrier board conductive post penetrating the carrier board dielectric layer, the first side and the second side; wherein each carrier board conductive post is exposed to the outside of the carrier board to form a second solder pad on the carrier board; Step S2: Using the technique of filling the grooves with metal paste and then grinding to form the conductive lines, multiple first conductive lines are formed on the dielectric layer of the substrate: First, a first dielectric layer is laid on the second surface of the substrate. Then, multiple first grooves are formed horizontally on the first dielectric layer. Next, metal paste is filled into each of the first grooves, and the thickness of the metal paste is higher than the surface of the first dielectric layer. Finally, the metal paste that is higher than the surface of the first dielectric layer is ground so that the surface of the metal paste is flush with the surface of the first dielectric layer to form multiple first conductive lines. Step S3: A plurality of first bare dies, cleaved from at least one wafer, are spaced apart on the second surface of the carrier; wherein each first bare die has a first surface and an opposite second surface, the first surface of each first bare die has a plurality of first die pads, and the vertical wafer region of the second surface of each first bare die is defined as a wafer region; wherein each first bare die has at least one wafer conductive pillar penetrating the first surface and the second surface of the first bare die; wherein each first bare die is fabricated on each first conductive line using a flip-chip technique, such that each die pad of each first bare die is electrically connected to each first conductive line; Step S4: Using the technique of filling the grooves with metal paste and then grinding to form conductive lines, multiple second conductive lines are formed on the second surface of each first bare die: First, a second dielectric layer is laid on the second surface of the substrate and on each first bare die, and the second dielectric layer covers the first bare die. Then, multiple second grooves and multiple through holes penetrating the second dielectric layer are formed horizontally on the second dielectric layer, so that each die pad of the first bare die can be exposed to the outside through each second groove, and each through hole is connected to each first groove and each second groove. After forming a conductive post in each connected through hole, metal paste is filled into each second groove, and the thickness of the metal paste is higher than the surface of the second dielectric layer. Finally, the metal paste higher than the surface of the second dielectric layer is ground so that the surface of the metal paste is flush with the surface of the second dielectric layer to form multiple second conductive lines. Step S5: Using a technique of first filling the groove with metal paste and then grinding to form the conductive lines, multiple third conductive lines are formed on the second dielectric layer: First, a third dielectric layer is laid on the second dielectric layer. Then, multiple openings are formed horizontally on the third dielectric layer. Next, metal paste is filled into each of the openings, and the thickness of the metal paste is higher than the surface of the third dielectric layer. Finally, the metal paste that is higher than the surface of the third dielectric layer is ground so that the surface of the metal paste is flush with the surface of the third dielectric layer to form multiple third conductive lines. At least one of the openings is located around the wafer area on the second surface of each first bare die. Each third conductive line is exposed to the outside by each opening, and a first bonding pad is formed in each opening. Step S6: A plurality of second bare dies cleaved from at least one wafer are spaced apart on each of the third conductive lines; wherein each of the second bare dies has a first surface and an opposite second surface, and the first surface of each of the second bare dies has a plurality of die pads; wherein each of the second bare dies has at least one wafer conductive pillar penetrating the first surface and the second surface of the second bare dies; wherein each of the second bare dies is flip-chip fabricated on each of the third conductive lines using a flip-chip technique, such that each die pad of the second bare dies is electrically connected to each of the third conductive lines; and Step S7: Perform a dicing operation to divide the wafer into multiple fan-out wafer-level packaging units.

7. The fan-out wafer-level packaging unit as described in claim 6, characterized in that, The carrier can be a silicon carrier, a glass carrier, or a ceramic carrier.

8. The fan-out wafer-level packaging unit as described in claim 6, characterized in that, The metal paste constituting each of the first conductive lines is silver paste, nano silver paste, copper paste, or nano copper paste; the metal paste constituting each of the second conductive lines is silver paste, nano silver paste, copper paste, or nano copper paste; and the metal paste constituting each of the third conductive lines is silver paste, nano silver paste, copper paste, or nano copper paste.

9. The fan-out wafer-level packaging unit as described in claim 6, characterized in that, Each of the second solder pads is further provided with a solder ball, and each solder ball can be electrically connected to each of the second solder pads.

10. The fan-out wafer-level packaging unit as described in claim 9, characterized in that, The fan-out wafer-level packaging unit can be electrically connected on a printed circuit board using each of the solder balls.

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