Semiconductor device including semiconductor transistor die and clip for connecting pads of semiconductor transistor die
By designing drain clamp shapes with reduced width, such as "I", "Z", "8" or "Ω", the die tilting problem during GaN transistor die connection is solved, improving the stability and reliability of semiconductor devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- INFINEON TECH AUSTRIA AG
- Filing Date
- 2025-10-09
- Publication Date
- 2026-04-17
AI Technical Summary
In the prior art, undesirable die tilting problems can easily occur when connecting the contact pads of GaN transistor dies, especially due to uneven bonding line thickness caused by the weight difference of the drain clamp.
Design a semiconductor device that employs a drain clamp with a narrower width in the middle section of the second clamp than the second section, thereby reducing the overall weight of the clamp. By using an improved clamp shape, such as the letter "I", "Z", "8" or "Ω", the contact pressure of the drain clamp on the die can be reduced, thus preventing the die from tilting.
It effectively reduces the gravity difference between the drain clamp and the die, avoids or reduces die tilting, and improves the stability and reliability of semiconductor devices.
Smart Images
Figure CN121889003A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to semiconductor devices. Background Technology
[0002] Power semiconductor transistors can be electrically connected together to form circuits typically housed in a common package. A specific example is a semiconductor transistor device in which two GaN transistor dies are connected in parallel. To connect the contact pads of the GaN transistor dies, electrical clamps are typically used to avoid the high cost of copper wire bonding. Due to the weight of the drain and source clamps, problems such as undesirable die tilting can occur.
[0003] This disclosure is necessary for these and other reasons. Summary of the Invention
[0004] One aspect of this disclosure relates to a semiconductor device comprising: a lead frame including a die pad, a first lead, and a second lead, wherein the second lead is connected to a lead post; a first lateral transistor die including a first pad, a second pad, and a third pad; a first clamp configured to connect the first pad to the die pad, the die pad being connected to the first lead; and a second clamp configured to connect a second pad to a lead post of the second lead, wherein the lead post is disconnected from the die pad, wherein the second clamp includes a first segment contacting the second pad of the first lateral transistor die, a second segment contacting the lead post of the second lead, and an intermediate segment between the first segment and the second segment, wherein the intermediate segment has a width partially smaller than that of the second segment.
[0005] The feature that the middle section of the second clamp has a width smaller than that of the second section can be provided by different shapes of the second clamp. In one of these shapes, the second clamp includes the shape of the letter "I". In another of these shapes, the second clamp includes the shape of the letter "Z". In yet another of these shapes, the second clamp includes the shape of the number "8".
[0006] The second fixture is typically a drain fixture, as shown in the example below. A significant advantage of this type of drain fixture is that its weight can be significantly reduced compared to drain fixtures consisting only of rectangles (where the middle section has the same width as the upper and lower sections).
[0007] The main idea of some embodiments is to reduce the overall weight of the second fixture by reducing the size or width of the middle section of the second fixture, rather than reducing the first section, the middle section and the second section simultaneously, without negatively affecting the connection between the second fixture and the second pad and the connection between the second fixture and the second lead.
[0008] Because of the lower weight of the drain clamp, the contact pressure of the drain clamp on the semiconductor die can be reduced, and die tilting can be avoided or reduced.
[0009] In conventional packaging, the drain clamp (e.g., the second clamp) is significantly heavier than the source clamp (e.g., the first clamp), causing the drain clamp to exert a greater gravitational force than the source clamp. This can further cause die tilting, sometimes referred to as uneven BLT (bond wire thickness). By using improved clamps in some embodiments of the invention, the difference between the gravitational force exerted on the die by the second clamp and the gravitational force exerted on the die by the first clamp is significantly reduced.
[0010] Specific examples will be shown and described further below.
[0011] According to an embodiment of the semiconductor device, the first pad is a first source pad, the second pad is a first drain pad, and an optional additional pad of the first semiconductor die is a first gate pad.
[0012] According to an embodiment of the semiconductor device, the semiconductor device further includes a second semiconductor transistor die, the second semiconductor transistor die including a fourth pad, a fifth pad, and a sixth pad. According to an example, the fourth pad is a second source pad, the fifth pad is a second drain pad, and the sixth pad is a second gate pad.
[0013] According to embodiments of the semiconductor device, each of the first semiconductor transistor die and the second semiconductor transistor die includes a lateral transistor that includes a load current path in a direction parallel to one of the main surfaces of the semiconductor transistor die. As an example, each of the first semiconductor transistor die and the second semiconductor transistor die includes a high electron mobility transistor (HEMT).
[0014] Furthermore, one or both of the first semiconductor transistor die and the second semiconductor transistor die can be wide-bandgap semiconductor transistor dies, especially GaN or SiC transistor dies.
[0015] Furthermore, the first semiconductor transistor die and the second semiconductor transistor die are configured as power semiconductor transistor dies. Power transistors are switching devices rated to withstand a voltage of at least 20V (more typically on the order of 100V, 600V, 1200V or greater) and / or rated to withstand a current of at least 1A (more typically on the order of 10A, 50A, 100A or even greater).
[0016] According to an embodiment of the semiconductor device, the lead post of the second lead is arranged in a plane that is higher than the die pad.
[0017] According to an embodiment of the semiconductor device, the first clamp includes a rectangular shape.
[0018] According to an embodiment of the semiconductor device, the first semiconductor die and the second semiconductor die are electrically connected in parallel with each other.
[0019] According to an embodiment of the semiconductor device, in the case of a second semiconductor transistor die, the semiconductor device further includes a fourth clamp and a fifth clamp, the fourth clamp being configured to connect a fourth pad to a die pad, and the fifth clamp being configured to connect a fifth pad to a lead post of a second lead, wherein the fifth clamp includes a first segment contacting the fifth pad of the second lateral transistor die, a second segment contacting the lead post of the second lead, and an intermediate segment between the first segment and the second segment, wherein the intermediate segment has a smaller width than the second segment.
[0020] In the aforementioned embodiments, the fourth clamp may include a shape that is the same as or different from that of the second clamp. In particular, the fourth clamp may include the shape of the letter "I", the shape of the letter "Z", or the shape of the letter "B" or the number "8". Attached Figure Description
[0021] The accompanying drawings are included to provide a further understanding of the embodiments, and these drawings are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain the principles of the embodiments. Other embodiments and many anticipated advantages will be readily understood as they become more apparent with reference to the following detailed description.
[0022] The elements in the accompanying drawings are not necessarily proportional to each other. The same reference numerals denote corresponding similar parts.
[0023] Figure 1A and 1B A top view (A) and a cross-sectional side view (B) of a semiconductor device are shown, in which two semiconductor transistor dies are connected to two corresponding I-shaped drain clamps.
[0024] Figure 2A and 2B A top view (A) and a cross-sectional side view (B) of a semiconductor device are shown, in which two semiconductor transistor dies are connected to two corresponding Z-shaped drain clamps.
[0025] Figure 3A and 3B A top view (A) and a cross-sectional side view (B) of a semiconductor device are shown, in which two semiconductor transistor dies are connected to two corresponding 8-shaped drain clamps.
[0026] Figure 4A and 4BA top view (A) and a cross-sectional side view (B) of a semiconductor device are shown, in which two semiconductor transistor dies are connected to a large I-shaped drain clamp.
[0027] Figure 5A and 5B A top view (A) and a cross-sectional side view (B) of a semiconductor device are shown, in which two semiconductor transistor dies are connected to a large Ω-shaped drain clamp. Detailed Implementation
[0028] In the following detailed description, reference is made to the accompanying drawings, which form a part of this document, in which specific embodiments of the present disclosure may be implemented by way of illustration. In this regard, directional terms such as “top,” “bottom,” “front,” and “rear” are used to indicate the orientation of the drawings described. Because components of the embodiments may be located in multiple different orientations, the directional terms are for illustrative purposes and are by no means limiting. It should be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be considered limiting, and the scope of the present disclosure is defined by the appended claims.
[0029] It should be understood that, unless otherwise specifically indicated, the features of the various exemplary embodiments described herein can be combined with each other.
[0030] As used herein, the terms “joining,” “attachment,” “connection,” “coupling,” and / or “electrical connection / electrical coupling” do not imply that elements or layers must be in direct contact with each other; intermediate elements or layers may be provided between elements that are “joined,” “attached,” “connected,” “coupled,” and / or “electrically connected / electrically coupled,” respectively. However, according to this disclosure, the foregoing terms may optionally also have a specific meaning that elements or layers are in direct contact with each other, i.e., no intermediate elements or layers are provided between elements that are “joined,” “attached,” “connected,” “coupled,” and / or “electrically connected / electrically coupled,” respectively.
[0031] Furthermore, the term "above" as used with respect to components, elements, or material layers formed or disposed "above" a surface may be used herein to indicate that the components, elements, or material layers are disposed "indirectly" (e.g., placed, formed, deposited, etc.) on an underlying surface, wherein one or more additional components, elements, or layers are arranged between the underlying surface and the components, elements, or material layers. However, the term "above" as used with respect to components, elements, or material layers formed or disposed "above" a surface may optionally also have a specific meaning, namely, that the components, elements, or material layers are disposed "directly" (e.g., placed, formed, deposited, etc.) on the underlying surface, such as being in direct contact with the underlying surface.
[0032] Figure 1Aand 1B A top view (A) and a cross-sectional side view (B) of a semiconductor device are shown, in which two semiconductor transistor dies are connected to two corresponding I-shaped drain clamps.
[0033] like Figure 1A The illustrated semiconductor device 10 includes a lead frame 11, which includes a die pad 11.1, a first lead 11.2, and a second lead 11.3, wherein the second lead 11.3 is connected to a lead post 11.3A. A first lateral transistor die 12 is applied to the die pad 11.1a and includes a source pad on the lower side, a drain pad on the opposite upper side, and a gate pad. The gate pad is located at a corner position other than the source pad. However, it may be located at other positions, and this disclosure is not concerned with that. A second lateral transistor die 15 is also applied to the die pad 11.1a and includes a source pad on the lower side, a drain pad on the opposite upper side, and a gate pad on the lower edge.
[0034] The semiconductor device 10 also includes a first clamp 13 configured to connect a source pad to a die pad 11.1, wherein the die pad 11.1 is connected to a first lead 11.2, in other words, the die pad 11.1 and the first lead 11.2 are physically integrated.
[0035] The semiconductor device 10 also includes a second clamp 14 configured to connect a second pad to a lead post 11.3A of a second lead 11.3, wherein the lead post 11.3A is physically disconnected from the die pad 11. In the illustrated embodiment, the second clamp 14 is a drain clamp.
[0036] The second clamp 14 shown in Figure 1 includes the shape of the letter "I" and is therefore an example of the shape, which includes a first segment that contacts the second pad of the first lateral transistor die 12, a second segment that contacts the lead post 11.3A of the second lead 11.3, and a third intermediate segment connecting the first segment and the second segment, wherein the intermediate segment has a width smaller than both the first segment and the second segment.
[0037] As shown in the figure, the first section of the drain clamp 14 is a crossbar connected to the drain pad of the first semiconductor transistor die 12. The second section of the drain clamp 14 is also a crossbar, which connects to the lead post 11.3A of the second lead 11.3 above the die pad 11.1. The first and second sections can have the same width, as in the illustrated embodiment. However, the widths can also be different. An intermediate section connects the first and second sections and has a smaller width. For example, it can be between one-quarter and one-half the width of either the first or second section.
[0038] like Figure 1B As shown, lead post 11.3A is located in a plane higher than die pad 11.1, and drain clamp 14 is located above pad 11.1 without contacting it and connected to lead post 11.3A of second lead 11.3. Sometimes the lead frame is called a downset leadframe.
[0039] As already mentioned, in another embodiment, the semiconductor device 10 also includes a second semiconductor transistor die 15, which is also applied to the die pad 11.1 and is formed in the embodiment of FIG1 as the same as the first semiconductor die 12, i.e., including a source pad on the lower side, a drain pad on the opposite upper side, and a gate pad on the lower corner.
[0040] The semiconductor device 10 also includes a third clamp 16 and a fourth clamp 17. The third clamp 16 is configured to connect the source pad of the second semiconductor transistor die 15 to the die pad 11.1, and the fourth clamp 17 is configured to connect the drain pad of the second semiconductor transistor die 15 to the lead post 11.3A of the second lead 11.3. The fourth clamp 17 may have a shape similar to the second clamp 14, i.e., the shape of the letter "I", including a first segment contacting the fifth pad of the second lateral transistor die 15, a second segment contacting the lead post 11.3A of the second lead 11.3, and an intermediate segment between the first and second segments, wherein the intermediate segment has a smaller width than the second segment.
[0041] Each of the first semiconductor transistor die 12 and the second semiconductor transistor die 15 may include a lateral transistor comprising a load current path in a direction parallel to one of the main surfaces of the semiconductor transistor die. Therefore, source pads, drain pads, and gate pads are disposed on the upper main surface of the semiconductor die. Furthermore, each of the first semiconductor transistor die 12 and the second semiconductor transistor die 15 may include a high electron mobility transistor (HEMT).
[0042] Therefore, the configuration shown in Figure 1 means that the first semiconductor transistor die 12 and the second semiconductor transistor die 15 are connected in parallel with each other. This configuration can be used in different switching circuits, such as in DC / DC (buck), AC / DC, or DC / AC converter circuits.
[0043] Figure 2A and 2B A top view (A) and a cross-sectional side view (B) of a semiconductor device are shown, in which two semiconductor transistor dies are connected to two corresponding Z-shaped drain clamps.
[0044] like Figure 2AThe semiconductor device 20 shown is similar to the semiconductor device 10 in Figure 1, and differs from the drain clamp in all other respects.
[0045] As shown in Figure 2, drain clamps 24 and 27 each include the shape of the letter "Z" and are therefore another example of the shape, which includes a first segment contacting the second pad of the first lateral transistor die 12, a second segment contacting the lead post 11.3A of the second lead 11.3, and a third intermediate segment connecting the first segment and the second segment, wherein the intermediate segment has a width smaller than both the first segment and the second segment.
[0046] As shown in the figure, the first section of drain clamps 24 and 27 is a crossbar connecting to the corresponding drain pads of the two semiconductor transistor dies 12 and 15. The third section of drain clamps 24 and 27 is also a crossbar, connecting to the lead post 11.3A of the second lead 11.3 above the die pad 11.1. The first and third sections can have the same width, as in the illustrated embodiment. However, the widths can also be different. A second section connects the first and third sections and has a smaller width. For example, it can be between one-quarter and one-half the width of either the first or third section.
[0047] Compared to the semiconductor device 10 in FIG1, the configuration shown in FIG2 prevents the second intermediate section of the drain clamp 24 from forming a vertical connection between the first and second sections of the drain clamp. Instead, the corners of the first and second sections of the drain clamp 24 are connected to each other via the second intermediate section of the drain clamp 24, thus forming an inverted letter "Z" on one side of the first semiconductor transistor 12. On the opposite side of the second semiconductor transistor 15, this configuration results in the letter "Z" being formed by the drain clamp 27.
[0048] Figure 3A and Figure 3B A top view (A) and a cross-sectional side view (B) of a semiconductor device are shown, in which two semiconductor transistor dies are connected to two corresponding 8- or B-type drain clamps.
[0049] As shown in Figure 3, drain clamps 34 and 37 each include the shape of the number "8" or the letter "B", and are therefore another example of the shape, which includes a first segment contacting the second pad of the first lateral transistor die 12, a second segment contacting the lead post 11.3A of the second lead 11.3, and a third intermediate segment connecting the first segment and the second segment, wherein the intermediate segment only partially includes a width smaller than both the first segment and the second segment.
[0050] The difference between this embodiment and previous embodiments is that the third intermediate section is not homogeneous but hollow, which reduces the total weight of the drain clamp, and thus reduces the gravity on the die pads accordingly.
[0051] Figure 4A and Figure 4B A top view (A) and a cross-sectional side view (B) of a semiconductor device are shown, in which two semiconductor transistor dies are connected to a large I-shaped drain clamp.
[0052] The previous embodiments in Figures 1 to 3 illustrate a configuration of a semiconductor device including two drain clamps connecting two respective semiconductor transistor dies to lead posts of a second lead. The embodiment shown in Figure 4 now illustrates how a single drain clamp 44, shaped in the form of an "I", connects two semiconductor transistor dies 12 and 15 to lead post 11.3A.
[0053] In the embodiment of FIG4, a single drain clamp 44 connects the drain pads of two semiconductor transistor dies 12 and 15 to the lead post 11.3A of the second lead 11.3. As shown in FIG4, the drain clamp 44 comprises the shape of the letter "I", and again, is an example of the shape, comprising a first segment contacting the drain pads of the semiconductor transistor dies 12 and 15, a second segment contacting the lead post 11.3A of the second lead 11.3, and a third intermediate segment connecting the first and second segments, wherein the intermediate segment has a width smaller than both the first and second segments.
[0054] Figure 5A and 5B A top view (A) and a cross-sectional side view (B) of a semiconductor device are shown, in which two semiconductor transistor dies are connected to a large Ω-shaped drain clamp.
[0055] The previous embodiments in Figures 1 to 3 illustrate a configuration of a semiconductor device including two drain clamps connecting the respective two semiconductor transistor dies to the lead post of the second lead. The embodiment shown in Figure 5 now illustrates how a single drain clamp 54, shaped in the form of an "Ω", connects the two semiconductor transistor dies 12 and 15 to the lead post 11.3A.
[0056] In the embodiment of FIG5, a single drain clamp 54 connects the drain pads of the two semiconductor transistor dies 12 and 15 to the lead post 11.3A of the second lead 11.3. As shown in FIG5, the drain clamp 54 comprises the shape of the letter "Omega," and again, is an example of the shape, comprising a first segment contacting the drain pads of the semiconductor transistor dies 12 and 15, a second segment contacting the lead post 11.3A of the second lead 11.3, and a third intermediate segment connecting the first and second segments, wherein the intermediate segment has a width smaller than both the first and second segments.
[0057] Example The following describes specific examples of this disclosure.
[0058] Example 1 is a semiconductor device comprising: a lead frame including a die pad, a first lead, and a second lead, wherein the second lead is connected to a lead post; a first lateral transistor die including a first pad, a second pad, and a third pad; a first clamp configured to connect the first pad to the die pad, the die pad being connected to the first lead; and a second clamp configured to connect a second pad to a lead post of the second lead, wherein the lead post is disconnected from the die pad, wherein the second clamp includes a first segment contacting the second pad of the first lateral transistor die, a second segment contacting the lead post of the second lead, and an intermediate segment between the first segment and the second segment, wherein the intermediate segment has a width partially smaller than that of the second segment.
[0059] Example 2 is a semiconductor device according to Example 1, wherein the lead post of the second lead is arranged in a plane higher than the die pad.
[0060] Example 3 is a semiconductor device according to Example 1 or 2, wherein the first pad is a first source pad, the second pad is a first drain pad, and the third pad is a first gate pad.
[0061] Example 4 is a semiconductor device according to any of the preceding examples, wherein the second clamp comprises the shape of the letter "I".
[0062] Example 5 is a semiconductor device according to any one of Examples 1 to 3, wherein the second clamp includes the shape of the letter "Z".
[0063] Example 6 is a semiconductor device according to any one of Examples 1 to 3, wherein the second clamp comprises the shape of the number "8" or the letter "B".
[0064] Example 7 is a semiconductor device according to any of the preceding examples, wherein the first clamp comprises a rectangular shape.
[0065] Example 8 is a semiconductor device according to any of the foregoing examples, further comprising a second semiconductor transistor die, the second semiconductor transistor die including a fourth pad, a fifth pad, and a sixth pad.
[0066] Example 9 is a semiconductor device according to Example 8, wherein the fourth pad is a second source pad, the fifth pad is a second drain pad, and the sixth pad is a second gate pad.
[0067] Example 10 is a semiconductor device according to Example 8 or 9, wherein a first semiconductor die and a second semiconductor die are electrically connected in parallel with each other.
[0068] Example 11 is a semiconductor device according to any one of Examples 8 to 10, further comprising: a third clamp configured to connect a fourth pad to a die pad; and a fourth clamp configured to connect a fifth pad to a lead post of a second lead, wherein the fourth clamp includes a first segment contacting the fifth pad of the second lateral transistor die, a second segment contacting the lead post of the second lead, and an intermediate segment between the first and second segments, wherein the intermediate segment has a smaller width than the second segment.
[0069] Example 12 is a semiconductor device according to any one of Examples 7 to 10, wherein the fourth clamp includes the shape of the letter "I".
[0070] Example 13 is a semiconductor device according to any one of Examples 7 to 10, wherein the fourth clamp includes the shape of the letter “Z”.
[0071] Example 14 is a semiconductor device according to any one of Examples 7 to 10, wherein the fourth clip includes the shape of the number "8" or the letter "B".
[0072] Example 15 is a semiconductor device according to any of the preceding examples, wherein the first semiconductor transistor die includes a lateral transistor die, the lateral transistor die including a load current path in a direction parallel to one of the main surfaces of the semiconductor transistor die.
[0073] Furthermore, while specific features or aspects of embodiments of this disclosure may have been disclosed with respect to only one of several implementations, such features or aspects may be combined with one or more other features or aspects of other implementations, as may be desired and advantageous for any given or particular application. Moreover, the use of the terms “comprising,” “having,” “with,” and variations thereof in the detailed description or claims is intended to be inclusive in a manner similar to the term “including.” Furthermore, it should be understood that embodiments of this disclosure may be implemented in discrete circuits, partially integrated circuits, or fully integrated circuits or programmable devices. Additionally, the term “exemplary” is meant only as an example and not as optimal or best practice. It should also be understood that, for purposes of simplicity and ease of understanding, features and / or elements depicted herein are shown in specific dimensions relative to each other, and actual dimensions may differ substantially from those shown herein.
[0074] While specific embodiments have been shown and described herein, those skilled in the art will understand that various alternatives and / or equivalent implementations may be made in place of the specific embodiments shown and described without departing from the scope of this disclosure. This application is intended to cover any modifications or variations of the specific embodiments discussed herein. Therefore, this disclosure is intended to be limited only by the claims and their equivalents.
Claims
1. A semiconductor device (10), comprising: A lead frame (11) includes a die pad (11.1), a first lead (11.2) and a second lead (11.3), wherein the second lead (11.3) is connected to a lead post (11.3A); The first lateral transistor die (12) includes a first pad, a second pad and a third pad; A first clamp (13) is configured to connect the first pad to the die pad (11.1), which is connected to the first lead (11.2); A second clamp (14) is configured to connect the second pad to the lead post (11.3A) of the second lead (11.3), wherein the lead post (11.3A) is disconnected from the die pad (11.1); The second clamp (14) includes a first segment contacting the second pad of the first lateral transistor die (12), a second segment contacting the lead post (11.3A) of the second lead (11.3), and an intermediate segment between the first segment and the second segment, wherein the intermediate segment has a width that is partially smaller than that of the second segment. The first clamp (13) directly connects the first pad of the first lateral transistor die (12) to the die pad (11.1).
2. The semiconductor device (10) according to claim 1, wherein The second clamp (14) directly connects the second pad of the first lateral transistor die (12) to the lead post (11.3A), and The first pad and the second pad are located on the upper surface of the first lateral transistor die (12) and on the opposite end of the first lateral transistor die (12).
3. The semiconductor device (10) according to claim 1 or 2, wherein, The lead post (11.3A) of the second lead (11.3) is arranged in a plane that is higher than the die pad (11.1).
4. The semiconductor device (10) according to claim 1 or 2, wherein, The first pad is a first source pad, the second pad is a first drain pad, and the third pad is a first gate pad.
5. The semiconductor device (10) according to any one of the preceding claims, wherein, The second clamp (14) includes the shape of the letter "I".
6. The semiconductor device (10) according to any one of claims 1-4, wherein, The second clamp (14) includes the shape of the letter "Z".
7. The semiconductor device (10) according to any one of claims 1-4, wherein, The second clamp (14) includes the shape of the number "8" or the letter "B".
8. The semiconductor device (10) according to any one of the preceding claims, wherein, The first clamp (13) has a rectangular shape.
9. The semiconductor device (10) according to any one of the preceding claims further comprises: The second lateral transistor die (15) includes a fourth pad, a fifth pad, and a sixth pad.
10. The semiconductor device (10) according to claim 9, wherein, The fourth pad is the second source pad, the fifth pad is the second drain pad, and the sixth pad is the second gate pad.
11. The semiconductor device (10) according to claim 9 or 10, wherein, The first lateral transistor die (12) and the second lateral transistor die (15) are electrically connected in parallel to each other.
12. The semiconductor device (10) according to any one of claims 9-11, further comprising: A third clamp (16) is configured to connect the fourth pad to the die pad (11.1). A fourth clamp (17) is configured to connect the fifth pad to the lead post (11.3A) of the second lead (11.3). The fourth clamp (17) includes a first section that contacts the fifth pad of the second lateral transistor die (15), a second section that contacts the lead post (11.3A) of the second lead (11.3), and an intermediate section between the first section and the second section, wherein the intermediate section has a smaller width than the second section.
13. The semiconductor device (10) according to any one of claims 8-11, wherein, The fourth clamp (17) includes the shape of the letter "I".
14. The semiconductor device (10) according to any one of claims 8-11, wherein, The fourth clamp (17) includes the shape of the letter "Z".
15. The semiconductor device (10) according to any one of claims 8-11, wherein, The fourth clamp (17) includes the shape of the number "8" or the letter "B".
16. The semiconductor device (10) according to any one of the preceding claims, wherein, The first lateral transistor die (12) includes a lateral transistor die, the lateral transistor die including a load current path in a direction parallel to one of the main surfaces of the lateral transistor die.
17. The semiconductor device (10) according to any of the preceding claims, wherein The first clamp (13) has a width greater than that of the second clamp (14), and / or the first clamp (13) has a length less than that of the second clamp (14).