Semiconductor package and method of forming same

Abstract

A semiconductor package includes a first substrate including a first surface and a second surface opposite to each other; an antenna located near the first surface of the first substrate; a first integrated circuit mounted on the second surface of the first substrate and coupled to the antenna; a molding compound encapsulating the first integrated circuit; a shield layer covering the molding compound; and the first shielding wall structure is embedded in the first substrate and is coupled with the shielding layer. Therefore, the shielding layer does not need to cover the side wall of the substrate, the first shielding wall structure embedded into the first substrate is used for providing shielding protection for signal transmission of the first integrated circuit, the shielding layer does not need to be accurately controlled in the manufacturing process, and the shielding layer is easier to manufacture and form; the shielding layer may have a simple manufacturing process and a reduced manufacturing cost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to semiconductor packaging and its formation methods. Background Technology

[0002] Wireless communication devices are becoming increasingly popular and complex. These devices typically include antennas to support communication across a range of frequencies. Antenna-in-package (AiP) technology is commonly used to integrate one or more antennas with other electronic circuitry into the same package. Implementing AiP technology, which integrates antennas within a semiconductor package structure, can balance antenna performance with overall cost and desired device size reduction. For example, integrating an antenna and a radio frequency integrated circuit (RFIC) into the same unit can improve signal strength and reduce transmission loss.

[0003] While existing antenna packaging structures generally meet requirements, they are not entirely satisfactory. Integrating the antenna and RFIC into a single unit also presents some challenges. For example, the antenna needs to radiate and receive electromagnetic waves; however, the RFIC should be isolated to prevent electromagnetic interference. This creates a contradiction. Therefore, further improvements to antenna packaging are needed. Summary of the Invention

[0004] In view of this, the present invention provides a novel semiconductor package and its formation method, which makes it easier to form shielding protection for integrated circuits.

[0005] One embodiment of the present invention provides a semiconductor package. The semiconductor package includes a first substrate, a first integrated circuit (IC), an antenna, a molding compound, a shielding layer, and a first shielding wall structure. The first substrate includes a first surface and a second surface opposite to each other. The antenna is located near the first surface of the first substrate. The first integrated circuit (IC) is mounted on the second surface of the first substrate and coupled to the antenna. The molding compound encapsulates the first integrated circuit. The shielding layer covers the molding compound. The first shielding wall structure is embedded in the first substrate and coupled to the shielding layer.

[0006] Furthermore, the first shielding wall structure includes: a non-conductive material wall; and a conductive material covering the sidewalls and bottom surface of the non-conductive material wall. This forms a first shielding wall structure with better structural stability, ensuring the mechanical structural stability of the semiconductor package.

[0007] Furthermore, the first shielding wall structure is exposed from the first substrate and completely covered by the passivation layer. This forms a first shielding wall structure embedded within the first substrate to create the desired shielding structure.

[0008] Furthermore, the first shielding wall structure is separated from the sidewall of the first substrate. Therefore, the first shielding wall structure is not formed on the sidewall of the first substrate, and there is no contact between the first shielding wall structure and the sidewall of the first substrate, thereby reducing the manufacturing complexity of forming the shielding structure.

[0009] Furthermore, the first shielding wall structure is coupled to the grounding trace of the first substrate. This grounding provides effective shielding protection for wiring or traces connected to the integrated circuit.

[0010] Furthermore, the first shielding wall structure forms a closed pattern to surround at least one conductive trace of the first substrate coupled to the first integrated circuit. This provides effective shielding protection for the wiring or traces connected to the integrated circuit.

[0011] Furthermore, the first shielding wall structure includes: a first portion having a first height; and a second portion having a second height. The different portions of the first shielding wall structure can be freely configured in height according to the wiring or structure in their respective vicinity, improving design flexibility and adaptability.

[0012] Furthermore, the antenna is formed in a dielectric layer on the first substrate away from the first integrated circuit. This avoids the negative impact of the shielding structure on the antenna's function and ensures the antenna's normal operation.

[0013] Furthermore, the first height is the same as the second height, and both the first height and the second height are less than or equal to half the thickness of the first substrate. Alternatively, the first height and the second height are the same, and both the first height and the second height are greater than or equal to half the thickness of the first substrate; of course, both the first height and the second height can be less than the thickness of the first substrate. Therefore, in this invention, the height of different parts of the first shielding wall structure can be set according to different needs.

[0014] Furthermore, the first height is greater than the second height, and the first height is greater than half the thickness of the first substrate. Therefore, in this invention, the height of different parts of the first shielding wall structure can be set according to different needs.

[0015] Furthermore, the first height is greater than the second height, and the second height is less than the thickness of the first substrate. Therefore, in this invention, the height of different parts of the first shielding wall structure can be set according to different needs.

[0016] Furthermore, it includes a second shielding wall structure embedded in the first substrate and coupled to the shielding layer, wherein the first shielding wall structure and the second shielding wall structure are separated from each other. Therefore, in this invention, multiple independent shielding wall structures can be provided as needed to achieve adaptive shielding protection.

[0017] Furthermore, at least one of the first shielding wall structure and the second shielding wall structure is coupled to the shielding layer through at least one conductive trace on the first substrate. This forms an interconnected shielding structure to shield and protect the integrated circuit and related wiring.

[0018] Furthermore, each of the first and second shielding wall structures forms a closed pattern to surround at least one conductive line of the first substrate coupled to the first integrated circuit. This provides effective shielding protection for the wiring or traces connected to the integrated circuit.

[0019] Furthermore, it includes a second substrate mounted on the first surface of the first substrate, wherein the antenna is disposed in the second substrate. Thus, the antenna can be disposed on another substrate, thereby reducing mutual interference between the integrated circuit and related wiring and the antenna.

[0020] Furthermore, the first shielding wall structure does not extend into the second substrate. This avoids or reduces the negative impact of the shielding structure on antenna operation.

[0021] Furthermore, the first shielding wall structure forms a closed and continuous pattern without any breaks. Therefore, the first shielding wall structure is a continuous and unbroken pattern to achieve shielding protection.

[0022] Furthermore, at least a portion of the first shielding wall structure has a height less than the thickness of the substrate, thereby ensuring the structural stability of the substrate.

[0023] One embodiment of the present invention provides a method for forming a semiconductor package. The method includes forming a first substrate. The first substrate includes a first surface and a second surface opposite to each other. The method further includes forming a first shielding wall structure embedded in the first substrate. The method further includes forming an antenna near the first surface of the substrate. The method further includes mounting a first integrated circuit (IC) on the second surface of the first substrate and coupling it to the antenna. The method further includes forming a molding compound to encapsulate the first integrated circuit. The method further includes forming a shielding layer covering the molding compound, wherein the first shielding wall structure is coupled to the shielding layer.

[0024] Further, it includes: forming a trench in a first substrate, wherein the trench forms a closed pattern to surround at least one conductive trace of the first substrate coupled to a first integrated circuit; forming a conductive material lining the sidewalls and bottom surface of the trench; filling the trench with a non-conductive material to form a first shielding wall structure; and forming a passivation layer on the first shielding wall structure.

[0025] The semiconductor package of the present invention includes a first substrate; an antenna; a first integrated circuit; a molding compound encapsulating the first integrated circuit; a shielding layer covering the molding compound; and a first shielding wall structure embedded in the first substrate and coupled to the shielding layer. Therefore, in the present invention, the shielding layer does not need to cover the sidewalls of the substrate; instead, the first shielding wall structure embedded in the first substrate provides shielding protection for the signal transmission of the first integrated circuit. Thus, the shielding layer does not require precise control during manufacturing, making it easier to form and simplifying the manufacturing process, resulting in lower manufacturing costs. Furthermore, the first shielding wall structure embedded in the first substrate is also easier to manufacture and has lower manufacturing costs. Therefore, the present invention can reduce overall manufacturing complexity and costs, and has broader and more practical industrial applicability. Attached Figure Description

[0026] Figure 1 This is a schematic cross-sectional view of a semiconductor package according to some embodiments of the present invention;

[0027] Figure 2A This is shown in some embodiments according to the present invention. Figure 1 A schematic top view of the substrate of the semiconductor package;

[0028] Figure 2B This is shown in some embodiments according to the present invention. Figure 2A A cross-sectional view of the semiconductor package substrate along line A-A' (or line B-B');

[0029] Figure 3A This is shown in some embodiments according to the present invention. Figure 1 A schematic top view of the substrate of the semiconductor package;

[0030] Figure 3B This is shown in some embodiments according to the present invention. Figure 3A A cross-sectional view of the semiconductor package substrate along line A-A';

[0031] Figure 4A This is shown in some embodiments according to the present invention. Figure 1 A schematic top view of the substrate of the semiconductor package;

[0032] Figure 4B This is shown in some embodiments according to the present invention. Figure 4A A cross-sectional view of the semiconductor package substrate along line A-A';

[0033] Figure 5A This is shown in some embodiments according to the present invention. Figure 1 A schematic top view of the substrate of the semiconductor package;

[0034] Figure 5B This is shown in some embodiments according to the present invention. Figure 5A A cross-sectional view of the semiconductor package substrate along line A-A';

[0035] Figure 6 This is a schematic cross-sectional view of a semiconductor package according to some embodiments of the present invention;

[0036] Figure 7A This is shown in some embodiments according to the present invention. Figure 6 A schematic top view of the substrate of the semiconductor package;

[0037] Figure 7B This is shown in some embodiments according to the present invention. Figure 7A A cross-sectional view of the semiconductor package substrate along line A-A';

[0038] Figure 8A , 8B 8C, 8D, 8E, 9A, 9B, 9C, 9D, and 9E are shown in some embodiments according to the present invention. Figure 2B , 3B The shielding structure of semiconductor packages in 4B, 5B and 7B forms a schematic cross-sectional view of different stages. Detailed Implementation

[0039] The following description is intended to illustrate the general principles of the invention and should not be considered as a limiting description. The scope of the invention is best determined by referring to the appended claims.

[0040] The following description is for illustrative purposes only and should not be construed as limiting. The scope of the invention is best determined by reference to the appended claims. In embodiments of the invention, when a component or layer is referred to as being “located,” “connected to,” or “coupled to” another component or layer, it may be directly located, connected to, or coupled to that other component or layer, or there may be intermediate components or layers. Conversely, when a component is referred to as being “directly located,” “directly connected to,” or “directly coupled to” another component or layer, there are no intermediate components or layers. The same numbers always refer to the same component. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items. “Directly above” or “directly below” may indicate that the projections of two or more of them at least partially overlap, while “not directly above” or “directly below” may indicate that the projections of two or more of them do not overlap at all. The same numbers refer to the same component throughout the document. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0041] For electromagnetic compatibility (EMC) and electromagnetic interference (EMI) considerations, a sputtered conformal shield is typically applied across the entire outline of a semiconductor package. However, for antenna-in-module / package (AiM / AiP) applications, this conformal shielding may block the antenna from receiving signals from and / or transmitting signals to external devices. Therefore, selective and effective partial shielding is necessary.

[0042] Traditional AiM / AiP packaging typically involves laterally extending ground traces to expose them from the sidewalls of the substrate, allowing partial shielding to be partially coated on the substrate sidewall portion surrounding the ground trace without obstructing the sidewall portion surrounding the antenna. However, traditional partial shielding presents several challenges in the manufacturing process. For example, controlling the vertical height of the partial shielding with precision is difficult. Tooling and maintenance costs for partial shielding are also high. Furthermore, traditional partial shielding is coated onto the manufactured AiM / AiP unit, resulting in low yields. Therefore, a novel AiM / AiP package is needed.

[0043] Figure 1This is a schematic cross-sectional view of a semiconductor package 500A according to some embodiments of the present invention. In some embodiments, the semiconductor package 500A may include an antenna package. The semiconductor package 500A includes a substrate 200A, integrated circuits (ICs) 102 and 104, an antenna 220, a molding compound 110, a shielding layer 250, and a shielding wall structure 260 (including shielding wall structures 260A, 260B, 260C, and 260D in the following figures).

[0044] like Figure 1 As shown, substrate 200A may include a multilayer packaging substrate. Substrate 200A can provide mechanical support and electrical connections between integrated circuit (IC) chips and conductive bumps attached to the top surface 200AT and bottom surface 200AB of substrate 200A. Substrate 200A can be of various types, including, for example, a cored substrate, including thin cores, thick cores (e.g., laminated BT (bismaleimide-triazine resin) or FR-4 type fiberboard materials), and laminated cores. Alternatively, the cored packaging substrate may be constructed layer by layer, for example, around a central core, with conductive material (typically copper) layers separated from insulating dielectric layers, and interlayer connections formed through vias or microvias.

[0045] The substrate 200A can be of various types, including, for example, a cored substrate or a coreless substrate (a coreless substrate is, for example, a laminated substrate). In some embodiments, when the substrate 200A is a cored substrate, the substrate 200A includes a core 202 and redistribution layers (RDLs) 210-1A and RDL 210-2A. The core 202 has a top surface 202T and a bottom surface 202B. In some embodiments, the core 202 can be formed of organic materials, glass materials, ceramic materials, semiconductor materials, similar materials, or combinations thereof. Organic materials may include polypropylene, prepreg (PP), fiberglass resin (e.g., fiberglass resin, FR-4), bismaleimidetriazine (BT) resin, similar materials, or combinations thereof. Semiconductor materials may include silicon, germanium, or compound materials, including silicon germanium, silicon carbide, gallium arsenide, silicon germanium carbide, similar materials, or combinations thereof. Redistribution layer structures 210-1A and 210-2A are respectively disposed on the top surface 202T and bottom surface 202B of the core 202. In some embodiments, each redistribution layer structure 210-1A and 210-2A includes a conductive trace 208 and a via 212 disposed in one or more dielectric layers 206. In addition, redistribution layer structure 210-1A may also include a conductive pad 214.

[0046] In some embodiments, the dielectric layers 206 of the redistribution layer structures 210-1A and 210-2A are symmetrically disposed on the top surface 202T and bottom surface 202B of the core 202. For example, the number of dielectric layers 206 in the redistribution layer structure 210-1A is the same as the number of dielectric layers 206 in the redistribution layer structure 210-2A. In some embodiments, the dielectric layer 206 may be formed of an organic polymer, including polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, Ajinomoto build-up film (ABF), bismaleimide-triazine (BT) resin, other suitable organic dielectric materials, or combinations thereof, but not limited thereto. Alternatively, the dielectric layer 206 may be formed of silicon oxide, silicon nitride, silicon oxynitride, similar materials, or combinations thereof. In some embodiments, the dielectric layer 206 may be formed by a lamination process, a spin coating process, a chemical vapor deposition (CVD) process, or other suitable processes. According to some embodiments, the dielectric layer 206 may be patterned by one or more photolithography and / or etching processes.

[0047] In some embodiments, the redistribution layer structure 210-1A is located between the core 202 and the integrated circuits (ICs) 102 and 104. The redistribution layer structure 210-1A includes circuit wiring consisting of conductive traces 208 and vias 212 formed in the dielectric layer 206, and conductive pads 214 for electrical connection between the integrated circuits (ICs) 102 and 104 and the antenna 220 in the redistribution layer structure 210-2A.

[0048] Conductive traces 208 are formed in dielectric layers 206 of different layers. In some embodiments, the conductive layer 208 in each layer of the redistribution layer structure 210-1A may include power traces, signal traces or ground traces for input / output (I / O) connections of ICs 102 and 104.

[0049] like Figure 1 As shown, via 212 is disposed in the dielectric layer 206 of the redistribution layer structure 210-1A. The via 212 can be formed through the dielectric layer 206 of the redistribution layer structures 210-1A and 210-2A to couple to the conductive traces 208 of different layers.

[0050] The conductive pad 214 of the redistribution layer structure 210-1A is disposed near the top surface 200AT of the substrate 200A. The conductive pad 214 is coupled to different terminals of the conductive trace 208. The conductive pad 214 disposed near the top surface 200AT of the substrate 200A is used for direct mounting of ICs 102 and 104.

[0051] In some embodiments, redistribution layer structure 210-2A is located on the bottom surface 202B of core 202 and opposite to redistribution layer structure 210-1A. Furthermore, redistribution layer structure 210-2A is separated from ICs 102 and 104 by core 202 and redistribution layer structure 210-1A. Redistribution layer structure 210-2A includes conductive traces 208, vias 212, and an antenna 220 formed in dielectric layer 206. Antenna 220 is formed in dielectric layer 206 away from first substrate 200A of ICs 102 and 104. Antenna 220 consists of a conductive layer and vias. Furthermore, redistribution layer structure 210-2A may further include a heat sink, feed lines, other suitable components, or combinations thereof.

[0052] In some embodiments, the conductive trace 208, the through-hole 212, and the conductive pad 214 comprise conductive materials, such as metals including tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold, alloys thereof, or combinations thereof.

[0053] It should be noted that Figure 1The number of vias 212, conductive traces 208, dielectric layers 206, conductive pads 214 in the redistribution layer structures 210-1A and 210-2A shown are merely examples and do not constitute a limitation on the present invention.

[0054] In some embodiments, substrate 200A further includes a plated through hole (PTH) (not shown) that passes through and is embedded in core 202. The PTH is used to couple redistribution layer structures 210-1A and 210-2A. For example, antenna 220 of redistribution layer structure 210-2A can be coupled to circuit wiring of redistribution layer structure 210-1A via PTH.

[0055] In some embodiments where substrate 200A is a coreless substrate, the fabrication of substrate 200A does not include a core, and the redistribution layer structure 210-2A is laminated on the redistribution layer structure 210-1A (or vice versa). In some embodiments where the substrate is a coreless substrate, the other structures of the substrate are basically similar to those of substrate 200A, except that there is no core, so they will not be described in detail.

[0056] like Figure 1 As shown, the semiconductor package 500A also includes passivation layers 230-1 and 230-2 disposed on the respective redistribution layer structures 210-1A and 210-2A. Passivation layer 230-1 may have an opening (not shown) to expose a corresponding conductive pad 214 coupled to the conductive trace 208. Furthermore, passivation layer 230-2 may completely cover the antenna 220. Passivation layers 230-1 and 230-2 may include a solder resist layer. In some embodiments, passivation layers 230-1 and 230-2 may be formed of a resin material (e.g., a thermosetting resin, a photosensitive resin, or a similar material), an ink material, an adhesive tape material (e.g., polyimide tape, Kapton tape, or a similar material), similar materials, or combinations thereof. Passivation layers 230-1 and 230-2 may be formed by printing, coating, or other suitable methods.

[0057] ICs 102 and 104 are disposed on substrate 200A and coupled to conductive pads 214 of the redistribution layer structure 210-1A of substrate 200A via conductive structures 103 and 105. Furthermore, ICs 102 and 104 can be coupled to antenna 220 via conductive structures 103 and 105 and the redistribution layer structure 210-1A. In some embodiments, ICs 102 and 104 include radio frequency integrated circuits (RFICs), power management integrated circuits (PMICs), or combinations thereof. In some embodiments, ICs 102 and 104 include electronic components other than passive components. In some embodiments, conductive structures 103 and 105 include conductive ball structures, such as copper balls, conductive bump structures, such as copper bumps or solder bump structures, or conductive pillar structures, such as copper pillar structures. For example, conductive structures 103 and 105 may be microbumps, controlled collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, other suitable conductive connectors, or combinations thereof.

[0058] like Figure 1 As shown, the semiconductor package 500A may further include a connector assembly 106 formed on the top surface 200AT of the substrate 200A. The connector assembly 106 may be adjacent to ICs 102 and 104. The connector assembly 106 may be coupled to ICs 102 and 104 via circuit routing of conductive structure 107 and redistribution layer structure 210-1A. In some embodiments, the connector assembly 106 includes a distributor / merger. In some embodiments, conductive structures 103, 105, and 107 may include the same or similar structures.

[0059] ICs 102 and 104 and connector assembly 106 may be disposed on the same surface (e.g., top surface 200AT) of substrate 200A and may be arranged near the circuit routing of redistribution layer structure 210-1A and away from antenna 220. ICs 102 and 104 and connector assembly 106 may be arranged on the side of substrate 200A opposite to antenna 220.

[0060] like Figure 1As shown, molding compound 110 may partially cover substrate 200A and encapsulate ICs 102 and 104. Furthermore, connector assembly 106 may be exposed from molding compound 110 so that semiconductor package 500A can be electrically coupled to other electronic components (e.g., printed circuit board (PCB) or any suitable component (not shown)) via connector assembly 106. In some embodiments, molding compound 110 is made of a resin comprising, for example, a Novolac-based resin (a thermoplastic phenolic resin formed by the condensation of phenol and formaldehyde), an epoxy-based resin, a silicone-based resin, or other suitable encapsulation material. Molding compound 110 may contain suitable fillers, such as powdered SiO2. Molding compound 110 can be applied using any of a variety of molding techniques, such as compression molding, injection molding, or transfer molding.

[0061] A shielding layer 250 is disposed on the passivation layer 230-1 to cover the molding compound 110 and ICs 102 and 104. The shielding layer 250 may extend to partially cover the redistribution layer structure 210-1A. Furthermore, the shielding layer 250 does not cover the sidewalls 200AE of the substrate 200A, nor does it extend to the sidewalls 200AE of the substrate 200A. In some embodiments, the shielding layer 250 may include a conductive material, such as a metal comprising copper, aluminum, the like, alloys thereof, or combinations thereof. In some embodiments, the shielding layer 250 may be formed by a deposition process, such as sputtering.

[0062] like Figure 1 As shown, the sidewall 200AE of the substrate 200A, away from the connector assembly 106, protrudes from the corresponding sidewall 250E of the shielding layer 250 and the corresponding sidewall 110E of the molding compound 110. Therefore, the shielding layer 250 does not cover the sidewall 200AE of the substrate 200A. The shielding layer 250 does not require precise control during manufacturing. Furthermore, the shielding layer 250 can have a simple manufacturing process and reduced manufacturing costs. Therefore, the shielding layer 250 is feasible and beneficial for large-scale production with increased yield and reduced costs.

[0063] like Figure 1As shown, the shielding wall structure 260 is embedded in the substrate 200A. The shielding wall structure 260 is exposed from the surface 200AT of the substrate 200A and is completely covered by the passivation layer 230-1. In some embodiments, the shielding wall structure 260 is embedded in at least one dielectric layer 206 of the redistribution layer structure (RDL structure) 210-1A. In some embodiments, the shielding wall structure 260 may penetrate at least one dielectric layer 206 of the redistribution layer structure 210-1A. In some embodiments where the substrate 200A is a core substrate, the shielding wall structure 260 may be embedded in at least one dielectric layer 206 and the core layer, or the shielding wall structure 260 may not be embedded in the core layer. In some embodiments, the shielding wall structure 260 is coupled to the shielding layer 250 in the following ways: (1) the shielding wall structure 260 is coupled to the shielding layer 250 (or an extension of the shielding layer 250, such as an extension on the passivation layer 230-1) through a via; (2) the shielding wall structure 260 is coupled to a conductive trace 208 located at a certain level of the redistribution layer structure 210-1A, the conductive trace 208 being exposed from the sidewall 200AE of the substrate 200A, and the shielding layer 250 having an extension to connect to the exposed conductive trace 208, wherein method (1) is easier and more suitable for manufacturing. Furthermore, the shielding wall structure 260 and the shielding layer 250 can be coupled through at least one ground trace of the substrate 200A (which is part of the conductive trace 208). This grounding provides effective shielding protection for wiring or traces connected to integrated circuits. The shielding wall structure 260 and the shielding layer 250 can prevent the antenna 220 from transmitting signals (wireless signals) in the direction of the electrical (circuit) wiring of the integrated circuits (ICs) 102 and 104 and the redistribution layer structure 210-1A, thereby reducing electromagnetic interference to the traces or wiring of the integrated circuits (ICs) 102 and 104.

[0064] In some embodiments, the shielding wall structure 260 may include a non-conductive material wall 205 and a conductive material 204. The non-conductive material wall 205 is formed from the top of the redistribution layer structure 210-1A and extends to a portion of the substrate 200A. In some embodiments, the conductive material 204 may be formed as a thin conductive layer covering the sidewalls and bottom surface of the non-conductive material wall 205. In some embodiments, the non-conductive material wall 205 comprises epoxy resin, such as ink. In some embodiments, the conductive material 204 comprises copper or nickel-copper and is formed by an electroplating process, such as electroless plating, electroplating, or electroless plating. The non-conductive material wall 205 and the conductive material 204 form a first shielding wall structure with better structural stability, ensuring the mechanical structural stability of the semiconductor package.

[0065] The structure and arrangement of shielding wall structures 260A, 260B, 260C, and 260D will be... Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A and Figure 5B The explanation is as follows.

[0066] Figure 2A This is shown according to some embodiments disclosed herein. Figure 1 A schematic top view of the substrate 200A of the semiconductor package 500A. Figure 2B This is shown according to some embodiments disclosed herein. Figure 2A A cross-sectional view of the substrate 200A of the semiconductor package 500A along line A-A' (or line B-B'). Figure 2A and Figure 2B The structure and arrangement of the shielding wall structure 260A are also described. For the sake of brevity, [the following is a continuation of the previous sentence, but the translation is incomplete and cannot be translated accurately]. Figure 1 Components of the same or similar embodiments previously described in the references will not be repeated here. For illustration, Figure 2A Components below the intermediate passivation layer 230-1 (except for the shielding wall structure 260A) are omitted.

[0067] like Figure 2A and Figure 2B As shown, the shielding wall structure 260A can form a single closed pattern to surround the electrical wiring (including at least one conductive trace 208, at least one through-hole 212, and at least one conductive pad 214) of the redistribution layer structure 210-1A of the substrate 200A, which is connected to integrated circuits (ICs) 102 and 104. Figure 1 Coupling. In some embodiments, such as Figure 2A As shown, the shielding wall structure 260A is a continuous pattern without any breaks. The shielding wall structure 260A can also be a closed and continuous pattern. The shielding wall structure 260A is separated from the sidewall 200AE of the substrate 200A. In other words, the shielding wall structure 260A is not exposed from the sidewall 200AE of the substrate 200A, and there is no contact between the shielding wall structure 260A and the sidewall of the substrate 200A. Therefore, the first shielding wall structure is not formed on the sidewall of the first substrate, and there is no contact between the first shielding wall structure and the sidewall of the first substrate, thereby reducing the manufacturing complexity of forming the shielding structure. In this embodiment, the shielding wall structure 260A may include, for example, Figure 2BThe portions 260A1 and 260A2 are shown. Portion 260A1 has a height HA1. Portion 260A2 has a height HA2. In this embodiment, heights HA1 and HA2 may have substantially the same value. In this embodiment, heights HA1 and HA2 may be less than or equal to half the thickness H200A of the substrate 200A. For example, portions 260A1 and 260A2 of the shielding wall structure 260A may penetrate the redistribution layer structure 210-1A and extend to a portion of the core 202. In some embodiments, heights HA1 and HA2 may have different values. In some embodiments, at least one portion of the shielding wall structure 260A (e.g., portions 260A1 and 260A2) does not penetrate the substrate 200A to ensure the mechanical strength and structural stability of the substrate. In other words, at least one portion of the shielding wall structure 260A (e.g., portions 260A1 and 260A2) has a height (e.g., height HA1 and height HA2) less than the substrate thickness H200A to ensure the mechanical strength and structural stability of the substrate. In some embodiments, heights HA1 and HA2 can both be greater than or equal to half the thickness of the first substrate; of course, heights HA1 and HA2 can both be less than the thickness of the first substrate. Therefore, the heights of different portions of the first shielding wall structure can be set according to different needs in this invention.

[0068] Figure 3A This is a schematic top view of the substrate 200A of the semiconductor package 500A, shown according to some embodiments of this disclosure. Figure 1 . Figure 3B It is along Figure 3A The diagram shows a cross-sectional view along line A-A' of the substrate 200A of the semiconductor package 500A. Figure 3A and Figure 3B The structure and arrangement of the shielding wall structure 260B were also demonstrated. For the sake of brevity, [the text is incomplete and ends abruptly]. Figure 1 , Figure 2A and Figure 2B Components of the same or similar embodiments previously described will not be repeated here. For illustration, Figure 3A Components below the passivation layer 230-1, except for the shielding wall structure 260B, are all omitted.

[0069] like Figure 3A and Figure 3B As shown, the shielding wall structure 260B can form a single closed pattern to surround integrated circuits 102 and 104 ( Figure 1The circuit wiring of the coupled substrate 200A includes at least one conductive trace 208, at least one via 212, and at least one conductive pad 214. The shielding wall structure 260B is separated from the sidewall 200AE of the substrate 200A. In other words, the shielding wall structure 260B is not exposed from the sidewall 200AE of the substrate 200A. In this embodiment, the shielding wall structure 260B may include portions 260B1 and 260B2 with different heights HB1 and HB2, such as... Figure 3B As shown. For example, a portion 260B1 of the shielding wall structure 260B can pass through the RDL structure 210-1A and the core 202. A portion 260B2 of the shielding wall structure 260B can pass through the RDL structure 210-1A, the core 202, and the RDL structure 210-2A. In this embodiment, a portion 260B1 of the shielding wall structure 260B can be exposed from the top surface 200AT of the substrate 200A and the bottom surface 202B of the core 202. A portion 260B2 of the shielding wall structure 260B can be exposed from the top surface 200AT of the substrate 200A and the bottom surface 200AB of the core 202. In this embodiment, the height HB2 of portion 260B2 is greater than the height HB1 of portion 260B1. In this embodiment, the heights HB1 and HB2 can be greater than half the thickness H200A of the first substrate 200A. The height HB1 can be less than the thickness H200A of the substrate 200A. In some embodiments, the height HB2 may be greater than half the thickness H200A of the substrate 200A, while the height HB1 may be less than or equal to half the thickness H200A of the substrate 200A. In some embodiments, at least one portion (e.g., portion 260B1) of the shielding wall structure 260B does not penetrate the substrate 200A to ensure the mechanical strength and structural stability of the substrate. In other words, at least one portion (e.g., portion 260B1) of the shielding wall structure 260B has a height (e.g., height HB1) less than the thickness of the substrate 200A to ensure the mechanical strength and structural stability of the substrate.

[0070] In this embodiment, since a portion 260B2 of the shielding wall structure 260B passes through the substrate 200A, a portion 260B1 of the shielding wall structure 260B can be designed as an RDL structure 210-2A that does not pass through the substrate 200A, in which the antenna 220 is embedded, so that the portion of the substrate 200A surrounded by the shielding wall structure 260B can remain connected to the other portions of the substrate 200A. The integrity of the substrate 200A can thus be maintained.

[0071] Figure 4A This is a schematic top view of the substrate 200A of the semiconductor package 500A, shown according to some embodiments of this disclosure. Figure 1 . Figure 4B It is along Figure 4AThe diagram shows a cross-sectional view along line A-A' of the substrate 200A of the semiconductor package 500A. Figure 4A and Figure 4B The structure and arrangement of the shielded wall structure 260C were also demonstrated. For the sake of brevity, [the text is incomplete and likely refers to a different topic]. Figure 1 , Figure 2A , Figure 2B , Figure 3A and Figure 3B Components of the same or similar embodiments previously described will not be repeated here. For illustration, Figure 4A Components below the passivation layer 230-1, except for the shielding wall structure 260C, are all omitted.

[0072] like Figure 4A and Figure 4B As shown, the shielding wall structure 260C can form a single closed pattern to surround integrated circuits (ICs) 102 and 104. Figure 1 The circuit wiring of the coupled substrate 200A includes at least one conductive trace 208, at least one via 212, and at least one conductive pad 214. In some embodiments, such as Figure 4A As shown, the shielding wall structure 260C forms a closed and continuous pattern without any breaks. The shielding wall structure 260C is separated from the sidewall 200AE of the substrate 200A. In other words, the shielding wall structure 260C is not exposed from the sidewall 200AE of the substrate 200A. In this embodiment, the shielding wall structure 260C may include, for example, Figure 4B The portions 260C1, 260C2, 260C3, and 260C4 are shown. Portion 260C1 has a height HC1. Portion 260C2 has a height HC2. Portion 260C3 has a height HC3. Portion 260C4 has a height HC4. For example, portions 260C1, 260C2, and 260C3 of the shielding wall structure 260C can pass through the redistribution layer (RDL) structure 210-1A and core 202. Portion 260C4 of the shielding wall structure 260C can pass through RDL structure 210-1A, core 202, and RDL structure 210-2A.

[0073] In this embodiment, portions 260C1, 260C2, and 260C3 of the shielding wall structure 260C are exposed from the top surface 200AT of the substrate 200A and the bottom surface 202B of the core 202. A portion 260C4 of the shielding wall structure 260C is exposed from the top surface 200AT of the substrate 200A and the bottom surface 200AB of the core 202. In this embodiment, the height HC1 of portion 260C1, the height HC2 of portion 260C2, and the height HC3 of portion 260C3 may have substantially the same value. Furthermore, the height HC4 of portion 260C4 is greater than the height HC1 of portion 260C1, the height HC2 of portion 260C2, and the height HC3 of portion 260C3. In this embodiment, the height HC4 may be greater than half the thickness H200A of the first substrate 200A. The heights HC1, HC2, and HC3 may be less than the thickness H200A of the substrate 200A.

[0074] In some embodiments, at least one portion of the shielding wall structure 260C (e.g., portions 260C1, 260C2, and 260C3) does not penetrate the substrate 200A to ensure the mechanical strength and structural stability of the substrate. In other words, at least one portion of the shielding wall structure 260C (e.g., portions 260C1, 260C2, and 260C3) has a height (e.g., heights HC1, HC2, and HC3) less than the thickness H200A of the substrate 200A to ensure the mechanical strength and structural stability of the substrate.

[0075] In this embodiment, since a portion 260C4 of the shielding wall structure 260C passes through the substrate 200A, portions 260C1, 260C2, and 260C3 of the shielding wall structure 260C can be designed not to pass through the RDL structure 210-2A of the substrate 200A with the embedded antenna 220, so that the portion of the substrate 200A surrounded by the shielding wall structure 260C can remain connected to the other portions of the substrate 200A. This maintains the integrity of the substrate 200A.

[0076] Figure 5A According to some embodiments of the present invention Figure 1 A schematic top view of the substrate 200A of the semiconductor package 500A shown. Figure 5B According to some embodiments of the present invention Figure 5A The diagram shows a cross-sectional view of the substrate 200A of the semiconductor package 500A along line A-A'. Figure 5A and Figure 5B The structure and arrangement of the shielded wall structure 260D (including shielded wall structures 260DA and 260DB) are also described. For the sake of brevity, [the following is a continuation of the previous sentence, but the translation is incomplete and cannot be translated accurately without further context]. Figure 1 , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A and Figure 4B Components that are the same or similar as those previously described in the references will not be repeated here. For illustration, Figure 5A Components below the 230-1 passivation layer (except for shielding wall structures 260DA and 260DB) are omitted.

[0077] like Figure 5A and Figure 5B As shown, the semiconductor package 500A may include multiple shielding wall structures 260DA and 260DB, embedded in the substrate 200A and coupled to the shielding layer 250. The shielding wall structures 260DA and 260DB may form a closed pattern spaced apart from each other to surround integrated circuits 102 and 104 (…). Figure 1 The circuitry of the coupled substrate 200A includes at least one conductive trace 208, at least one via 212, and at least one conductive pad 214. In some embodiments, such as Figure 5A As shown, shielding wall structures 260DA and 260DB each form a closed and continuous pattern without any breaks. Shielding wall structures 260DA and 260DB can be independent patterns, without intersection or interference between them. Shielding wall structures 260DA and 260DB are separated from the sidewall 200AE of the substrate 200A. In other words, shielding wall structures 260DA and 260DB are not exposed from the sidewall 200AE of the substrate 200A. In this embodiment, at least one of the shielding wall structures 260DA and 260DB is coupled to the shielding layer 250 through at least one conductive trace 208 of the substrate 200A, thereby forming an interconnected shielding structure to shield and protect the integrated circuit and related wiring. Therefore, in this embodiment of the invention, multiple independent shielding wall structures can be provided as needed for adaptive shielding protection.

[0078] like Figure 5BAs shown, in this embodiment, the shielding wall structure 260DA may include portions 260DA1 and 260DA2 having heights HDA1 and HDA2, respectively. The shielding wall structure 260DB may include portions 260DB1 and 260DB2 having heights HDB1 and HDB2, respectively. For example, portion 260DA1 of the shielding wall structure 260DA may pass through the RDL structure 210-1A and the core 202. Portion 260DA2 of the shielding wall structure 260DA may pass through one dielectric layer 206 of the RDL structure 210-1A. Portion 260DB1 of the shielding wall structure 260DB may pass through both dielectric layers 206 of the RDL structure 210-2A. Portion 260DB2 of the shielding wall structure 260DB may pass through the RDL structure 210-1A, the core 202, and the RDL structure 210-2A. In this embodiment, the height HDB2 of portion 260DB2 is greater than the height HDA1 of portion 260DA1. The height HDA1 of portion 260DA1 is greater than the height HDB1 of portion 260DB1. The height HDB1 of portion 260DB1 is greater than the height HDA2 of portion 260DA2. In this embodiment, heights HDA1 and HDB2 can be greater than half the thickness H200A of the first substrate 200A. Heights HDA2 and HDB1 can be less than half the thickness H200A of the substrate 200A.

[0079] In this embodiment, since a portion 260DB2 of the shielding wall structure 260DB passes through the substrate 200A, a portion 260DB1 of the shielding wall structure 260B can be designed not to pass through the substrate 200A, so that the portion of the substrate 200A surrounded by the shielding wall structure 260DB can remain connected to the other portions of the substrate 200A. The integrity of the substrate 200A can thus be maintained.

[0080] In some embodiments, Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B and Figure 5A , Figure 5B The number, shape (top view), and partial height of the shielding wall structures 260A, 260B, 260C, 260DA, and 260DB shown are merely examples and do not constitute a limitation on the present invention.

[0081] Figure 6 This is a schematic cross-sectional view of a semiconductor package 500B according to some embodiments of the present invention. For simplicity, it is... Figure 1 The same or similar embodiment components described previously will not be repeated here.

[0082] The semiconductor package 500B includes a substrate 200B, integrated circuits (ICs) 102 and 104, passivation layers 230-1 and 230-2, a connector assembly 106, a molding compound 110, a shielding layer 250, a substrate 300, an antenna 320, and a shielding wall structure 460.

[0083] like Figure 6 As shown, substrate 200B may include a multilayer packaging substrate. Substrate 200B can provide mechanical support and electrical (electrical) connections between integrated circuits (ICs) 102, 104 and conductive structures 222 attached to the top surface 200BT and bottom surface 200BB of substrate 200B. In some embodiments, substrate 200B includes a core 202 and redistribution layers (RDLs) 210-1B and 210-2B. Redistribution layer structures 210-1B and 210-2B are respectively disposed on the top surface 202T and bottom surface 202B of core 202. In some embodiments, each redistribution layer structure 210-1B and 210-2B includes conductive traces 208, vias 212 disposed in one or more dielectric layers 206, and conductive pads 214.

[0084] In this embodiment, each redistribution layer structure 210-1B and 210-2B includes a circuit consisting of conductive traces 208 and vias 212 formed in the dielectric layer 206 for electrical connections between integrated circuits (ICs) 102 and 104 on the redistribution layer structure 210-1B. In this embodiment, no antenna is provided in the redistribution layer structures 210-1B and 210-2B of the substrate 200B. Therefore, the substrate 200B can also be referred to as the wiring substrate for integrated circuits (ICs) 102 and 104.

[0085] In this embodiment, conductive traces 208 are formed in dielectric layers 206 of different layers. In some embodiments, the conductive layer 208 of each layer of the redistribution layer structures 210-1B and 210-2B may include power traces, signal traces, or ground traces for input / output (I / O) connections of integrated circuits 102 and 104.

[0086] like Figure 1 As shown, via 212 is disposed in the dielectric layer 206 of redistribution layers 210-1B and 210-2B. Via 212 can be formed through the dielectric layer 206 of redistribution layer structures 210-1B and 210-2B to couple to conductive traces 208 of different layers.

[0087] Conductive pads 214 are disposed near the top surface 200BT and bottom surface 200AB of substrate 200B. Conductive pads 214 are coupled to different terminals of conductive traces. Conductive pads 214 of redistribution layer structure 210-1B, near the top surface 200BT of substrate 200B, are used for direct mounting of integrated circuits 102 and 104 thereon. Conductive pads 214 of redistribution layer structure 210-2B, near the bottom surface 200BB of substrate 200B, are used for mounting conductive structures 222 thereon. Therefore, substrate 200B can be mounted and coupled to substrate 300 via conductive structures 222. In some embodiments, conductive structures 222 include conductive ball structures, such as copper balls, conductive bump structures, such as copper bumps or solder bump structures, or conductive pillar structures, such as copper pillar structures. For example, conductive structures 222 may be microbumps, controlled-collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, other suitable conductive connectors, or combinations thereof.

[0088] like Figure 6 As shown, the semiconductor package 500B further includes passivation layers 230-1 and 230-2 disposed on corresponding redistribution layer structures 210-1B and 210-2B. In addition, passivation layers 230-1 and 230-2 may have openings (not shown) to expose corresponding conductive pads 214 coupled to conductive traces 208.

[0089] Integrated circuits 102 and 104 are disposed on the top surface 200BT of substrate 200B and coupled to the conductive pad 214 of the redistribution layer structure 210-1B of substrate 200B through conductive structures 103 and 105.

[0090] like Figure 6 As shown, the semiconductor package 500B may further include a connector assembly 106 formed on the top surface 200BT of the substrate 200B. The connector assembly 106 may be adjacent to the integrated circuits 102 and 104. The connector assembly 106 may be coupled to the integrated circuits 102 and 104 through the redistribution layer structure 210-1B of the substrate 200B.

[0091] like Figure 6 As shown, molding compound 110 can partially cover substrate 200A and encapsulate integrated circuits 102 and 104. Furthermore, connector assembly 106 can be exposed from molding compound 110.

[0092] A shielding layer 250 is provided to cover the molding compound 110 and integrated circuits 102 and 104. Furthermore, the shielding layer 250 does not cover the sidewalls 200BE of the substrate 200B. The shielding layer 250 may extend to partially cover the redistribution layer structure 210-1B.

[0093] like Figure 6As shown, substrate 300 is mounted on the bottom surface 200BB of substrate 200B. Substrate 300 has a top surface 300T and a bottom surface 300B. The top surface 300T of substrate 300 faces the bottom surface 200BB of substrate 200B and provides a mounting surface for substrate 200B. In this embodiment, antenna 320 is disposed in substrate 300. Therefore, substrate 300 can also be referred to as antenna substrate. In this embodiment, shielding layer 250 does not cover the sidewall 300E of second substrate 300. Antenna 320 is disposed on substrate 300 to avoid the negative impact of shielding structure on antenna function and ensure normal operation of antenna.

[0094] In some embodiments, substrates 200A and 300 may have similar structures and arrangements, except that no shielding wall structure is embedded in substrate 300.

[0095] like Figure 6 As shown, in some embodiments, substrate 300 includes a core 302 and redistribution layers (RDLs) 310-1 and 310-2. Redistribution layer structures 310-1 and 310-2 are disposed on the top surface 302T and bottom surface 302B of the core 302, respectively. In some embodiments, each redistribution layer structure 310-1 and 310-2 includes a conductive trace 308, a via 312 disposed in one or more dielectric layers 306, and a conductive pad 314. Alternatively, substrate 300 may be manufactured without a core, and redistribution layer structure 310-1 may be laminated onto redistribution layer structure 310-2 (or vice versa).

[0096] In some embodiments, dielectric layers 206 and 306 may have the same or similar materials and structures. Conductive traces 208 and 308 may have the same or similar materials and structures. Vias 212 and 312 may have the same or similar materials and structures. Conductive pads 214 and 314 may have the same or similar materials and structures.

[0097] In some embodiments, the redistribution layer structure 310-1 includes electrical (circuit) wiring consisting of conductive traces 308 and vias 312 formed in a dielectric layer 306 for electrical connections between integrated circuits (ICs) 102 and 104 on the redistribution layer structure 310-1 and an antenna 320 in the redistribution layer structure 310-2. In some embodiments, the redistribution layer structure 310-2 includes an antenna 320 formed in the dielectric layer 306. The antenna 320 consists of a conductive layer, vias, and conductive pads. Furthermore, the redistribution layer structure 310-2 may further include a radiator, a feed line, other suitable components, or a combination thereof.

[0098] like Figure 6As shown, the semiconductor package 500B further includes passivation layers 330-1 and 330-2, which are disposed on the corresponding redistribution layer structures 310-1 and 310-2 of the substrate 300. Furthermore, passivation layer 330-1 may have an opening (not shown) to expose a corresponding conductive pad 314 coupled to the conductive trace 308. In some embodiments, passivation layers 230-1, 230-2, 330-1, and 330-2 may have the same or similar materials and structures.

[0099] like Figure 6 As shown, ICs 102 and 104, as well as connector assembly 106, can be disposed on the same surface (e.g., top surface 200BT) of substrate 200B, and can be arranged near the electrical wiring of redistribution layer structure 210-1B and away from antenna 320 of substrate 300. ICs 102 and 104, as well as connector assembly 106, can be arranged on the side of substrate 200B opposite to antenna 320 of substrate 300.

[0100] like Figure 6 As shown, the shielding wall structure 460 is embedded in the substrate 200B. The shielding wall structure 460 is exposed from the top surface 200BT and / or the bottom surface 200BB of the substrate 200B and is completely covered by passivation layers 230-1 and / or 230-2, respectively. Furthermore, the shielding wall structure 460 is coupled to the shielding layer 250. Additionally, the shielding wall structure 460 and the shielding layer 250 can be coupled via at least one ground trace of the substrate 200B (which is a portion of the conductive trace 208). The shielding wall structure 460 and the shielding layer 250 can prevent the antenna 320 from transmitting signals in the direction of the electrical wiring layers of ICs 102 and 104 and the redistribution layer structures 210-1B and 210-2B, thereby reducing electromagnetic interference. In this embodiment, the shielding wall structure 460 does not extend into the substrate 300, thereby avoiding or reducing the negative impact of the shielding structure on antenna operation.

[0101] In some embodiments, the shielding wall structure 460 may include a non-conductive material wall 405 and a conductive material 404. In some embodiments, the conductive material 404 may be formed as a thin conductive layer covering the sidewalls 405S and bottom surface 405B of the non-conductive material wall 405. In some embodiments, the non-conductive material walls 205 and 405 may have the same or similar materials and structures. In some embodiments, the conductive materials 204 and 404 may have the same or similar materials and structures.

[0102] The structure and arrangement of the shielding wall structure 460 will be Figure 7A and Figure 7B The explanation is as follows.

[0103] Figure 7A This is shown in some embodiments according to the present invention. Figure 1 A schematic top view of the substrate 200B of the semiconductor package 500B. Figure 7B This is shown in some embodiments according to the present invention. Figure 7A A cross-sectional view of the substrate 200B of the semiconductor package 500B along line A-A'. Figure 7A and Figure 7B The structure and arrangement of the shielding wall structure 460 are also explained. For the sake of brevity, [the following is a continuation of the previous sentence, which is not directly related to the previous sentence]. Figure 1 Components of the same or similar embodiments previously described in the references will not be repeated here. For illustration, Figure 7A The components below the passivation layer 230-1 are omitted, except for the shielding wall structure 460.

[0104] like Figure 7A and Figure 7B As shown, the shielding wall structure 460 can form a single closed pattern to surround integrated circuits (ICs) 102 and 104. Figure 1 The circuit wiring of the coupled substrate 200B includes at least one conductive trace 208, at least one via 212, and at least one conductive pad 214. In some embodiments, such as Figure 7A As shown, the shielding wall structure 460 forms a closed and continuous pattern without any breaks. The shielding wall structure 460 is separated from the sidewall 200BE of the substrate 200B. In other words, the shielding wall structure 460 is not exposed from the sidewall 200BE of the substrate 200B. In this embodiment, the shielding wall structure 460 may include portions 460-1 and 460-2 with different heights H-1 and H-2, such as... Figure 7BAs shown. For example, a portion 460-1 of the shielding wall structure 460 may pass through the redistribution layer (RDL) structure 210-1 and the core layer 202. A portion 460-2 of the shielding wall structure 460 may pass through the RDL structure 210-1, the core layer 202, and the RDL structure 210-2. In this embodiment, a portion 460-1 of the shielding wall structure 460 may be exposed from the top surface 200BT of the substrate 200B and the bottom surface 202B of the core layer 202. A portion 460-2 of the shielding wall structure 460 may be exposed from the top surface 200BT of the substrate 200B and the bottom surface 200BB of the core layer 202. In this embodiment, the height H-2 of portion 460-2 is greater than the height H-1 of portion 460-1. In this embodiment, the height H-2 may be greater than half the thickness H200B of the substrate 200B. The height H-1 may be less than the thickness H200B of the substrate 200B. In some embodiments, the height H-2 may be greater than half the thickness H200B of the substrate 200B, while the height H-1 may be less than or equal to half the thickness H200B of the substrate 200B. Since no antenna is embedded in the substrate 200B, at least a portion of the shielding wall structure 460 may pass through the substrate 200B to improve the shielding effect.

[0105] In this embodiment, since a portion 460-2 of the shielding wall structure 460 passes through the substrate 200B, a portion 460-1 of the shielding wall structure 460 can be designed not to pass through the substrate 200B (e.g., only the RDL structure 210-1B of the substrate 200B), so that the portion of the substrate 200B surrounded by the shielding wall structure 460 can remain connected to the other portions of the substrate 200B. This maintains the integrity of the substrate 200B.

[0106] In some embodiments, Figure 7A and Figure 7B The number, shape, grooves, and part of the height of the shielding wall structure 460 shown are merely examples and do not constitute a limitation on the content of this invention.

[0107] The following describes the methods for forming semiconductor packages 500A and 500B. Figure 8A , Figure 8B , Figure 8C , Figure 8D , Figure 8E , Figure 9A , Figure 9B , Figure 9C , Figure 9D and Figure 9E Schematic cross-sectional views of shielding wall structures 260A, 260B, 260C, 260DA, 260DB, and 460 at different stages in the substrates 200A and 200B (single unit) forming semiconductor packages 500A and 500B. Figure 2B , Figure 3B , Figure 4B , Figure 5B and Figure 7B As shown, for convenience, the embodiments of the present invention are not limited thereto. In some embodiments, the method of forming the shielding wall structure may form a periodically arranged shielding wall structure in a strip substrate.

[0108] Figure 8A and Figure 9A Schematic cross-sectional views of different stages in forming the shielding wall structure 260A of the semiconductor package 500A, according to some embodiments of the present invention, such as Figure 2B As shown.

[0109] like Figure 8A As shown, a substrate 200A is formed. In some embodiments, the substrate 200A may be in a strip shape to fabricate multiple package units. The process of forming the substrate 200A may include providing a core layer 202 having a top surface 202T and a bottom surface 202B. Then, RDL structures 210-1A and 210-2A, comprising a dielectric layer 206, conductive traces 208, vias 212, and conductive pads 214, are formed on the top surface 202T and bottom surface 202B of the core layer 202 by a stacking process. In some embodiments, an antenna 220 is formed near the bottom surface 200AB of the substrate 200A during the formation of the RDL structure 210-2A. Alternatively, when the substrate 200A is a coreless substrate, the process of forming the substrate 200A may include laminating the dielectric layer 206 of the RDL structure 210-2A onto the dielectric layer 206 of the RDL structure 210-1A (or vice versa).

[0110] Next, trenches 226A are formed in substrate 200A by a milling process. In some embodiments, trenches 226A form a closed pattern to define a shielding wall structure 260A. Figure 2A The location of the circuit wiring (including at least one conductive trace 208, at least one via 212 and at least one conductive pad 214) surrounding the substrate 200A coupled to the subsequently formed integrated circuits (ICs) 102 and 104.

[0111] In some embodiments, trench 226A may include portions 226A1 and 226A2. Portion 226A1 has a height HTA1. Portion 226A2 has a height HTA2. Heights HTA1 and HTA2 may be less than or equal to half the thickness H200A of substrate 200A. In this embodiment, heights HTA1 and HTA2 may have approximately the same value. For example, portions 226A1 and 226A2 of trench 226A may pass through RDL structure 210-1A and extend to a portion of core 202. Different portions of the shielding wall structure can be freely configured in height according to their respective nearby wiring or structures, improving design flexibility and adaptability.

[0112] Next, as Figure 9A As shown, conductive material 204 is formed on a portion of the top surface 200AT of substrate 200A and on the sidewalls and bottom surface of trench 226A through an electroplating process. That is, a lining of conductive material 204 is formed on the sidewalls and bottom surface of trench 226A. In some embodiments, conductive material 204 does not completely fill trench 226A.

[0113] Next, a non-conductive material wall 205 is formed through a deposition process and a subsequent etch-back process to fill the remaining space of the trench 226A, thereby forming a shielding wall structure 260A. In some embodiments, the height HA1 of a portion 260A1 (and the height HA2 of a portion 260A2) of the resulting shielding wall structure 260A is greater than the height HTA1 of a portion 226A1 (and the height HTA2 of a portion 226A2) of the trench 226A.

[0114] Next, as Figure 2A and 2B As shown, passivation layers 230-1 and 230-2 are formed on RDL structures 210-1A and 210-2A and shielding wall structure 260A through a deposition process and a subsequent patterning process.

[0115] Next, as Figure 1 As shown, integrated circuits 102 and 104, along with connector assembly 106, are mounted on the top surface 200AT of substrate 200A. Integrated circuits 102 and 104 are coupled to connector assembly 106 and antenna 220. Next, molding compound 110 of integrated circuits 102 and 104 is packaged by a molding process. Next, a shielding layer 250 is formed by a deposition process (e.g., sputtering) covering the molding compound 110 and the shielding wall structure 260A exposed from the top surface 200AT of substrate 200A. In some embodiments, shielding wall structure 260A is coupled to shielding layer 250.

[0116] Next, a dicing process is performed to cut the strip-shaped substrate 200A into individual units. Following the above process, as... Figure 1 As shown, this forms a separate semiconductor package 500A.

[0117] Figures 8B and 9B are schematic cross-sectional views of different stages in forming the shielding wall structure 260B of the semiconductor package 500A according to some embodiments of the present invention, such as... Figure 3B As shown.

[0118] like Figure 8B As shown, a substrate 200A is formed. Next, trenches 226B are formed in the substrate 200A by a milling process. In some embodiments, the trenches 226B form a closed pattern to define a shielding wall structure 260B. Figure 3A The location of the circuit (including at least one conductive trace 208, at least one via 212 and at least one conductive pad 214) surrounding the substrate 200A is coupled to the subsequently formed integrated circuits (ICs) 102 and 104.

[0119] In some embodiments, trench 226B may include portions 226B1 and 226B2 with different heights HTB1 and HTB2. For example, portion 226B1 of trench 226B may pass through RDL structure 210-1A and core 202, and stop on conductive trace 208 formed on the bottom surface 202B of core 202. Portion 226B2 of trench 226B may pass through RDL structure 210-1A, core 202, and RDL structure 210-2A. In this embodiment, the height HTB2 of portion 226B2 is greater than the height HTB1 of portion 226B1. Height HTB2 may be greater than half the thickness H200A of substrate 200A. Height HTB2 may be less than the thickness H200A of substrate 200A.

[0120] Next, as Figure 9B As shown, conductive material 204 is formed on the sidewalls and bottom surface of trench 226B through an electroplating process. This forms a lining of conductive material 204 on the sidewalls and bottom surface of trench 226B. In some embodiments, the conductive material 204 does not completely fill trench 226B.

[0121] Next, a non-conductive material wall 205 is formed through a deposition process and a subsequent etch-back process to fill the remaining space of the trench 226B, thereby forming a shielding wall structure 260B. In some embodiments, the heights HB1 and HB2 of portions 260B1 and 260B2 of the resulting shielding wall structure 260B are greater than the heights HTB1 and HTB2 of portions 226B1 and 226B2 of the trench 226B.

[0122] Next, as Figure 3A and 3B As shown, passivation layers 230-1 and 230-2 are formed on RDL structures 210-1A and 210-2A and shielding wall structure 260B through a deposition process and a subsequent patterning process.

[0123] Next, as Figure 1 As shown, integrated circuits 102 and 104, along with connector assembly 106, are mounted on the top surface 200AT of substrate 200A. Integrated circuits 102 and 104 are coupled to connector assembly 106 and antenna 220. Next, molding compound 110 encapsulates integrated circuits 102 and 104 through a molding process. Next, shielding layer 250 is formed through a deposition process (e.g., sputtering) covering molding compound 110 and shielding wall structure 260B exposed from the top surface 200AT of substrate 200A. In some embodiments, shielding wall structure 260B is coupled to shielding layer 250.

[0124] Next, a dicing process is performed to cut the strip-shaped substrate 200A into individual units. After the above process, as shown... Figure 1 As shown, a discrete semiconductor package 500A is formed.

[0125] Figure 8C and Figure 9C Based on some embodiments disclosed herein Figure 4B The diagram shows a schematic cross-sectional view of different stages in forming the shielding wall structure 260C of the semiconductor package 500A.

[0126] like Figure 8C As shown, a substrate 200A is formed. Next, trenches 226C are formed in the substrate 200A by a milling process. In some embodiments, the trenches 226C form a closed pattern to define a shielding wall structure 260C. Figure 4A The location of the circuit wiring (including at least one conductive trace 208, at least one via 212 and at least one conductive pad 214) around the substrate 200A is coupled to the subsequently formed integrated circuits (ICs) 102 and 104.

[0127] In this embodiment, trench 226C may include, for example, Figure 8CThe portions 226C1, 226C2, 226C3, and 226C4 are shown. Portion 226C1 has a height THC1. Portion 226C2 has a height HTC2. Portion 226C3 has a height HTC3. Portion 226C4 has a height HTC4. For example, portions 226C1, 226C2, and 226C3 of trench 226C may pass through RDL structure 210-1A and core 202, and stop on conductive trace 208 formed on the bottom surface 202B of core 202. Portion 226C4 of trench 226C may pass through RDL structure 210-1A, core 202, and RDL structure 210-2A. In this embodiment, the height HTC1 of portion 226C1, the height HTC2 of portion 226C2, and the height HTC3 of portion 226C3 may have approximately the same value. Furthermore, the height HTC4 of part 226C4 is greater than the height HTC1 of part 226C1, the height HTC2 of part 226C2, and the height HTC3 of part 226C3. The height HTC4 can be greater than half the thickness H200A of the substrate 200A. The heights HTC1, HTC2, and HTC3 can be less than the thickness H200A of the substrate 200A.

[0128] Next, as Figure 9C As shown, a conductive material 204 is formed by an electroplating process. The conductive material 204 is lined within the trench 226C and extends to portions of the top surface 200AT and bottom surface 200AB of the substrate 200A. In some embodiments, the conductive material 204 does not completely fill the trench 226C.

[0129] Next, a non-conductive material wall 205 is formed through a deposition process and a subsequent etch-back process to fill the remaining space of the trench 226C, thereby forming a shielding wall structure 260C. In some embodiments, the heights HC1, HC2, HC3, and HC4 of portions 260C1, 260C2, 260C3, and 260C4 of the resulting shielding wall structure 260C are greater than the heights HTC1, HTC2, HTC3, and HTC4 of portions 226C1, 226C2, 226C3, and 226C4 of the trench 226C.

[0130] Next, as Figure 4A and Figure 4B As shown, passivation layers 230-1 and 230-2 are formed on RDL structures 210-1A and 210-2A and shielding wall structure 260C through a deposition process and a subsequent patterning process.

[0131] Next, as Figure 1As shown, integrated circuits 102 and 104, along with connector assembly 106, are mounted on the top surface 200AT of substrate 200A. Integrated circuits 102 and 104 are coupled to connector assembly 106 and antenna 220. Next, molding compound 110 encapsulates integrated circuits 102 and 104 through a molding process. Next, shielding layer 250 is formed through a deposition process (e.g., sputtering) covering molding compound 110 and shielding wall structure 260C exposed from the top surface 200AT of substrate 200A. In some embodiments, shielding wall structure 260C is coupled to shielding layer 250.

[0132] Next, a dicing process is performed to cut the strip-shaped substrate 200A into individual units. After the above process, as shown... Figure 1 As shown, a discrete semiconductor package 500A is formed.

[0133] Figure 8D and Figure 9D Based on some embodiments disclosed herein Figure 5B The diagram shows schematic cross-sectional views of different stages in forming the shielding wall structures 260DA and 260DB of the semiconductor package 500A.

[0134] like Figure 8D As shown, a substrate 200A is formed. In this embodiment, a portion 260DA2 of the shielding wall structure 260DA is formed during the formation of the RDL layer structure 210-1. More specifically, a portion 226DA2 of a trench 226DA with a height HTDA2 is formed directly on the top surface 202T of the core 202 in the dielectric layer 206 and on the conductive trace 208 by a patterning process. Next, a portion of a conductive material 204 is formed by an electroplating process, the conductive material 204 lining the sidewalls and bottom surface of the portion 226DA2 of the trench 226DA. In some embodiments, the portion of the conductive material 204 does not fill the portion 226DA2 of the trench 226DA. Next, a portion of a non-conductive material wall 205 is formed by a deposition process and a subsequent etch-back process to fill the remaining space of the portion 226DA2 of the trench 226DA, thereby forming the portion 260DA2 of the shielding wall structure 260DA.

[0135] Next, the remaining portion of trench 226DA and trench 206DB are formed in substrate 200A by a milling process. In some embodiments, trenches 226DA and 226DB form closed patterns that are separated from each other to define shielding wall structures 260DA and 260DB. Figure 5A The circuit (including at least one conductive trace 208, at least one via 212 and at least one conductive pad 214) surrounding the substrate 200A is coupled to the subsequently formed integrated circuits (ICs) 102 and 104.

[0136] In this embodiment, trench 226DA may include portions 226DA1 and 226DA2 having heights HTDA1 and HTDA2. Trench 226DB may include portions 226DB1 and 226DB2 having heights HTDB1 and HTDB2. For example, portion 226DA1 of trench 226DA may pass through RDL structure 210-1A and core 202 and stop on conductive trace 208 formed on the bottom surface 202B of core 202. Portion 226DA2 of trench 226DA may pass through one dielectric layer 206 of RDL structure 210-1A and stop on conductive trace 208 formed on the top surface 202T of core 202. Portion 226DB1 of trench 226DB may pass through both dielectric layers 206 of RDL structure 210-2A and stop on another conductive trace 208 formed on the bottom surface 202B of core 202. A portion 226DB2 of trench 226DB can pass through RDL structure 210-1A, core 202, and RDL structure 210-2A. In this embodiment, the height HTDB2 of portion 226DB2 is greater than the height HTDA1 of portion 226DA1. The height HTDA1 of portion 226DA1 is greater than the height HTDB1 of portion 226DB1. The height HTDB1 of portion 226DB1 is greater than the height HTDA2 of portion 226DA2. Heights HTDA1 and HTDB2 can be greater than half the thickness H200A of substrate 200A. Heights HTDA2 and HTDB1 can be less than half the thickness H200A of substrate 200A.

[0137] Next, as Figure 9D As shown, the remaining portion of the conductive material 204 is formed, which is lined within the remaining portions of trenches 226DB and 226DA, and extends to portions of the top surface 200AT and / or bottom surface 200AB of the substrate 200A. In some embodiments, the remaining portion of the conductive material 204 does not completely fill the remaining portions of trenches 226DA and 226DB.

[0138] Next, the remaining portion of the non-conductive material wall 205 is formed through a deposition process and a subsequent etching rollback process to fill the remaining space of the remaining portions of trenches 226DB and 226DA, thereby forming shielding wall structures 260DA and 260DB. In some embodiments, the heights HDA1 and HDA2 of portions 260DA1 and 260DA2 of the resulting shielding wall structure 260DA are greater than the heights HTDA1 and HTDA2 of portions 226DA1 and 226DA2 of trench 226DA. The heights HDB1 and HDB2 of portions 260DB1 and 260DB2 of the resulting shielding wall structure 260DB are greater than the heights HTDB1 and HTDB2 of portions 226DB1 and 226DB2 of trench 226DB.

[0139] Next, as Figure 5A and 5B As shown, passivation layers 230-1 and 230-2 are formed on RDL structures 210-1A and 210-2A and shielding wall structures 260DA and 260DB through a deposition process and a subsequent patterning process.

[0140] Next, as Figure 1 As shown, integrated circuits 102 and 104, along with connector assembly 106, are mounted on the top surface 200AT of substrate 200A. Integrated circuits 102 and 104 are coupled to connector assembly 106 and antenna 220. Next, molding compound 110 of integrated circuits 102 and 104 is packaged by a molding process. Next, one or more shielding layers 250 are formed by a deposition process (e.g., sputtering) covering the molding compound 110 and shielding wall structures 260DA and 260DB exposed from the top surface 200AT of substrate 200A. In some embodiments, shielding wall structures 260DA and 260DB are coupled to shielding layer 250.

[0141] Next, a dicing process is performed to cut the strip substrate 200A into individual units. After the above process, a structure is formed as shown below. Figure 1 The discrete semiconductor package shown is 500A. Figure 8E and Figure 9E Based on some embodiments disclosed herein Figure 7B The diagram shows schematic cross-sectional views of different stages in forming the shielding wall structure 460 of the semiconductor package 500B. Figure 8E As shown, a substrate 200B is formed. In some embodiments, the substrate 200B may be in a strip shape to fabricate multiple package units. The process of forming the substrate 200B may include providing a core 202 having a top surface 202T and a bottom surface 202B. Next, RDL structures 210-1B and 210-2B, comprising a dielectric layer 206, conductive traces 208, vias 212, and conductive pads 214, are formed on the top surface 202T and bottom surface 202B of the core 202 by a stacking process.

[0142] Next, trenches 426 are formed in substrate 200B by a milling process. In some embodiments, trenches 426 form a closed pattern to define a shielding wall structure 460. Figure 3AThe trench 426 is positioned to surround circuit wiring (including at least one conductive trace 208, at least one via 212, and at least one conductive pad 214) of the substrate 200B coupled to subsequently formed integrated circuits (ICs) 102 and 104. In some embodiments, the trench 426 may include portions 426-1 and 426-2 with different heights HT-1 and HT-2. For example, portion 426-1 of the trench 426 may pass through the RDL structure 210-1B and the core 202 and stop on the conductive trace 208 formed on the bottom surface 202B of the core 202. Portion 426-2 of the trench 426 may pass through the RDL structure 210-1B, the core 202, and the RDL structure 210-2B. In this embodiment, the height HT-2 of portion 426-2 is greater than the height HT-1 of portion 426-1. The height HT-2 may be greater than half the thickness H200B of the substrate 200B. The height HT-1 may be less than the thickness H200B of the substrate 200B.

[0143] Next, as Figure 9E As shown, a conductive material 404 is formed through an electroplating process. The conductive material 404 is lined within the trench 426 and extends to portions of the top surface 200BT and / or bottom surface 200BB of the substrate 200B. In some embodiments, the conductive material 204 does not completely fill the trench 426. Next, a non-conductive material wall 405 is formed through a deposition process and a subsequent etch-back process to fill the remaining space in the trench 426, thereby forming a shielding wall structure 460. In some embodiments, the heights H-1 and H-2 of portions 460-1 and 460-2 of the resulting shielding wall structure 460 are greater than the heights HT-1 and HT-2 of portions 426-1 and 426-2 of the trench 426.

[0144] Next, as Figure 7A and Figure 7B As shown, passivation layers 230-1 and 230-2 are formed on the RDL structures 210-1B and 210-2B and the shielding wall structure 460 through a deposition process and subsequent patterning process. Next, as... Figure 1As shown, ICs 102 and 104, along with connector assembly 106, are mounted on the top surface 200BT of substrate 200B. ICs 102 and 104 are coupled to connector assembly 106 and antenna 220. Next, molding compound 110 of ICs 102 and 104 is packaged by a molding process. Next, a shielding layer 250 is formed by a deposition process (e.g., sputtering) covering molding compound 110 and shielding wall structure 460 exposed from the top surface 200BT of substrate 200B. In some embodiments, shielding wall structure 460 is coupled to shielding layer 250. Next, an intermediate structure comprising substrate 200B, shielding wall structure 460, passivation layers 230-1 and 230-2, ICs 102 and 104, connector assembly 106, molding compound 110, and shielding layer 250 is mounted on substrate 300 comprising antenna 320 via conductive structure 222.

[0145] Next, a dicing process is performed to cut the strip substrate 200A into individual units. After the above process, a structure is formed as shown below. Figure 1 The discrete semiconductor package shown is 500A.

[0146] The embodiments provide a semiconductor package and a method of forming a semiconductor package (e.g., semiconductor packages 500A and 500B), such as an antenna (AiM / AiP) in a module / package. The semiconductor package includes shielding wall structures (e.g., shielding wall structures 260A, 260B, 260C, 260D, and 460) embedded in a substrate (e.g., substrate 200) and coupled to a shielding layer (e.g., shielding layer 250) that shields one or more integrated circuits (e.g., ICs 102 and 104) disposed on the substrate. The shielding wall structure may serve as an extension of the shielding layer to surround circuit wiring (e.g., at least one conductive trace 208, at least one via 212, and at least one conductive pad 214) of the substrate coupled to the integrated circuits. Therefore, the shielding layer does not need to cover the sidewalls of the substrate (e.g., sidewall 200AE of substrate 200A and sidewall 200BE of substrate 200B). In some embodiments, the shielding wall structure can be formed by plating a conductive material (e.g., conductive material 204) in trenches (e.g., trenches 226A, 226B, 226C, 226DA, 226DB, and 426) created in the substrate before forming the shielding layer. Therefore, the height of the shielding wall structure (e.g., heights HA1, HA2, HB1, HB2, HC1, HC2, HC3, HC4, HD1, HD2, H-1, H-2) can be precisely controlled by the height of the trenches (e.g., heights HTA1, HTA2, HTB1, HTB2, HTC1, HTC2, HTC3, HTC4, HTD1, HTD2, HT-1, HT-2). In some embodiments, the number, top view shape, and height of the shielding wall structures can be varied according to the product design. The fabrication process of the shielding wall structure can be integrated into the substrate fabrication process, thus reducing tooling costs and tooling maintenance costs for partial shielding. Furthermore, periodically arranged shielding wall structures can be formed simultaneously in a strip substrate. After the shielding wall structure, integrated circuit, and shielding layer are formed, discrete semiconductor packaging units are created. Therefore, the method for forming semiconductor packages can achieve high throughput.

[0147] This invention provides a semiconductor package. The semiconductor package includes a first substrate, a first integrated circuit (IC), an antenna, a molding compound, a shielding layer, and a first shielding wall structure. The first substrate includes a first surface and a second surface opposite to each other. The antenna is located near the first surface of the first substrate. The first integrated circuit (IC) is mounted on the second surface of the first substrate and coupled to the antenna. The molding compound encapsulates the first IC. The shielding layer covers the molding compound. The first shielding wall structure is embedded in the first substrate and coupled to the shielding layer.

[0148] In some embodiments, the first shielding wall structure includes a non-conductive material wall and a conductive material. The conductive material covers the sidewalls and bottom surface of the non-conductive material wall.

[0149] In some embodiments, the first shielding wall structure is exposed from the first substrate and is completely covered by a passivation layer.

[0150] In some embodiments, the first shielding wall structure is separated from the sidewall of the first substrate.

[0151] In some embodiments, the first shielding wall structure is coupled to the ground trace of the first substrate.

[0152] In some embodiments, the first shielding wall structure forms a closed pattern to surround at least one conductive trace of a first substrate coupled to the first integrated circuit.

[0153] In some embodiments, the first shielding wall structure includes a first portion having a first height and a second portion having a second height.

[0154] In some embodiments, the first substrate includes a core, a first dielectric layer, and a second dielectric layer. The core has a third surface and a fourth surface. The third surface is adjacent to the first surface of the first substrate, and the fourth surface is adjacent to the second surface of the first substrate. The first dielectric layer is disposed on the third surface of the core. The second dielectric layer is disposed on the fourth surface of the core.

[0155] In some embodiments, the antenna is formed in a dielectric layer of a first substrate away from the first integrated circuit.

[0156] In some embodiments, the first height and the second height are the same, and the first and second portions of the first shielding wall structure pass through at least one first dielectric layer and are embedded in the core of the first substrate. The first height and the second height are less than or equal to half the thickness of the first substrate.

[0157] In some embodiments, the first height is greater than the second height, and a first portion of the first shielding wall structure passes through at least one first dielectric layer, a core, and at least one second dielectric layer. The first height and the second height are less than or equal to half the thickness of the first substrate.

[0158] In some embodiments, the first height is greater than the second height, and a second portion of the first shielding wall structure passes through at least one first dielectric layer or at least one second dielectric layer. The second height is less than the thickness of the first substrate.

[0159] In some embodiments, the semiconductor package further includes a second shielding wall structure embedded in a substrate and coupled to a shielding layer. The first shielding wall structure and the second shielding wall structure are separated from each other.

[0160] In some embodiments, at least one of the first shielding wall structure and the second shielding wall structure is coupled to the shielding layer through at least one conductive trace on the first substrate.

[0161] In some embodiments, each of the first and second shielding wall structures forms a closed pattern to surround at least one conductive line of the first substrate coupled to the first integrated circuit.

[0162] In some embodiments, the semiconductor package further includes a second substrate mounted on a first surface of the first substrate. An antenna is disposed in the second substrate.

[0163] In some embodiments, the first shielding wall structure does not extend into the second substrate.

[0164] In some embodiments, the shielding wall structure forms a closed and continuous pattern without any breaks.

[0165] In some embodiments, at least one portion of the shielding wall structure has a height less than the thickness of the substrate.

[0166] This invention provides a method for forming a semiconductor package. The method includes forming a first substrate. The first substrate includes a first surface and a second surface opposite to each other. The method further includes forming a first shielding wall structure embedded in the first substrate. The method further includes forming an antenna near the first surface of the substrate. The method further includes mounting a first integrated circuit (IC) on the second surface of the first substrate and coupling it to the antenna. The method further includes forming a molding compound to encapsulate the first IC. The method further includes forming a shielding layer covering the molding compound, wherein the first shielding wall structure is coupled to the shielding layer.

[0167] In some embodiments, forming the first substrate includes providing a core having a third surface and a fourth surface. The third surface is adjacent to the first surface of the first substrate, and the fourth surface is adjacent to the second surface of the first substrate. Forming the first substrate includes forming a first dielectric layer on the third surface of the core. Forming the first substrate includes forming a second dielectric layer on the fourth surface of the core. In some embodiments, forming the first substrate includes laminating a dielectric layer. In some embodiments, the method further includes forming a trench in the first substrate, wherein the trench forms a closed pattern to surround at least one conductive trace of the first substrate coupled to the first IC. The method further includes forming a conductive material lining the sidewalls and bottom surface of the trench. The method further includes filling the trench with a non-conductive material to form the first shielding wall structure. The method further includes forming a passivation layer on the first shielding wall structure.

[0168] While the invention has been described by way of example and according to preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and similar arrangements (as will be apparent to those skilled in the art). Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims

1. A semiconductor package, characterized by, include: The first substrate includes a first surface and a second surface that are opposite to each other; The antenna is located near the first surface of the first substrate; A first integrated circuit is mounted on the second surface of the first substrate and coupled to the antenna; A molding compound is used to encapsulate the first integrated circuit; A shielding layer covering the molding compound; as well as The first shielding wall structure is embedded in the first substrate and coupled to the shielding layer.

2. The semiconductor package of claim 1, wherein, The first shielding wall structure includes: Non-conductive material walls; and Conductive material is used to cover the sidewalls and bottom surface of the non-conductive material wall.

3. The semiconductor package of claim 1, wherein, The first shielding wall structure is separated from and does not contact the sidewall of the first substrate.

4. The semiconductor package of claim 1, wherein, The first shielding wall structure is coupled to the grounding trace of the first substrate.

5. The semiconductor package of claim 1, wherein, The first shielding wall structure forms a closed and continuous pattern without any breaks, surrounding at least one conductive trace of the first substrate coupled to the first integrated circuit.

6. The semiconductor package of claim 1, wherein, The first shielding wall structure includes: The first part having the first height; and The second part has a second height; The first height is the same as the second height, and the first height and the second height are less than or equal to half the thickness of the first substrate; or, the first height is greater than the second height, and the first height is greater than half the thickness of the first substrate, while the second height is less than the thickness of the first substrate.

7. The semiconductor package of claim 1, wherein the semiconductor package is a flip chip semiconductor package. Further includes: A second shielding wall structure is embedded in the first substrate and coupled to the shielding layer, wherein the first shielding wall structure and the second shielding wall structure are separated from each other.

8. The semiconductor package of claim 1, wherein, Further includes: A second substrate is mounted on the first surface of the first substrate, wherein the antenna is disposed in the second substrate.

9. A method of forming a semiconductor package, comprising: include: A first substrate is formed, comprising a first surface and a second surface that are opposite to each other; A first shielding wall structure is formed and embedded in the first substrate; An antenna is formed near the first surface of the substrate; The first integrated circuit is mounted on the second surface of the first substrate and coupled to the antenna; The first integrated circuit is packaged using a molding compound. as well as A shielding layer is formed to cover the molding compound, wherein the first shielding wall structure is coupled to the shielding layer.

10. The method for forming a semiconductor package as described in claim 9, characterized in that, Further includes: A trench is formed in a first substrate, wherein the trench forms a closed pattern to surround at least one conductive trace of the first substrate coupled to a first integrated circuit; A conductive material is formed as a lining on the sidewalls and bottom surface of the trench; The trench is filled with a non-conductive material to form a first shielding wall structure; And a passivation layer is formed on the first shielding wall structure.

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