Chip structure with multiple layers of core particles

Abstract

The invention discloses a multi-layer core particle chip structure, and belongs to the field of semiconductor chip design. The invention provides the types of core particles forming the whole chip, the geometric layout of interfaces among the core particles, and the geometric layout and the connection relation when multiple core particles form the whole chip aiming at several types of multi-core-particle chips. According to the geometric layout of the multi-core-particle chips and the core particle interfaces disclosed by the invention, the core particles have the characteristics of short connecting lines, uniform length and no intersection during integration, and design and manufacturing of the core particles and interface circuits as well as design and manufacturing of intermediate layers are facilitated.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip design and manufacturing, and in particular to multilayer chip structures. Background Technology

[0002] In semiconductor manufacturing processes, chip size is limited to 800mm due to constraints such as light source power, photomask size, and chip yield. 2 Approximately 2nm. Therefore, reducing the feature size of transistors to increase integration density has always been the main approach to advancing chip manufacturing processes. However, in recent years, the feature size of transistors has reached the 2nm level, approaching the limits of quantum materials, and can no longer support the continued advancement of Moore's Law. Against this backdrop, advanced packaging technology has come to the forefront, becoming an important technical means to support the continued advancement of chip scale. Currently, advanced packaging technologies mainly include chiplet integration and 3D-IC packaging. Chiplet integration mainly emphasizes the use of silicon interposers to achieve high-density, high-bandwidth, short-distance interconnections between dies; 3D-IC mainly emphasizes the use of through-silicon via (TSV) technology to penetrate the die's interconnects from the top surface to the bottom surface of the silicon substrate, thereby achieving top-to-bottom interconnections of multiple dies. Figure 1 As shown. In fact, silicon interposers are also used in 3D-ICs, and 3D-ICs are also a type of chip integration.

[0003] Due to the use of high-precision photolithography and silicon manufacturing processes, the main characteristics of silicon interposers (TIS) and TSV interconnects are: high interconnect density, short interconnect distance, and wide interconnect bandwidth (i.e., high frequency). High interconnect density means that thousands of interconnects can be accommodated between chips, allowing the circuitry that would otherwise be contained in a single chip (die) to be distributed across two chips; short interconnect distance means lower drive capability requirements and lower power consumption for the interface circuitry; and wide interconnect bandwidth means that it can support a large amount of information exchange between chips.

[0004] Generally, information exchange between cores is bidirectional. Functionally, information exchange requires an initiator (Master) and a responder (Slave). Bidirectional information exchange necessitates that each core has a Master and a Slave, such as... Figure 2 As shown in (a). From a circuit perspective, information exchange requires a sender (Tx) and a receiver (Rx). Two-way information exchange requires each chip to have a Tx and an Rx, as shown in (a). Figure 2 As shown in (b). Assuming that Tx corresponds to Master and Rx corresponds to Slave, we only label Tx and Rx, and no longer label Master and Slave.

[0005] Figure 3 A chip and its interface layout are shown. Figure 3 The circuit contains four chips (Chiplet 1, Chiplet 2, Chiplet 3, and Chiplet 4), all connected in pairs. The connection between Chiplet 1 and Chiplet 3 overlaps with the connection between Chiplet 2 and Chiplet 4. In manufacturing, this overlap necessitates the use of TSV technology to implement partial interconnects on the back side of the silicon interposer, increasing manufacturing costs. Compared to other non-overlapping connections (between Chiplet 1 and Chiplet 2, Chiplet 2 and Chiplet 3, Chiplet 3 and Chiplet 4, and Chiplet 4 and Chiplet 1), this increases the connection length, requires greater drive capability from the interface circuitry, and may result in a lower switching frequency. Therefore, from a circuit perspective, the drive circuits for the cross-connections and the non-cross-connections are asymmetrical, increasing the complexity of the circuit design.

[0006] On the other hand, generally speaking, the area of ​​the chip is relatively large, and the design and manufacturing cost is high. Therefore, when the chip is integrated into the whole chip, as few types of chips as possible should be used. Ideally, the same type of chip should be used as much as possible, which can effectively reduce the design cost. Summary of the Invention

[0007] Based on the above problems, this invention proposes a multi-layer chip structure, which makes the interconnections on the silicon interposer simple, symmetrical and non-intersecting during chip integration. This reduces the manufacturing cost of the silicon interposer, reduces the types of chips, simplifies the types of chip interface circuits, and lowers chip design costs, thereby reducing the overall cost of the integrated chip.

[0008] The technical solution adopted in this invention is as follows:

[0009] A multi-layer chip structure includes multiple chips, with the Tx and Rx interfaces of each chip located in the center of the chip in the form of TSVs. The chips are stacked, and in the stacked state, the even-numbered chips are rotated 180 degrees clockwise to align the Tx interfaces of the odd-numbered chips with the Rx interfaces of the even-numbered chips, and vice versa.

[0010] A multi-layer chip structure includes multiple chips, each chip having a Tx interface and an Rx interface on both its left and right sides, and both the Tx interface and the Rx interface are configured in TSV form. The TSVs on both sides of the core are rotationally symmetrical; the cores of the odd-numbered layers are exactly the same as those of the even-numbered layers; the cores are stacked, and in the stacked state, the cores of the even-numbered layers are rotated 180 degrees clockwise from the cores of the odd-numbered layers, so that the Tx interface of the odd-numbered cores is aligned with the Rx interface of the even-numbered cores, and the Tx interface of the even-numbered cores is aligned with the Rx interface of the odd-numbered cores.

[0011] The beneficial effects of this invention are as follows: The interface between the chips in this invention is simple and consistent, with no cross-connections, and the design and manufacturing of the interposer layer are simple; there are few types of chips, and the design and manufacturing cost of the entire chip is low. Attached Figure Description

[0012] Figure 1 This is a schematic diagram showing multiple layers and multiple cores interconnected through TSVs and interposers; Figure 2 This is a schematic diagram of the interface between the core particles, in which, Figure 2 (a) is a schematic diagram of the initiation / response interface. Figure 2 (b) is a schematic diagram of the send / receive interface; Figure 3 This is a schematic diagram of an interface layout that leads to wire crossings; Figure 4 This is a schematic diagram of the geometric layout of the dual-chip and chip interface; Figure 5 This is a schematic diagram of the geometric layout of the four-chip assembly and its interface. Figure 6 This is a schematic diagram of the geometric layout of the TSV interface of the first type of multilayer chip; Figure 7 This is a schematic diagram of the geometric layout of the TSV interface of the second type of multilayer chip; Figure 8 This is a schematic diagram of the geometric layout of a nine-core chip; Figure 9 This is a schematic diagram of the geometric layout of the chip interface; Figure 10 This is a schematic diagram of the geometric layout of the first type of 25-core chip; Figure 11 This is a schematic diagram of the geometric layout of the second type of core interface; Figure 12 This is a schematic diagram of the geometric layout of the second type of 25-core chip; Figure 13 This is a schematic diagram of the geometric layout of a 49-chip assembly. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0014] Reference Figure 4 , Figure 4 The geometric layout of the dual-chip and chip interface is given. Figure 4 In this design, the dual-chip system comprises Chiplet 1 and Chiplet 2. Each chip has an inter-chip interface (Tx and Rx interfaces), an L1 interface for DDR and High Bandwidth Memory (HBM), and an L2 interface for peripherals. Chiplet 1 and Chiplet 2 are symmetrically positioned; in terms of orientation, Chiplet 2 is essentially a 180-degree rotation of Chiplet 1. Therefore, only one type of chip needs to be designed.

[0015] Reference Figure 5 , Figure 5 The geometric layout of the four-chip array and its interface is given. Figure 5 The four-chip design includes Chiplet 1, Chiplet 2, Chiplet 3, and Chiplet 4. The Tx and Rx interfaces are inter-chip interfaces, L1 is the DDR and High Bandwidth Memory (HBM) interface, and L2 is the peripheral interface. Chiplet 1, Chiplet 2, Chiplet 3, and Chiplet 4 are arranged in a 2×2 rectangular array. In terms of orientation, Chiplet 2 is essentially a 90-degree rotation of Chiplet 1, Chiplet 3 is a 180-degree rotation of Chiplet 1, and Chiplet 4 is a 270-degree rotation of Chiplet 1. Therefore, only one type of chip needs to be designed.

[0016] Reference Figure 6 , Figure 6 The first type of multilayer chip TSV geometry layout is presented. Figure 6 In this design, multiple layers of core chips are stacked. The Tx and Rx interfaces, serving as TSV interfaces between the multiple layers, are located at the center of the core chip. Odd-numbered and even-numbered core chips are symmetrical, with even-numbered core chips being 180 degrees rotated from odd-numbered core chips. Therefore, only one type of core chip needs to be designed. Additionally, L1, L2, and peripheral interfaces reside on other core chips.

[0017] Reference Figure 7 , Figure 7 The TSV geometry layout of the second type of multilayer chip is presented. Figure 7In this design, multiple layers of core chips are stacked. Tx and Rx interfaces, serving as TSV interfaces between these layers, are located on both sides of the core chip. Odd-numbered and even-numbered core chips are symmetrical, with even-numbered core chips being a 180-degree rotation of the odd-numbered core chips. Therefore, only one type of core chip needs to be designed. Additionally, L1, L2, and peripheral interfaces reside on other core chips.

[0018] Reference Figure 8 , Figure 8 The nine-chip structure and its interface geometry are presented. It comprises nine chips: eight peripheral chips and one central chip, arranged in a 3×3 configuration. The eight peripheral chips are processing unit chips (Chiplet 1 to Chiplet 8), and the central chip is the cache coherence chip. Figure 9 As shown, NoC (Network-on-Chip) is the interface between these two types of chips. NoC includes both Tx and Rx interfaces. DDR / HBM and peripheral interfaces are not included in these 9 chips; additional NoC interface chips can be added to L1 and L2. Therefore, to construct the entire chip, a total of 3 types of chips need to be designed.

[0019] Reference Figure 10 , Figure 10 The first type of 25-chip structure and its interface geometry are presented. It consists of 25 chips arranged in a 5×5 rectangular array. The chip types are: Chiplet(a, b), where 1 ≤ a ≤ 5, 1 ≤ b ≤ 5, and a and b are both positive integers, where a represents the row number of the chip and b represents the column number. The 25 chips are divided into three categories. The first category consists of processing unit chips, including Chiplet(1,1), Chiplet(1,3), Chiplet(1,5), Chiplet(2,2), Chiplet(2,3), Chiplet(2,4), Chiplet(3,2), Chiplet(3,4), Chiplet(4,2), and Chiplet(4,2). (4,3), Chiplet (4,4), Chiplet (5,1), Chiplet (5,3), Chiplet (5,5), and the chip has Figure 9The chip interface shown is shown; the second type is a processing unit chip, which includes chiplets (1,2), (1,4), (2,1), (2,5), (4,1), (4,5), (5,2), and (5,4), and the chiplet has... Figure 11 The chip interface shown; the third type is the Cache Coherence Chiplet, which is a chiplet (3,3). Figure 11 In this context, L1 and L2 interfaces include not only DDR and HBM interfaces but also peripheral interfaces. To construct a complete chip, a total of three types of chips need to be designed during the chip design process.

[0020] Reference Figure 12 , Figure 12 The second type of 25-chip and chip interface geometry layout is presented. Figure 12 It includes 25 chips: 24 peripheral chips and 1 central chip, arranged in a 5x5 pattern. The central chip handles cache coherency among the 24 peripheral chips. Each chip uses a NoC interface, distributed around its top, bottom, left, and right sides. The first type is the processing unit chip (Chiplet 1~24), and this chip has... Figure 9 The first type is the chip interface shown; the second type is the cache coherence chip. For example... Figure 9 As shown, NoC represents the interface between these two types of chips. DDR, HBM, and peripheral interfaces are not included in these 25 chips; additional NoC interface chips can be added to L1 and L2. Therefore, to construct the entire chip, a total of three types of chips need to be designed during the chip design phase.

[0021] Reference Figure 13 , Figure 13The first type of 49-chip and its interface geometry are presented. It consists of 49 chips arranged in a 7×7 rectangular array. The chip types are: Chiplet(a, b), where 1 ≤ a ≤ 7, 1 ≤ b ≤ 7, and a and b are both positive integers, where a represents the row number of the chip and b represents the column number. The 49 chips are divided into three categories. The first category consists of processing unit chips, including Chiplet(1,1), Chiplet(1,4), Chiplet(1,7), Chiplet(2,2), Chiplet(2,3), Chiplet(2,4), Chiplet(2,5), Chiplet(2,6), Chiplet(3,2), Chiplet(3,3), Chiplet(3,4), Chiplet(3,5), and Chiplet(3,6). (3,6), Chiplet (4,1), Chiplet (4,2), Chiplet (4,3), Chiplet (4,4), Chiplet (4,5), Chiplet (4,6), Chiplet (4,7), Chiplet (5,2), Chiplet (5,3), Chiplet (5,4), Chiplet (5,5), Chiplet (5,6), Chiplet (6,2), Chiplet (6,3), Chiplet (6,4), Chiplet (6,5), Chiplet (6,6), Chiplet (7,1), Chiplet (7,2), Chiplet (7,3), Chiplet (7,4), Chiplet (7,5), Chiplet (7,6), Chiplet (7,7), and the chip has Figure 9The chip interface shown is shown; the second type is a processing unit chip, which includes chiplets (1,2), (1,3), (1,5), (1,6), (2,1), (2,7), (3,1), (3,7), (5,1), (5,7), (6,1), (6,7), (7,2), (7,3), (7,5), and (7,6), and the chiplet has... Figure 11 The chip interface shown; the third type is the Cache Coherence Chiplet, which is a chiplet (4,4). Figure 11 In this context, L1 and L2 interfaces include not only DDR and HBM interfaces but also peripheral interfaces. To construct a complete chip, a total of three types of chips need to be designed during the chip design process.

[0022] With 49 chips together, the area is close to that of a 300mm diameter wafer, so no additional interface chips are usually integrated.

[0023] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A multilayer chip structure, characterized in that, It includes multiple cores, and the Tx and Rx interfaces of the cores are both located in the center of the core in the form of TSV. The cores are stacked. In the stacked state, the even-numbered cores are rotated 180 degrees clockwise to the odd-numbered cores, so that the Tx interface of the odd-numbered cores is aligned with the Rx interface of the even-numbered cores, and the Tx interface of the even-numbered cores is aligned with the Rx interface of the odd-numbered cores.

2. A multilayer chip structure, characterized in that, It includes multiple cores, and each core has a Tx interface and an Rx interface on both the left and right sides, and both the Tx interface and the Rx interface are set in TSV form; The TSVs on both sides of the core are rotationally symmetrical; the cores of the odd-numbered layers are exactly the same as those of the even-numbered layers; the cores are stacked, and in the stacked state, the cores of the even-numbered layers are rotated 180 degrees clockwise from the cores of the odd-numbered layers, so that the Tx interface of the odd-numbered cores is aligned with the Rx interface of the even-numbered cores, and the Tx interface of the even-numbered cores is aligned with the Rx interface of the odd-numbered cores.

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