Semiconductor package and related methods

Abstract

The invention relates to a semiconductor package and a related method. An embodiment discloses a method for forming a semiconductor package. The method includes providing a first insulator layer coupled with a first metal layer. A recess is formed in the first metal layer, and the semiconductor die is mechanically coupled therein. The die is mechanically coupled with the second metal layer, and the second metal layer is coupled with the second insulator layer. The die and the layer are at least partially encapsulated to form the semiconductor package. The first metal layer and / or the second metal layer may be an insulator-metal substrate, a metal-insulator-metal (MIM) substrate, or may be formed from a lead frame. In an embodiment, the package does not include a spacer between the die and the first metal layer, and does not include a spacer between the die and the second metal layer. In embodiments, the first insulator layer and the second insulator layer are exposed by an encapsulant, or mechanically coupled with a metal layer exposed by an encapsulant.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 202011210389.4, filed on November 3, 2020, entitled "Semiconductor Package and Related Method". Technical Field

[0002] This document relates in general to semiconductor packages. More specific embodiments relate to substrates used to form semiconductor packages. Background Technology

[0003] Semiconductor packages can be used to electrically interconnect the electrical contacts of a die with electrical leads that electrically couple the semiconductor package to a printed circuit board (PCB). Various semiconductor packages can be attached to heat sinks to dissipate heat from the semiconductor die. Summary of the Invention

[0004] An embodiment of the method for forming a semiconductor package may include: providing a first insulating layer coupled to a first metal layer; forming a recess in the first metal layer; mechanically coupling a semiconductor die at least partially within the recess, the periphery of the semiconductor die being completely within the periphery of the recess; mechanically coupling the semiconductor die to a second metal layer coupled to a second insulating layer; and sealing the first insulating layer, the first metal layer, the semiconductor die, the second insulating layer, and the second metal layer at least partially in a sealant to form a semiconductor package.

[0005] The implementation of the method for forming a semiconductor package may include one, all, or any of the following:

[0006] The semiconductor package may not include the spacer between the semiconductor die and the first metal layer, and the semiconductor package may not include the spacer between the semiconductor die and the second metal layer.

[0007] The lead frame can form the first metal layer.

[0008] The lead frame can form the second metal layer.

[0009] The first insulating layer and the second insulating layer may be exposed by a sealant.

[0010] An embodiment of a method for forming a semiconductor package may include: providing a first metal-insulator-metal (MIM) substrate having a first metal layer and a second metal layer coupled to opposite sides of a first insulator layer; forming a recess in the first metal layer; mechanically coupling a semiconductor die at least partially within the recess, the periphery of the semiconductor die being entirely within the periphery of the recess; mechanically coupling the semiconductor die to a third metal layer of a second MIM substrate, the second MIM substrate including the third metal layer and a fourth metal layer on opposite sides of a second insulator layer; and sealing the first MIM substrate, the semiconductor die, and the second MIM substrate at least partially in a sealant to form a semiconductor package.

[0011] Implementations of forming a semiconductor package may include one, all, or any of the following:

[0012] The semiconductor package may not include the spacer between the semiconductor die and the first metal layer, and the semiconductor package may not include the spacer between the semiconductor die and the third metal layer.

[0013] The first metal layer may include two metal segments that are electrically isolated from each other before the semiconductor die is coupled to the first metal layer.

[0014] The second metal layer and / or the fourth metal layer may include slots configured to reduce warpage of the semiconductor package.

[0015] An embodiment of a semiconductor package may include: a first insulating layer coupled to at least a first metal layer, the first metal layer including a recess; a semiconductor die at least partially mechanically coupled within the recess, the periphery of the semiconductor die being entirely within the periphery of the recess; at least a second metal layer coupled to a second insulating layer, the second metal layer being mechanically coupled to the semiconductor die; and a sealant at least partially sealing the first insulating layer, the first metal layer, the semiconductor die, the second insulating layer, and the second metal layer.

[0016] Implementations of semiconductor packages may include one, all, or any of the following:

[0017] The semiconductor die can be mechanically coupled within the groove using either a solder metal or a sintered metal, and the semiconductor die can be mechanically coupled to the second metal layer using either a solder metal or a sintered metal.

[0018] The semiconductor package may not include the spacer between the semiconductor die and the first metal layer, and the semiconductor package may not include the spacer between the semiconductor die and the second metal layer.

[0019] The lead frame can form the first metal layer.

[0020] The lead frame can be mechanically attached to the first insulating layer using a siloxane elastomer.

[0021] The lead frame can form the second metal layer.

[0022] The first insulating layer and the second insulating layer may be exposed by a sealant.

[0023] The first insulating layer and the first metal layer may be components of a first metal-insulator-metal substrate. The first MIM substrate includes the first metal layer and the third metal layer, which are coupled to opposite sides of the first insulating layer.

[0024] The second insulating layer and the second metal layer may be components of a second metal-insulator-metal substrate. The second MIM substrate includes the second metal layer and a fourth metal layer, which are coupled to opposite sides of the second insulating layer.

[0025] The first metal layer may include two metal segments that are electrically isolated from each other before the semiconductor die is coupled to the first metal layer.

[0026] The second metal layer and / or the fourth metal layer may include slots configured to reduce warpage of the semiconductor package.

[0027] The above and other aspects, features and advantages will become apparent to those skilled in the art from the specific embodiments, the accompanying drawings and the claims. Attached Figure Description

[0028] The embodiments will be described below in conjunction with the accompanying drawings, in which similar reference numerals denote similar elements, and:

[0029] Figure 1 This is a cross-sectional view of an embodiment of the semiconductor component;

[0030] Figure 2 This is a cross-sectional view of an embodiment of a semiconductor package;

[0031] Figure 3 It includes Figure 1 A top view of an embodiment of a semiconductor package for a semiconductor component;

[0032] Figure 4 yes Figure 3 A side view of a semiconductor package;

[0033] Figure 5 This is a top perspective view of another embodiment of the semiconductor package;

[0034] Figure 6 This is a top perspective view of another embodiment of the semiconductor package;

[0035] Figure 7 This is a top perspective view of another embodiment of the semiconductor package;

[0036] Figure 8 yes Figure 5 A cross-sectional view of a semiconductor package;

[0037] Figure 9 yes Figure 6 A cross-sectional view of a semiconductor package;

[0038] Figure 10 yes Figure 7 A cross-sectional view of a semiconductor package;

[0039] Figure 11 This is a cross-sectional view of another embodiment of the semiconductor package;

[0040] Figure 12 This is a cross-sectional view of another embodiment of the semiconductor package;

[0041] Figure 13 This is a cross-sectional view of another embodiment of the semiconductor package;

[0042] Figure 14 This is a cross-sectional view of another embodiment of the semiconductor package;

[0043] Figure 15 This is a top view of an embodiment of a substrate configuration for forming a semiconductor package; and

[0044] Figure 16 This is a top view of another embodiment of a substrate configuration for forming a semiconductor package. Detailed Implementation

[0045] This disclosure, its aspects, and embodiments are not limited to the specific components, assembly processes, or method elements disclosed herein. Numerous additional components, assembly processes, and / or method elements known in the art for the intended operation and methods of semiconductor packages and related methods will be readily apparent for use with specific embodiments of this disclosure. Therefore, for example, although specific embodiments are disclosed, such embodiments and implementing components may include any shape, size, style, type, model, version, measurement result, concentration, material, quantity, method element, step, etc., of such structures and methods for semiconductor packages and related methods known in the art for the intended operation and methods.

[0046] Now see that the component dimensions and thicknesses are not necessarily drawn to scale (as with other appendices). Figure 1 (like) Figure 1 This illustrates an implementation of semiconductor component (component) 2. Figure 1 In this embodiment, component 2 is shown without a sealant to focus on the other elements of the component, but the component can be sealed to form a semiconductor package. Component 2 includes a top metal layer 4, which in the illustrated embodiment is a 200µm (or approximately 200µm) copper layer. Layer 4 is coupled to an insulating layer 6, which in the illustrated embodiment is a 320µm (or approximately 320µm) Al2O3 layer. Layer 6 is coupled to a metal layer 8, which in the illustrated embodiment is a 400µm (or approximately 400µm) copper layer. In the illustrated embodiment, layers 4, 6, and 8 are all contained within a first direct copper-clad (DBC) substrate.

[0047] The first DBC substrate is coupled to a first solder layer (layer 10), which in this embodiment is a 200µm (or approximately 200µm) solder layer. In some embodiments, the solder may be SAC305 lead-free solder or other conductive attachment materials. Layer 10 is coupled to a spacer 12, which in the illustrated embodiment is a 1.93mm (or approximately 1.93mm) conductive material layer, such as CuMo. 70A layer or Cu layer. A spacer is coupled to a second solder layer (layer) 14, which in the illustrated embodiment is a 200µm (or approximately 200µm) PbSn8Ag2 solder layer or other conductive attachment material layer. Layer 14 is coupled to a semiconductor die (die) 16, which in the illustrated embodiment is an insulated-gate bipolar transistor (IGBT) or MOSFET. The IGBT or MOSFET has one or more polyimide (PI) layers (layers) 18 having portions that are selectively removed to apply solder top metal / solderable top metal (STM) 20, and is subsequently coupled to a third solder or conductive material layer (layer) 22 (which in the illustrated embodiment includes two separate solder regions) to couple the IGBT to the second substrate. In the illustrated embodiment, layer 22 is a 200µm (or approximately 200µm) SnSb5 solder layer or other solder layer or other conductive material layer.

[0048] The second substrate includes a metal layer 26, which in the illustrated embodiment is a 400µm (or about 400µm) copper layer or other metal layer (and includes two or more separate portions forming the layer). Layer 26 is coupled to an insulating layer 28, which in the illustrated embodiment is a 320µm (or about 320µm) Al2O3 layer or other ceramic material layer. Layer 28 is coupled to a layer 30, which in the illustrated embodiment is a 200µm (or about 200µm) copper layer or other metal layer. In the illustrated embodiment, layers 26, 28, and 30 form the second DBC substrate. A photoimageable solder resist (PSR) layer 24 is coupled to the second DBC substrate, and portions thereof are selectively removed before layer 26 is mechanically coupled to an IGBT or MOSFET using solder layer 22. In addition to mechanical coupling, the IGBT can also be electrically coupled to layer 8 via layer 26 and / or via spacers to be electrically coupled to the leads of the package.

[0049] As used herein, the term "layer" includes a layer consisting of multiple parts that lie in a similar plane, are made of similar materials, and have similar heights.

[0050] As shown in the figure, semiconductor component 2 includes three solder layers and a spacer, and is formed into a package (such as...) by sealing and / or cutting. Figures 3 to 4 When the semiconductor component is a semiconductor package 58), the semiconductor component has (or has about) a package size of 55.0 mm × 55.0 mm × 4.7 mm (as with other package sizes disclosed herein, the package size includes the size of the sealing portion but does not include the leads extending from the sealant). Figure 3The metal layers (layers) 61 (such as layers 4 and / or 30) are shown to be exposed through sealant 60 (such as on the top and bottom), and leads 62 extend from the sealant to electrically couple the die's electrical contacts to a power source and other components, such as for transmitting signals to / from the die and controlling the connected power source / receiving power from the connected power source. Figure 4 Leads are shown that can be configured in various ways to couple with external components as needed.

[0051] Metals other than copper can be used for the copper layer, and in such embodiments, the DBC substrate can alternatively be a metal-insulator-metal (MIM) substrate. Aluminum is merely one example for the exemplary purposes of this disclosure. Similarly, other insulating materials can be used for the insulating layer, and other metals can be used for the solder layer and spacers. In the illustrated embodiment, the two DBC substrates act as heat sinks to draw heat away from the die, and the package formed by the assembly is a double-sided cooled automotive high-power module (AHPM), although the layers and methods discussed can be used to form other types of semiconductor packages.

[0052] In some embodiments, the spacer may be narrower than the die. However, in such embodiments, die breakage and / or fragmentation may occur near the spacer mounting area during processing. In other embodiments, the spacer may be wider than the die (e.g., Figure 1 (As shown). This eliminates some die cracks near the spacer, but this dimensional mismatch can lead to solder "voids" between the spacer and the die at die corners, and can cause die corner breakage. Such solder "voids" are representatively shown in... Figure 1 In this embodiment, there are areas between spacer 12 and die 16 where no solder is present above the die. In this embodiment, die corner breakage is caused by a mismatch in the coefficients of thermal expansion (CTE) between the spacer, solder, and molding underfill (MUF) epoxy resin or epoxy molding compound (EMC). When the package cools after sealing, the spacer shrinks faster than the MUF or EMC, and the MUF or EMC prevents die movement at the die corner due to solder voids causing die corner breakage (caused by spacer shrinkage).

[0053] See now Figure 2This illustrates another embodiment of a semiconductor package. The semiconductor package (package 2) includes a first MIM substrate formed of a metal layer (layer) 34, an insulating layer (layer) 36, and a metal layer (layer) 38. A second MIM substrate is formed of a metal layer (layer) 48, an insulating layer (layer) 50, and a metal layer (layer) 52. In the illustrated embodiment, the MIM substrate is a DBC substrate using a copper layer coupled to an Al2O3 insulating layer, although materials other than copper can be used for the metal layers, and insulating materials other than Al2O3 can be used for the insulating layers. In embodiments, the metal layers can be, for example, aluminum, copper, or stainless steel. As a non-limiting example, in various embodiments, the insulating layer can be Al2O3, Zr-doped Al2O3, AlN, BeO, an epoxy resin base layer, and other ceramic, composite, or organic insulating materials. One or more MIM substrates in the MIM substrate may be an insulating metal substrate (IMS) comprising an aluminum layer, an insulating layer, and a copper layer.

[0054] The metal layer (layer) 38 has a groove 40 formed therein. This groove can be formed using any material removal technique, which, as a non-limiting example, may include etching, grinding, laser ablation, casting, forming, drilling, and any other material removal or forming process. The semiconductor die (die) 44 is mechanically coupled within the groove using a metal layer 43, which in the illustrated embodiment is formed from a high-melting-temperature solder (as a non-limiting example, such as PbSn8Ag2), or formed using Ag sintering to form a solder layer or sintered layer. Metals other than Ag may be used for the sintered layer; as a non-limiting example, this metal may be gold, and / or solders other than PbSn8Ag2 may be used for the solder layer. The sintered layer may be formed using a dry powder or paste that is heated to form the sintered layer. In the illustrated embodiment, the die 44 is a metal-oxide-semiconductor field-effect transistor (MOSFET) die or an IGBT die, although in other embodiments it may be any other type of semiconductor die.

[0055] After the die is coupled within the recess, a photoresist layer 42 is deposited. In this embodiment, the photoresist layer is shown to penetrate into the area between the die and the sidewall of the recess, and also covers the metal layer 38 and the bottom of the die 44. As a non-limiting example, the photoresist layer may be a polyimide (PI) photoresist or a photomask solder resist (PSR), and may be imaged and selectively removed to expose the electrical contacts of the die. After the electrical contacts are exposed, a metal layer (layer) 46 is used to mechanically couple the die to layer 48. The photoresist helps prevent layer 46 from overflowing into undesirable areas. The die may be electrically coupled to the leads (not shown) of the package via layer 38 and / or layer 48 (such as via leads later electrically coupled to layer 38 and / or 48).

[0056] Metal layer 46 may be formed of solder with a lower melting temperature than metal layer 43, such that metal layer 43 does not reflow during the reflow of layer 46. As a non-limiting example, layer 46 may be SnSb5 solder, while layer 43 may be PbSn8Ag2 solder. Alternatively, if layer 43 is formed by Ag sintering, then layer 46 may be formed of a high melting temperature solder, or both layers 46 and 43 may be formed using Ag sintering.

[0057] Various sealing techniques (such as molding, transfer molding, cavity molding, or injection molding, as non-limiting examples) are used to apply sealant 56 to at least partially seal the die and layers to form package 32. Metal layers 34 and 52 are exposed through the sealant, which helps to draw heat away from the die. Figure 2 In the illustrated embodiment, only two solder layers or sintered layers exist, and there is no spacer between the die and either of the MIM substrates. As used herein, the term "spacer" does not include solder layers, sintered layers, solder bumps, solderable top metal (STM) layers, under-bump metal (UBM) layers, substrates or any portion thereof, or semiconductor dies or any portion thereof.

[0058] As shown in the figure, in various embodiments, a slot 54 may be included in layer 52 to reduce, control, and / or balance the warpage of the package. This slot can be formed using any material removal technique. In one embodiment, package 32 has (or approximately has) dimensions from 55.0 mm × 55.0 mm × 2.3 mm to 2.6 mm. Therefore, it can have dimensions similar to... Figure 3 The package 58 has a similar top profile, but may have a larger top profile. Figure 4 The illustrated profile features a thin side profile, due to a reduction in thickness from 4.7 mm to approximately 2.3 mm to 2.6 mm. In the illustrated embodiment, package 32 is an ultra-thin double-sided cooled (DSC) automotive high-power module (AHPM) with one or more embedded dies on a DBC or MIM substrate. In other embodiments, the package may be a non-AHPM package.

[0059] See now Figure 5 and Figure 8 This illustrates another implementation of a semiconductor package. Figure 5 In the diagram, a semiconductor package (package) 64 is shown including a sealant 90, a metal layer (layer) 66 exposed through the sealant (and similar metal layers exposed through the bottom of the package), and leads 88 extending from the sealant to couple the internal die to other components.

[0060] See Figure 8Package 64 is shown as including a first MIM substrate comprising a metal layer 66, an insulating layer 68, and a metal layer 70. A second MIM substrate is also shown, comprising a metal layer 82, an insulating layer 84, and a metal layer 86. In the illustrated embodiment, both MIM substrates are DBC substrates, although they may be any other substrate type as described herein with respect to other packages. Solder layer 72 is used to couple the topmost MIM substrate to spacer 74, which may have the same characteristics as other spacers described herein, and solder layer 76 is used to mechanically couple the spacer to a semiconductor die 78, which in the illustrated embodiment is an IGBT, although in other embodiments they may be other die types. Solder layer 80 (which in this flip-chip design is the solder bump first deposited onto the die / chip) is used to mechanically couple the die to the bottommost MIM substrate. Although photoresists (such as PI or PSR photoresists) can be used at different stages, they are not shown in the accompanying drawings to allow for viewing of other components. Lead 88 and sealant 90 are shown. Figure 8 Metal layers 66 and 86 are shown exposed through a sealant. Package 64 is an AHPM package, but in other embodiments, package 64 may be configured as another package type. In embodiments, the die may be electrically coupled to leads via layer 70 and / or layer 82.

[0061] See now Figure 6 , Figure 7 and Figures 9 to 11 This illustrates other embodiments of the semiconductor package. Figures 6 to 7 Semiconductor packages (packages) 92 and 120 are shown to be thinner than package 64, despite having a relatively similar footprint. Figure 9 It is shown that package 92 is thinner than package 64, and Figures 10 to 11 Packages 120 and 150 are similarly thinner than package 64.

[0062] See Figure 6 and Figure 9In the illustrated embodiment, the semiconductor package (package) 92 includes a first MIM substrate and a second MIM substrate, and is formed using a flip-chip method. The first MIM substrate includes a metal layer 94 (with slots 96 to reduce warpage, as previously discussed), an insulating layer 98, and a metal layer 100 having a recess 102 therein. The second MIM substrate includes a metal layer 114 (with slots 115 to reduce warpage, as previously discussed), an insulating layer 112, and a metal layer 110. The MIM substrates in the illustrated embodiment are DBC substrates, each DBC substrate having two copper layers on opposite sides of the Al2O3 layer, but they may be formed from other insulators and metals as discussed herein with respect to other packages.

[0063] Metal layer 104 (which may be a high-melting-temperature solder or Ag sintering as previously discussed) is used to couple semiconductor die 106 within the recess; and metal layer 108 (which in this flip-chip design includes solder bumps initially deposited onto the die / chip) (which may be a lower-melting-temperature solder (or Ag sintering, or a high-melting-temperature solder if layer 106 is Ag sintering)) is used to mechanically couple the die (including the die's electrical leads) to layer 110. This may include, for example, reflowing the solidified solder bumps once the die is properly positioned. In an embodiment, the die may be electrically coupled to lead 116 via layer 110 and / or layer 100 (e.g., via leads later electrically coupled to layer 110 and / or layer 100).

[0064] The die in the illustrated embodiment is a MOSFET die, and the package is an AHPM package; however, in other embodiments, the same technology may be used to form another type of die and / or package. Photoresists (such as PI or PSR) may be used in conjunction with metal layers 104 and / or 108, but they are not shown to facilitate easy viewing of other components. In the illustrated embodiment, lead 116 is electrically coupled to the die through layer 110, and sealant 118 is used to at least partially seal the die and the layers. Figure 9 Layers 94 and 114 are shown to be exposed through the sealant. Slots 96 and 115 may not extend the entire length of the package, but can be intermittent, such as... Figure 6 The implementation methods are shown representatively.

[0065] Package 92 is similar to package 64 in many respects, except that it includes fewer solder (or other metal reflow / sintering) layers, does not include spacers, and has a thinner profile. Package 64 has (or approximately has) package dimensions of 55.0 mm × 55.0 mm × 4.7 mm and is formed using a flip-chip method. Package 92, also formed using a flip-chip method, has (or approximately has) package dimensions of 55.0 mm × 55.0 mm × 2.30 mm. Therefore, package 92 is an ultra-thin DSC AHPM with an embedded die on a DBC / MIM substrate.

[0066] See Figure 7 and Figure 10 The semiconductor package (package) 120 includes a first MIM substrate and a second MIM substrate, and is formed using a chip-up design. The first MIM substrate includes a metal layer 122 (with slots 124 to reduce warpage, as previously discussed), an insulating layer 126, and a metal layer 128. The second MIM substrate includes a metal layer 142 (with slots 144 to reduce warpage, as previously discussed), an insulating layer 140, and a metal layer 136 having a recess 138 therein. The MIM substrates in the illustrated embodiment are DBC substrates, each DBC substrate having two copper layers on opposite sides of the Al2O3 layer, but they may be formed of other insulators and metals as discussed herein with respect to other packages.

[0067] Metal layer 134 (which may be a high-melting-temperature solder or Ag sintering as previously discussed) is used to couple semiconductor die 132 within the recess, and metal layer 130 (which may be a lower-melting-temperature solder (or Ag sintering, or a high-melting-temperature solder if layer 134 is Ag sintering)) is used to mechanically couple the die to layer 128. In an embodiment, the die may be electrically coupled to lead 146 via layer 136 and / or layer 128 (such as via leads that are later electrically coupled to layer 136 and / or layer 128).

[0068] The die in the illustrated embodiment is a MOSFET die or an IGBT die, and the package is an AHPM package; however, in other embodiments, the same technology may be used to form another type of die and / or package. Photoresists (such as PI or PSR) may be used in conjunction with metal layers 130 and / or 134, but they are not included in the drawings for easy viewing of other components. In the illustrated embodiment, lead 146 is electrically coupled to the die through layer 136, and sealant 148 is used to at least partially seal the die and layers. Figure 10As shown, layers 122 and 142 are both exposed by sealant. The slots 124 and 144 may not extend the entire length of the package, but can be intermittent, as typically shown in... Figure 7 middle.

[0069] Package 120 is similar to package 64 in many respects, except that it includes fewer solder (or other metal reflow / sintering) layers, does not include spacers, and has a thinner profile. Package 120 has (or approximately has) package dimensions of 55.0 mm × 55.0 mm × 2.30 mm. Therefore, package 120 is an ultra-thin DSC AHPM with an embedded die on a DBC / MIM substrate.

[0070] See Figure 11 From similar Figure 7 From a perspective view, the semiconductor package (package) 150 appears identical to package 120, including a first MIM substrate and a second MIM substrate, and is formed using a chip-down design. The first MIM substrate includes a metal layer 152 (with slots 154 to reduce warpage, as previously discussed), an insulating layer 156, and a metal layer 158 having recesses 160 therein. The second MIM substrate includes a metal layer 172 (with slots 174 to reduce warpage, as previously discussed), an insulating layer 170, and a metal layer 168. The MIM substrate in the illustrated embodiment is a DBC substrate, each DBC substrate having two copper layers on opposite sides of the Al2O3 layer, but the substrate can be any other substrate type disclosed in this document.

[0071] A metal layer (layer) 162 (which may be a high-melting-temperature solder or Ag-sintered as previously discussed) is used to couple the semiconductor die (die) 164 within the recess. A metal layer (layer) 166 (which may be a low-temperature solder (or Ag-sintered, or a high-melting-temperature solder if layer 162 is Ag-sintered)) is used to mechanically couple the die to layer 168. In an embodiment, the die may be electrically coupled to lead 176 via layer 158 and / or layer 168 (such as via leads later electrically coupled to layer 158 and / or layer 168).

[0072] The die in the illustrated embodiment is a MOSFET or IGBT die, and the package is an AHPM package; however, in other embodiments, the same technology may be used to form another type of die and / or package. Photoresists (such as PI or PSR) may be used in conjunction with metal layers 162 and / or 166, but they are not shown to facilitate easy viewing of other components. In the illustrated embodiment, lead 176 is electrically coupled to the die via layer 168, and sealant 178 is used to at least partially seal the die and layers. Figure 11Layers 152 and 172 are shown to be exposed through a sealant. The slots 154 and 174 may not extend the entire length of the package, but can be intermittent, as shown regarding... Figures 6 to 7 A representative example of the package is shown.

[0073] Package 150 is similar to package 64 in many respects, except that it includes fewer solder (or other metal reflow / sintering) layers, does not include spacers, and has a thinner profile. Package 150 has (or approximately has) package dimensions of 55.0 mm × 55.0 mm × 2.30 mm. Therefore, package 150 is an ultra-thin DSC AHPM with an embedded die on a DBC / MIM substrate.

[0074] Finite element analysis (FEA) was used to model the plastic peel strain of the signal pad solder joints and the die top stress of packages 64 and 92 (two flip-chip designs). It was found that the plastic peel strain of package 92 was less than 0.5 times that of package 64. The die top stress of package 92 was less than 0.8 times that of package 64.

[0075] See now Figure 12 This illustrates another embodiment of a semiconductor package. The semiconductor package (package) 180 includes a first insulator-metal substrate and a second insulator-metal substrate. The first insulator-metal substrate is formed of an insulating layer (layer) 182 coupled to a metal layer (layer) 184 in which recesses 186 are formed. The second insulator-metal substrate is formed of an insulating layer (layer) 198 coupled to a metal layer (layer) 196. The MIM substrates in the illustrated embodiment are single-sided copper-clad (SBC) substrates, each SBC substrate having a copper layer coupled to an Al2O3 layer, but they may be formed of other insulators and metals as discussed herein with respect to other packages.

[0076] A metal layer (layer) 190 (which may be a high-melting-temperature solder or Ag sintered as previously discussed) is used to couple a semiconductor die (die) 192 within a recess. A photoresist 188 (such as PI or PSR) is deposited and selectively removed to expose the die's electrical contacts. After the electrical contacts are exposed, a metal layer (layer) 194 (which may be a low-temperature solder (or Ag sintered, or a high-melting-temperature solder if layer 190 is Ag sintered) is used to mechanically couple the die's electrical contacts to layer 196. In an embodiment, the die may be electrically coupled to the package leads (not shown) via layer 184 and / or layer 196 (such as via leads later electrically coupled to layer 184 and / or 196). A sealant 200 is used to at least partially seal the die and the layers.

[0077] The die in the illustrated embodiment is a MOSFET or IGBT die, and the package is an AHPM package; however, in other embodiments, the same technology may be used to form another type of die and / or package. For example... Figure 12 As shown, in various embodiments, both insulating layers 182 and 198 are exposed by a sealant. In embodiments, the insulating layers may be formed of a high thermal conductivity ceramic material, such as Al2O3, AlN, Si3N4, or other thermally conductive materials, as a non-limiting example, to help draw heat away from the die.

[0078] Package 180 has (or approximately has) dimensions of 55.0 mm × 55.0 mm × 1.7 mm to 2.0 mm, giving it a similar footprint to package 58, but with a thinner side profile. It also has only two sintered or reflowed metal layers and no spacers. Package 180 has no exposed metal layers on the exterior of the package, which helps reduce warpage (such as during die attachment processes that couple the die within the recess) and helps reduce the likelihood of peeling or damage to either of the sintered or reflowed metal layers (one or both of which may be signal carriers). An alternative design for package 180 may use one or more lead frames instead of one or more insulator-metal substrates. Package 180 is an ultrathin DSC AHPM SBC (with embedded chip) on an SBC. In other embodiments, since the package is already relatively thin, layer 184 may not include recesses, and the die may be coupled only to the non-recessed surface of layer 184.

[0079] See now Figure 13 This illustrates another embodiment of a semiconductor package. The semiconductor package (package) 202 includes a lead frame coupled to an insulating layer and a MIM substrate. The lead frame 208 is mechanically coupled to the insulating layer (layer) 204 using a high thermal conductivity adhesive layer (layer) 206. As a non-limiting example, the high thermal conductivity adhesive layer may be epoxy, glue, polyurethane, siloxane elastomer, and any other adhesive type. In the illustrated embodiment, layer 206 is a siloxane elastomer. The lead frame has recesses 209 formed therein. The MIM substrate is formed of a metal layer (layer) 218 ​​coupled to an insulating layer (layer) 220, which in turn is coupled to a metal layer (layer) 222. The MIM substrate in the illustrated embodiment is a DBC substrate having two copper layers coupled to an Al2O3 layer, but it may be formed of other insulators and metals as discussed herein with respect to other packages.

[0080] A metal layer (layer) 210 (which may be a high-melting-temperature solder or Ag sintered as previously discussed) is used to couple the semiconductor die (die) 212 within the recess. A photoresist 214 (such as PI or PSR) is deposited and selectively removed to expose the die's electrical contacts. After the electrical contacts are exposed, a metal layer (layer) 216 (which may be a lower-melting-temperature solder (or Ag sintered, or a high-melting-temperature solder if layer 210 is Ag sintered) is used to mechanically couple the die's electrical contacts to metal layer 218. In an embodiment, the die may be electrically coupled to the package leads (not shown) via a lead frame and / or layer 218 (such as via leads later electrically coupled to the lead frame and / or layer 218). A sealant 224 is used to at least partially seal the die, layers, and lead frame.

[0081] The die in the illustrated embodiment is a MOSFET die or an IGBT die, and the package is an AHPM package. However, in other embodiments, the same technology can be used to form another type of die and / or package. Figure 13 As shown, both the insulating layer 204 and the metal layer 222 are exposed through a sealant. In an embodiment, the insulating layer may be formed of a high thermal conductivity ceramic material as discussed herein with regard to other packages, to help draw heat away from the die.

[0082] Package 202 has (or approximately has) dimensions of 55.0 mm × 55.0 mm × 2.6 mm to 3.2 mm, giving it a similar footprint to package 58, but with a thinner side profile. It also has only two sintered or reflowed metal layers and no spacers. Package 202 has only one exposed metal layer on the exterior of the package, which helps reduce warpage (such as during die attachment processes that couple the die within the recess) and helps reduce the likelihood of peeling or damage to either the sintered or reflowed metal layers (one or both of which may be signal carriers). Package 202 is an ultra-thin DSC AHPM, where the die is located on a leadframe / insulator coupled to the DBC substrate. In other embodiments, the leadframe may not include recesses, and the die may simply be coupled to the non-recessed surface of the leadframe. The leadframe may initially have recesses formed therein, or recesses may subsequently be formed therein using any of the material removal processes disclosed herein.

[0083] See now Figure 14This illustrates another embodiment of a semiconductor package. The semiconductor package (package) 226 includes a first lead frame coupled to an insulating layer and a second lead frame coupled to an insulating layer. The first lead frame 232 is mechanically coupled to the insulating layer 228 using a high thermal conductivity adhesive layer 230. As a non-limiting example, the high thermal conductivity adhesive layer may be epoxy resin, glue, polyurethane, siloxane elastomer, and various other adhesive materials. In the illustrated embodiment, layer 230 is a siloxane elastomer. The lead frame has recesses 234 formed therein. The second lead frame 244 is mechanically coupled to the insulating layer 248 using a high thermal conductivity adhesive layer 246, which may have the same or different material as layer 230. In the illustrated embodiment, layer 246 is a siloxane elastomer.

[0084] A metal layer (layer) 236 (which may be a high-melting-temperature solder or Ag sintered as previously discussed) is used to couple the semiconductor die (die) 238 within the recess. A photoresist 240 (such as PI or PSR) is deposited and selectively removed to expose the die's electrical contacts. After the electrical contacts are exposed, a metal layer (layer) 242 (which may be a lower-melting-temperature solder (or Ag sintered, or a high-melting-temperature solder if layer 236 is Ag sintered) is used to mechanically couple the die's electrical contacts to a second lead frame 244. In an embodiment, the die may be electrically coupled to the leads (not shown) of the package via a first lead frame and / or a second lead frame (such as via leads later electrically coupled to the first lead frame and / or the second lead frame). A sealant 250 is used to at least partially seal the die and the layers.

[0085] The die in the illustrated embodiment is a MOSFET die or an IGBT die, and the package is an AHPM package. However, in other embodiments, the same technology can be used to form another type of die and / or package. Figure 14 As shown, insulating layers 228 and 248 are both exposed by a sealant. In an embodiment, the insulating layers may be formed of a high thermal conductivity ceramic material as discussed herein with respect to other packages, to help draw heat away from the die.

[0086] Package 226 has (or approximately has) dimensions of 55.0 mm × 55.0 mm × 2.6 mm to 3.2 mm, giving it a similar footprint to package 58, but with a thinner side profile. It also has only two sintered or reflowed metal layers and no spacers. Package 226 has no exposed metal layers on the exterior of the package, which helps reduce warpage (such as during die attachment processes that couple the die within the recess) and helps reduce the likelihood of peeling or damage to either the sintered or reflowed metal layers (one or both of which may be signal carriers). Package 226 is an ultra-thin DSC AHPM, where the die is located on a leadframe / insulator coupled to the leadframe / insulator. In other embodiments, the first leadframe may not include a recess, and the die may be coupled only to the non-recessed surface of the first leadframe. The first leadframe may initially have a recess formed therein, or the recess may subsequently be formed therein using any material removal technique.

[0087] The methods and packages of this invention, shown as a single die coupled only within a recess, may be drawn to scale to include multiple dies coupled within multiple recesses or multiple dies coupled within a common recess. The lead frame of any package discussed herein may be formed of any metal, including, by way of non-limiting example, copper, copper alloys, steel, and any other conductive material. By way of non-limiting example, the sealant material may be formed of a polymer resin / epoxy resin, a thermosetting resin / epoxy resin, etc.

[0088] See now Figure 15 This illustrates an implementation of a MIM structure. Only the metal layers of the MIM structure are shown for ease of observation; an insulating layer is included between them. Figure 15 In the structure, the first metal layer (layer) 252 is formed from a single adjacent metal sheet. However, the second metal layer (layer) 254 is formed from a first portion 256 and a second portion 258, which are initially electrically isolated from each other by a slit 260 between them. If desired, they can then be electrically coupled during package formation. In the first portion 256, a recess 257 is shown, and a semiconductor die (die) 261 is shown as coupled therein. This top view shows that the outer periphery of the die is completely within the outer periphery of the recess, and this is also the case for all other packages disclosed herein that position the die within a recess.

[0089] The second portion 258 is shown without a recess, but it may also have a recess, and in various embodiments, it includes a die, and the recess in each portion may additionally include other components / dies and / or may include additional recesses for additional components / dies. In the illustrated embodiment, the MIM substrate is a DBC substrate using a copper layer coupled to an insulating layer (not shown), but in other embodiments, other metal layer materials and / or insulating layer materials as discussed in other packages discussed herein may be used. In some embodiments, splitting the second metal layer into separate portions may be advantageous, for example, embedding a high-side (HS) die in the recess of one portion and a low-side (LS) die in the recess of another portion. This concept can also be applied to insulator-metal substrates comprising only one metal layer, wherein the single metal layer is split into multiple portions.

[0090] Figure 16 A similar MIM structure is shown, also illustrating a first metal layer (layer) 262 and a second metal layer (layer) 264, but without an insulating layer. The second metal layer comprises a first portion 266 and a second portion 268, and in this case, the slit 270 is a straight vertical slit. Therefore, the slit can be designed to accommodate different components on the two portions as needed. The two portions of layer 264 can again be used for a high-side die and a low-side die that can be embedded in a recess. For example, as a non-limiting example, each portion may include a separate MOSFET (HS MOSFET and LS MOSFET), or each portion may include a separate insulated-gate bipolar transistor (IGBT) and a fast recovery diode (FRD).

[0091] In one implementation, instead of splitting a single metal layer of a substrate into two parts, separate substrates can be used on one side (top or bottom) of the package to achieve separation of the HS and LS dies / components. In this implementation, at least three substrates may subsequently be present—one substrate on the top or bottom side, and two substrates on opposite sides to hold the HS / LS die within the recess.

[0092] In embodiments of the package disclosed herein, a solder mask / photoresist layer may be used prior to laying or depositing a first metal layer that couples the die within the recess. While high-melting-temperature solder and Ag sintering are disclosed herein for coupling the die within the recess, in other embodiments, any thermally conductive die attachment material may be used, and this thermally conductive die attachment material may need to be reflowed to form a first portion or half of the package (the top substrate or leadframe coupled to the die). The lower half or portion is formed by providing or forming a bottom substrate / leadframe structure. As discussed herein, the two halves or portions are coupled together using a solder layer or sintered layer, and the die and layers are subsequently sealed to form the package.

[0093] Some embodiments of the semiconductor packages disclosed herein protect the die from damage in part by omitting spacers and by embedding the die within recesses in the metal layers or leadframes. For those packages without spacers, all failure modes associated with spacers are eliminated. Embedding the die within recesses also reduces or eliminates solder voids, thus reducing or eliminating damage caused by such voids. Some packages described herein have shorter thermal and electrical paths due to the absence of spacers and the embedding of the die within recesses, thereby enhancing thermal and electrical performance. Material costs are also reduced for packages that do not include spacers and have fewer reflow or sintered metal layers. The packages disclosed herein allow for ultra-thin AHPMs, enabling more compact three-phase inverters and increased power density.

[0094] Other steps not discussed herein may be used to form the package, and those steps disclosed merely highlight some steps in the manufacturing process. For example: multiple photoresist layers may be laid and sequentially patterned for patterning purposes, and those layers may be exposed, with the exposed portions being removed (or left); a passivation layer may be formed on a metal layer, with the passivated portions being removed by selective material removal (such as using photoresist and etching); cutting may be performed after sealing, and so on.

[0095] As used herein, the terms "partial seal," "complete seal," and their variations have specific meanings. See also Figures 2 to 14 Following the sealing step, each die in the die is considered to be completely sealed in the sealant, even if there is no sealant directly above and / or below each die (instead having one or more solder or sintered metals and / or residual photoresist), because each die is completely surrounded by the sealant and the combination of components that are themselves at least partially sealed within the sealant. Each metal layer or insulating layer exposed through the sealant is only partially sealed in the sealant, because a portion is exposed through the sealant. For ease of viewing other components, not all packages shown in the figures show electrical leads except for the metal layers exposed on the outside of the package, but all packages shown in the figures allow leads to be exposed through or extend from the sealant, and such leads will only be partially sealed in the sealant.

[0096] In various package implementations, the first metal layer may include two metal segments that are electrically isolated from each other before the semiconductor die is coupled to the first metal layer.

[0097] In various packaging implementations, the lead frame can be mechanically attached to the first insulating layer using a silicon elastomer.

[0098] In various package implementations, the lead frame may include a first metal layer.

[0099] In various package implementations, the lead frame may include a second metal layer.

[0100] In various package implementations, the semiconductor die may be mechanically coupled within the recess using solder metal or sintered metal, wherein the semiconductor die is mechanically coupled to the second metal layer using solder metal or sintered metal.

[0101] In various package implementations, the semiconductor package does not include a spacer between the semiconductor die and the first metal layer, and the package does not include a spacer between the semiconductor die and the second metal layer.

[0102] Where specific embodiments of semiconductor packages and related methods, as well as implementing components, sub-components, methods, and sub-methods, are mentioned in the above description, it should be apparent that various modifications can be made without departing from the substance, and that these embodiments, implementing components, sub-components, methods, and sub-methods can be applied to other semiconductor packages and related methods.

Claims

1. A semiconductor package, comprising: A first insulating layer, the first insulating layer being coupled to a first metal layer, the first metal layer including a groove; A semiconductor die, said semiconductor die being at least partially mechanically coupled within the groove, the periphery of said semiconductor die being completely located within the periphery of the groove; A second metal layer is coupled to a second insulating layer and mechanically coupled to the semiconductor die; as well as A sealant that at least partially seals the first insulating layer, the first metal layer, the semiconductor die, the second insulating layer, and the second metal layer; The semiconductor die is directly coupled to the first metal layer via a first welding metal or a first sintered metal, and the semiconductor die is directly coupled to the second metal layer via a second welding metal or a second sintered metal. The lead frame includes the first metal layer; The lead frame is mechanically attached to the first insulating layer using a siloxane elastomer. and The semiconductor die is located between the first metal layer and the second metal layer.

2. The semiconductor package of claim 1, wherein the lead frame includes the second metal layer.

3. The semiconductor package of claim 1, wherein the second metal layer comprises two metal segments electrically isolated from each other prior to coupling the semiconductor die to the second metal layer.

4. A semiconductor package, comprising: A first metal-insulator-metal (MIM) substrate, the first metal-insulator-metal substrate including a first insulating layer coupled to a first metal layer, the first metal layer including a groove; A semiconductor die, said semiconductor die being at least partially mechanically coupled within the groove, the periphery of said semiconductor die being completely located within the periphery of the groove; The second metal-insulator-metal substrate includes a second metal layer, which is coupled to a second insulating layer and mechanically coupled to the semiconductor die. as well as A sealant that at least partially seals the first insulating layer, the first metal layer, the semiconductor die, the second insulating layer, and the second metal layer; The first metal-insulator-metal substrate and the second metal-insulator-metal substrate are exposed through the sealant.

5. A semiconductor package, comprising: A first metal-insulator-metal (MIM) substrate, the first metal-insulator-metal substrate including a first insulating layer coupled to a first metal layer, the first metal layer including a groove; A semiconductor die, said semiconductor die being at least partially mechanically coupled within the groove, the periphery of said semiconductor die being completely located within the periphery of the groove; The second metal-insulator-metal substrate includes a second metal layer, which is coupled to a second insulating layer and mechanically coupled to the semiconductor die. as well as A sealant that at least partially seals the first insulating layer, the first metal layer, the semiconductor die, the second insulating layer, and the second metal layer; The semiconductor die is directly coupled to the first metal layer via a first solder metal or a first sintered metal, and the semiconductor die is directly coupled to the second metal layer via a second solder metal or a second sintered metal.

6. The semiconductor package of claim 5, wherein the semiconductor die is directly coupled to the first metal layer in the groove via a first solder metal or a first sintered metal, and wherein the semiconductor die is directly coupled to the second metal layer via a second solder metal or a second sintered metal.

7. The semiconductor package of claim 5, wherein the lead frame includes the first metal layer.

8. The semiconductor package of claim 5, wherein the second metal layer comprises two metal segments electrically isolated from each other prior to coupling the semiconductor die to the second metal layer.

9. The semiconductor package of claim 5, wherein the second metal-insulator-metal substrate further comprises a third metal layer opposite to the second metal layer, the third metal layer being directly coupled to the second insulating layer, the third metal layer including a slot.

10. The semiconductor package of claim 5, further comprising a photoresist layer coupled between the semiconductor die and a plurality of sidewalls of the recess.

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