Assembly with face-to-face bonded chiplets

Abstract

Integrated circuits (240) and related methods are disclosed. The integrated circuit (240) includes a first semiconductor device (245). The first semiconductor device (245) includes: a first programmable gate array (246); a plurality of interface logics (252, 259), the plurality of interface logics (252, 259) including a first interface logic (259); and a first memory port connected to a first set (258, 260) of bonds on a surface of a first semiconductor device (245). The first programmable gate array (245) is operatively coupled to the first interface logic (252) to communicate via the first memory port (251).

Description

Cross-references to related applications

[0001] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 518,988, filed August 11, 2023, entitled “INTEGRATED CIRCUIT HAVINGMEMORIES AND A SHARED WRITE PORT”, the entire contents of which are incorporated herein by reference.

[0002] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 602,733, filed November 27, 2023, entitled “METHOD AND SYSTEM FORKNOWN-GOOD-DIE TESTABILITY OF FACE-TO-FACE BONDED CHIPLETS”, the entire contents of which are incorporated herein by reference.

[0003] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 602,737, filed November 27, 2023, entitled “SYSTEM AND METHOD FORHAVING CORRECT-BY-CONSTRUCTION TIMING CLOSURE”, the entire contents of which are incorporated herein by reference.

[0004] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 567,649, filed March 20, 2024, entitled “ASSEMBLY HAVING A FACE-TO-FACE BONDED CHIPLET”, which is incorporated herein by reference in its entirety.

[0005] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 637,742, filed April 23, 2024, entitled “INTEGRATED CIRCUIT HAVINGMICROVAULT MEMORIES”, identified by Case No. P24-081-US-PSP, the entire contents of which are incorporated herein by reference.

[0006] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 637,764, filed April 23, 2024, entitled “FEFET STRUCTURES ON INTEGRATED CIRCUITS”, identified by Case No. P24-082-US-PSP, the entire contents of which are incorporated herein by reference.

[0007] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 674,471, filed July 23, 2024, entitled “SYSTEM, METHOD, ANDAPPARATUS FOR WAFER-SCALE MEMORY”, the entire contents of which are incorporated herein by reference. Technical Field

[0008] This disclosure relates to integrated circuits. More specifically, this disclosure relates to integrated circuits of face-to-face bonding components forming chiplets. Background Technology

[0009] Chiplets refer to tiny chips designed to operate as a single entity when using advanced packaging technologies. These miniaturized chips are created by dividing a larger chip into several smaller chips, each with its own function or capability. The concept originated from the semiconductor industry's need to overcome the physical limitations of traditional monolithic chip designs and achieve higher levels of integration. The idea behind chiplets is to create modular systems composed of interconnected and interchangeable chips that can be combined in different configurations to create advanced computing systems with improved performance, power efficiency, and functionality.

[0010] Chiplets can be based on different architectures, such as CPUs, GPUs, memory, or I / O, and can be assembled and stacked in various ways depending on specific application requirements. One advantage of the chiplet approach is its ability to mix and match different chiplets from different manufacturers to create custom solutions that meet specific computing needs. This approach also allows for faster time-to-market, reduced development costs, and increased flexibility, as chiplets can be upgraded or replaced without requiring a complete system redesign. Summary of the Invention

[0011] One embodiment of the integrated circuit may include a first semiconductor device, the first semiconductor device including a first programmable gate array (PGA). This array may be coupled to various interface logics, the first interface logic being within the various interface logics. Furthermore, a first memory port may be present, the first memory port being connected to a first set of bonds on the surface of the first semiconductor device. The first PGA is operatively connected to the first interface logic, thereby allowing communication via the first memory port.

[0012] In some embodiments, the first interface logic of the integrated circuit may be constituted by a first programmable gate array. The integrated circuit may have the first interface logic distributed in a spaced pattern within the first programmable gate array. Embodiments of a first semiconductor device within the integrated circuit may include a plurality of memory ports, the plurality of memory ports including the first memory port, wherein these ports are formed in a spaced pattern on the semiconductor device.

[0013] Furthermore, the integrated circuit may also include multiple sets of bonding elements, the multiple sets of bonding elements including a first set of bonding elements, wherein these sets are distributed in a spaced pattern on the surface of the first semiconductor device. In some embodiments, the first semiconductor device of the integrated circuit may include multiple memory ports, such as a first memory port. Here, each interface logic from multiple interface logics may be coupled to a corresponding memory port from the multiple memory ports.

[0014] In some embodiments, the first semiconductor device may further include a plurality of programmable gate arrays (PGAs) encompassing the first PGA. Each PGA from the plurality of PGAs may be coupled to a corresponding interface logic from a plurality of interface logics. The integrated circuit may further include a plurality of cores, wherein each core from the plurality of cores is coupled to a corresponding interface logic in the plurality of interface logics. Embodiments of the integrated circuit may include various sets of bonding elements on the surface of the first semiconductor device. In this configuration, each memory port from a plurality of memory ports is coupled to a bonding element from a corresponding set of a plurality of sets of bonding elements, the plurality of sets of bonding elements including a first set of bonding elements.

[0015] In some embodiments, the first set of bonding elements may include metal pads. The first semiconductor device of the integrated circuit may optionally include an on-chip network. This network is configured to enable communication among at least two of a plurality of programmable gate arrays (PGA). Optionally, the first semiconductor device may include at least one on-chip network communication system. This system connects at least two processing elements implemented on the first PGA, which is operatively coupled to a plurality of interface logics for communication via a memory port. In some embodiments of the integrated circuit, the first memory port may act as a read port. In some embodiments, the first memory port, when acting as a read port, may also be a multi-cycle port. Alternatively, the first memory port may act as a write port in the integrated circuit. Similar to the read port configuration, in some embodiments, the write port may also be designed as a multi-cycle port.

[0016] In some configurations, the first memory port may be a combined read / write port. When acting as a read / write port, it may also be configured as a multi-cycle port in some embodiments. In some embodiments, the first programmable gate array within the integrated circuit may be a field-programmable gate array (FPGA). Alternatively, the first programmable gate array may be a reconfigurable gate array. In some cases, the reconfigurable gate array may be dynamically programmable. Alternatively, in one embodiment, the reconfigurable gate array may be programmable only once.

[0017] A first semiconductor device in an integrated circuit may include an on-chip network architecture. Within the integrated circuit, a programmable gate array (PGA) may include an array of embedded PGA cores. These cores are configured to communicate with each other via the on-chip network architecture. In some embodiments, the on-chip network architecture is formed by a first PGA. Embodiments of the first PGA within the integrated circuit may include an array of embedded PGA cores. Each core from this array may be operatively coupled to corresponding interface logic from a plurality of interface logics. In the integrated circuit, the first PGA may involve at least two embedded PGA cores. Each core from at least two cores is operatively coupled to corresponding interface logic from a plurality of interface logics.

[0018] The first programmable gate array (PGA) may include an array of embedded PGA cores. Each core from the array is operatively coupled to at least one of a plurality of interface logics. Alternatively, each core from the array of embedded PGA cores may be operatively coupled to a single interface logic of the plurality of interface logics. The integrated circuit may also include a second semiconductor device. The device includes a plurality of memory modules, with a first memory module among the plurality of memory modules. The module is coupled to a second set of bonding members on the surface of the second semiconductor device, wherein the first set and the second set of bonding members are configured to interface with each other when bonded together. In some embodiments, the first memory port is specifically a write memory port. The first memory port may be configured to write to all of the memory modules among the plurality of memory modules. The first semiconductor device may also include a plurality of read memory ports. The plurality of interface logics includes a plurality of read interface logics, wherein each read interface logic is operatively coupled to a corresponding read memory port among the read memory ports. Each of the plurality of read interface logics may interface with a corresponding memory module from the plurality of memory modules.

[0019] Multiple memory modules within the second semiconductor device may include an array of SRAMs. Alternatively, the memory modules may include an array of non-volatile memory. In some embodiments, the memory modules may be EEPROMs. Alternatively, the memory modules may be ROMs. Optionally, the memory modules may include read-optimized non-volatile memory. In an integrated circuit, a programmable gate array (PGA) may utilize antifuse, SRAM, or flash memory technologies for its programming. Within the integrated circuit, PGA cores may be interconnected in a mesh topology via an on-chip network architecture. The interface logic of the integrated circuit may include voltage level shifters. These shifters are designed to convert signals from the PGA to voltage levels at or from the first memory port.

[0020] Embodiments may include methods for operating an integrated circuit, the method involving utilizing a first semiconductor device equipped with a first programmable gate array (PGA). This embodiment may include employing a plurality of interface logics, one of which is a first interface logic. It may also involve connecting a first memory port to a set of bonding members located on the surface of the first semiconductor device. Furthermore, the method may include operative coupling of the first PGA with the first interface logic, enabling communication via the first memory port. In some embodiments, employing the first interface logic may involve forming the first interface logic from the first PGA. In one embodiment, employing the first interface logic may include distributing the logic in a spaced pattern within the first PGA. Embodiments may also include a plurality of memory ports, such as the first memory port, and may involve forming a spaced pattern with these ports on the surface of the first semiconductor device. In one embodiment, the method may further include distributing a plurality of sets of bonding members, including the first set, in a spaced pattern on the surface of the first semiconductor device.

[0021] One embodiment of the method may utilize a plurality of memory ports, including a first memory port. Here, each interface logic from a plurality of interface logics may be coupled to a corresponding memory port from the plurality of memory ports. In some embodiments, the method may include employing a plurality of programmable gate arrays, such as a first programmable gate array, wherein each gate array is coupled to a corresponding interface logic from the plurality of interface logics. Embodiments may involve coupling a plurality of cores, wherein each core from the plurality of cores is coupled to a corresponding interface logic from the plurality of interface logics. In another embodiment, the method may involve coupling a plurality of sets of bonding elements on the surface of a first semiconductor device. Here, each memory port from the plurality of memory ports may be coupled to a corresponding set of bonding elements from a plurality of sets of bonding elements, including a first set.

[0022] In some embodiments, utilizing the first set of bonding elements may involve employing metal pads. One embodiment of the method may involve employing a plurality of programmable gate arrays (PGAs), the PGAs including a first PGA; and configuring an on-chip network to enable communication between at least two PGAs. In one embodiment, the method may further include implementing at least one on-chip network communication system to connect at least two processing elements on the first PGA, and operatively coupling the first PGA to a plurality of interface logic to enable communication via a memory port. In some embodiments, utilizing the first memory port may involve using it as a read port. In some embodiments, using the first memory port as a read port may further include using it as a multi-cycle port.

[0023] Embodiments may involve using a first memory port as a write port. In one embodiment, using the first memory port as a write port may further include using it as a multi-cycle port. In some embodiments, the method may involve using the first memory port as a read / write port. In some embodiments, using the first memory port as a read / write port may further include using it as a multi-cycle port. In one embodiment, utilizing the first programmable gate array may include employing a field-programmable gate array. Embodiments may involve using the first programmable gate array as a reconfigurable gate array. In some embodiments, employing a reconfigurable gate array may further include dynamically programming the gate array.

[0024] Alternatively, in one embodiment, employing a reconfigurable gate array may include one-time programming of the gate array. One embodiment of the method may further include including an on-chip network architecture in a first semiconductor device. In some embodiments, utilizing the on-chip network architecture may include employing an array of embedded programmable gate array cores configured to communicate via the on-chip network architecture. In one embodiment, forming the on-chip network architecture may be accomplished by a first programmable gate array. Embodiments may include utilizing a first programmable gate array having an array of embedded programmable gate array cores, each embedded programmable gate array core operatively coupled to a corresponding interface logic from a plurality of interface logics. In some embodiments, utilizing the first programmable gate array may include employing at least two embedded programmable gate array cores, each embedded programmable gate array core operatively coupled to a corresponding interface logic from a plurality of interface logics. Embodiments may involve using an array of embedded programmable gate array cores, each embedded programmable gate array core operatively coupled to at least one of a plurality of interface logics.

[0025] Alternatively, in one embodiment, utilizing the first programmable gate array (FPGA) may include an array employing embedded FPGA cores, each FPGA core being operatively coupled to a single interface logic among a plurality of interface logics. One embodiment may also involve utilizing a second semiconductor device comprising a plurality of memory modules, the plurality of memory modules including a first memory module, and a second set of bonding members coupling the module to a surface of the second semiconductor device. The first set and the second set of bonding members may be configured to interface with each other when the first and second semiconductor devices are bonded together. In some embodiments, utilizing the first memory port may involve using it as a write memory port. In one embodiment, using the first memory port as a write memory port may include configuring it to write to all memory modules among the plurality of memory modules. One embodiment may also include a plurality of read memory ports within the first semiconductor device, wherein each read interface logic from a plurality of read interface logics is operatively coupled to a corresponding read memory port among the plurality of read memory ports. In some embodiments, each read interface logic among the plurality of read interface logics may interface with a corresponding memory module from the plurality of memory modules.

[0026] Embodiments may involve employing an array of multiple memory modules as SRAM. Alternatively, in one embodiment, the multiple memory modules may be used as an array of non-volatile memory. In some embodiments, employing multiple memory modules may include using EEPROM. In another embodiment, the multiple memory modules may be used as ROM. Embodiments may involve using multiple memory modules as read-optimized non-volatile memory. In some embodiments, utilizing a programmable gate array (PGA) may involve programming using antifuse, SRAM, or flash memory technologies. One embodiment may involve using a mesh topology to connect the PGA core via an on-chip network architecture. In one embodiment, employing interface logic may include using voltage level shifters to convert or shift voltage levels from or to the first memory port of the PGA. Attached Figure Description

[0027] These and other aspects will become more apparent from the following detailed description of various embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0028] Figure 1 This is a block diagram of an integrated circuit that may be a part of a semiconductor device such as a chiplet, according to embodiments of this disclosure;

[0029] Figure 2 A perspective view of a component according to an embodiment of the present disclosure is shown, the component having Figure 1An integrated circuit is implemented on a semiconductor device, which is electrically connected to another device to form the component;

[0030] Figure 3A An embodiment of the present disclosure is shown having Figure 1 A perspective view of an integrated circuit component, which is implemented on a semiconductor device electrically connected to another device having a field-programmable gate array architecture to form the component;

[0031] Figure 3B It shows Figure 3A A perspective view of the components, illustrating the bonding elements on the surface of a semiconductor device according to an embodiment of the present disclosure;

[0032] Figure 4 An embodiment of the present disclosure is shown having Figure 1 A perspective view of an integrated circuit component, wherein the integrated circuit is implemented on a semiconductor device electrically connected to another device having a field-programmable gate array core interconnected via a network to form the component;

[0033] Figure 5 An illustration of an embodiment according to the present disclosure is shown. Figure 1 A block diagram of the memory address space of an integrated circuit;

[0034] Figure 6 An illustration of an embodiment according to the present disclosure is shown, illustrating a... Figure 1 A block diagram of the memory address space of the signal interface of an integrated circuit;

[0035] Figure 7 A diagram of two semiconductor devices (such as two chiplets) according to an embodiment of the present disclosure is shown, wherein the two semiconductor devices automatically test the connectivity and integration connectivity of read interconnects within the semiconductor devices;

[0036] Figure 8 The diagram illustrates two semiconductor devices (such as two chiplets) according to one embodiment of the present disclosure, which automatically test the connectivity and integration connectivity of write interconnects within the semiconductor devices; and

[0037] Figures 9A to 9B A block diagram of a system employing correct timing convergence according to an embodiment of the present disclosure is shown, the system being used for an application chiplet and a memory chiplet having read registers and write registers. Detailed Implementation

[0038] Figure 1A block diagram of an integrated circuit 100 according to one embodiment of the present disclosure is shown. The integrated circuit 100 can be packaged as a bondable chiplet (e.g., face-to-face chiplet bonding). The integrated circuit (IC) 100 includes a module group 106 comprising modules 108, 110, 112, and 114. The IC 100 also has a shared write port 102 configured to write to the module group 106 using a write peripheral 104. Furthermore, it includes read peripherals 116, 118, 120, and 122 and read ports 124, 126, 128, and 130 configured to read from modules 108, 110, 112, and 114.

[0039] Write port 102 can be configured to provide a single write address space to all module groups 106, where each of modules 108, 110, 112, and 114 has dedicated read ports 124, 126, 128, and 130, respectively. Integrated circuit 100 can be packaged as a portion of a chiplet configured to be electrically connected to another integrated circuit device (e.g., another chiplet, or an IC package, with or without electrical contacts, electrical bumps, etc.). The chiplet can be electrically connected to the other device, including, for example, by bonding, soldering, wafer-to-wafer bonding, face-to-face chiplet bonding, chiplet-to-wafer bonding, chiplet-to-interposer bonding, and / or the chiplets can be connected together using an interposer or other interface technologies. When electrically connecting the chiplet to another device, an interposer may not be used, one interposer may be used, or multiple interposers may be used, or other interface technologies common in heterogeneous 3D system-in-package solutions may be utilized.

[0040] Each read port (124, 126, 128, 130) in the chiplet may have electrical contacts on a side (e.g., top or bottom) or multiple sides of the chiplet. Read ports 124, 126, 128, 130 may use multi-loop pipeline circuitry. When bonded to another device (e.g., wafer, chiplet, sOC, package, FPGA, etc.), the electrical contacts may be queued in a manner that provides dedicated access to a specific module among modules 108, 110, 112, 114. For example, a processing / computing element may exclusively access module 108 via read port 124, and module 108 may contain neural network weights in its registers. Similarly, different processing / computing elements may exclusively access module 110 via read port 126, and module 110 may include different registers. In this particular embodiment, the arrangement of the electrical contacts ensures that each computing / processing element has dedicated access required to efficiently perform its specific computations, thereby providing a compact, modular, and scalable system that allows different processing elements to maintain dedicated access to specific modules 108, 110, 112, and 114. Without dedicated access, different processing elements might have to queue to use the same resources, which would slow down overall processing speed. By providing dedicated access, the proposed chiplet ensures that each processing element can operate at its maximum capacity without interference from other computing elements in this particular embodiment.

[0041] The write peripheral 104 is a peripheral circuit device responsible for processing data and writing data to memory cells located within modules 108, 110, 112, and 114. The write peripheral 104 may include dedicated contacts that allow the chip to be electrically connected (e.g., bonded) to a chiplet of the integrated circuit, enabling the write port 102 to be accessed via a shared write logic system. This shared write logic system involves utilizing a shift register-based design with different voltage levels, preferably a high-voltage design, having shared write address and data components. This shared write logic system is designed to be accessed via a bonded chiplet, another bonded chiplet, and / or via other circuit devices within the same package as the integrated circuit 100. The shift register allows the system to move data through a series of stages, where each subsequent stage receives data from the previous stage. By utilizing shift registers, the system can increase data throughput while maintaining a low data transfer rate. The shared write address space refers to the location within the chiplet where data is written.

[0042] In another embodiment, interlock 132 can disable read ports 124, 126, 128, and 130 while data is being written to module group 106 via write port 102. Similarly, interlock 132 can disable write port 102 while read operations are being performed on read ports 124, 126, 128, and 130. The written data can then be accessed concurrently by all processing elements that need to read data via the corresponding read port among read ports 124, 126, 128, and 130. This ensures that all processing elements have their most frequently used data available, regardless of other reads performed concurrently by other processing elements.

[0043] The write peripheral 104 circuitry includes a write driver. This unit receives the data to be written and converts it into a suitable signal that can change the state of the memory cell. Depending on the type of memory technology used, these signals may involve voltage levels, current pulses, or other types of energy. Due to the specific voltage requirements of the chiplet, the shared write logic system may be high-voltage. The write driver must provide sufficient power to reliably change the state of the memory cell, but it must also operate within appropriate parameters to avoid damage or unnecessary wear.

[0044] The write peripheral 104 circuit can also have a data buffer or a write buffer. This component temporarily stores the data to be written, allowing write operations to be performed at a predetermined pace. By balancing the rate at which data enters the memory with the rate at which memory cells can be written, the write buffer helps prevent data loss and optimize system performance.

[0045] In some embodiments, the write peripheral 104 may further include a write control unit that orchestrates the sequence of operations during the write process. It generates control signals to activate the write driver at appropriate times, controls the data flow from the write buffer, and coordinates the timing of the write operations. By synchronizing these various activities, the write control unit ensures efficient and reliable write operations.

[0046] The write peripheral 104 may also include data encoding mechanisms to improve reliability and data integrity. For example, these mechanisms encode the data in a way that allows potential errors to be detected and, in some cases, corrected when the data is read later, before it is written to the memory cell. This can be helpful in systems where data integrity is a higher priority, such as in servers or scientific research equipment.

[0047] The write peripheral 104 may also include a timing unit that acts as the system heartbeat, supplying clock signals to synchronize the operation of various components of the system. In some systems, it may include components such as an oscillator, clock generator, or phase-locked loop. The timing unit ensures that all operations occur at appropriate times relative to each other.

[0048] IC 100 can be implemented as a face-to-face bonded chiplet, wherein modules 108, 110, 112, and 114 are formed from non-volatile memory. In some specific embodiments, IC 100 may also have dynamic allocation circuitry to allocate memory blocks to module group 106 based on the usage of module group 106 (e.g., each module 108 may include dynamic allocation circuitry for dynamically allocating a series of read locations for a corresponding processing element).

[0049] IC 100 has multiple clocks, each of which feeds into a corresponding module among the multiple modules, thereby providing decoupled timing for each corresponding module relative to the other modules among the multiple modules. Module group 106 can be arranged in any topology known to those skilled in the art. The bit cell density in module group 106 can be up to 10 times higher than that of embedded SRAM cells.

[0050] IC 100 can be formed on a chiplet, which includes a first side and a second side, wherein the second side is configured for bonding to a second semiconductor device. IC 100 may include high-voltage write logic adjacent to the first side of the chiplet. Decoder circuitry, driver circuitry, and register circuitry can be formed on a silicon substrate portion of the chiplet, while module group 106 is formed on a second layer portion of the chiplet. The second semiconductor device may include a plurality of processing elements. Each processing element includes a corresponding interface for communicating with a corresponding module among the plurality of modules on module group 106 when the second semiconductor device is bonded to the chiplet.

[0051] Silicon substrates have traditionally served as the initial stage in IC manufacturing, focusing on creating active components, particularly transistors. Techniques such as diffusion, ion implantation, oxidation, and material deposition are employed to shape complex transistor structures. These processes operate on a very small scale. The application of photolithography, etching, and implantation techniques enables precise definition of transistor structures. The importance of silicon substrates lies in their ability to establish the fundamental building blocks required for signal processing, amplification, and control within ICs. This layer is sometimes referred to as the "front-end process" ("FEOL").

[0052] Next, a second layer can be added in the manufacturing process. This second layer traditionally serves the role of interconnect fabrication, facilitating electrical connections between various IC components. Interconnects can include, but are not limited to, wires, conductive paths, waveguides, signal paths, logic paths, digital paths, buses, ports, etc. This level traditionally focuses on the creation of passive components, including interconnects, vias, and metal-insulator-metal (MIM) capacitors. The second-layer process typically differs from the process used on the silicon substrate in terms of precision and scale. Interconnects are formed by depositing and patterning metal layers (typically aluminum or copper) to build a wiring network. Dielectric layers, such as silicon dioxide or low-k dielectrics, are introduced to insulate the interconnects and prevent signal interference between different wiring layers. The traditional function of the second layer is to establish the necessary interconnects, enabling the routing and distribution of electrical signals throughout the IC. However, as described herein, circuitry can be used within this second layer (sometimes referred to as the “back-end process” or “BEOL”).

[0053] Alternative embodiments of IC 100 can be implemented as stacked dies and / or monolithic designs, wherein electrical connections via TSVs and / or through-silicon vias (TSVs) are used. In a stacked die design, several dies can be stacked on top of each other, with each die performing different functions, such as memory and processing. The stacked dies can communicate via wire bonding, microbumps, or bumpless bonding. In a monolithic design, various functions and modules of IC 100 can be integrated onto a single die, resulting in a more compact and power-efficient design.

[0054] In addition, IC 100 may include one or more interlocks 132 to manage conflicts during data read and write operations. Module group 106 may be formed from various non-volatile or semi-volatile (e.g., extremely long refresh periods) memory technologies, such as static random access memory (SRAM), ferroelectric field-effect transistor (FeFET), ferroelectric random access memory (FeRAM), resistive random access memory (ReRAM), spin-orbit torque (SOT) memory, spin-transfer torque (STT) memory, charge traps, floating gate memory, and / or Schottky diodes.

[0055] Module group 106 may utilize a static random access memory (SRAM) topology. The SRAM topology may employ a cross-coupled flip-flop structure (e.g., latch flip-flops) to ensure that the stored data remains intact as long as power is supplied. Therefore, in some specific embodiments, module group 106 may utilize heterogeneous types of memory, including volatile and non-volatile memory types.

[0056] Module group 106 can utilize a flash memory topology. Flash memory is a non-volatile memory technology used in applications requiring data persistence, such as solid-state drives (SSDs) and USB flash drives. The flash memory topology disclosed herein has a matrix of memory cells, each memory cell including a floating-gate transistor or a charge trapping device. Module group 106 can also use wear leveling techniques to extend the lifetime of the memory cells.

[0057] Module group 106 may utilize a ferroelectric random access memory (FeRAM) topology. FeRAM topology utilizes ferroelectric materials capable of maintaining polarization states. In a particular embodiment, such a memory topology may utilize FeFETs to retain state information and program the ferroelectric material. These ferroelectric materials can be used to retain state information and act as memory bit cells.

[0058] Module group 106 can utilize phase change memory (PCM) topology, which is a non-volatile memory technology that uses reversible phase changes in materials to store data. PCM topology can include any phase change material, such as chalcogenide alloys or chalcogenide glasses housed in memory cells.

[0059] Module 106 can utilize a resistive random access memory (ReRAM) topology, which is a non-volatile memory technology based on the resistance switching phenomenon. The ReRAM topology can utilize thin film materials that exhibit reversible resistance changes when an electrical excitation is applied.

[0060] Module group 106 can utilize a spin-orbit torque (SOT) magnetic random access memory topology. SOT-MRAM is a non-volatile memory that uses spin-orbit torque to switch the magnetic state of storage elements. The SOT-MRAM topology can incorporate a magnetic tunnel junction (MTJ) structure and utilize spin-orbit coupling effects for writing and reading data. The MTJ can have a dielectric layer between the magnetically fixed layer and the magnetically free layer. Writing can be accomplished by switching the magnetization of the free magnetic layer by injecting an in-plane current into an adjacent SOT layer. Reading can be accomplished by injecting current into the MTJ. In some specific embodiments, SOT-MRAM can optimize the spin-orbit material by using a current-driven switching scheme while minimizing write power consumption.

[0061] Module group 106 can utilize a spin-transfer torque (STT) magnetic random access memory topology. STT-MRAM is another type of non-volatile memory that relies on spin-transfer torque to manipulate the magnetic state of the storage elements. The STT-MRAM topology can use a magnetic tunnel junction (MTJ) structure, where the magnetization orientation determines the stored data. Furthermore, for example, the orientation of the magnetic layers in the magnetic tunnel junction or spin valve can be changed using spin-polarized current.

[0062] IC 100 may include a single write peripheral 104 with a dedicated clock, or each module 108, 110, 112, 114 may have its own dedicated write peripheral utilizing a shared clock. Figure 1 (Not shown in the image). In addition, module group 106 can be organized into separate partitions, each partition including dedicated read peripherals 116, 118, 120, and 122 with independent clocks.

[0063] Another possible embodiment of IC 100 includes an interface (e.g., the same, different, higher, or lower voltage) to enable data transfer outside the IC 100 package. In other specific embodiments, IC 100 may also include an integrated microcontroller unit (MCU) or digital signal processor (DSP) for processing data within the IC.

[0064] Figure 2 An embodiment according to this disclosure is shown. Figure 1 The diagram shows a perspective view of component 200 implemented on chiplet 230, where integrated circuit 212 is bonded to second device 226. Integrated circuit 212 is a circuit arrangement within chiplet 230. Second device 226 may be a chiplet, semiconductor wafer, semiconductor package, encapsulated circuit arrangement, etc. For example, second device 226 may be an AI accelerator, such that each processing unit has read access to a module (or a predetermined set) of module group 236. In another embodiment, second device 226 may be a network controller, in which offloading circuitry is present to read data from each module to process incoming / outgoing packets, etc. Component 200 includes module group 236, which has multiple modules, including first module 232 and second module 234. Figure 2 Several modules are shown; however, for clarity, only modules 232 and 234 are indicated by reference numerals. Integrated circuit 212 also includes a shared write port 222. Shared write port 222 is connected to write peripheral 202.

[0065] While the second device 226 can write data to any module within the module group 236 via the address and data buses, using clock and enable signals and the shared write port 222, other methods of writing data can also be considered. For example, serial connections, parallel connections, and various buses or ports can be used, such as DDR (Double Data Rate) interfaces, SRAM (Static Random Access Memory) interfaces, NAND flash memory interfaces, NOR flash memory interfaces, HBM (High Bandwidth Memory) interfaces, GDDR (Gradient Double Data Rate) interfaces, NVMe (Non-Volatile Memory Fast Display) interfaces, SPI, I2C, etc. Each module in the group has a read port with a read address 218 (for sending an address to module 234) and read data 214 (which is data read from chip 232).

[0066] Module group 236 is formed on a chiplet 230 having two sides. Chiplet 230 includes a surface 228, which can be bonded to and complement the second device 226. Chiplet 230 can be formed by forming circuitry on a silicon substrate 204 and then by adding a second layer 206. In other embodiments, these layers can be reversed and / or other layers can be added, removed, etc. Read address 218 and read data 220 are used to read module 232.

[0067] While the second device 226 can read data from module 232 using the clock and enable signals via the address and data buses, other methods of reading data can also be considered. For example, serial connections, parallel connections, and various buses or ports can be used, such as DDR (Double Data Rate) interfaces, SRAM (Static Random Access Memory) interfaces, NAND flash memory interfaces, NOR flash memory interfaces, HBM (High Bandwidth Memory) interfaces, GDDR (Gradient Double Data Rate) interfaces, NVMe (Non-Volatile Memory for Graphics) interfaces, SPI, I2C, etc.

[0068] All read ports (e.g., 218 and 222) are configured to be inactive when a write operation is applied to shared write port 222. Read ports can also be configured to process reads concurrently with each other. Shared write port 222 is configured to write to the address space, wherein shared write port 222 is configured to write to the first module 232 via a first portion of the address space and to the second module 234 via a second portion of the address space. Each of the plurality of modules 236 includes an independent read port for concurrent reading via the respective independent read port of any of the plurality of modules.

[0069] Each read port for a given module may include a contact for mating with circuitry found within the second device 226 via metal contacts. Therefore, metal contacts may be present on the top layer 208, configured to mate with metal contacts on the surface 228 of the chiplet 230, such that the metal contact module group 236 allows for a read space that extends together with the read space of the modules within module 236. The read spaces of module group 236 may all extend together (as shown in Figure 3 and...). Figure 4 (as described).

[0070] In one embodiment, the read peripheral for the first module 232 is implemented on the silicon substrate 204 (sometimes referred to as the front-end process). A second layer 206 (sometimes referred to as the back-end process) may then be built on top of the silicon substrate 204 (and any circuitry) during the manufacturing process and may contain corresponding memory bit cells. In another embodiment, the read peripheral for the first module 232 is implemented in the second layer 206 and is disposed between the module group 236 and the surface 228 of the chiplet 230. In some embodiments, a read peripheral is present for each module of the module group 236.

[0071] Module group 236 can be configured to process write commands only during reset. The write command can be a "slow write" command. That is, module group 236 can have a very low write speed relative to its read speed. When module group 236 is used to read data, the write logic can be frozen (or disabled). In some specific embodiments, integrated circuit 212 provides the functionality to allocate memory blocks to module group 236 based on its usage. In other embodiments, the memory addresses, along with the allocation, are fixed. Integrated circuit 212 can be implemented as a face-to-face bonded chiplet 230. Face-to-face bonding can be bumpless wafer bonding.

[0072] Module group 236 may have a single write peripheral 202. In other embodiments, each module of module group 236 may have a dedicated write peripheral utilizing a shared clock. In other embodiments, module group 236 may also be organized into separate partitions, each partition having a dedicated read peripheral, wherein each dedicated read peripheral has an independent clock. A partition may be one, two, or more modules of module group 236.

[0073] The overall architecture of the write peripheral 202 circuitry may include a series of different components, including write drivers, address decoders, sense amplifiers, data input latches, data buses, and / or some combination thereof. Write drivers or write buffers are responsible for transferring data to memory cells. They amplify input signals to achieve a level suitable for the memory cell. Address decoders are used to interpret the memory address fed as input, the address to which data needs to be written. They can be used to select the target memory cell by activating specific rows and columns of the memory array linked to that address. Sense amplifiers are used to identify and amplify signals from memory cells during read operations and also participate in flushing memory cells after data is written during write operations. Write operations are triggered by a write enable signal. When a write command is initiated, this signal drives the write driver and decoder into the write process. Data input latches can be used as temporary storage units, holding the dataset to be written to memory until the write operation is performed. A data bus with a transmission path can be used to facilitate the movement of data from the data input latches to the memory cells.

[0074] Write operations to the module group can be performed via a priority arbitration circuit that facilitates access to modules in a predetermined order, and the shared write port 222 can be configured to write to a virtual address space mapped onto the physical memory space. The integrated circuit 212 may include high-voltage write logic used within the write peripheral 202, and the second semiconductor device 226 may include multiple processing elements, each including a corresponding interface for communicating with a corresponding module of the module group 236. Furthermore, the chiplet 230 may include an interface on the second side to the shared write port 222, thereby interfacing with a supplementary interface on the second semiconductor device 226.

[0075] Integrated circuit 212 may also include a power gating circuit that selectively shuts off the power of modules in the plurality of modules 236 when not in use. Furthermore, integrated circuit 212 may have a write peripheral 202 for the module group 236 connected to dedicated I / O pads to enable external data transfer from the integrated circuit package.

[0076] Integrated circuit 212 may utilize multiple modules of module group 234 grouped together. In certain embodiments, these modules may be synchronized with each other. In some cases, all modules are synchronized, while in other instances, only specific modules will be synchronized. For example, when data is read from one module in module group 236, the circuitry on second device 226 is synchronized with the specific module.

[0077] To synchronize the modules, integrated circuit 212 can use various timing techniques. In some cases, multiple clocks can feed each corresponding module of module group 236, thereby allowing each module to have decoupled timing relative to other modules in the group. This decoupling ensures that any delay in one module will not affect the functionality of other modules. It is worth noting that the clocks used may or may not need to be synchronized. In some cases, a common clock can be used to synchronize the modules. In other embodiments, one or more clock signals may be provided by second device 226.

[0078] In alternative embodiments, other synchronization techniques can be used, such as phase comparison of the clock signal or phase-locked loop (PLL) synchronization methods. Another embodiment of the synchronization module in the IC can use delay-locked loop (DLL) synchronization. In this method, a delay element is added to the clock signal path, and the output is compared with the input clock signal. The feedback loop adjusts the delay element until the output of the DLL matches the input, thereby resulting in synchronization of the clock signals.

[0079] In another embodiment, integrated circuit 212 can use a combination of different synchronization techniques to achieve synchronization between modules. For example, depending on the specific requirements of the modules, some modules may use PLL synchronization, while other modules may use clock delay lines or DLL synchronization. Furthermore, integrated circuit 212 may also use redundant synchronization techniques to ensure reliability and redundancy in the event of a failure of one method. For example, integrated circuit 212 may use both phase-locked loop (PLL) synchronization and DLL synchronization simultaneously, so that if one method fails, the other method can still maintain synchronization.

[0080] Figure 3A A perspective view of component 240 according to an embodiment of the present disclosure is shown. Component 240 has Figure 1An integrated circuit is implemented on a memory module semiconductor device 243, which is electrically connected to an FPGA semiconductor device 245 having a field-programmable gate array architecture 246 to form a component 240. The memory module semiconductor device 243 has a plurality of memory modules 253, which can be written to by a shared write peripheral 241. In some embodiments, the memory modules 253 may be an interleaved pattern (e.g., a grid). Each memory module 253 includes a read peripheral 242, which is also on the memory module semiconductor device 243. A 3D memory structure 244 may be used to form the memory modules 253. Write data can be received via a shared write port 251, which is coupled to write interface logic 252 of the FPGA semiconductor device 245. The FPGA semiconductor device 245 has a programmable gate array architecture 246, which may be an FPGA. The FPGA semiconductor device 245 includes interface logic, which may include read address interface logic 249 and read data interface logic 250. Data read port 248 can transfer data from memory module semiconductor device 243 to FPGA semiconductor device 245. Address read port 247 can transfer address read from FPGA semiconductor device 245 to memory module semiconductor device 243.

[0081] Component 240 includes a memory module semiconductor device 243, which is bonded to an FPGA semiconductor device 245. The memory module semiconductor device 243 contains a plurality of memory modules 253 capable of storing data. The memory modules 253 are formed using a 3D memory structure 244 to achieve high-density data storage.

[0082] Memory module 253 can be accessed independently via read peripherals 242 located within memory module semiconductor device 243. Each read peripheral 242 is connected to a corresponding memory module 253. For example, read peripheral A is connected to memory module A, read peripheral B is connected to memory module B, and so on. This independent connectivity allows different parts of FPGA semiconductor device 245 to concurrently access different memory modules 253 via separate read ports 247, 248 without interference. Read peripherals 242 can be positioned in an interval pattern (e.g., a grid).

[0083] In some embodiments, the memory module semiconductor device 243 includes a plurality of memory modules 253 organized into a 3D memory structure 244, which may be arranged to maximize memory density. The memory modules 253 may store data accessed by different processing elements within the FPGA semiconductor device 245.

[0084] The read peripheral 242 provides access to the memory module 253 via read address port 247 and read data port 248. Each read address port 247 interfaces with the read peripheral 242 and receives a read address specified by a processing element in the FPGA semiconductor device 245. These addresses are used by the read peripheral 242 to query the appropriate location within the corresponding memory module 253. The read data port 248 then transmits the data retrieved from the memory module 253 to the interface logic in the FPGA semiconductor device 245.

[0085] All read operations via read address port 247 and read data port 248 can occur independently without interfering with each other. This ensures that multiple processing elements can concurrently read data from different memory modules 253 without latency. Independent read access also allows processing elements (in some embodiments) to efficiently access the desired data stored in dedicated memory module 253 without queuing or arbitration between read requests.

[0086] Shared write peripheral 241 facilitates writing to memory module 253. Shared write peripheral 241 receives a shared write address and write data via shared write port 251. Using the shared write address, shared write peripheral 241 writes the received data to any specified memory location within memory module 253. During a write operation, read ports 247 / 248 can be disabled via an interlock (not shown) to avoid read conflicts. This shared write access allows for efficient, single-cycle writing of updated data to memory module 253.

[0087] The FPGA semiconductor device 245 includes a programmable gate array architecture 246, which may also include various processing elements. Interface logic may include read address interface logic 249 and read data interface logic 250, which can connect logic and / or processing elements to memory interconnects. Read address interface logic 249 interfaces with read address port 247, and read data interface logic 250 interfaces with read data port 248. A shared write port 251 is connected to write interface logic 252, which interfaces with a shared write peripheral 241 via the shared write port 251 to facilitate write access to memory module 253.

[0088] FPGA semiconductor device 245 includes a field-programmable gate array architecture 246, which provides programmable logic and interconnect resources. The field-programmable gate array architecture 246 comprises an array of configurable logic blocks (CLBs) arranged in a two-dimensional grid layout. Each CLB includes a programmable lookup table (LUT), flip-flops, and programmable interconnects to implement user logic functions and connections between functions.

[0089] The field-programmable gate array architecture 246 may also include a hierarchical programmable interconnect structure with various types of interconnects, including short lines connecting adjacent CLBs, longer lines connecting more distant CLBs, and even longer lines spanning the entire FPGA semiconductor device 245. These interconnects can be programmably connected at a programmable switch box to provide configurable routing of signals between different logic blocks.

[0090] The interconnect structure within the Field Programmable Gate Array (FPGA) architecture 246 can utilize passive routing switches, such as antifuses or SRAM, to programmatically connect different logic and interconnect resources. These passive routing switches can be configured to implement user designs by loading a configuration bitstream, which sets the switch states and programs the functionality implemented by the LUTs and flip-flops.

[0091] In addition to programmable logic blocks and interconnects, the FPGA semiconductor device 245 may also include configurable input / output blocks (IOBs) arranged around the peripherals of the field-programmable gate array architecture 246. IOBs include programmable power buffers, registers, and high-speed serial transceivers to interface between the programmable architecture and external package pins.

[0092] The FPGA semiconductor device 245 may also include dedicated memory interface circuitry, which may be integrated into some areas of the IOB or programmably distributed throughout the CLB. These memory interface circuits provide ports compatible with common memory standards to interface with off-chip memory or with on-chip memory interfaces of other devices within the component. In this particular embodiment, the FPGA semiconductor device 245 may include a shared write peripheral 241, which is integrated into one area. The shared write peripheral 241 may include circuitry for implementing protocols required to write data to any memory module 253 within the memory module semiconductor device 243 via the shared write port 251. The shared write peripheral 241 may utilize the programmable resources of the field-programmable gate array architecture 246 and may be connected to the shared write port 251 via dedicated I / O pins or programmably routed throughout the FPGA.

[0093] The FPGA semiconductor device 245 also includes interface logic in the form of read address interface logic 249 and read data interface logic 250. This interface logic can be programmably distributed across the FPGA's CLBs to interface with read address port 247 and read data port 248 respectively within the programmable architecture. The interface logic may include registers, buffers, and other auxiliary circuitry to meet timing requirements for high-speed memory read transfers.

[0094] The field-programmable gate array architecture 246 (including CLBs, IOBs, and programmable interconnects) in some embodiments can be programmed and reprogrammed multiple times within the system using a configuration bitstream loaded via an external active serial or parallel configuration interface. This facilitates modifications to user designs implemented in the FPGA semiconductor device 245 throughout the system's lifetime.

[0095] A Field-Programmable Gate Array (FPGA) architecture 246 resides on an FPGA semiconductor device 245. The FPGA architecture 246 provides programmable logic and routing resources. The FPGA architecture 246 may include an array of programmable logic blocks, which can be configured to perform basic logic functions such as AND, OR, NOT, NAND, NOR, and XOR. The programmable logic blocks can be interconnected via a configurable routing structure, which allows for the routing of customizable logic signals between blocks. This programmable interconnection of logic and routing resources allows for the implementation of different combinational or timing functions within the FPGA architecture 246 through a process known as hardware description language programming.

[0096] The field-programmable gate array (FPGA) architecture 246 can utilize non-volatile memory elements (such as static RAM (SRAM) cells, antifuse, or flash memory) to store configuration data for programmable logic blocks and switches. Each memory cell corresponds to a programmable resource within the FPGA architecture 246, such as a lookup table, routing switch, or logic gate. The state of each memory cell determines whether the associated logic block or interconnect is active and its specific configuration.

[0097] The field-programmable gate array (FPGA) architecture 246 may include interface logic that provides connectivity to external circuitry integrated on the FPGA semiconductor device 245. Specifically, the FPGA architecture 246 may include read address interface logic 249 coupled to read address port 247 and read data interface logic 250 coupled to read data port 248. This interface logic facilitates communication between the programmable logic and routing resources of the FPGA architecture 246 and other components located on the FPGA semiconductor device 245, such as memory modules on a bonded memory semiconductor device.

[0098] In summary, the Field Programmable Gate Array (FPGA) architecture 246 provides configurable logic and routing capabilities for the FPGA semiconductor device 245. The FPGA architecture 246 can be programmed to implement various digital circuits by loading configuration data, thereby allowing for flexible and reconfigurable utilization in a wide range of system applications and designs.

[0099] The interface logic located within the FPGA semiconductor device 245 includes read address interface logic 249 and read data interface logic 250. The read address interface logic 249 and read data interface logic 250 facilitate communication between the programmable gate array architecture 246 and the memory module 253 on the memory module semiconductor device 243.

[0100] The read address interface logic 249 may include circuitry for transmitting read address signals from the programmable gate array architecture 246 to the memory module semiconductor device 243. The read address interface logic 249 may include a plurality of read address interconnects that form a path for the read address signals to exit the FPGA semiconductor device 245 from the gate array architecture 246. These read address interconnects are routed to terminate at a set of read address bonds located on the surface of the FPGA semiconductor device 245. The read address may be a raw address, or it may be transformed by the read address interface logic 249 in some embodiments.

[0101] The read address bonding element is configured to electrically interconnect with a supplementary set of read address bonding elements on memory module semiconductor device 243 when the two devices are bonded together. Using this electrical coupling, a read address signal output from read address interface logic 249 can propagate from FPGA semiconductor device 245 to memory module semiconductor device 243 to access a specific memory location.

[0102] The read address interface logic 249 may further include a read address register circuitry for registering the read address signal before it is transmitted from the programmable gate array architecture 246 to the read address interconnect and bonding elements. This read address register can act as an interface between the gate array architecture 246 and the timing domain of the memory module semiconductor device 243. The read address register can sample the read address signal on the register clock edge and then transmit the sampled read address to the interconnect based on timing constraints to ensure that correct setup and hold times are met.

[0103] In some specific embodiments, the read address interface logic 249 may include an address decoder circuitry for decoding a portion of the transmitted read address signal on the memory module semiconductor device 243 side to selectively access the appropriate memory module 253. The address decoder circuitry converts a portion of the transmitted read address into a decoded signal that enables a specific row, column, or other access line of a given memory module 253. In other embodiments, the read address interface logic 249 transmits the address to the semiconductor device 243 without decoding.

[0104] The read data interface logic 250 may include circuitry for receiving read data returned from the memory module 253 on the memory module semiconductor device 243. The read data interface logic 250 may include read data interconnects that form paths for the received read data to enter the FPGA semiconductor device 245 from the memory module semiconductor device 243. These read data interconnects terminate at an assembly of read data bonds on the surface of the FPGA semiconductor device.

[0105] Similar to the read address bonding, the read data bonding can be configured to be electrically coupled to a supplementary set of read data bonding on memory module semiconductor device 243. Through this coupling, read data signals can propagate from the memory location accessed on memory module 253 to memory module semiconductor device 243, and then across to FPGA semiconductor device 245 via read data interconnect paths and bonding.

[0106] The read data interface logic 250 may include a read data register circuit arrangement for registering the received read data signal before transmitting it to an internal read data interconnect coupled to the programmable gate array architecture 246. The read data register can act as a docking element between timing domains and can latch the read data signal using a register clock edge, and then transmit the latched read data signal according to defined setup / hold constraints.

[0107] The read data interface logic 250 may include latch or decoder circuitry on the FPGA semiconductor device 245 side for accessing read data signals in a format suitable for the gate array architecture 246. The read data interface logic 250 coordinates data transfers between the memory module semiconductor device 243 and the internal resources of the programmable gate array architecture 246.

[0108] The read address interface logic 249 and the read data interface logic 250 together enable the programmable gate array architecture 246 to interface with the memory module 253 on the memory module semiconductor device 243 via a suitable timing sequence. Interface logics 249 and 250 enable address, data, and control signals to be transmitted and received across the bonded semiconductor device in a constructively correct manner, thereby satisfying all timing constraints.

[0109] In some embodiments, as described herein, interface logic 249, 250 may further include test circuitry, such as a boundary scan unit or logic for performing built-in self-tests on interconnect paths and bonding between the bonded semiconductor devices. Boundary scan units may be daisy-chained to test interconnects prior to semiconductor device bonding. Overall, read address interface logic 249 and read data interface logic 250 provide an interface between the programmable logic resources of the FPGA and the memory on the memory chip.

[0110] As previously described, the read address interface logic 249 is part of the interface logic, which facilitates communication between the FPGA semiconductor device 245 and the memory module semiconductor device 243. The read address interface logic 249 includes circuitry for transmitting a read address signal from the FPGA semiconductor device 245 to the memory module semiconductor device 243 during a memory read operation to select a specific memory location.

[0111] The read address interface logic 249 resides within an integrated circuit formed by face-to-face bonding between the FPGA semiconductor device 245 and the memory module semiconductor device 243. The read address interface logic 249 is positioned between the field-programmable gate array architecture 246 and the read address port 247. This allows the read address interface logic 249 to receive read address signals from the field-programmable gate array architecture 246 and transmit the corresponding read address signals to the memory module semiconductor device 243 via the read address port 247.

[0112] The read address interface logic 249 includes an input / output interface operatively coupled to a field-programmable gate array (FPGA) architecture 246 and a read address port 247. The interface to the FPGA architecture 246 receives read address signals originating from the programmable logic array core or other processing elements within the FPGA semiconductor device 245. The interface to the read address port 247 transmits appropriate read address signals received by the memory module semiconductor device 243.

[0113] In addition to the signal interface and as previously described, the read address interface logic 249 may include register circuitry, decoding logic, and transfer driver circuitry. The register circuitry latches the read address signal from the field-programmable gate array architecture 246 in preparation for transmission. The decoding logic decodes the address information and selects one or more appropriate read address lines. The transfer driver circuitry amplifies the read address signal to the voltage level required for reliable transmission through the read address port 247.

[0114] The read address interface logic 249 may include circuitry for supporting various embodiments. In one embodiment, the read address interface logic 249 supports a single read address line for addressing an individual memory location. In another embodiment, the read address interface logic 249 supports multiple parallel read address lines to allow for higher memory bandwidth through wider addressing. The read address interface logic 249 may also incorporate error detection or correction mechanisms to facilitate reliable transmission of address signals.

[0115] The read address signal transmitted by read address interface logic 249 is received by memory module semiconductor device 243 through read address port 247, for example via an array of metal contacts on the surface of memory module semiconductor device 243. These metal contacts are aligned with corresponding contacts on the bonded surface of FPGA semiconductor device 245, thereby enabling direct electrical connection when the two semiconductor devices are bonded face-to-face. Once received, the read address signal is used by the read peripheral within memory module semiconductor device 243 to access a specific memory location based on a given read address.

[0116] In this manner, the read address interface logic 249 allows programming logic and processing elements within the FPGA semiconductor device 245 to indirectly access the contents of the 3D memory structure 244 by selecting a target memory location through the transmission of an appropriate read address signal, thereby providing access to the integrated memory. The read address interface logic 249 provides an interface that facilitates reliable read operations between the logic-programmable FPGA semiconductor device 245 and the large-capacity, directly addressable memory implemented by the 3D stacked memory structure 244.

[0117] As previously described, the read data interface logic 250 is responsible for transmitting read data from the memory module 253 to the FPGA semiconductor device 245. The read data interface logic 250 may include read data registers, which are used to capture and buffer read data received from the memory module 253. These read data registers can provide temporary storage for the read data, thereby allowing time for the read data to drive onto the read data interconnect, while also taking into account any timing delays during read data propagation. The read data registers can be configured to provide data integrity and prevent data loss during read operations.

[0118] The read data interface logic 250 may also include read data interface circuitry connected to the read data register. This read data interface circuitry drives the read data buffered in the register to the read data interconnect 218. Taking into account factors such as interconnect length and load, the driver strength of the read data interface circuitry can be set to safely transmit the read data signal. In some embodiments, the read data interface circuitry may provide additional amplification or buffering of the read data signal.

[0119] Read data interconnects 218 form part of read data interface logic 250 and can be used to transfer read data from registers to bonding members 248 on the surface of memory module semiconductor device 243. These read data interconnects can extend from the location of the read data register to the bonding member. In some embodiments, the read data interconnects can utilize a low-resistance metal (such as copper) to minimize signal delay.

[0120] The bonding element may be part of the read data interface logic 250, providing an electrical connection between the read data interconnect and the surface of the memory module semiconductor device 243. These bonding elements allow read data signals to be transmitted to the FPGA semiconductor device 245 once bonding enables electrical communication between devices 243 and 245. In some embodiments, the bonding element 248 may be a metal solder ball, copper pillar, metal pad, etc.

[0121] The read data register, read data interface circuit, read data interconnect, and bonding element of read data interface logic 250 are used together to transmit read data from memory module 253, capture and buffer read data signals, drive read data onto the interconnect, and transmit read data signals to the bonded FPGA semiconductor device 245. Read data interface logic 250 thus enables reliable transmission of read data from memory module 253 for use by the FPGA core.

[0122] In some embodiments, the read data interface logic 250 may include additional components, such as data encryption / decryption circuitry or error detection and correction circuitry, to ensure the security and reliability of read data transmission between the memory module 253 and the FPGA semiconductor device 245. The read data interface logic 250 provides an interface between the memory device and the programmable logic, which seamlessly transmits read data while satisfying timing and signal integrity constraints.

[0123] Write interface logic 252 provides an interface between FPGA semiconductor device 245 and shared write port 251 to facilitate the transfer of write address, write data and write control signals from FPGA semiconductor device 245 to shared write port 251.

[0124] The write interface logic 252 may include a write address register that receives a write address from an address generation circuitry within the field-programmable gate array architecture 246 of the FPGA semiconductor device 245. The write address register holds the write address to be transferred to the shared write port 251. The write interface logic 252 may also include write address interconnects that transfer the write address from the output of the write address register to a plurality of write address bonds 750 on the surface of the FPGA semiconductor device 245. These write address bonds 750 provide an interface between the write address interconnects and the shared write port 251 when the FPGA semiconductor device 245 is bonded to the memory module semiconductor device 243.

[0125] In addition to the write address register and interconnects, the write interface logic 252 includes a write data register that receives write data from circuitry within the programmable gate array architecture 246. For example, the write data may include weights, instructions, or other data to be written to the memory module 253. The write data register holds write data to be transferred to the shared write port 251. The write interface logic 252 also includes write data interconnects coupled to the output of the write data register. These write data interconnects transfer write data to multiple write data bonds on the surface of the FPGA semiconductor device 245, which interface with the shared write port 251 upon bonding.

[0126] The write interface logic 252 further includes a write control register that receives write control signals, such as a write enable signal, from control circuitry within the programmable gate array architecture 246. For example, the write control signal may include a write enable signal that initiates a write operation when activated. The write control register holds write control signals to be transmitted to the shared write port 251. The write interface logic 252 also includes write control signal interconnects coupled to the output of the write control register. These write control signal interconnects transmit write control signals (such as the write enable signal) to a write control signal bond 754 on the surface of the FPGA semiconductor device 245, which interfaces with the shared write port 251.

[0127] The write interface logic 252 also includes a write clock pad for receiving a write clock signal. This write clock pad can be coupled to write clock interconnects that distribute the write clock signal to the write address register, write data register, and write control register within the write interface logic 252. The write clock signal synchronizes the operation of these registers and the timing of the write operation. The write interface logic 252 may optionally include a frequency divider circuit to generate a divided write clock signal, which is transmitted to the shared write port 251 via a write clock bond 756 on the surface of the FPGA semiconductor device 245.

[0128] The write interface logic 252 can provide write timing control signals via timing controller circuitry within the write interface logic 252. These timing control signals are transmitted via timing control signal bonding on the surface of the FPGA semiconductor device 245 to interface with the shared write port 251. The timing control signals synchronize write address generation, data transfer, and the operation of other timing-sensitive circuitry associated with the write operation.

[0129] In an alternative embodiment, write interface logic 252 may include level shifter circuitry to adjust the voltage level of the write signal to match the voltage requirements and specifications of the shared write port 251. For example, the shared write logic system may employ a high-voltage design for write reliability and durability. The level shifter circuitry helps ensure compatibility between write interface logic 252 and the shared write port 251.

[0130] Write address bonding member 750, write data bonding member 752, write control signal bonding member 754, write clock bonding member 756, and timing control bonding member 758 formed on the surface of FPGA semiconductor device 245 are configured to physically, electrically, and signal-interact with shared write port 251 when FPGA semiconductor device 245 is bonded to memory module semiconductor device 243, thereby enabling the transmission of write address, write data, and control signals from FPGA semiconductor device 245 to shared write port 251 and memory module 253 during write operations.

[0131] In summary, the write interface logic 252 provides an interface between the programmable gate array architecture 246 of the FPGA semiconductor device 245 and the shared write port 251 to transmit write address, write data, and control signals in appropriate timing during write operations to the memory module 253, thereby facilitating the writing of data from circuitry within the programmable gate array architecture 246 to the memory module 253. The write interface logic 252 can handle signal transmission, timing control, voltage level conversion, and physical interfacing between the two semiconductor devices 245 and 243 during write operations to the memory module 253.

[0132] The memory module semiconductor device 243 includes a 3D memory structure 244, which forms a plurality of memory modules 253. The 3D memory structure 244 utilizes the vertical stacking of memory cell layers separated by interlayer dielectric layers to significantly increase memory density. This vertical integration enables the formation of a large number of memory cells within a limited chip surface area.

[0133] Each memory module 253 may include an array of non-volatile memory cells capable of retaining data when power is off. The memory cells may utilize flash memory, resistive random access, spin torque transfer, phase-change memory technology, etc.

[0134] The memory module 253 can be accessed independently via the read peripheral 242 included within the memory module semiconductor device 243. This independent connectivity allows different parts of the FPGA semiconductor device 245 to concurrently access different memory modules 253 via separate read address ports 247 and read data ports 248 without interference.

[0135] Each read peripheral 242 may include circuitry that interfaces with its corresponding memory module 253. This may include row address decoders and column address decoders for selecting memory cells based on supplied addresses, sense amplifiers for detecting and amplifying signal levels during read operations, I / O circuitry for transmitting data to and from the memory module 253, and control logic for orchestrating read operations in response to control signals.

[0136] Memory module 253 can be written to via shared write peripheral 241. Shared write peripheral 241 includes circuitry such as write address decoder, write driver, data buffer, and control logic to perform write operations on any memory location within the plurality of memory modules 253.

[0137] In some specific embodiments, when power is disconnected or the memory module semiconductor device 243 is not being written to, the memory module 253 can maintain its data retention for an extended period of time without requiring power. This non-volatility allows data to persist even after power is removed, thereby allowing the memory to act as a permanent or semi-permanent storage device in some embodiments.

[0138] The independent read ports provided by each read peripheral 242, combined with the high-density combination achieved through 3D integration, allow the memory module semiconductor device 243 to provide parallel access to independent memory spaces through different processing elements or logic within the FPGA semiconductor device 245. This can provide efficient data access for a variety of memory-intensive applications, such as those required for AI accelerators.

[0139] Each memory module 253 can be formed on a memory module semiconductor device 243 in a second layer above a silicon substrate. The memory modules 253 can be arranged in an array structure within a 3D memory structure 244 utilizing vertically stacked memory cells. The memory cells within each memory module 253 can utilize various memory technologies, including SRAM, DRAM, flash memory, resistive RAM (ReRAM), magnetoresistive RAM (MRAM), phase-change memory (PCM), etc.

[0140] Memory cells can be arranged in a matrix of rows and columns, where word lines and bit lines are used to access individual memory cells based on the supplied memory address. Sensing amplifiers can be used to detect and amplify signals from the bit lines during read operations. Voltage generation circuitry supplies the voltage required for programming, erasing, or reading memory cells based on the memory technology employed. Additional circuitry, such as address decoders, input / output circuitry, and control logic, is used to orchestrate memory operations in response to supplied control signals and commands.

[0141] Error correction circuitry, such as ECC (Error Correction Code) encoder / decoder blocks, can be included within each memory module 253 or implemented at a higher level to protect data integrity. For example, wear leveling and bad block management circuitry can be used to increase memory durability after multiple program / erase cycles. On-chip voltage regulators can be used to ensure a stable power supply, thereby enabling reliable memory operation. In some specific embodiments, a finite state machine or control processor manages the overall sequence of memory operations.

[0142] Each memory module 253 has a dedicated read peripheral 242, which includes register and buffer circuitry associated with read operations from that memory module 253. For example, read peripheral 242A is dedicated to memory module 253A. Read peripheral 242 is responsible for receiving and latching a read address from the associated read address interconnect 247. It then decodes and activates the appropriate word lines and bit lines to access the addressed memory location. Data is sensed and amplified, and then latched and buffered in read peripheral 242 before being output on the associated read data interconnect 248.

[0143] The read peripheral 242 may include control circuitry such as an address decoder, data sense amplifier, input / output buffer, and latches to reliably interface between the associated memory module 253 and the shared read data interconnect 248. It can operate based on control signals supplied by a clock from the read clock interconnect 249.

[0144] In this manner, each memory module 253 can be accessed independently and concurrently via a dedicated read peripheral 242 when serving multiple read requests from different processing elements in FPGA 245, thereby maximizing memory productivity. In some specific embodiments, the read peripheral 242 can provide buffering and control to interface between a potentially higher-speed FPGA 245 and a lower-speed memory technology in the memory module 253.

[0145] All memory modules 253 can share the same write peripheral 241 to receive write addresses and data via the shared write port 251 under the control of write interface logic 252. The write peripheral 241 may include addressing circuitry, data input / output circuitry, and control logic to program memory cells in any memory module 253 across a common write address space based on the supplied address values.

[0146] In summary, each memory module 253 within the 3D memory structure 244 provides an independent data storage device that can be randomly accessed via a dedicated read peripheral 242. Concurrent and independent read accesses to different memory modules 253 maximize memory bandwidth when servicing multiple read requests, while the shared write peripheral 241 efficiently handles memory programming via a shared write port 251.

[0147] The shared write port 251 is configured to write data to multiple memory modules 253 via a shared write peripheral 241 located on the memory module semiconductor device 243. The shared write peripheral 241 receives write data, write address, and write clock signal from the FPGA semiconductor device 245. Specifically, write data is received from the write interface logic 252 of the FPGA semiconductor device 245 via the shared write port 251, and the shared write port 251 is coupled to the shared write peripheral 241.

[0148] The shared write peripheral 241 includes various components and circuitry for performing write operations to the memory module 253. It may include a write driver that receives write data from the shared write port 251 and converts it into appropriate signals, such as voltage levels or current pulses, capable of altering the state of memory cells within the memory module 253. The shared write peripheral 241 may also include a write buffer or a data buffer that temporarily stores write data received from the shared write port 251. This allows write operations to the memory module 253 to be performed at a controlled pace, balancing the rate of incoming write data with the write speed capability of the memory module 253.

[0149] The shared write peripheral 241 also includes a write control unit that sequences write operations. It can generate control signals at appropriate times to activate the write driver, control the flow of write data from the write buffer, and coordinate the timing of write operations. By synchronizing these write operations, the write control unit can facilitate efficient and reliable writing of data to the addressed locations within the memory module 253. In some specific embodiments, the shared write peripheral 241 may also include error detection and correction mechanisms to improve the reliability and integrity of the written data.

[0150] In some specific embodiments, the shared write peripheral 241 may be a single peripheral circuit shared by all memory modules in memory module 253. It receives write data, address, and control / timing signals via the shared write port 251, and uses the aforementioned components and techniques to control / arrange the writing of that data to multiple target memory locations within the addressed memory module(s) ...

[0151] Each read peripheral 242 may include read address interface logic 249 to receive and decode a read address sent from the FPGA semiconductor device 245. The read address interface logic 249 translates the received read address to determine which memory location within the corresponding memory module 253 is being requested.

[0152] Furthermore, each read peripheral 242 may include read data interface logic 250 to interface with a corresponding memory module 253 and send read data to the FPGA semiconductor device 245. The read data interface logic 250 may include circuitry for accessing the corresponding memory module 253 based on a decoded read address. This may include enabling appropriate word lines and bit lines within the 3D memory structure 244 to access the requested memory cell / location. The read data interface logic 250 also includes output drivers, registers, and / or latches to temporarily store read data and to transfer the read data to the read data port 248 at appropriate times based on a read clock signal.

[0153] Each read peripheral 242 can operate independently and concurrently with other read peripherals, allowing different processing modules or cores within the FPGA 245 to simultaneously read non-overlapping portions of the address space. The read address interface logic 249 and read data interface logic 250 within each read peripheral 242 include logic and circuitry to prevent interference or conflicts between concurrent read operations.

[0154] In some embodiments, each read peripheral 242 may include additional circuitry, such as decoders, latches, multiplexers, and synchronous or asynchronous control logic, to manage the read operation flow and coordinate interaction with the corresponding memory module 253. In some embodiments, error-correcting code (ECC) encoding and decoding circuitry may also be included.

[0155] Timing circuitry such as programmable delay lines, clocks, and phase-locked loops (PLLs) can be distributed across the read peripherals 242 to synchronize operations between peripherals and across the memory bus. Alternatively, an independent timing source (such as a ring oscillator) embedded within each read peripheral 242 provides a local clock isolated from other peripherals.

[0156] Read peripheral circuitry can be implemented using standard digital and memory interface circuitry, which includes logic gates, registers, and other basic elements built depending on memory technology and interface requirements. In some embodiments, the read peripheral logic incorporates any suitable adaptive techniques, such as power gating, voltage / frequency scaling, or adaptive circuitry that can modify gate size adjustments or interconnect schemes to optimize operation.

[0157] In an alternative embodiment, any components, circuitry, and techniques described above in reference to read peripheral 242 may be partially or wholly contained within the interface logic block 247 itself, rather than distributed within the individual read peripheral circuitry. Various applicable architectures will be understood by those skilled in the art.

[0158] The 3D memory structure 244 can be formed on the memory module semiconductor device 243 and can be used to implement multiple memory modules 253. The 3D memory structure 244 can employ a three-dimensional crosspoint resistive memory array, such as a three-dimensional resistive random access memory (ReRAM) array, to increase the memory density of the memory modules 253 in some specific embodiments.

[0159] 3D memory structure 244 may include vertically stacked memory layers, each layer comprising a regular arrangement of metal wires that act as electrodes to access memory elements within the layer. These wires are orthogonally arranged in different layers such that the intersections of the wires between layers form memory elements accessible via their respective electrodes. For example, the wires in the first layer may extend in a lateral direction, while the wires in directly adjacent second and third layers extend orthogonally in the vertical and lateral directions, respectively. This orthogonal arrangement of lines at the intersections of each layer creates three-dimensional intersection nodes that integrate memory elements, such as oxide-based reversible resistive switching elements.

[0160] The memory elements within the 3D memory structure 244 can utilize any resistance-switching material suitable for non-volatile memory applications. In one embodiment, the memory element uses transition metal oxide materials, such as hafnium oxide (HfOx), titanium oxide (TiOx), tantalum oxide (TaOx), aluminum oxide (AlOx), zinc oxide (ZnOx), and / or niobium oxide (NbOx), as a reversible resistance-switching layer between electrodes. Other candidate materials for the memory element include chalcogenide materials (such as germanium-antimony-tellurium (GST)) and various solid electrolytes.

[0161] Regardless of the specific material, each memory element can be switched between a high-resistance reset state and a low-resistance set state by applying appropriate write voltages of different polarities across the element via its respective top and bottom electrodes. The state of each memory element can be read non-destructively by applying a lower read voltage and sensing the resulting read current or resistance. This allows each three-dimensional junction to operate as a single memory bit, thereby increasing the memory bit density per unit area compared to conventional two-dimensional memory device implementations in some specific embodiments.

[0162] Each memory module 253 comprises a three-dimensional block portion of the entire 3D memory structure 244. The block size can be configured based on factors such as desired module capacity and manufacturing constraints. Each block can be addressed via row and column decoding circuitry associated with a corresponding read peripheral 242. Word lines and bit lines are connected to the rows and columns within each block, respectively, to allow selective access to individual memory elements via their intersections. Sensing amplifiers can also be associated with each read peripheral 242 to detect the resistance state of the addressed memory element during a read operation.

[0163] Each row of memory elements within the block can be implemented as a vertically extending metal nanowire electrode, where orthogonally extending bit lines serve as a lateral thin metal layer, acting as another electrode for each three-dimensional memory junction. An additional thin dielectric layer is sandwiched between the nanowire layer and the bit line layer to provide electrical isolation in non-crossing regions. The vertical nanowires can be formed using a top-down nanofabrication process involving deposition and patterning. The bit lines can be deposited and patterned using damascene processes common in back-to-office (BEOL) semiconductor manufacturing.

[0164] To achieve full three-dimensional memory density, multiple blocks within each memory module 253 can be vertically stacked. In one approach, vertical stacking may involve iteratively depositing alternating horizontal and vertical thin film layers to progressively build a monolithic three-dimensional structure. In another approach, pre-formed vertical blocks can be horizontally integrated in a chip stacking method using a combination of photolithography, thin film deposition, and planarization techniques to progressively build a complete multi-block structure. Interconnects are routed within the 3D memory structure 244 and to read peripherals 242 for addressing individual blocks and the entire three-dimensional memory array within each memory module 253.

[0165] Regardless of the internal 3D structure used, each memory module 253 can interact with its corresponding read peripheral 242. The read peripheral 242 receives a read address signal from the FPGA device 245 to access the corresponding memory location within the block-level 3D memory structure 244 of the associated memory module 253. Data is read and then returned from the selected memory location to the FPGA device 245 via the read peripheral 242. Additional control and power delivery circuitry may also be included within the memory module 253 or the 3D memory structure 244 thereof, as needed, to enable normal storage operations and support writing, reading, and erasing of memory elements at the module or system level.

[0166] Additional components can optionally be included in the 3D memory structure 244 to support various operations and functions. For example, redundant rows and columns can be added to replace defective areas and improve manufacturing yield. Voltage generators, address decoders, and other analog control circuitry can be placed within the structure as needed. Temperature sensors and thermal removal structures can be integrated for thermal monitoring and management. Furthermore, dynamic partitioning and wear leveling schemes can be implemented within the 3D memory structure 244 to balance write and erase cycles across its elements.

[0167] In summary, the 3D memory structure 244 can use three-dimensional stacking of thin films and cross-point resistive memory elements to increase the density of non-volatile data storage devices within each memory module 253 compared to conventional two-dimensional memory implementations. This increased storage density allows the high-capacity memory module 253 to interface individually with the processing core via corresponding read peripherals 242, thereby providing dedicated high-speed access to data and instructions for each core or processor within the overall system.

[0168] Read address port 247 provides an interface for transmitting read address signals from FPGA semiconductor device 245 to memory module semiconductor device 243. Read address port 247 includes a plurality of conductive contacts or pads formed on the surface of memory module semiconductor device 243. These contacts are arranged such that when two semiconductor devices 243, 245 are bonded together, they will align with and bond to a supplementary set of contacts on FPGA semiconductor device 245.

[0169] The read address port 247 can be coupled to receive read address signals from read address interface logic 249 located within the interface logic of the FPGA semiconductor device 245. The read address interface logic 249 includes circuitry for receiving read address signals from other components within the FPGA 245, such as programmable logic circuitry or a processor core, and for appropriately modulating the signals for transmission via the read address port 247.

[0170] The read address interface logic 249 includes read address buffer and register circuitry that temporarily stores the incoming read address signal and synchronizes the signal with the read clock signal. This ensures that the read address signal is transmitted to read address port 247 at the appropriate point in the read clock cycle. The buffer and registers allow the read address signal to be pipelined and transmitted continuously, thereby maximizing productivity and efficiency.

[0171] The read address port 247 includes a plurality of conductive lines or traces formed within the memory module semiconductor device 243, which electrically connect pads on the surface of the device to circuitry within the device. In some embodiments, the conductive lines may be formed within a back-end process metal stack on top of the silicon substrate of the device 243. In other embodiments, the conductive lines may be routed along the silicon substrate itself or within the silicon substrate itself.

[0172] The internal read address lines are routed to connect the pads of read address port 247 to read address decoders and distribution circuitry associated with each individual memory module 253 within the memory module group. These decoder circuits receive read address signals, decode the values, and selectively activate the specific memory module 253 corresponding to the address value.

[0173] Furthermore, the read address port 247 may include signal conditioning and amplification circuitry to ensure that the read address signal can be transmitted with sufficient voltage level, timing margin, etc., so as to reliably activate the appropriate memory module 253 once received. In some embodiments, the read address port 247 circuitry may include a level shifter or converter element to convert the voltage signaling level from a voltage signaling level compatible with interface logic 249 to a voltage signaling level compatible with memory module 253.

[0174] In some embodiments, read address port 247 may include additional error detection and correction circuitry, such as parity bits or ECC bits, to ensure that the read address can be reliably transmitted and received. Port 247 thus provides an integrated interface for robustly and reliably transmitting the read address signal from FPGA 245 to the precise memory location specified by that address within memory module 253.

[0175] Read address port 247 thus provides an electrical interface between FPGA semiconductor device 245 and memory module semiconductor device 243 to facilitate the transmission of read address signals from FPGA 245 during memory read operations. These read address signals are used to select a target memory location within memory module 253. Port 247 includes all necessary conductive contact structures, internal routing, and signal conditioning circuitry to perform this function efficiently and reliably.

[0176] Read data port 248 provides an interface for reading data from memory module 253. Read data port 248 includes multiple read data interconnects that terminate at an aggregation of read data bonds on the surface of memory module semiconductor device 243. The read data interconnects are laid out in a direction perpendicular to the surface of memory module semiconductor device 243 to minimize path length and ensure consistent timing.

[0177] The read data interconnects can be formed using multiple metal layers during the back-end fabrication of the memory module semiconductor device 243. Low-k dielectric materials are used between the metal layers to reduce parasitic capacitance. Wider metal lines with lower resistivity (such as aluminum or copper) are used for the read data interconnects to minimize RC delay.

[0178] The read data interconnect incorporates a serializer / deserializer circuit arrangement to transfer read data from memory module 253 to the read data bonding member in a serialized format. This allows multiple parallel read data bits to be transmitted using fewer interconnects. The serializer / deserializer circuit arrangement includes latching circuitry that sequentially captures read data bits in response to non-overlapping clock phases. Clock-phase-controlled transmission gates sequentially route the latched read data bits along the read data interconnect to the read data bonding member.

[0179] The read data bond can be arranged in a layout that matches the arrangement of pins or contacts on the FPGA semiconductor device 245 used for bonding. The read data bond may include metallized pads of different sizes, shapes, and pitches optimized for the bonding technology used, such as solder bumps or microbumps. Matching anti-pads are positioned beneath the read data bond to prevent short circuits.

[0180] The interface circuitry within memory module 253 can buffer read data and synchronize the read data with the relevant clock signal before it is transmitted over the data interconnect. The interface circuitry also applies error-correcting codes to the read data to enable the detection and correction of transmission errors.

[0181] The read data port 248 can provide an interface for off-chip transfer of read data from the memory module 253. In some specific embodiments, its physical design and circuitry can be used to optimize timing convergence, signal integrity, and error recovery for the desired memory application.

[0182] Figure 3B An embodiment according to this disclosure is shown. Figure 3A A perspective view of component 240, illustrating the bonding elements on the surface of the semiconductor device. That is, Figure 3B Used for the ports and bonding components illustrated below. Although Figure 3B The document describes a single write interface logic, read interface logic, and memory module; however, those skilled in the art will understand that the pattern can be repeated for all memory modules shown herein. Write interface logic 252 is coupled to a shared write port 257, which is coupled to a set of bonding elements 258. The set of bonding elements 258 may include supplemental connections of FPGA semiconductor device 245 relative to semiconductor device 243. Semiconductor device 243 includes a shared write port 251 coupled to a shared write peripheral 241.

[0183] The read interface logic 259 may include, for example: Figure 3AThe data read interface logic 250 and the address read interface logic 249 are shown. The data read interface logic 259 is coupled to the address read port 247 of the FPGA semiconductor device 254. The address read port 247 is coupled to a set of bonding elements 260, and the set of bonding elements 260 is also coupled to the address read port 262 of the semiconductor device 243. The set of bonding elements 260 may include supplementary connections of the FPGA semiconductor device 245 relative to the semiconductor device 243. The address read is sent to... Figure 3B The memory module 263 is shown. Data is returned via the read data port 261 of the semiconductor device 243, which is coupled to the bonding member 260, and the bonding member 260 is further coupled to the read data port 248 of the FPGA semiconductor device.

[0184] Figure 4 A perspective view of component 264 according to an embodiment of the present disclosure is shown. Component 264 has Figure 1 The integrated circuit, implemented on a semiconductor device, is electrically connected to another device having a field-programmable gate array core interconnected via a network to form the component. Although Figure 4 The bonding components are not shown, but those skilled in the art will understand how they can be referenced. Figure 3B The accompanying description is used to arrange the bonding components.

[0185] Component 264 allows communication between a semiconductor device 256 containing an FPGA core (e.g., 254) and a memory module semiconductor device 243. Specifically, component 264 includes a memory module semiconductor device 243. This device 243 includes non-volatile memory storage devices in the form of memory modules (such as memory module 253). These memory modules are arranged in a grid pattern across device 243 and can be implemented using memory technologies such as SRAM, FeRAM, ReRAM, or flash memory.

[0186] The memory capacity and performance characteristics of semiconductor device 243 can be optimized for massive storage of data that needs to be accessed by the FPGA core on device 256. This could include neural network weights, lookup tables, or other application data.

[0187] Component 264 uses a shared write peripheral 241 on semiconductor device 243. This peripheral 241 is connected to a shared write port and allows the FPGA core (e.g., 254) to simultaneously write data to one or all of the memory modules 253. The shared write peripheral 241 includes the necessary write circuitry, such as write drivers, registers, and control logic.

[0188] To read data, each memory module 253 has its own dedicated read peripheral 242 located on device 243. This allows different FPGA cores 254 to concurrently read and access different memory modules 253. Each read peripheral 242 has independent ports for read address 247 and read data 248.

[0189] Component 264 also includes a semiconductor device 256 housing FPGA cores (e.g., 254). These FPGA cores 254 communicate with the read and write ports of device 243 to access data in memory module 253. The FPGA cores 254 are connected to the memory ports via interconnects and bonding devices between the two devices 243 and 256. Furthermore, the FPGA cores 254 can communicate with each other using an on-chip network 255. This on-chip network (NoC) 255 allows the cores 254 to coordinate memory accesses and exchange data as needed.

[0190] Semiconductor device 256 includes an FPGA core 254 that can access and utilize the memory module 253 on the memory module semiconductor device 243.

[0191] Semiconductor device 256 can be implemented as an integrated circuit chip, comprising multiple FPGA cores 254 fabricated on its silicon substrate. FPGA cores 254 are programmable logic blocks that can be configured to implement custom logic functions and circuitry. Each FPGA core 254 includes an array of programmable logic elements, such as lookup tables, registers, digital signal processing blocks, I / O elements, and interconnects. The function of each FPGA core 254 is determined by configuration data loaded into the programmable elements.

[0192] The FPGA core 254 can be implemented using SRAM, flash memory, or antifuse technology. SRAM-based FPGA cores offer dynamic reconfigurability, allowing logic functions to be repeatedly reprogrammed during runtime. Flash- or antifuse-based FPGA cores are one-time programmable, with the logic configuration set during manufacturing or system startup.

[0193] The FPGA cores 254 on the semiconductor device 256 are arranged in a distributed pattern, evenly spaced across chip regions. One purpose of this distribution is to enable parallel data processing of multiple FPGA cores 254 by taking advantage of the spatial architecture.

[0194] FPGA core 254 can utilize features tailored for data-centric workloads. This can include digital signal processing blocks for math-intensive algorithms, high-speed I / O elements, and abundant interconnects for massive data production. FPGA core 254 is optimized to provide the parallel processing power required for compute-intensive applications. Communication between FPGA cores 254 is enabled using on-chip network 255. This on-chip network (NoC) 255 allows FPGA cores 254 to coordinate memory access, exchange data, and synchronize operation.

[0195] To interface with the memory module semiconductor device 243, each FPGA core 254 is connected to dedicated interface logic circuitry. This interface logic handles signal conversion between the FPGA core 254 and the memory read / write ports. This provides each FPGA core 254 with independent access to the memory module 253, enabling parallel memory operations.

[0196] FPGA core 254 is one of a plurality of FPGA cores implemented on semiconductor device 256. Semiconductor device 256 includes an array of FPGA cores distributed in a spaced pattern across its surface, the array of FPGA cores including FPGA core 254.

[0197] An FPGA core (e.g., 254) is a programmable logic block that can be configured to implement desired logic functions and circuits. Each FPGA core 254 includes an interconnected array of basic programmable elements, such as lookup tables, registers, digital signal processing blocks, input / output elements, and programmable interconnects.

[0198] The specific logic implemented by each FPGA core 254 is determined by configuration data loaded into the programmable element. The configuration data defines the logic functions executed by the LUT, the connections between logic blocks and I / O established by the programmable interconnect, the operating modes of the DSP blocks, and other aspects of the FPGA core's functionality.

[0199] Several possible technologies exist that can be used to implement an FPGA core (e.g., 254). Some options include SRAM-based FPGAs, antifuse-based FPGAs, and flash memory-based FPGAs. SRAM-based FPGA cores offer dynamic reconfigurability, allowing the logic configuration to be repeatedly reprogrammed at runtime. Antifuse and flash memory-based FPGA cores are one-time programmable, where their logic configuration is set during manufacturing or system startup.

[0200] As previously mentioned, FPGA Core 254 can contain high-performance components tailored for data-centric workloads. This includes abundant DSP blocks for math-intensive algorithms, high-speed I / O elements, and dense programmable interconnects for massive data production. The hardware architecture of FPGA Core 254 is optimized to enable the high throughput and parallel processing capabilities required for compute-intensive applications.

[0201] To facilitate communication between FPGA cores (e.g., 254), semiconductor device 256 implements an on-chip network 255. This on-chip network (NoC) 255 allows the FPGA cores 254 to coordinate memory access, exchange data, and synchronize operations. NoC 255 provides high-bandwidth and low-latency connectivity between the distributed FPGA cores 254.

[0202] The FPGA core 254 interfaces with the memory module 253 via dedicated connection components. These connection components include interface logic circuitry that handles signal conversion between the FPGA core 254 and the memory read / write ports. This interface logic enables the FPGA core 254 to independently access the memory module 253 for parallel data transfer.

[0203] As previously described, the on-chip network (NoC) 255 enables communication between the FPGA cores 254 implemented on the semiconductor device 256. The NoC 255 acts as an interconnect architecture, facilitating data transfer between the distributed FPGA cores 254 across the semiconductor device 256.

[0204] The NoC 255 can utilize a mesh topology, interconnecting FPGA cores 254 in a mesh pattern using network switches and links. This provides multiple redundant paths between any two FPGA cores 254, enhancing overall network resilience and performance.

[0205] In some embodiments, the NoC 255 can use wormhole or cut-through switching to reduce latency. As packets traverse the NoC 255, they are progressively forwarded to their destination via a pipelined approach through network switches, without waiting for complete packets to arrive before transmission begins. This allows for significantly lower latency compared to store-and-forward techniques.

[0206] The links interconnecting the network switch with the FPGA core 254 in the NoC 255 include dedicated communication wires and circuitry optimized for data transmission. These links provide high-bandwidth connectivity between the FPGA cores 254 and can support various signaling standards, such as differential signaling or low-voltage signaling, to achieve high data rates.

[0207] Optionally, the NoC 255 can utilize multiple virtual channels on each physical link to avoid protocol deadlock scenarios and achieve Quality of Service (QoS) traffic differentiation. Traffic from different applications or with different latency requirements can be assigned to separate virtual channels.

[0208] For power efficiency, the NoC 255 can utilize clock gating or power gating techniques. Inactive network switches and links can be powered down when not in use. The NoC 255 can also adaptively scale link width and voltage based on current traffic load.

[0209] To coordinate access to NoC 255 and avoid conflicts, various arbitration schemes can be employed. One possible approach is round-robin arbitration, where each FPGA core 254 transmits in a cyclical order. Alternatively, priority-based schemes can provide differentiated quality of service.

[0210] Error detection and recovery features can also be incorporated into NoC 255. Each packet may include a cyclic redundancy check (CRC) to detect transmission errors. Corrupted packets will be discarded and a retry will be requested to handle the error.

[0211] In summary, the NoC 255 provides a flexible on-chip communication infrastructure to match the distributed parallel nature of computation across multiple FPGA cores 254. The NoC 255's redundant connectivity, advanced switching modes, and QoS features enable efficient data exchange and coordination between FPGA cores. This allows the overall component 264 to meet the high throughput and low latency requirements of data-intensive applications mapped across FPGA cores.

[0212] Figure 5 An illustration of an embodiment according to the present disclosure is shown. Figure 1 A block diagram 300 of the memory address space of the integrated circuit is shown. The memory address space includes a write address space 316 and read data address spaces 310, 312, and 314.

[0213] The write address space 316 includes various units that can store data (e.g., weights) and / or instructions. These units are referred to as memory addresses. Module group 302 includes multiple memory modules 304, 306, and 308. The write address space 316 can be distributed among memory modules 304, 306, and 308, such that the write address space 316 spans from 0 to N. M-1. For example... Figure 5 As shown, module group 302 has N memory modules 304, 306, and 308, where N is a positive integer, and each module has a memory size of M. The total number of specific write memory addresses in the write address space will be N. M, the write memory address can range from 0 to N. Integer references of M-1.

[0214] Starting from address 0, the memory addresses written into address space 316 are arranged sequentially up to N. M-1. In other words, the first address is 0, and the last address is N. M-1, covering a total of N There are M addresses. The sorting can be linear (increasing by 1 for each address) or dependent on some other specified pattern.

[0215] Write-to-memory addressing can be implemented in various ways based on the system architecture. One approach used in a particular embodiment is to use a base register and a limit register. In one specific embodiment, the base register holds the minimum legal physical write-to-memory address, and the limit register specifies the size of the range. Therefore, to generate a logical address, you need to add the base address to the relative address. In other embodiments, a memory addressing scheme can be used where the base address is set to 0. Other write-to-memory addressing techniques will be understood by those skilled in the art.

[0216] For any device writing to module group 302, each memory module can have a specific set of write memory addresses, such that all memory addresses within module group 302 are specific to the write data. For example, the first module starts at address 0, and the last module starts at address N. The allocation ends at M-1. In some embodiments, the allocation may depend on the memory management system of the device writing data to modules 304, 306, 308, and the allocation ranges from simple fixed partitioning schemes to more complex dynamic partitioning models.

[0217] For example, in a simple linear model where each module (304, 306, or 308) has M addresses of equal size, the first module 304 would have write addresses 0 to M-1, the second module would have write addresses M to 2M-1, and the third module would have write addresses 2M to 3M-1. M-1, and so on. Module N, 308, will therefore have a sequence from (N-1) M to N The write address of M-1.

[0218] It is expected that ordinary technical personnel in related fields can use it from 0 to N Other implementations of the write memory address of M-1 depend on various factors, such as hardware architecture, operating system, memory management scheme, and the nature of the programs running on the system.

[0219] Module group 302 has different read data address spaces 310, 312, and 314. These read address spaces 310, 312, and 314 can have overlapping address spaces, can have contiguous address spaces, or can have a common extension address space. Read address spaces 310, 312, and 314 can be independent of each other. The system includes three independent read address spaces, labeled as read address spaces 310, 312, and 314. Each of these read address spaces is different from the others, meaning that reads can be performed in each space without affecting the others.

[0220] The read address spaces 310, 312, and 314 can be defined as contiguous blocks of memory addresses, each with its own start and end addresses. Within module group 302, each read address space 310, 312, and 314 can have an address range corresponding to values ​​from 0 to M-1, where M is the maximum value determined by the size of the modules 304, 306, and 308 used.

[0221] In one embodiment, a processing unit is allowed to interface with each of the read address spaces 310, 312, 314, and concurrent reads can be implemented as described herein. The independence of the read address spaces 310, 312, 314 ensures that each processing unit can access the data it needs without causing any interference or conflict with other processing units.

[0222] Figure 6 The illustration shows an embodiment according to the present disclosure. Figure 1 A block diagram of the memory address space with signal interfaces in an integrated circuit. Figure 6 The signals used can be used in conjunction with any of the embodiments described herein. However, those skilled in the art will understand that different signaling schemes can be used.

[0223] Module group 402 includes modules 404, 406, and 408 that share a common write peripheral 411. The write peripheral 411 includes a write address bus with the address of the data to be written, a write data bus with the data, and a write clock that causes a write to occur (e.g., on the rising or falling edge of a clock signal). A write occurs only when a write enable signal indicates that a write should occur. Any logic can be used; for example, a high voltage can correspond to 1 and a low voltage can correspond to 0, or vice versa. In some embodiments, the write peripheral 411 may be on chiplet 230, and in other embodiments, the write peripheral 411 may be on a second device 226.

[0224] Module group 402 includes modules 404, 406, and 408, each module having a corresponding read peripheral 410, 412, and 414. Each of the read peripherals 410, 412, and 414 has a read address bus for sending read addresses, a read data bus for receiving data, a read clock for timing the output of digital data, and an output enable as a prerequisite for outputting data. Any logic can be used; for example, a high voltage can correspond to 1 and a low voltage can correspond to 0, and vice versa. In other embodiments, multi-bit or analog data storage can be used. In some embodiments, one or more of the read peripherals 410, 412, and 414 can be on chip 230, and in other embodiments, one or more of the read peripherals 410, 412, and 414 are on a second device 226.

[0225] Figure 7 The illustration shows a stack 500 including two semiconductor devices 562 and 502 that can be bonded together. The first semiconductor device 562 may be an application chiplet, while the second semiconductor device 502 may be a memory chiplet. The application chiplet 562 includes circuitry for facilitating pre-bonding interconnect testing using interconnect loopbacks 522, 532, and 542. The first semiconductor device 562 has several test signal connectors 580, 582, and 550, which can be used to test paths by examining how signals are returned via a corresponding return signal connector 558, 554, and 584. These connectors can be coupled to external circuitry outside the boundary scan unit and / or interface logic 548. A tri-state buffer 544 may have an enable connector 586 that controls whether the tri-state buffer 544 is active or inactive.

[0226] Stacking 500 can facilitate the design and integration of a second semiconductor device 502 (e.g., a system-on-a-chip (SoC) or application chiplet) with a first semiconductor device 562 (e.g., a co-chiplet), and more specifically, facilitate independent testing using known good die application design methods.

[0227] In some embodiments, the first semiconductor device 562 and the second semiconductor device 502 are bonded together at the final stage. Therefore, to achieve independently validated chiplets, the disclosed method provides a thin interface module (e.g., interface logic 548) on the first semiconductor device 562 (e.g., an application SoC base die), where inputs and outputs can be registered on clock edges. By doing so, application designers can focus on ensuring the independent validity of each semiconductor device.

[0228] With the thin interface logic 548 in its proper place, the application designer's primary responsibility is to interface with the thin interface logic 548 according to the specifications. By following this approach, the design complexity associated with co-chip integration can be effectively managed, leading to improved efficiency and reliability.

[0229] Independent testing of semiconductor devices 562 and 502 can be used to minimize yield losses during post-integration stages. For example, in a 3D memory factory, each memory chiplet can be manufactured and tested individually to identify known good dies, which are then warehoused. The testing process utilizes Built-in Self-Test (BIST) technology based on serial scans to ensure comprehensive testing and verification of the memory chiplets. During the placement and routing stages, interface logic 548 is placed by placement tools, while custom scripts facilitate vertical routing of loopback pieces 522, 532, 542 and bonding pieces 518, 524, 536, etc. The remainder of the design can then be fully routed to establish complete connectivity. Subsequently, the application wafer for the first semiconductor device 562 can be manufactured with top metal bonding pieces 518, 524, 536.

[0230] The first semiconductor device 562 (e.g., as a fully manufactured application chip) can undergo testing using transparent interface logic, allowing for a comprehensive evaluation of the application device's functionality and performance. Optionally, wafer-level testing can also be performed to further ensure the quality and reliability of the first semiconductor device 562 (e.g., as an application chiplet). Throughout this testing phase, the goal is to identify any defects or problems that may affect device functionality or integration.

[0231] During the hybrid packaging integration phase, a known good second semiconductor device 502 (e.g., a memory chiplet) obtained from previous testing can be bonded face-to-face to a known good first semiconductor device 562 (e.g., an application chiplet). This bonding process enables a secure and reliable connection between semiconductor devices 502 and 562 (e.g., a memory chiplet and an application chiplet). Furthermore, by optionally performing semiconductor device bonding at the wafer level, post-packaging yield can be enhanced, thereby reducing potential yield losses and improving overall production efficiency.

[0232] The first semiconductor device 562 includes interface logic 548, which facilitates communication with external circuitry and external semiconductor devices. The interface logic 548 also includes interconnect loopbacks 522, 532, and 542 to test connectivity between the interface logic 548 and conductive pads (or bonding elements) 518, 526, and 536 located on the surface of the first semiconductor device 562. These connections can be tested before bonding to another device (or, in some embodiments, after bonding). The conductive pad 518 of the first semiconductor device 562 can be electrically coupled to the conductive pad 516 of the second semiconductor device 502. Furthermore, the conductive pad 526 of the first semiconductor device 562 can be electrically coupled to the conductive pad 528 of the second semiconductor device 502. Additionally, the conductive pad 526 of the first semiconductor device 562 can be electrically coupled to the conductive pad 538 of the second semiconductor device 502.

[0233] Interface logic 548 includes several input or output interfaces to other circuitry (not shown) within the first semiconductor device 562, including a read address input 564, a read clock input 560, and a read data output 546 (each of which may have a boundary scan unit to facilitate boundary scan testing). The read clock input 560 is connected to a read clock interconnect 520, which extends to the surface of the first semiconductor device 562 and terminates at a conductive pad 518. Furthermore, the conductive pad 518 is connected to an interconnect loopback 522, which is coupled to a buffer 556. The buffer 556 is also connected to a read clock output 558, which should have the same value as the read clock input 560 of interface logic 548 if the circuit integrity is intact. Therefore, buffer 556 can couple and / or amplify the signal from interconnect loopback 522 so that when an external circuitry applies a clock signal to read clock input 560, the value output to read clock output 558 can be checked to test the integrity of the path from interface logic 548 to conductive pad 518 and finally back to read clock output 558.

[0234] Similarly, interface logic 548 includes a read address interconnect 524 connected to a read address input 564. The read address interconnect 524 extends to the surface of the first semiconductor device 562 and is connected to a conductive pad 526. An interconnect loopback 532 is coupled to the conductive pad 526 and linked to a buffer 522, thereby allowing external test circuitry to test the read address output 554. Although only one interconnect is shown, those skilled in the art will know how to extend it to parallel data lines (e.g., eight interconnects with eight conductive pads, eight interconnect loopbacks, eight buffers, etc.) to form an 8-bit address space. Any other number of bits or address size can be used.

[0235] Furthermore, for the read address interconnect 524, consider the test signal as the read address, and the return signal as the return read address obtained from the interconnect loopback 522. The return read address 532 can be applied to the read data output bus 546 of the interface logic 548, amplified or coupled by the buffer 552, and used for testing, etc.

[0236] The interconnect loopback components 522, 532, and 542 in interface logic 548 may include additional components, such as comparators and delay circuits, to ensure signal integrity and test timing characteristics. Testing may include dynamically adjusting test signals based on predefined test patterns, thereby allowing for comprehensive testing and verification of the interconnects.

[0237] For clock interconnect 520, the test signal is the clock signal, and the return signal is the return clock signal received from interconnect loopback 532. Similarly, the return clock signal can be applied to the read data output bus of interface logic 548, buffered in a register, tested, etc.

[0238] For the read data interconnect 534, the test signal represents the test data applied via the read data input connector 550. The test data can be amplified by the tri-state buffer 544, and the return signal is the return test data received from the test data applied to the interconnect loopback connector 542 via the read data output connector 584. The test data can be received and / or output to the bus of the interface logic 548, buffered in a register, tested, etc.

[0239] When the first semiconductor device 562 and the second semiconductor device 502 are bonded together, their corresponding conductive pads (518, 516), (526, 528), and (536, 538) are electrically coupled together. This enables the transmission of electrical signals between the first semiconductor device 562 and the second semiconductor device 502.

[0240] The second semiconductor device 502 includes interface logic 568 composed of various interconnects (each interconnect may include a boundary scan unit for testing). The interface logic 568 includes a read clock interconnect 514 that receives a read clock signal from the first semiconductor device 562, a read address interconnect 530 that receives a read address from the first semiconductor device 562, and a read data interconnect 540 that transmits data from a memory cell to the first semiconductor device 562 via a read data output 504. That is, read data from the memory cell 504 is passed to the read data interconnect 540 through the interface logic 568. Similarly, the read address interconnect 530 is passed to a read address 508 through the interface logic 568, and the read address 508 is used to access the memory cell. The read clock interconnect 514 is a clock sent to the memory cell and / or internal logic, allowing the interface logic to buffer the read data presented to the read data interconnect 540.

[0241] Interface logic 568 can also perform a boundary scan using serial test data input 510, test clock 512, and serial test data output 566. These components enable interface logic 568 to test the connectivity of interconnects and verify signal integrity. Interface logic 548 also includes a boundary scan unit comprising serial test data input 570 and serial test data output 574. Optionally, a separate clock (e.g., test clock 574) can be used instead of read clock 560. However, in some embodiments, the boundary scan unit may use read clock 560. Therefore, connectivity from interface logic 548 of the first semiconductor device 562 to the second semiconductor device 502 can be tested to ensure that the integrity of the connectivity between them is adequate.

[0242] Boundary scan is a test technique used to verify the connectivity and integrity of interconnects within a semiconductor device. Therefore, boundary scan can be used to test the connectivity between interface logic 548 of the first semiconductor device 562 and interface logic 568 of the second semiconductor device 502 to ensure the suitability of the connectivity. Any, all, or some of the inputs and / or outputs of the interface logics 548 and 568 may include a boundary scan unit to control, modify, or test any, all, or some of the inputs and / or outputs.

[0243] Boundary scan testing can be performed by forming a boundary scan chain, connecting the boundary scan units within each interface logic 548, 568 in a daisy-chain configuration. This creates a serial shift register arrangement, enabling controlled shifting of test data and return data via the boundary scan chain.

[0244] Boundary scan units within interface logics 548 and 568 provide control and capture capabilities to manipulate and observe test and return data within the boundary scan chain via connected devices. This ensures reliable testing of connectivity between interface logic 548 of the first semiconductor device 562 and interface logic 568 of the second semiconductor device 502. Therefore, through boundary scan testing, the interconnects between the two interface logics 548 and 568 can be thoroughly inspected and verified to ensure proper connectivity and expected operation. The boundary scan unit within each interface logic 548 and 568 enables precise control over test and return data, allowing for comprehensive analysis and evaluation of connectivity between the two semiconductor devices.

[0245] During testing, various test patterns and data can be loaded into the boundary scan cells via serial test data input 570 of interface logic 548 of the first semiconductor device 562 and / or serial test data input 510 of interface logic 568 of the second semiconductor device 502. These test patterns simulate different input scenarios and conditions, allowing for the examination of various connectivity scenarios between the two interface logics. The loaded test data is then shifted through the boundary scan chain using test clocks 512 and 574. Note that the clocks can be bundled together, synchronized, and / or other clocks can be used. With each clock cycle, the test data propagates through the cascaded boundary scan cells, advancing sequentially to subsequent cells. This shifting process allows the test data to traverse the interconnects between the two interface logics 548 and 568, verifying the connectivity and integrity of the interconnects. This allows for subsequent analysis and comparison of the expected return data. By comparing the sampled return data with the expected value, the integrity of the connectivity between the two interface logics 548 and 568 can be accurately evaluated.

[0246] Furthermore, at specific points within the boundary scan chain, return data from the interface logic 548 of the first semiconductor device 562 and / or serial test data input 510 from the interface logic 568 of the second semiconductor device 502 are sampled into additional boundary scan units. These boundary scan units capture and retain the return data for further analysis and comparison.

[0247] Figure 8A diagram illustrates two semiconductor devices 622, 602 (such as two chiplets) according to one embodiment of the present disclosure, which automatically test the connectivity and integrated connectivity of write interconnects 620, 624, 634 within the semiconductor devices. A first semiconductor device 662 has a plurality of test signal connectors 680, 682, 684, which can be used to test paths by examining how signals are returned via a corresponding return signal connector among return signal connectors 668, 664, 660. In some embodiments, write interconnects 620, 624, 634 can be connected to… Figure 7 The read interconnects 520, 524, and 534 are integrated on the same interface logic.

[0248] like Figure 8 As shown, a stack 600 of two semiconductor devices 662 and 602 is represented: an application chiplet (first semiconductor device 662) and a memory chiplet (second semiconductor device 602). The application chiplet 662 includes interconnect loopbacks 622, 632, and 642 for interconnect testing prior to bonding. Interface logic 648 within the application chiplet facilitates communication with external circuitry and includes interconnect loopbacks 622, 632, and 642 to test connectivity with conductive pads 618, 626, and 636.

[0249] Interface logic 648 includes input / output interfaces for connecting to write address 624, write clock 620, and write data 634 of the first semiconductor device 662. These interfaces, along with interconnect loopbacks 622, 632, and 642, enable testing of connectivity between interface logic 648 and conductive pads (or bonding elements) 618, 626, and 636 prior to bonding. Furthermore, conductive pads 618, 626, and 636 of the first semiconductor device 662 can be electrically coupled to conductive pads 616, 628, and 638 of the second semiconductor device 602, allowing interface logic 648 to provide write functionality connectivity to memory located within the second semiconductor device 602.

[0250] Interface logic 648 includes interconnects such as write clock interconnect 620, which is connected to write clock input 660 and terminates at conductive pad 618. It also includes interconnect loopback 622 and buffer 656. Circuit integrity can be tested by applying a clock signal to write clock input 660 and comparing it to write clock output 658.

[0251] Similarly, interface logic 648 includes a write address interconnect 624, which is connected to the write address input 664 and terminates at conductive pad 626. An interconnect loopback 632 coupled to buffer 622 allows testing of the write address output 664.

[0252] Interconnect loopback components 622, 632, and 642 may include additional components, such as comparators and delay circuits, to ensure signal integrity and test timing characteristics. Test signals and return signals used for testing may include write address 624, write data 634, and write clock signal 620. By applying these signals through the interconnect loopback components and comparing them to expected values, the connectivity and integrity of the interconnects can be verified.

[0253] When the first semiconductor device 662 and the second semiconductor device 602 are bonded together, their corresponding conductive pads (618, 616), (626, 628), and (636, 638) are electrically coupled, enabling the transmission of electrical signals between them.

[0254] The second semiconductor device 602 has its own interface logic 668, which includes interconnects for a write clock 614, a write address 630, and write data 640. Write data applied to the write data interconnect 634 is passed through the interface logic 668 to write data 604, which is used to write to the memory cell addressed by the write address 608 on the write clock 606. The write clock interconnect 614 can receive a clock signal to control the writing to the memory cell and internal logic.

[0255] Interface logic 668 also incorporates components for boundary scan, such as serial test data input 610, test clock 612, and serial test data output 666. Boundary scan allows testing the connectivity of interconnects and verifying signal integrity between interface logics 648 and 668 of two semiconductor devices.

[0256] Boundary scan testing involves forming a boundary scan chain by connecting boundary scan units in a daisy-chain configuration within each interface logic 648, 668. This allows for the controlled shifting of test data and return data through the boundary scan chain. The boundary scan units provide control and capture capabilities to manipulate and observe the test data and return data within the boundary scan chain. This enables reliable testing of connectivity between interface logics 648 and 668. As known to those skilled in the art, some or all of the inputs and / or outputs of interface logics 648, 668 may include boundary scan units to facilitate the reading, writing, or recording of test data.

[0257] During testing, test patterns and data are loaded into the boundary scan unit via serial test data inputs 610 and 670 of interface logics 668 and 648. These test patterns simulate different input / output scenarios, allowing for the examination of various connectivity scenarios between the two interface logics 668 and 648. The loaded test data is then shifted through the boundary scan chain using test clocks 612 and 660. With each clock cycle, the test data propagates through the boundary scan unit, verifying the connectivity and integrity of the interconnects.

[0258] Return data from the interface logic is sampled into additional boundary scan units within the boundary scan chain for analysis and comparison. By comparing the sampled return data with expected values, the integrity of the connectivity between the two interface logics can be accurately assessed.

[0259] Figures 9A to 9B A block diagram of a system 700 according to an embodiment of the present disclosure is shown. System 700 employs construct-correct timing convergence for an application chip 702 and a memory chip 704 having interface circuitry 701, which includes read registers 726a, 726b and a write register 728. Therefore, system 700 may include two separate semiconductor devices, such as application chip 702 and memory chip 704, which may have been formed on two separate dies. Interface circuitry 701 (which may be referred to as an interface module) may include registers 726a, 726b, 728 to allow construct-correct timing convergence between application chip 702 and memory bank 706 on memory chip 704.

[0260] Memory chiplet 704 may include module group 706, having modules 708a, 708b, and 708c that are independently accessible via read peripherals 722a, 722b, and 722c, respectively. Memory chiplet 704 may also include a shared write peripheral 710, where data can be written to memory locations within module group 706. In a particular embodiment, for example when semiconductor devices 702 and 704 are bonded together in a stacked configuration, interconnects found within memory chiplet 704 may be coupled to surfaces via bonding members to facilitate communication between semiconductor devices 702 and 704. The designer of application chiplet 702 may use a netlist to place interface module 701 at a predetermined distance from the surface of application chiplet 702. That is, signal timing and characteristics can be predefined to cooperate with the memory of memory chiplet 704. For example, the travel time of a signal from read register 726 may be less than a predetermined time.

[0261] Interface module 701 may include one or more read registers 726a, 726b and write register 728, which can be accessed via, for example... Figures 9A to 9B The several bonding elements shown communicate with the memory chip 704.

[0262] The read register 726a can interface and communicate with other circuit devices within the application chip 702 via the read application programming interface (“API”) 714a. That is, the read API 714a can be a bus in which data can be requested by an external circuit device (e.g., via the CPU) to provide data from the memory chip 704 to other circuit devices (e.g., the exemplary CPU).

[0263] The read register 726a can be controlled by a read clock, which is received via read clock interconnect 712a. Read clock interconnect 712a can also be coupled to read clock bonding 738a, which can be connected to the read peripheral 722a on the memory chip 704 to provide clock control for the memory contained therein. The interconnect can be established via the read clock bonding 738a on the surface of the chip 702 and the corresponding bonding on the memory chip 704 (in... Figures 9A to 9B (Not explicitly shown in the text) are connected together.

[0264] The read register 726a can be coupled to a read address interconnect 716a (which may include multiple parallel interconnects), which transmits the read address that has been loaded into the read register 726a. The read address interconnect 716a is coupled to multiple read address bonding elements 740a, allowing the read address to be received by the memory chip 704. The read address is a value that the read peripheral 722a can translate to query a location within module 708a.

[0265] The read register 726a also includes a read data interconnect 718a, which can receive data from module 708 via multiple read data bonds 742a. ​​The data can be held in register 726a for communication with other circuitry via read API 714a.

[0266] The read register 726a may also include a read data enable interconnect 720a to enable the output of data from module 708a. The read data enable interconnect 720a is coupled to a read data enable bond 744a, so that chiplets 702 and 704 can communicate electrically with each other when stacked.

[0267] The read register 726b may be similar to or the same as the read register 726a on the application chip 702. The read register 726a can communicate with other circuit devices through the read application programming interface (API) 714b. The read API 714b acts as a bus in which external circuit devices (such as the CPU) can request data from the memory chip 704.

[0268] The read register 726b is controlled by a read clock, which is received via read clock interconnect 712b. Read clock interconnect 712b is also connected to read clock bond 738b, which provides clock control for memory chip 704. Read clock bond 738b connects the interconnects on application chip 702 and memory chip 704.

[0269] Read register 726b is connected to read address interconnect 716b, which transmits the loaded read address. Read address interconnect 716b is connected to multiple read address bonding elements 740b, allowing memory chip 704 to receive read addresses. The read address is used by read peripheral 722b to query the location within module 708b.

[0270] The read register 726b also has a read data interconnect 718b, which receives data from module 708. The data is stored in register 726b and can be transferred to other circuit devices via read API 714b.

[0271] Furthermore, the read register 726b includes a read data enable interconnect 720b, which enables the output of data from module 708b. The read data enable interconnect 720b is connected to the read data enable bond 744b to ensure electrical communication between the stacked chiplets 702 and 704.

[0272] Interface module 701 also includes a write interface register 728, which receives write data and a write address via a write application programming interface 724 to write write data to module group 706. Write interface register 728 receives a write clock via a write clock interconnect 730, which is also coupled to the surface of a semiconductor device via a write clock bond 746. Write interface register 728 is also coupled to a write address interconnect 732 to provide a write address from write interface register 728 to a plurality of write address bonds 748 on the surface. Write interface register 728 is also coupled to a write data interconnect 734 to transmit data via a plurality of write data bonds 750. Write interface register 728 is also coupled to a write data enable interconnect 736, which transmits a write enable signal via a write enable bond 752.

[0273] Various alternatives and modifications can be devised by those skilled in the art without departing from this disclosure. Therefore, this disclosure is intended to cover all such alternatives, modifications, and variations. Furthermore, while several embodiments of this disclosure have been shown in the figures and / or discussed herein, this is not intended to limit the disclosure thereto, as this disclosure is intended to cover as broadly as possible the scope permitted by the prior art, and the specification should be interpreted accordingly. Therefore, the foregoing description should not be construed as restrictive, but merely as illustrative of particular embodiments. Other modifications will be foreseen by those skilled in the art within the scope and spirit of the appended claims. Other elements, steps, methods, and techniques that are substantially different from those described in the foregoing description and / or the appended claims are also intended to be within the scope of this disclosure.

[0274] The embodiments shown in the figures are merely illustrative of certain examples of this disclosure. Furthermore, the figures described are illustrative only and not restrictive. In the figures, the dimensions of some elements may be exaggerated for illustrative purposes and are not drawn to scale. Additionally, depending on the context, elements shown in the figures with the same reference numerals may be the same element or may be similar elements.

[0275] When the term "comprising" is used in this specification and claims, it does not exclude other elements or steps. When referring to a singular noun (e.g., "a," "an," or "the"), the use of an indefinite or definite article includes the plural form of that noun unless otherwise specified. Therefore, the term "comprising" should not be construed as limited to the items listed thereafter; it does not exclude other elements or steps, and thus the scope of "device comprising items A and B" should not be limited to a device that includes only components A and B. This expression means that, with respect to this disclosure, the only relevant components of the device are A and B.

[0276] As used herein, the term “stack” can mean any such coupling, bonding, fixing, gluing, electrical coupling, physical coupling, signal coupling, optical coupling, or otherwise mating one or more devices together in any orientation such that they are fixed together on any heterogeneous or homogeneous surface between them.

[0277] Furthermore, the terms “first,” “second,” “third,” etc., used in the specification or claims are provided to distinguish similar elements and are not necessarily used to describe order or chronological sequence. It should be understood that such terms are interchangeable where appropriate (unless otherwise explicitly disclosed), and the embodiments of this disclosure described herein can operate in other sequences and / or arrangements different from those described or illustrated herein.

[0278] Each feature and example, and combination thereof, described herein can be considered to be covered by this disclosure. This disclosure therefore relates to the following non-limiting numbered aspects:

[0279] 1. An integrated circuit comprising: a first semiconductor device including a first programmable gate array; a plurality of interface logics including first interface logic; and a first memory port connected to a first set of bonding elements on a surface of the first semiconductor device, the first programmable gate array being operatively coupled to the first interface logic for communication via the first memory port.

[0280] 2. The integrated circuit according to aspect 1, wherein the first interface logic is formed by the first programmable gate array.

[0281] 3. The integrated circuit according to aspect 1, wherein the first interface logic is distributed in the first programmable gate array in an interval pattern.

[0282] 4. The integrated circuit according to aspect 1, wherein the first semiconductor device includes a plurality of memory ports, the plurality of memory ports including the first memory port, wherein the plurality of memory ports are formed in a spaced pattern on the first semiconductor device.

[0283] 5. The integrated circuit according to aspect 1 further includes a plurality of sets of bonding members, the plurality of sets of bonding members including the first set of bonding members, wherein the plurality of sets of bonding members are distributed in a spaced pattern on the surface of the first semiconductor device.

[0284] 6. The integrated circuit according to aspect 1, wherein the first semiconductor device further includes a plurality of memory ports, the plurality of memory ports including the first memory port, wherein each of the plurality of interface logics is coupled to a corresponding memory port among the plurality of memory ports.

[0285] 7. The integrated circuit according to aspect 6, the first semiconductor device further includes a plurality of programmable gate arrays, the plurality of programmable gate arrays including the first programmable gate array, wherein each of the plurality of programmable gate arrays is coupled to a corresponding interface logic in the plurality of interface logics.

[0286] 8. The integrated circuit according to aspect 6 further includes a plurality of cores, wherein each of the plurality of cores is coupled to a corresponding interface logic in the plurality of interface logics.

[0287] 9. The integrated circuit according to aspect 6 further includes a plurality of sets of bonding elements on the surface of the first semiconductor device, wherein each of the plurality of memory ports is coupled to a bonding element of a corresponding set of the plurality of sets of bonding elements, wherein the plurality of sets of bonding elements includes the first set of bonding elements.

[0288] 10. The integrated circuit according to aspect 1, wherein the first set of bonding elements is a metal pad.

[0289] 11. The integrated circuit according to aspect 1, wherein the first semiconductor device further comprises: a plurality of programmable gate arrays, the plurality of programmable gate arrays including the first programmable gate array; and an on-chip network configured to enable communication between at least two of the plurality of programmable gate arrays.

[0290] 12. The integrated circuit according to aspect 1, wherein the first semiconductor device further comprises: at least one on-chip network communication system, the at least one on-chip network communication system connecting at least two processing elements implemented on the first programmable gate array, the first programmable gate array being operatively coupled to the plurality of interface logics for communication via the memory port.

[0291] 13. The integrated circuit according to aspect 1, wherein the first memory port is a read port.

[0292] 14. The integrated circuit according to aspect 13, wherein the first memory port is a multi-cycle port.

[0293] 15. The integrated circuit according to aspect 1, wherein the first memory port is a write port.

[0294] 16. The integrated circuit according to aspect 15, wherein the first memory port is a multi-cycle port.

[0295] 17. The integrated circuit according to aspect 1, wherein the first memory port is a read / write port.

[0296] 18. The integrated circuit according to aspect 17, wherein the first memory port is a multi-cycle port.

[0297] 19. The integrated circuit according to aspect 1, wherein the first programmable gate array is a field-programmable gate array.

[0298] 20. The integrated circuit according to aspect 1, wherein the first programmable gate array is a reconfigurable gate array.

[0299] 21. The integrated circuit according to aspect 20, wherein the reconfigurable gate array is dynamically programmable.

[0300] 22. The integrated circuit according to aspect 20, wherein the reconfigurable gate array is programmable at one time.

[0301] 23. The integrated circuit according to aspect 1, wherein the first semiconductor device includes an on-chip network architecture.

[0302] 24. The integrated circuit according to aspect 23, wherein the programmable gate array includes an array of embedded programmable gate array cores configured to communicate with each other via the on-chip network architecture.

[0303] 25. The integrated circuit according to aspect 23, wherein the on-chip network architecture is formed by the first programmable gate array.

[0304] 26. The integrated circuit according to aspect 1, wherein the first programmable gate array includes an array of embedded programmable gate array cores, wherein each embedded programmable gate array core in the array of embedded programmable gate array cores is operatively coupled to a corresponding interface logic in the plurality of interface logics.

[0305] 27. The integrated circuit according to aspect 1, wherein the first programmable gate array includes at least two embedded programmable gate array cores, wherein each of the at least two embedded programmable gate array cores is operatively coupled to a corresponding interface logic in the plurality of interface logics.

[0306] 28. The integrated circuit according to aspect 1, wherein the first programmable gate array includes an array of embedded programmable gate array cores, wherein each embedded programmable gate array core in the array of embedded programmable gate array cores is operatively coupled to at least one of the plurality of interface logics.

[0307] 29. The integrated circuit according to aspect 1, wherein the first programmable gate array includes an array of embedded programmable gate array cores, wherein each embedded programmable gate array core in the array of embedded programmable gate array cores is operatively coupled to a single interface logic among the plurality of interface logics.

[0308] 30. The integrated circuit according to aspect 1 further includes: a second semiconductor device, the second semiconductor device including: a plurality of memory modules, the plurality of memory modules including a first memory module, the first memory module being coupled to a second set of bonding members on a surface of the second semiconductor device, wherein the first set of bonding members and the second set of bonding members are configured to dock with each other when the first semiconductor device and the second semiconductor device are bonded together.

[0309] 31. The integrated circuit according to aspect 30, wherein the first memory port is a write memory port.

[0310] 32. The integrated circuit according to aspect 31, wherein the first memory port is configured to write to all of the plurality of memory modules.

[0311] 33. The integrated circuit according to aspect 31 or 32, the first semiconductor device further includes: a plurality of read memory ports, wherein the plurality of interface logics includes a plurality of read interface logics, wherein each of the plurality of read interface logics is operatively coupled to a corresponding read memory port of the plurality of read memory ports.

[0312] 34. The integrated circuit according to aspect 33, wherein each of the plurality of read interface logics interfaces with a corresponding memory module among the plurality of memory modules.

[0313] 35. The integrated circuit according to aspect 30, wherein the plurality of memory modules comprises an array of SRAM.

[0314] 36. The integrated circuit according to aspect 30, wherein the plurality of memory modules comprises an array of non-volatile memory.

[0315] 37. The integrated circuit according to aspect 30, wherein the plurality of memory modules include EEPROM.

[0316] 38. The integrated circuit according to aspect 30, wherein the plurality of memory modules include ROM.

[0317] 39. The integrated circuit according to aspect 30, wherein the plurality of memory modules include read-optimized non-volatile memory.

[0318] 40. The integrated circuit according to aspect 1, wherein the programmable gate array is programmed using antifuse, SRAM or flash memory technology.

[0319] 41. The integrated circuit according to aspect 1, wherein the programmable gate array core is connected in a mesh topology via the on-chip network architecture.

[0320] 42. The integrated circuit according to aspect 1, wherein the interface logic includes a voltage level shifter to convert a signal of the programmable gate array to a voltage level of the first memory port or to convert a voltage level of the first memory port.

[0321] 43. A method of operating an integrated circuit, the method comprising: utilizing a first semiconductor device, the first semiconductor device including a first programmable gate array; employing a plurality of interface logics, the plurality of interface logics including first interface logic; connecting a first memory port to a first set of bonding elements on a surface of the first semiconductor device; and operatively coupling the first programmable gate array to the first interface logic to enable communication via the first memory port.

[0322] 44. The method according to aspect 43, wherein employing the first interface logic comprises: forming the first interface logic from the first programmable gate array.

[0323] 45. The method according to aspect 43, wherein employing the first interface logic comprises: distributing the first interface logic in a spaced pattern within the first programmable gate array.

[0324] 46. ​​The method according to aspect 43 further includes: including a plurality of memory ports, such as the first memory port, wherein a spacing pattern is formed on the first semiconductor device using the plurality of memory ports.

[0325] 47. The method according to aspect 43, further comprising: distributing a plurality of sets of bonding members in a spaced pattern on the surface of the first semiconductor device, the plurality of sets of bonding members including the first set of bonding members.

[0326] 48. The method according to aspect 43 further comprises: utilizing a plurality of memory ports, the plurality of memory ports including the first memory port, wherein each of the plurality of interface logics is coupled to a corresponding memory port among the plurality of memory ports.

[0327] 49. The method according to aspect 48 further comprises: employing a plurality of programmable gate arrays, the plurality of programmable gate arrays including the first programmable gate array, wherein each of the plurality of programmable gate arrays is coupled to a corresponding interface logic in the plurality of interface logics.

[0328] 50. The method according to aspect 48 further includes: coupling a plurality of cores, wherein each of the plurality of cores is coupled to a corresponding interface logic in the plurality of interface logics.

[0329] 51. The method according to aspect 48, further comprising: coupling a plurality of sets of bonding elements on the surface of the first semiconductor device, wherein each of the plurality of memory ports is coupled to a bonding element of a corresponding set of the plurality of sets of bonding elements, the plurality of sets of bonding elements including the first set of bonding elements.

[0330] 52. The method according to aspect 43, wherein the first set utilizing the bonding elements involves employing metal pads.

[0331] 53. The method according to aspect 43 further includes: employing a plurality of programmable gate arrays, the plurality of programmable gate arrays including the first programmable gate array, and configuring the on-chip network to enable communication between at least two of the plurality of programmable gate arrays.

[0332] 54. The method according to aspect 43 further includes: implementing at least one on-chip network communication system to connect at least two processing elements on the first programmable gate array, and operatively coupling the first programmable gate array to the plurality of interface logics for communication via the memory port.

[0333] 55. The method according to aspect 43, wherein utilizing the first memory port includes: using the first memory port as a read port.

[0334] 56. The method according to aspect 55, wherein using the first memory port as a read port further comprises: using the first memory port as a multi-cycle port.

[0335] 57. The method according to aspect 43, wherein utilizing the first memory port includes: using the first memory port as a write port.

[0336] 58. The method according to aspect 57, wherein using the first memory port as a write port further comprises: using the first memory port as a multi-cycle port.

[0337] 59. The method according to aspect 43, wherein utilizing the first memory port includes: using the first memory port as a read / write port.

[0338] 60. The method according to aspect 59, wherein using the first memory port as a read / write port further comprises: using the first memory port as a multi-cycle port.

[0339] 61. The method according to aspect 43, wherein utilizing the first programmable gate array includes: employing a field-programmable gate array.

[0340] 62. The method according to aspect 43, wherein utilizing the first programmable gate array includes employing a reconfigurable gate array.

[0341] 63. The method according to aspect 62, wherein employing a reconfigurable gate array further comprises: dynamically programming the reconfigurable gate array.

[0342] 64. The method according to aspect 62, wherein employing a reconfigurable gate array further includes: performing a one-time programming of the reconfigurable gate array.

[0343] 65. The method according to aspect 43 further includes: including an on-chip network architecture in the first semiconductor device.

[0344] 66. The method according to aspect 65, wherein utilizing the on-chip network architecture includes: an array employing embedded programmable gate array cores configured to communicate with each other via the on-chip network architecture.

[0345] 67. The method according to aspect 65, wherein the formation of the on-chip network architecture is accomplished by the first programmable gate array.

[0346] 68. The method according to aspect 43, wherein utilizing the first programmable gate array comprises: an array employing embedded programmable gate array cores, each embedded programmable gate array core being operatively coupled to a corresponding interface logic in the plurality of interface logics.

[0347] 69. The method according to aspect 43, wherein utilizing the first programmable gate array includes: employing at least two embedded programmable gate array cores, each embedded programmable gate array core being operatively coupled to a corresponding interface logic in the plurality of interface logics.

[0348] 70. The method according to aspect 43, wherein utilizing the first programmable gate array comprises: an array employing embedded programmable gate array cores, each embedded programmable gate array core being operatively coupled to at least one of the plurality of interface logics.

[0349] 71. The method according to aspect 43, wherein utilizing the first programmable gate array comprises: an array employing embedded programmable gate array cores, each embedded programmable gate array core being operatively coupled to a single interface logic among the plurality of interface logics.

[0350] 72. The method according to aspect 43 further comprises: utilizing a second semiconductor device, the second semiconductor device including a plurality of memory modules, the plurality of memory modules including a first memory module; and a second set of bonding members coupling the first memory module to a surface of the second semiconductor device, wherein the first set of bonding members and the second set of bonding members are configured to dock with each other when the first semiconductor device and the second semiconductor device are bonded together.

[0351] 73. The method according to aspect 72, wherein utilizing the first memory port includes: using the first memory port as a write memory port.

[0352] 74. The method according to aspect 73, wherein using the first memory port as a write memory port comprises: configuring the first memory port to write to all of the plurality of memory modules.

[0353] 75. The method according to aspect 73 or 74, further comprising: including a plurality of read memory ports within the first semiconductor device; and operatively coupling each of the plurality of read interface logics to a corresponding read memory port of the plurality of read memory ports.

[0354] 76. The method according to aspect 75, wherein each of the plurality of read interface logics interfaces with a corresponding memory module among the plurality of memory modules.

[0355] 77. The method according to aspect 72, wherein employing the plurality of memory modules includes: utilizing an array of SRAM.

[0356] 78. The method according to aspect 72, wherein employing the plurality of memory modules includes: utilizing an array of non-volatile memory.

[0357] 79. The method according to aspect 72, wherein employing the plurality of memory modules includes: using EEPROM.

[0358] 80. The method according to aspect 72, wherein employing the plurality of memory modules includes: using ROM.

[0359] 81. The method according to aspect 72, wherein employing the plurality of memory modules includes: using read-optimized non-volatile memory.

[0360] 82. The method according to aspect 43, wherein utilizing the programmable gate array includes: programming using antifuse, SRAM or flash memory technology.

[0361] 83. The method according to aspect 43 further includes: connecting the programmable gate array core and employing a mesh topology through the on-chip network architecture.

[0362] 84. The method according to aspect 43, wherein employing the interface logic includes: using a voltage level shifter to convert a signal of the programmable gate array to a voltage level of the first memory port or to convert a voltage level from the first memory port.

Claims

1. An integrated circuit, comprising: A first semiconductor device, the first semiconductor device comprising: First programmable gate array; and Multiple interface logics, including a first interface logic; and A first memory port is connected to a first set of bonding elements on the surface of the first semiconductor device, and the first programmable gate array is operatively coupled to the first interface logic for communication via the first memory port.

2. The integrated circuit according to claim 1, wherein the first interface logic is formed by the first programmable gate array.

3. The integrated circuit of claim 1, wherein the first interface logic is distributed in the first programmable gate array in an interval pattern.

4. The integrated circuit of claim 1, wherein the first semiconductor device includes a plurality of memory ports, the plurality of memory ports including the first memory port, wherein the plurality of memory ports are formed in a spacing pattern on the first semiconductor device.

5. The integrated circuit of claim 1, further comprising a plurality of sets of bonding members, the plurality of sets of bonding members including the first set of bonding members, wherein the plurality of sets of bonding members are distributed in an interval pattern on the surface of the first semiconductor device.

6. The integrated circuit of claim 1, wherein the first semiconductor device further comprises a plurality of memory ports, the plurality of memory ports including the first memory port, wherein each of the plurality of interface logics is coupled to a corresponding memory port among the plurality of memory ports.

7. The integrated circuit of claim 6, wherein the first semiconductor device further comprises a plurality of programmable gate arrays, the plurality of programmable gate arrays including the first programmable gate array, wherein each of the plurality of programmable gate arrays is coupled to a corresponding interface logic in the plurality of interface logics.

8. The integrated circuit of claim 6 further includes a plurality of cores, wherein each of the plurality of cores is coupled to a corresponding interface logic in the plurality of interface logics.

9. The integrated circuit of claim 6, further comprising a plurality of sets of bonding members on the surface of the first semiconductor device, wherein each of the plurality of memory ports is coupled to a bonding member of a corresponding set of the plurality of sets of bonding members, wherein the plurality of sets of bonding members includes the first set of bonding members.

10. The integrated circuit of claim 1, wherein the first set of bonding elements is a metal pad.

11. The integrated circuit of claim 1, wherein the first semiconductor device further comprises: A plurality of programmable gate arrays, wherein the plurality of programmable gate arrays includes the first programmable gate array; as well as An on-chip network configured to enable communication between at least two of the plurality of programmable gate arrays.

12. The integrated circuit of claim 1, wherein the first semiconductor device further comprises: At least one on-chip network communication system, wherein the at least one on-chip network communication system connects at least two processing elements implemented on the first programmable gate array, the first programmable gate array being operatively coupled to the plurality of interface logics for communication via the memory port.

13. The integrated circuit according to claim 1, wherein the first memory port is a read port.

14. The integrated circuit of claim 13, wherein the first memory port is a multi-cycle port.

15. The integrated circuit of claim 1, wherein the first memory port is a write port.

16. The integrated circuit of claim 15, wherein the first memory port is a multi-cycle port.

17. The integrated circuit of claim 1, wherein the first memory port is a read / write port.

18. The integrated circuit of claim 17, wherein the first memory port is a multi-cycle port.

19. The integrated circuit of claim 1, wherein the first programmable gate array is a field-programmable gate array.

20. The integrated circuit of claim 1, wherein the first programmable gate array is a reconfigurable gate array.

21. The integrated circuit of claim 20, wherein the reconfigurable gate array is dynamically programmable.

22. The integrated circuit of claim 20, wherein the reconfigurable gate array is programmable only once.

23. The integrated circuit of claim 1, wherein the first semiconductor device comprises an on-chip network architecture.

24. The integrated circuit of claim 23, wherein the programmable gate array comprises an array of embedded programmable gate array cores configured to communicate with each other via the on-chip network architecture.

25. The integrated circuit of claim 23, wherein the on-chip network architecture is formed by the first programmable gate array.

26. The integrated circuit of claim 1, wherein the first programmable gate array comprises an array of embedded programmable gate array cores, wherein each embedded programmable gate array core in the array of embedded programmable gate array cores is operatively coupled to a corresponding interface logic in the plurality of interface logics.

27. The integrated circuit of claim 1, wherein the first programmable gate array comprises at least two embedded programmable gate array cores, wherein each of the at least two embedded programmable gate array cores is operatively coupled to a corresponding interface logic in the plurality of interface logics.

28. The integrated circuit of claim 1, wherein the first programmable gate array comprises an array of embedded programmable gate array cores, wherein each embedded programmable gate array core in the array of embedded programmable gate array cores is operatively coupled to at least one of the plurality of interface logics.

29. The integrated circuit of claim 1, wherein the first programmable gate array comprises an array of embedded programmable gate array cores, wherein each embedded programmable gate array core in the array of embedded programmable gate array cores is operatively coupled to a single interface logic among the plurality of interface logics.

30. The integrated circuit according to claim 1, further comprising: A second semiconductor device, the second semiconductor device comprising: A plurality of memory modules, the plurality of memory modules including a first memory module coupled to a second set of bonding members on the surface of the second semiconductor device, wherein the first set of bonding members and the second set of bonding members are configured to dock with each other when the first semiconductor device and the second semiconductor device are bonded together.

31. A method of operating an integrated circuit, the method comprising: The first semiconductor device is used, the first semiconductor device including a first programmable gate array; Multiple interface logics are employed, and the multiple interface logics include a first interface logic; A first set of bonding members connecting the first memory port to the surface of the first semiconductor device; as well as The first programmable gate array is operatively coupled to the first interface logic to enable communication via the first memory port.

32. The method of claim 31, wherein employing the first interface logic comprises: The first interface logic is formed by the first programmable gate array.

33. The method of claim 31, wherein employing the first interface logic comprises: The first interface logic is distributed in the first programmable gate array in an interval pattern.

34. The method of claim 31, further comprising: It includes multiple memory ports, such as the first memory port, wherein the multiple memory ports are formed in a spacing pattern on the first semiconductor device.

35. The method of claim 31, further comprising: Multiple sets of bonding members are distributed in a spaced pattern on the surface of the first semiconductor device, the multiple sets of bonding members including the first set of bonding members.

Images