System and method for hybrid sampling plan generation and precise die loss projection

Abstract

Systems, methods, apparatus, and non-transitory computer readable media for generating inspection tool sampling plans. Systems, methods, apparatus, and non-transitory computer readable media may include generating a static sampling plan to determine a baseline for inspection; generating a dynamic sampling plan to determine an abnormal event; applying the static sampling plan; and applying the dynamic sampling plan by triggering additional sampling when the probability of defect predicted in a region of the sample having a historically low probability of defect exceeds a threshold.

Description

Cross-reference to related applications

[0001] This application claims priority to International Application No. PCT / CN2023 / 113385, filed August 16, 2023, and US Application No. 63 / 681,737, filed August 9, 2024, both of which are incorporated herein by reference in their entirety. Technical Field

[0002] The embodiments provided herein relate to generating inspection tool sampling plans, and more specifically to a hybrid approach for improving die loss projection or optimizing wafer region definition and sampling budget distribution based on inspection results, thereby projecting die loss with improved accuracy. Background Technology

[0003] In the manufacturing process of integrated circuits (ICs), both completed and unfinished circuit components are inspected to ensure they conform to the design and are free of defects. Inspection systems utilizing optical microscopes or charged particle (e.g., electron) beam microscopes (such as scanning electron microscopy (SEM)) can be employed. As the physical dimensions of IC components continue to shrink, the accuracy and yield of defect detection become increasingly important. Various metrology tools have been developed and used to inspect whether ICs are manufactured correctly. To improve defect inspection performance, computationally guided inspection (CGI) machine learning models can be used to assist these tools by indicating the areas of the wafer to be inspected. Summary of the Invention

[0004] The embodiments provided herein disclose methods for generating inspection tool sampling plans, and more specifically disclose hybrid methods for improving die loss projection or optimizing wafer region definition and sampling budget distribution based on inspection results, for improved die loss projection.

[0005] Some embodiments provide systems, methods, apparatus, and non-transitory computer-readable media for generating inspection tool sampling plans. Embodiments may include: generating a static sampling plan to determine a baseline for inspection; generating a dynamic sampling plan to determine anomalous events; applying the static sampling plan; and applying the dynamic sampling plan by triggering additional sampling when the predicted defect probability in a region of a sample with a historically low defect probability exceeds a threshold.

[0006] Some embodiments provide systems, methods, apparatuses, and non-transitory computer-readable media for defect inspection using computationally guided inspection sampling plans. Embodiments may include: generating a baseline sampling plan based on historical inspection data; generating an anomaly sampling plan based on manufacturing data and a computational model; applying the baseline sampling plan to a sample; and applying the anomaly sampling plan to the sample when the predicted defect probability in a region of the sample with a historically low defect probability exceeds a threshold.

[0007] Some embodiments provide systems, methods, apparatus, and non-transitory computer-readable media for generating inspection tool sampling plans. Embodiments may include: providing input data for a wafer to a computational defect probability prediction model; determining a defective die probability for a first region of the wafer from the computational defect probability prediction model; and generating a sampling plan for the wafer based on the determined defective die probability for the first region of the wafer and based on a predetermined second region of the wafer.

[0008] Other advantages of this disclosure will become apparent from the following description taken in conjunction with the accompanying drawings, in which certain embodiments of the disclosure are illustrated by way of description and example. Attached Figure Description

[0009] The above and other aspects of this disclosure will become more apparent from the description of exemplary embodiments taken in conjunction with the accompanying drawings.

[0010] Figure 1 This is a schematic diagram illustrating an exemplary electron beam inspection (EBI) system consistent with embodiments of the present disclosure.

[0011] Figure 2A This is a schematic diagram illustrating an exemplary multi-beam system consistent with embodiments of the present disclosure. Figure 1 This is part of an exemplary charged particle beam inspection system.

[0012] Figure 2B This is a schematic diagram illustrating an exemplary single-beam system consistent with embodiments of the present disclosure. Figure 1 This is part of an exemplary charged particle beam inspection system.

[0013] Figure 3 This is a schematic block diagram illustrating the throughput for generating input data, consistent with embodiments of this disclosure.

[0014] Figure 4 This is an example flowchart illustrating a method consistent with embodiments of the present disclosure, which uses a sampling plan generated based on input data defining a wafer region and a sampling budget distribution for each wafer to project die loss based on inspection results.

[0015] Figure 5 This is an example illustration of the expected input of an empirical sampling scheme consistent with embodiments of this disclosure.

[0016] Figure 6 This is an example flowchart of a method consistent with embodiments of the present disclosure for generating a dynamic sampling plan for a wafer based on a non-uniform defect density distribution within the wafer as predicted by a computational model, and projecting die losses based on inspection results.

[0017] Figure 7 This is an example flowchart of a method for generating a dynamic sampling plan for a wafer without a predetermined sampling budget distribution for each wafer region, consistent with embodiments of this disclosure.

[0018] Figure 8 It is an example sampling plan or estimated defective die probability map consistent with embodiments of this disclosure.

[0019] Figure 9 This is an example flowchart of a method for generating a dynamic sampling plan for a wafer without predefined wafer region boundaries and sampling budget distributions for each wafer region, consistent with embodiments of this disclosure.

[0020] Figure 10A and Figure 10B These are example estimated defect die probability maps and example cumulative defect die probability plots (plots) used to evaluate wafer region boundaries, consistent with embodiments of this disclosure.

[0021] Figure 11 It is consistent with the embodiments of this disclosure based on die loss projection R 2 Example flowchart of a method for directly optimizing wafer region limitation and sampling budget distribution using correlation scores.

[0022] Figure 12 An exemplary sampling scheme for a wafer, consistent with embodiments of this disclosure, is shown.

[0023] Figure 13 An exemplary metrology sampling scheme for a wafer, consistent with embodiments of this disclosure, is shown.

[0024] Figure 14 An example static sampling plan portion of a hybrid sampling plan consistent with embodiments of this disclosure is shown.

[0025] Figure 15 A schematic diagram of an example static sampling plan portion of a hybrid sampling plan consistent with embodiments of this disclosure is shown.

[0026] Figure 16 This is an example flowchart of a method for generating a hybrid sampling schedule for a wafer, consistent with embodiments of this disclosure. Detailed Implementation

[0027] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings, and unless otherwise stated, the same reference numerals in the different drawings denote the same or similar elements. The implementations set forth in the following description of the exemplary embodiments do not represent all implementations. Rather, they are merely examples of apparatuses and methods consistent with aspects of the embodiments of this disclosure as described in the appended claims. For example, although some embodiments are described in the context of utilizing electron beams, this disclosure is not limited thereto. Other types of charged particle beams (e.g., including protons, ions, muons, or any other charged particles) may also be applied similarly. Furthermore, other imaging systems may be used, such as optical imaging, photon detection, X-ray detection, ion detection, etc.

[0028] Electronic devices consist of circuits formed on a piece of semiconductor material called a substrate. Semiconductor materials can include, for example, silicon, gallium arsenide, indium phosphide, or silicon germanium. Many circuits can be formed together on the same silicon wafer and are called integrated circuits (ICs). The size of these circuits has been drastically reduced, allowing more circuitry to be housed on the substrate. By significantly increasing the packaging density of circuit components (such as transistors, capacitors, diodes, etc.) on IC chips, it is possible to enhance the computing power of electronic devices while reducing their physical size. For example, the IC chip in a smartphone, about the size of a fingernail, can contain over 2 billion transistors, each smaller than one-thousandth the thickness of a human hair.

[0029] ICs can be manufactured using photolithography, a manufacturing process involving drawing complex circuit patterns on a mask deposited on a substrate. Photolithography can be performed by a photolithography apparatus, a machine that applies a radiation source (e.g., light or X-rays) to a target portion of a substrate to form the desired pattern. The target portion of the substrate can be covered with a patterning device (e.g., a mask), which can be removed or developed after exposure to the radiation source. This process of transferring the desired pattern to the substrate is called a patterning process. The patterning process can include patterning steps that transfer a pattern from a patterning device (e.g., a mask) to the substrate. Additionally, one or more associated patterning steps may be present, such as mask development using a developing apparatus, baking the substrate using a baking tool, etching the pattern on the substrate using an etching apparatus, or other chemical and physical processing steps involved in patterning on the substrate. Variations in experimental parameters (e.g., random variations, errors, or noise due to inspection or patterning tools) can potentially limit photolithography implementation or process yield for high-volume manufacturing (HVM) of ICs and introduce defects into the IC structure.

[0030] In IC manufacturing using photolithography equipment, numerous photolithographic patterning steps are typically performed, thereby forming functional features in successive layers on a substrate. Therefore, a key aspect of the performance of a photolithography equipment is its ability to correctly and accurately place the applied pattern relative to features already formed in previous layers. For this purpose, the substrate is provided with one or more sets of alignment marks. Each mark is a structure with a position that can be measured later using tools such as electron beam inspection. Defects can occur when the applied patterned structure or patterned layer is incorrectly placed relative to the reference marks, or when manufacturing conditions are suboptimal. The reference marks or layout define the desired structure, structure dimensions, and distances between IC structures (such as gates, capacitors, etc.) or interconnects. This ensures that IC devices or lines do not interact in undesirable ways. The structural constraints provided by the reference layout are often referred to as critical dimensions. Critical dimensions of a circuit can be defined as the minimum width of a line or via, or the minimum spacing between two lines or two vias. Therefore, critical dimensions determine the overall size and package density of the designed IC. The goal of IC manufacturing is to faithfully replicate the original IC design on the substrate. If an error occurs during manufacturing, resulting in an IC design pattern that does not match the reference design, it may lead to defects in the IC structure and render the IC inoperable.

[0031] Manufacturing these ICs with their extremely small structures or components is a complex, time-consuming, and costly process, typically involving hundreds of individual steps. Even an error in a single step can significantly impact the functionality of the final product. Even a single "fatal defect" can cause device failure. The goal of manufacturing processes is to improve overall process yield. For example, for a 50-step process, to achieve a 75% yield, each individual step must have a yield greater than 99.4%, and if the yield of an individual step is 95%, the overall process yield drops to 7%.

[0032] In IC chip manufacturing plants, while high process yields are desirable, maintaining high wafer throughput (defined as the number of wafers processed per hour) is also essential. Both high process yields and high wafer throughput can be affected by the presence of defects, especially when operator intervention is required to inspect them. Therefore, high throughput inspection and identification of micron- and nanometer-scale defects are desirable. One approach to improving process yields and wafer throughput is to monitor the IC manufacturing process to ensure that the desired number of defect-free ICs are produced. One method of monitoring the manufacturing process is to inspect the chip circuit structure at various stages of manufacturing. For example, inspection using tools such as charged particle beam inspection tools can be used in this effort to maintain high process yields and high wafer throughput. Inspection of wafers using electron beam inspection tools can generate images of the wafer to measure the IC structure dimensions. The measured dimensions can be compared to a reference structure lacking any defects to determine the presence of defects in the imaged structure. If a defect is present in the structure, the manufacturing process can be adjusted so that the defect is less likely to reappear. However, since a wafer can contain up to a billion IC structures, inspection of ICs for defect detection is often a time-consuming process and may not be possible to inspect the wafer in the correct location to identify defects.

[0033] To mitigate the limitations of inspecting ICs for defects across the entire wafer, typical methods have been applied to estimate or project the total number of defective dies on the wafer at the end of production using wafer inspection results during High-Performance Manufacturing (HVM). The total number of defective dies on the wafer is referred to as the die loss per wafer. Typical methods rely on empirical or fixed sampling plans (e.g., a purely static sampling plan generated from a stacked probe probability map) to guide the inspection of each wafer during HVM. The sampling plan is a two-dimensional map of the wafer indicating the likely location of a particular defective die. Typical methods use historical inspection results to generate the sampling plan (e.g., by focusing on areas on the wafer with historically high defect probabilities, such as the wafer's edges or center), which identify defective dies from previously inspected wafers. The sampling plan is divided into wafer regions, with a predetermined number of dies to be inspected in each region (e.g., a sampling budget). Wafer inspection can be performed concurrently with wafer fabrication, and each wafer inspected during wafer fabrication is inspected according to this sampling plan. After obtaining inspection results for the wafers using an experienced and fixed sampling plan, the die loss at the end of production is projected for each wafer, assuming uniform defect density or distribution within each wafer area. The projected die loss can be used to confirm that satisfactory wafer yield is maintained throughout manufacturing and to estimate the failure rate at the end of production, or the actual die loss per wafer. Wafer processing continues until a batch of wafers is fully manufactured, and then the actual die loss is measured by applying probing tests to the manufactured wafers in that batch. The final metric for estimating the accuracy of this typical method can be R0, which determines the ratio between the projected die loss per wafer and the actual die loss per wafer. 2 Relevance score.

[0034] However, in some cases, the typical methods described above may not be desirable because they can limit the accuracy of projecting die losses for each wafer based on inspection results. Using a fixed sampling schedule to guide the inspection of each wafer inspected during HVM may not respond to wafer-to-wafer variations that occur during wafer processing. Therefore, this approach may not be optimal in terms of efficiently capturing defective dies in each inspected wafer. Typical methods for projecting die losses also assume a uniform defect density or distribution within each wafer, but this may not accurately reflect the actual defect density or distribution within the wafer. For example, a typical static sampling schedule may miss any systematic defect markers where defects rarely occur in wafer regions. Static sampling schedules cannot adequately address unexposed defect mechanisms and are ineffective at capturing future anomalous wafers. Furthermore, static sampling schedules rely solely on randomness and lack responsiveness to emerging defect patterns, resulting in low defect capture rates.

[0035] Furthermore, in a fixed sampling schedule, the wafer regions and the sampling budget allocated to each wafer region may not be optimal to ensure a high defect capture rate for each wafer inspected. Therefore, the typical approach of using a fixed sampling schedule to guide inspection and assuming uniform defect density or distribution may not be able to accurately predict defective dies for the wafer during HVM.

[0036] Other typical approaches may include model-based methods for generating defect probability estimates based on incoming wafer metrology data to produce a dynamic sampling plan. This dynamic sampling plan can be used to guide wafer inspection during HVM. Typical methods can provide a more accurate way to project die losses without assuming a uniform defect density or distribution within the wafer using model-based scaling factors. For example, these typical methods can use pre-trained computational models to translate probability estimates into a dynamic sampling plan for in-line electron beam inspection, thereby improving inspection efficiency by inspecting only areas of the wafer that the model predicts have a high defect probability. The inspection results can also be used to project the die loss of each wafer at the end of production (e.g., wafer probing results). The ultimate metric for these dynamic sampling plans is the correlation R between the projected die loss and the actual die loss. 2 And the capture rate of anomaly signatures (fingerprints).

[0037] However, dynamic sampling plans alone can also be subject to limitations. For example, in wafer manufacturing, static or semi-static electron scanning die-level sampling plans may be preferred for equipment yield monitoring purposes, ensuring that any yield anomalies captured by the monitoring system can be confirmed as genuine yield fluctuations, rather than the result of changes in the wafer-to-wafer sampling plan. Typical dynamic sampling plans can be disadvantageous because they force users to change their production line monitoring methods, risking an unstable baseline.

[0038] Furthermore, dynamic sampling plans are generated from model probabilistic predictions based on online metrology values. Due to throughput constraints, the data used by sampling plans based on online metrology is typically much sparser compared to the probe data available for each die on the wafer. Therefore, the resolution and accuracy of model predictions from dynamic sampling plans may be limited. For example, dynamic sampling plans may result in poor defect detection capabilities and missed defect signatures. Dynamic sampling plans cannot adequately address unexposed defect mechanisms and are not effective at detecting future anomalous wafers.

[0039] Embodiments of this disclosure address the aforementioned constraints by generating a hybrid sampling plan that includes a static sampling plan portion and a dynamic sampling plan portion. For example, the static sampling plan portion can maintain a stable baseline by sampling the wafer at locations historically associated with wafer defects. The dynamic sampling plan portion can generate anomaly sampling plans based on manufacturing data and computational models, thereby taking into account non-uniform defect densities or distributions within the wafer and improving the model's resolution and accuracy.

[0040] For clarity, the relative dimensions of components in the accompanying drawings may be enlarged. In the following description of the drawings, the same or similar reference numerals refer to the same or similar components or entities, and differences are described only with respect to individual embodiments. As used herein, unless expressly stated otherwise, the term "or" covers all possible combinations unless impractical. For example, if an illustrated component may include A or B, then unless expressly stated otherwise or impractical, the component may include A, or B, or A and B. As a second example, if an illustrated component may include A, B, or C, then unless expressly stated otherwise or impractical, the component may include A, B, or C, or A and B, or A and C, or B and C, or A, B, and C.

[0041] Without limiting the scope of this disclosure, some embodiments can be described in the context of providing detectors and detection methods in systems utilizing electron beams. However, this disclosure is not limited thereto. Other types of charged particle beams can also be applied similarly. Furthermore, the systems and methods used for detection can also be used in other imaging systems, such as optical imaging, photon detection, X-ray detection, ion detection, etc.

[0042] Figure 1 An exemplary electron beam detection (EBI) system 100 consistent with embodiments of this disclosure is shown. The EBI system 100 can be used for imaging. Figure 1 As shown, the EBI system 100 includes a main chamber 101, a loading / locking chamber 102, an electron beam tool 104, and a device front-end module (EFEM) 106. The electron beam tool 104 is located within the main chamber 101. The EFEM 106 includes a first loading port 106a and a second loading port 106b. The EFEM 106 may include (multiple) additional loading ports. The first loading port 106a and the second loading port 106b receive a wafer front-end opening unified chamber (FOUP), which contains a wafer (e.g., a semiconductor wafer or a wafer made of (multiple) other materials) or a sample to be inspected (wafers and samples can be used interchangeably). A "batch" is a group of wafers that can be loaded and processed as a single batch.

[0043] One or more robotic arms (not shown) in EFEM 106 can transfer the wafer to loading / locking chamber 102. Loading / locking chamber 102 is connected to a loading / locking vacuum pump system (not shown) that removes gas molecules from loading / locking chamber 102 to achieve a first pressure below atmospheric pressure. After reaching the first pressure, one or more robotic arms (not shown) can transfer the wafer from loading / locking chamber 102 to main chamber 101. Main chamber 101 is connected to a main chamber vacuum pump system (not shown) that removes gas molecules from main chamber 101 to achieve a second pressure below the first pressure. After reaching the second pressure, the wafer is subjected to inspection by electron beam tool 104. Electron beam tool 104 can be a single-beam system or a multi-beam system.

[0044] Controller 109 is electronically connected to electron beam tool 104. Controller 109 may be a computer configured to perform various controls of EBI system 100. Although controller 109 is... Figure 1 The controller 109 is shown outside the structure including the main chamber 101, the loading / locking chamber 102, and the EFEM 106, but it should be understood that the controller 109 may also be part of the structure.

[0045] In some embodiments, controller 109 may include one or more processors (not shown). A processor may be a general-purpose or special-purpose electronic device capable of operating or processing information. For example, a processor may include any number of central processing units (or “CPU”), graphics processing units (or “GPU”), optical processors, programmable logic controllers, microcontrollers, microprocessors, digital signal processors, intellectual property (IP) cores, programmable logic arrays (PLAs), programmable array logic (PALs), general-purpose array logic (GALs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), system-on-a-chip (SoCs), application-specific integrated circuits (ASICs), and any combination of any type of circuitry capable of data processing. A processor may also be a virtual processor, comprising one or more processors distributed across multiple machines or devices connected via a network.

[0046] In some embodiments, controller 109 may also include one or more memories (not shown). The memories may be general-purpose or special-purpose electronic devices capable of storing processor-accessible code and data (e.g., via a bus). For example, the memories may include any number of random access memory (RAM), read-only memory (ROM), optical discs, magnetic disks, hard disks, solid-state drives, flash drives, secure digital cards (SD cards), memory sticks, compact flash (CF) cards, or any combination of any type of storage device. The code may include an operating system (OS) and one or more applications (or "applications") for a specific task. The memories may also be virtual memory, comprising one or more memories distributed across multiple machines or devices coupled via a network.

[0047] Embodiments of this disclosure can provide a single-beam charged particle beam imaging system (“single-beam system”). Compared to a single-beam system, a multi-beam charged particle beam imaging system (“multi-beam system”) can be designed to optimize throughput for different scanning modes. Embodiments of this disclosure provide a multi-beam system with the ability to optimize throughput for different scanning modes by using beam arrays with different geometries and adapting to different throughput and resolution requirements.

[0048] Now for reference Figure 2A The figure is a schematic diagram illustrating an exemplary electron beam tool 104 consistent with embodiments of the present disclosure, which includes a multi-beam inspection tool. Figure 1 The electron beam tool 104 is part of the EBI system 100. In some embodiments, the electron beam tool 104 can serve as... Figure 1 The EBI system 100 includes a single-beam inspection tool operation. The multi-beam electron beam tool 104 (also referred to herein as apparatus 104) includes an electron source 201, a coulomb aperture plate (or "gun aperture plate") 271, a converging lens 210, a source conversion unit 220, a primary projection system 230, a stage 209, and a sample holder 207 supported by the stage 209 for holding a sample 208 (e.g., a wafer or photomask) to be inspected. The multi-beam electron beam tool 104 may also include a secondary projection system 250 and an electron detection device 240. The primary projection system 230 may include an objective lens 231. The electron detection device 240 may include multiple detection elements 241, 242, and 243. A beam splitter 233 and a deflection scanning unit 232 may be located within the primary projection system 230.

[0049] The electron source 201, coulomb aperture plate 271, converging lens 210, source conversion unit 220, beam splitter 233, deflection scanning unit 232, and primary projection system 230 can be aligned with the primary optical axis 204 of device 104. The secondary projection system 250 and electronic detection device 240 can be aligned with the secondary optical axis 251 of device 104.

[0050] The electron source 201 may include a cathode (not shown) and an extractor or anode (not shown), wherein during operation, the electron source 201 is configured to emit primary electrons from the cathode, and the primary electrons are extracted or accelerated by the extractor and / or anode to form a primary electron beam 202, which forms a primary electron beam cross (virtual or real) 203. The primary electron beam 202 can be visualized as being emitted from the primary electron beam cross 203.

[0051] Source conversion unit 220 may include an imaging element array (not shown), an aberration compensator array (not shown), a beam-limiting aperture array (not shown), and a pre-bending micro-deflector array (not shown). In some embodiments, the pre-bending micro-deflector array deflects a plurality of primary sub-beams 211, 212, 213 of the primary electron beam 202 to properly enter the beam-limiting aperture array, the imaging element array, and the aberration compensator array. In some embodiments, device 104 may operate as a single-beam system, such that a single primary sub-beam is generated. In some embodiments, converging lens 210 is designed to focus the primary electron beam 202 into a parallel beam and to properly incident on source conversion unit 220. The imaging element array may include a plurality of micro-deflectors or microlenses to influence the plurality of primary sub-beams 211, 212, 213 of the primary electron beam 202 and form a plurality of parallel images (virtual or real) of the primary beam cross 203, one parallel image for each of the primary sub-beams 211, 212, 213. In some embodiments, the aberration compensator array may include a field curvature compensator array (not shown) and an astigmatism compensator array (not shown). The field curvature compensator array may include a plurality of microlenses to compensate for field curvature aberrations of primary sub-bundles 211, 212, and 213. The astigmatism compensator array may include a plurality of micro-astigmatists to compensate for astigmatic aberrations of primary sub-bundles 211, 212, and 213. The beam-limiting aperture array may be configured to limit the diameter of individual primary sub-bundles 211, 212, and 213. Figure 2A Three primary sub-bundles 211, 212, and 213 are shown as examples. It should be understood that the source conversion unit 220 can be configured to form any number of primary sub-bundles. The controller 109 can be connected to... Figure 1The various components of the EBI system 100, such as the source conversion unit 220, the electronic inspection device 240, the primary projection system 230, or the motorized stage 209. In some embodiments, as explained in further detail below, the controller 109 can perform various image and signal processing functions. The controller 109 can also generate various control signals to control the operation of the charged particle beam inspection system.

[0052] Converging lens 210 is configured to focus primary electron beam 202. Converging lens 210 can also be configured to adjust the current in primary sub-beams 211, 212, and 213 downstream of source conversion unit 220 by changing the focusing capability of converging lens 210. Alternatively, the current can also be changed by changing the radial dimension of the beam-limiting aperture in the beam-limiting aperture array corresponding to the individual primary sub-beams. The current can be changed by changing both the radial dimension of the beam-limiting aperture and the focusing capability of converging lens 210. Converging lens 210 can be an adjustable converging lens, which can be configured such that the position of its first principal plane is movable. The adjustable converging lens can be configured to be magnetic, which may cause off-axis sub-beams 212 and 213 to irradiate source conversion unit 220 at a rotational angle. The rotational angle varies with the focusing capability of the adjustable converging lens or the position of the first principal plane. Converging lens 210 can be an anti-rotation converging lens, which can be configured to maintain a constant rotational angle while the focusing capability of converging lens 210 is changed. In some embodiments, the converging lens 210 may be an adjustable anti-rotation converging lens, wherein the rotation angle remains unchanged when its focusing capability and the position of its first principal plane are changed.

[0053] Objective lens 231 can be configured to focus sub-beams 211, 212, and 213 onto sample 208 for inspection, and in this embodiment, three probe spots 221, 222, and 223 can be formed on the surface of sample 208. Coulomb aperture plate 271 is configured in operation to block peripheral electrons of the primary electron beam 202 to reduce the Coulomb effect. The Coulomb effect can increase the size of each of the probe spots 221, 222, and 223 of the primary sub-beams 211, 212, and 213, thus reducing the inspection resolution.

[0054] For example, beam splitter 233 can be a Wien filter, including an electrostatic deflector that generates an electrostatic dipole field and a magnetic dipole field. Figure 2A(Not shown in the image). In operation, beam splitter 233 can be configured to apply an electrostatic force to the individual electrons of primary sub-bundles 211, 212, and 213 via an electrostatic dipole field. This electrostatic force is equal in magnitude to the magnetic force applied to the individual electrons by the magnetic dipole field of beam splitter 233, but opposite in direction. Therefore, primary sub-bundles 211, 212, and 213 can pass through beam splitter 233 at least substantially straight with a deflection angle of at least substantially zero.

[0055] Deflection scanning unit 232 is configured in operation to deflect primary sub-beams 211, 212, and 213 to scan probe spots 221, 222, and 223 on individual scanning regions within a portion of the surface of sample 208. In response to primary sub-beams 211, 212, and 213 or probe spots 221, 222, and 223 being incident on sample 208, electrons are emitted from sample 208, generating three secondary electron beams 261, 262, and 263. Each of the secondary electron beams 261, 262, and 263 typically comprises secondary electrons (having electron energies ≤50 eV) and backscattered electrons (having electron energies between 50 eV and the landing energies of primary sub-beams 211, 212, and 213). Beam splitter 233 is configured to deflect the secondary electron beams 261, 262, and 263 to secondary projection system 250. The secondary projection system 250 then focuses secondary electron beams 261, 262, and 263 onto detection elements 241, 242, and 243 of the electron detector 240. Detection elements 241, 242, and 243 are arranged to detect the corresponding secondary electron beams 261, 262, and 263 and generate corresponding signals, which are sent to the controller 109 or a signal processing system (not shown), for example, to construct an image of the corresponding scanned area of ​​the sample 208.

[0056] In some embodiments, detection elements 241, 242, and 243 respectively detect corresponding secondary electron beams 261, 262, and 263, and generate corresponding intensity signal outputs (not shown) to an image processing system (e.g., controller 109). In some embodiments, each detection element 241, 242, and 243 may include one or more pixels. The intensity signal output of a detection element may be the sum of signals generated by all pixels within that detection element.

[0057] In some embodiments, controller 109 may include an image processing system comprising an image acquirer (not shown) and a storage device (not shown). The image acquirer may include one or more processors. For example, the image acquirer may include a computer, server, mainframe, terminal, personal computer, any type of mobile computing device, or a combination thereof. The image acquirer may be communicatively coupled to the electronic inspection device 240 of device 104 via a medium such as an electrical conductor, fiber optic cable, portable storage medium, IR, Bluetooth, Internet, wireless network, radio, etc., or a combination thereof. In some embodiments, the image acquirer may receive signals from the electronic inspection device 240 and may construct an image. Thus, the image acquirer may acquire an image of sample 208. The image acquirer may also perform various post-processing functions, such as generating contours, overlaying indicators on the acquired image, etc. The image acquirer may be configured to perform adjustments to the brightness, contrast, etc., of the acquired image. In some embodiments, the storage device may be a storage medium such as a hard disk, flash drive, cloud storage device, random access memory (RAM), other types of computer-readable storage, etc. The storage device can be coupled to the image acquirer and can be used to save the original scanned image data as the original image and to save the post-processed image.

[0058] In one embodiment, the image acquirer may acquire one or more sample images based on imaging signals received from the electron detection device 240. The imaging signals may correspond to a scanning operation for imaging charged particles. The acquired image may be a single image comprising multiple imaging regions. This single image may be stored in a storage device. The single image may be a raw image, which may be divided into multiple regions. Each region may include an imaging region containing features of sample 208. The acquired images may include multiple images of a single imaging region of sample 208 sampled multiple times over a time series. These multiple images may be stored in a storage device. In some embodiments, the controller 109 may be configured to perform image processing steps on multiple images of the same location of sample 208.

[0059] In one embodiment, controller 109 may include a measurement circuitry (e.g., an analog-to-digital converter) to obtain the distribution of detected secondary electrons. Electron distribution data collected during the detection time window, combined with corresponding scan path data of each of the primary sub-beams 211, 212, and 213 incident on the wafer surface, can be used to reconstruct an image of the wafer structure under inspection. The reconstructed image can be used to reveal various features of the internal or external structure of sample 208, thereby revealing any defects that may be present in the wafer.

[0060] In some embodiments, the controller 109 may control the stage 209 to move the sample 208 during the examination of the sample 208. In some embodiments, the controller 109 may enable the stage 209 to continuously move the sample 208 in a certain direction at a constant speed. In other embodiments, the controller 109 may enable the stage 209 to change the speed of movement of the sample 208 over time depending on the steps of the scanning process.

[0061] although Figure 2A The apparatus 104 is shown using three primary electron beams; however, it should be understood that the apparatus 104 may use one, two, or more primary electron beams. This disclosure does not limit the number of primary electron beams used in the apparatus 104. In some embodiments, the apparatus 104 may be a SEM used for photolithography. In some embodiments, the electron beam tool 104 may be a single-beam system or a multi-beam system.

[0062] For example, such as Figure 2B As shown, the electron beam tool 100B (also referred to herein as apparatus 100B) can be a single-beam inspection tool consistent with embodiments of this disclosure, used in the EBI system 10. Apparatus 100B includes a wafer holder 136 supported by a motorized stage 134 to hold the wafer 150 to be inspected. The electron beam tool 100B includes an electron emitter that may include a cathode 103, an anode 121, and a gun aperture 122. The electron beam tool 100B also includes a beam-limiting aperture 125, a converging lens 126, a column aperture 135, an objective lens assembly 132, and a detector 144. In some embodiments, the objective lens assembly 132 may be a modified SORIL lens that includes a pole piece 132a, a control electrode 132b, a deflector 132c, and an excitation coil 132d. During imaging, an electron beam 161 emitted from the tip of cathode 103 is accelerated by the voltage of anode 121, passes sequentially through gun aperture 122, beam-limiting aperture 125, and converging lens 126, and is focused by a modified SORIL lens into a probe spot 170 that impacts the surface of wafer 150. The probe spot 170 can be scanned on the surface of wafer 150 by deflectors (such as deflector 132c or other deflectors in the SORIL lens). Secondary particles emitted from the wafer surface or scattered primary particles (such as secondary electrons or scattered primary electrons) can be collected by detector 144 to determine the beam intensity, allowing an image of the region of interest on wafer 150 to be reconstructed.

[0063] An image processing system 199 may also be provided, comprising an image acquirer 120, a storage device 130, and a controller 109. The image acquirer 120 may include one or more processors. For example, the image acquirer 120 may include a computer, server, mainframe, terminal, personal computer, any type of mobile computing device, or a combination thereof. The image acquirer 120 may be connected to the detector 144 of the electron beam tool 100B via a medium such as an electrical conductor, fiber optic cable, portable storage medium, IR, Bluetooth, Internet, wireless network, radio, or a combination thereof. The image acquirer 120 may receive signals from the detector 144 and construct an image. Thus, the image acquirer 120 may acquire an image of the wafer 150. The image acquirer 120 may also perform various post-processing functions, such as generating contours, overlaying indicators on the acquired image, etc. The image acquirer 120 may be configured to perform adjustments to the brightness, contrast, etc., of the acquired image. The storage device 130 may be a storage medium such as a hard disk, random access memory (RAM), cloud storage device, or other types of computer-readable storage. The storage device 130 can be coupled to the image acquirer 120 and can be used to save the original scanned image data as the original image and to save the post-processed image. The image acquirer 120 and the storage device 130 can be connected to the controller 109. In some embodiments, the image acquirer 120, the storage device 130, and the controller 109 can be integrated into a single electronic control unit.

[0064] In some embodiments, the image acquirer 120 may acquire one or more sample images based on imaging signals received from the detector 144. The imaging signals may correspond to scanning operations used for imaging charged particles. The acquired image may be a single image comprising multiple imaging regions, which may contain various features of the wafer 150. This single image may be stored in the storage device 130. Imaging may be performed based on imaging frames.

[0065] The converging lens and illumination optics system of an electron beam tool may include or be supplemented by an electromagnetic quadrupole electron lens. For example, such as Figure 2B As shown, the electron beam tool 100B may include a first quadrupole lens 148 and a second quadrupole lens 158. In some embodiments, the quadrupole lenses are used to control the electron beam. For example, the first quadrupole lens 148 can be controlled to adjust the beam, and the second quadrupole lens 158 can be controlled to adjust the beam spot size and beam shape.

[0066] Figure 2BA charged particle beam device is shown, wherein the inspection system can use a single primary electron beam, which can be configured to generate secondary electrons by interacting with a wafer 150. A detector 144 can be positioned along an optical axis 105, as shown. Figure 2B In the embodiment shown, the primary electron beam can be configured to travel along the optical axis 105. Therefore, the detector 144 may include a hole at its center, allowing the primary electron beam to pass through the hole to reach the wafer 150.

[0067] For reference Figure 3 This diagram is an example block diagram for generating input data, consistent with embodiments of this disclosure. Figure 3 As shown, the input data can be generated in two steps. The photolithography projection apparatus 301 can be used to manufacture wafers under constant manufacturing conditions (e.g., focusing and dose of the radiation source). The inspection tool 302 (e.g., Figure 1 EBI system 100, Figure 2A Electron beam tool 104 or Figure 2B The electron beam tool 100B can be used to measure metrological information of structures formed on a wafer by the photolithography projection apparatus 301. The metrological information may include, but is not limited to, necking, line pull-back, line thinning, critical dimensions, edge placement, overlap (e.g., overlay between wafer layers), resist top loss, resist undercut, missing defects, and bridging defects of the IC structure on the wafer. A processor 303 with memory (e.g., Figure 1 Controller 109 in Figure 2A Controller 109 Figure 2B The controller 109 can communicate with the inspection tool 302 to store the measurement information.

[0068] The images generated by inspection tool 302 can be used for wafer inspection. For example, a generated image capturing a test equipment area of ​​the wafer is compared with a reference image capturing the same test equipment area. The reference image can be predetermined (e.g., through simulation) and does not include any known defects. If the difference between the generated image and the reference image exceeds a tolerance level, a potential defect can be identified. For another example, inspection tool 302 can scan multiple areas of the wafer, each including test equipment areas designed to be identical, and generate multiple images capturing these test equipment areas during manufacturing. These multiple images can be compared with each other. If the difference between the multiple images exceeds a tolerance level, a potential defect can be identified.

[0069] In some embodiments, processor 303 may be a general-purpose or special-purpose electronic device capable of manipulating or processing information. For example, processor 303 may include any number of central processing units (or “CPU”), graphics processing units (or “GPU”), optical processors, programmable logic controllers, microcontrollers, microprocessors, digital signal processors, intellectual property (IP) cores, programmable logic arrays (PLAs), programmable array logic (PALs), general-purpose array logic (GALs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), system-on-a-chip (SoCs), application-specific integrated circuits (ASICs), and any combination of circuitry capable of data processing. Processor 303 may also be a virtual processor, comprising one or more processors distributed across multiple machines or devices coupled via a network.

[0070] In some embodiments, processor 303 may also include one or more memories (not shown). The memories may be general-purpose or processor-specific electronic devices capable of storing processor-accessible code and data (e.g., via a bus). For example, the memories may include any number of random access memory (RAM), read-only memory (ROM), optical discs, magnetic disks, hard disks, solid-state drives, flash drives, secure digital cards (SD cards), memory sticks, compact flash (CF) cards, or any combination of any type of storage device. The code and data may include an operating system (OS) and one or more applications (or “applications”) for a specific task. The memories may also be virtual memory, comprising one or more memories distributed across multiple machines or devices coupled via a network.

[0071] Current prediction methods for estimating defective die formation during wafer processing and projecting die loss at the end of wafer processing rely on wafer inspection using experience and a fixed sampling schedule. The sampling schedule can be generated by compiling historical inspection results (e.g., probe data from one or more wafers) that identify specific locations of wafer defects (e.g., historical probe data including die defect data from multiple wafers during inspection). In some embodiments, generating this sampling schedule may include: generating a probability estimation map based on historical probe data from multiple samples by averaging the historical probe data (e.g., averaging a stack map; the probability estimate from the stack / average could be the number of defective wafers divided by the total number of wafers), and generating a static sampling schedule based on the generated probability estimation map. In some embodiments, applying this sampling schedule includes: in regions corresponding to historically high defect probabilities (e.g., Figure 10A The gray area of ​​chip 1001 Figure 12 The samples were examined in the sampling area of ​​the sampling plan 1210.

[0072] This sampling plan is also used for each wafer inspected during wafer processing and is therefore considered "fixed" or "static". Once the inspection results for the wafers are obtained via the static sampling plan, the projected die loss can be calculated using the following equation: (Equation 1) (Equation 2)

[0073] In equation 1, This is the number of defective dies that have been identified. This is the number of dies that have been inspected, and This refers to the number of dies within the wafer region. Because the static method assumes that the defect density or distribution within the wafer region is uniform, therefore... It may be necessary to multiply by a scaling factor. According to Equation 1, the scaling factor can be considered as... and The ratio, which can be amplified. This is used to estimate the number of defective dies for the entire wafer region. In Equation 2, the summation proceeds from 1 wafer region up to M wafer regions, where M is an integer.

[0074] Besides assuming uniform defect density or distribution within the wafer region, static methods also require predetermined wafer region boundaries in the sampling plan and a sampling budget for each wafer region distribution. However, since defect density or distribution within the wafer region may not be uniform, and predetermined wafer region boundaries and sampling budgets for each wafer region may be highly dependent on experience, this can limit the accuracy of projected die losses (e.g., suboptimal R0). 2 Correlation coefficient). Furthermore, static methods maintain the same wafer region definition and sampling budget for each wafer region distribution for all incoming wafers. Since each wafer has an optimal wafer region definition or a difference in the sampling budget for each wafer region, this can limit the versatility of static methods in accurately projecting die losses across various wafers. This can lead to the sampling schedule inaccurately guiding the inspection tool during wafer inspection at HVM, resulting in missed defects and thus inaccurate projection of die losses (e.g., suboptimal R). 2 (Relevance score). In other words, static methods may lead to sample planning that directs samples to the same area without considering defects in other areas of the sample. Therefore, this will reduce the yield and throughput of defect-free wafers during HVM.

[0075] In some embodiments, the accuracy of the projected die loss can be improved by using a hybrid sampling scheme. In some embodiments, the hybrid sampling scheme can employ both a static sampling scheme and a dynamic sampling scheme (e.g., Figure 6 Method 600 Figure 7 Method 700, using Figure 8 801 chip Figure 9 Method 900, using Figure 10A Chip 1001, using the diagram in Figure 10, Figure 11 Method 1100) both take into account non-uniform defect density or distribution within the wafer, while still sampling the wafer at locations historically associated with wafer defects (e.g., locations historically prone to defects or already shown to be defective). For example, the static sampling plan portion of generating the hybrid method may include generating a baseline sampling plan based on historical inspection data. In some embodiments, the dynamic sampling plan portion of generating the hybrid method may include generating an anomaly sampling plan based on manufacturing data and computational models (e.g., scanner recipes based on computational lithography models, including scanner resolution enhancement techniques such as optical proximity correction).

[0076] Now for reference Figure 4 , Figure 4 This is an example flowchart of method 400 consistent with embodiments of the present disclosure, method 400 for projecting die loss for a wafer based on inspection results collected from an empirical static (e.g., wafer-to-wafer constant) sampling plan, the empirical static sampling plan having fixed wafer region boundaries and a sampling budget distributed for each wafer region. Figure 4 The steps can be performed by a computing device (e.g., Figure 3 The processor 303) and inspection tools (e.g., Figure 3 The inspection tool 302) is executed.

[0077] In step 401, an empirical sampling plan is generated. This sampling plan can be generated based on historical data from previously inspected wafers or a batch of previously inspected wafers. The historical data can be inspection images containing identified defects on the wafers. Therefore, the generated sampling plan can include these historical defect markers. Furthermore, the sampling plan is generated according to predetermined wafer area definitions and a sampling budget for each wafer area.

[0078] In step 402, an empirical sampling plan is used to guide the inspection of the wafer using inspection tools. For example, this sampling plan can be used to guide the inspection tools during wafer inspection. The wafer inspection is performed according to a predetermined sampling budget for each wafer region in the sampling plan. The wafer inspection is performed in accordance with HVM. The number of dies inspected in the first wafer region is equal to the sampling budget for the first wafer region, and the same applies to the second wafer region.

[0079] In step 403, the die loss assessment for the wafer is projected onto the wafer at the end of wafer processing using the obtained inspection results. For example, the die loss assessment for the wafer can be projected onto the wafer after development, etching, etc. The die loss assessment can be performed according to Equations 1 and 2 above (e.g., assuming that the defect density or distribution in the wafer region is uniform).

[0080] In step 404, the actual die loss is obtained at the end of wafer processing by applying a probing test to the wafer. In some embodiments, the probing results can be applied to the wafer during various steps of wafer processing (e.g., after development, after etching, etc.). The probing test determines whether there are defects in each die on the wafer. In step 405, R 2 The correlation score is evaluated based on both the actual die loss and the projected die loss. It should be understood that R... 2 The correlation score can be determined from a batch of wafers. The first and second wafers can be inspected according to step 402, and two projection die loss values ​​can be determined according to step 403. At the end of wafer processing, the first and second wafers can be measured according to step 404 to obtain two actual die loss values. In some embodiments, the first layer of the wafer and the second layer of the same wafer can be inspected according to step 402, and two projection die loss values ​​can be determined according to step 403. At the end of wafer processing, the wafer can be measured according to step 404 to obtain the actual die loss value.

[0081] In some embodiments, the accuracy of the projected die loss can be improved by using a hybrid sampling scheme. In some embodiments, the hybrid sampling scheme can use method 400 and a dynamic sampling scheme (e.g., Figure 6 Method 600 Figure 7 Method 700, using Figure 8 The method of the 801 chip Figure 9 Method 900, using Figure 10A The method of using chip 1001, using the diagram in Figure 10, Figure 11 Method 1100) both take into account non-uniform defect density or distribution within the wafer, while still sampling the wafer at locations historically associated with wafer defects (e.g., locations historically prone to defects or already shown to be defective). For example, the static sampling plan portion of generating the hybrid method may include generating a baseline sampling plan based on historical inspection data. In some embodiments, the dynamic sampling plan portion of generating the hybrid method may include generating an anomaly sampling plan based on manufacturing data and computational models (e.g., scanner recipes based on computational lithography models, including scanner resolution enhancement techniques such as optical proximity correction).

[0082] Now for reference Figure 5 This figure is an example illustration of the inputs required for an empirical sampling scheme consistent with embodiments of this disclosure. Figure 5 A wafer 501 is shown, having a first wafer region 502, a second wafer region 503, and a third wafer region 504. Each wafer region has a corresponding sampling budget. The definition of each wafer region and the corresponding sampling budget for each wafer region can be adjusted without following conventional methods. Furthermore, the definition of each wafer region remains constant for each wafer being inspected.

[0083] Simply following a static approach to generate an empirical sampling plan with predetermined wafer region boundaries and sampling budget distributions for each wafer region can lead to inaccurate guidance of the inspection tool during wafer inspection and reduced inspection throughput. Furthermore, relying on constant wafer region boundaries and sampling budget distributions for all incoming wafers, and assuming a uniform defect density distribution within the wafer region, can make it challenging to accurately project die losses for different wafers during HVM and thus ensure that ideal wafer yields are maintained.

[0084] In some embodiments of this disclosure, these constraints derived solely from static methods can be improved by using a hybrid sampling scheme. In some embodiments, the hybrid sampling scheme can use a static sampling scheme (e.g., Figure 4 Method 400 Figure 5 (e.g., chip 501) and dynamic sampling scheme (e.g., Figure 6 Method 600 Figure 7 Method 700, using Figure 8 The 801 chip, Figure 9 Method 900, using Figure 10A The chip 1001, using the diagram in Figure 10, Figure 11 Method 1100) both take into account non-uniform defect density or distribution within the wafer, while still sampling the wafer at locations historically associated with wafer defects (e.g., locations historically prone to defects or already shown to be defective). For example, the static sampling plan portion of generating the hybrid method may include generating a baseline sampling plan based on historical inspection data. In some embodiments, the dynamic sampling plan portion of generating the hybrid method may include generating an anomaly sampling plan based on manufacturing data and computational models (e.g., scanner recipes based on computational lithography models, including scanner resolution enhancement techniques such as optical proximity correction).

[0085] Regarding dynamic sampling planning, embodiments of this disclosure can provide a model-based approach to project die losses during wafer processing. The computationally guided inspection (CGI) process guides inspection tools to locations on the wafer with a high probability of defect formation. A machine learning-based CGI model receives input from various data sources, such as wafer characteristic data (which may include scanner data, metrology data, and manufacturing process data) and data from inspection results, to train the model. The CGI machine learning model can be built and used to output a sampling plan that indicates locations on the wafer where defects are likely to form after wafer processing steps, so that the inspection tool will proceed to the sampling locations more efficiently than if inspecting wafer locations based on experience (e.g., a history of previous defects detected during scanning). In some embodiments, the machine learning-based CGI model can be trained using historical data (e.g., a history of previous defects detected during scanning, historical inspection data, historical inspection results) to improve or generate an improved sampling plan. The CGI process is performed concurrently with wafer manufacturing and improves inspection tool efficiency by increasing the accuracy of defect detection on the wafer with a higher defect detection capture rate than a baseline. The test results can be used to confirm that satisfactory wafer yields are maintained throughout manufacturing, and to determine the projected failure rate or die loss per wafer at the end of production. This projected failure rate can be compared with the results of wafer probing tests, which determine the failure rate for each die manufactured on the wafer. The final metric for the CGI model use case can be the R-squared between the estimated die defects and the measured die defects for the wafer. 2 Relevance score.

[0086] A CGI model can be applied to characteristic wafer data to estimate the defect probability for each die on the wafer. A sampling plan optimizer or sampling plan generator then converts the estimated defect probability for each die on the wafer into a die-level sampling decision wafer map (also known as a sampling plan). In some embodiments, the sampling plan can be used to modify the processing parameters of tools in manufacturing (e.g., scanner parameters, etcher parameters, etc.) to provide feedback or feedforward during manufacturing, thereby mitigating identified defects. The sampling plan can be generated based on input information that defines predetermined wafer region boundaries and a sampling budget for each wafer region, as well as user-specified sampling options. The sampling plan can provide a die-level binary sampling decision (e.g., inspect or not inspect the dies on the wafer). The sampling plan can then be used to guide inspection tools (e.g., a scanning electron microscope (SEM) or optical tools) to regions on the wafer where the sampling plan has a set number of dies to inspect (e.g., a sampling budget). The inspection results obtained via the sampling plan indicate the actual number of defective dies present, and these results can then be used to project an estimated die loss for the wafer. In some embodiments, the CGI model can be trained using historical data (e.g., a history of previous defects detected during scanning, historical inspection data, historical inspection results) to improve or generate an improved sampling plan. The R-value for defect die projections provided by the CGI model sampling plan... 2 The correlation score can be determined by collecting "ground truth" results for the wafer. Ground truth results indicate the actual defective die results at the end of production and correspond to the probing test results for a fully completed wafer. Therefore, the probing test results provide an accurate identification of defects for each die on the wafer. The final metric for the CGI model and sampling schedule optimizer can be the correlation R between the estimated die loss projected by the CGI model and the actual die loss determined by the probing test results. 2 Fraction.

[0087] The CGI model provides an output of the defective die probability at the die-to-die level. This means that the CGI model estimates the defect probability for each die on the wafer, which may vary from die to die. The estimated defective die probabilities can be aggregated to generate a sampling plan for the wafer. Because the sampling plan can be generated for each wafer based on the specific defective die probability for each die on the wafer, the sampling plan generated by the CGI model can be called a “dynamic” sampling plan. Dynamic sampling plans can be used to guide inspection tools during wafer inspection to project the die loss for the wafer at the end of wafer processing.

[0088] In some embodiments of this disclosure, the projected die loss is determined without assuming a uniform defect density or distribution within the wafer region. As described above, the die loss can be projected after inspection results are collected by an inspection tool guided by a dynamic sampling plan generated by CGI. The projected die loss can be calculated, consistent with embodiments of this disclosure, via the following equation: (Equation 3) (Equation 4)

[0089] In equation 3, It is the number of defective dies. It is the total number of dies on the chip, and This is the scaling factor. The summation in Equation 3 is from one wafer region i to the total number M of wafer regions on the wafer. In Equation 4, unsampled dies are those not inspected according to the sampling plan generated by CGI, while sampled dies are those inspected. However, each die in wafer region i has a defective die probability determined by the CGI model. Therefore, the summation in the numerator of Equation 4 is equivalent to the expected number of uninspected defective dies, and the summation in the denominator of Equation 4 is equivalent to the expected number of inspected defective dies. Since the defective die probability for each die may differ within the wafer region and throughout the entire wafer, the scaling factor in Equation 4... Non-uniform defect density distributions can be considered. CGI models can determine which dies to inspect (e.g., the dies to be sampled) by sorting the defect die probabilities on a per-wafer-region basis and selecting a certain number of dies for each wafer region based on this sorting. The number of dies can be less than or equal to the sampling budget for the wafer region. In other words, the dynamic sampling plan generated by CGI can select N dies with the highest defect probabilities. i Number of die combinations, where N i This is the sampling budget for chip region i.

[0090] In some embodiments, the dynamic sampling plan portion of generating the hybrid sampling plan may include using a defect probability prediction model (e.g., trained) as described above to determine the defect die probability for a first region of the wafer. The first region of the wafer may exclude regions of the wafer already included in the static sampling plan portion of the hybrid sampling plan. In some embodiments, the dynamic sampling plan portion of generating the hybrid sampling plan may include converting the estimated defect die probabilities above a threshold in the first region into a die-level sampling decision wafer map. That is, the hybrid sampling plan may include regions of the wafer covered by the static sampling plan portion and regions of the wafer that historically have low defect die probabilities (the dynamic sampling plan portion). However, the dynamic sampling plan portion may only include dies with defect die probabilities above a certain threshold. Therefore, there may be no defect die probabilities in the first region of the wafer that meet this threshold, and the hybrid sampling plan may only include the static sampling plan.

[0091] In some embodiments, the first region (e.g., Figure 10A The white area of ​​chip 1001 Figure 12 The defect probability of the die in the dynamic sampling area of ​​the sampling plan 1230 may be higher than that in the area of ​​the wafer covered by the static sampling plan (e.g., Figure 10A The gray area of ​​chip 1001 Figure 12 The probability of defective dies in the sampling area of ​​the sampling plan 1210 is low. In some embodiments, the dynamic sampling plan portion of the hybrid sampling plan can be applied to the sample (in addition to applying the static sampling plan) by triggering additional sampling (e.g., the dynamic sampling plan can be used to determine anomalous events on the wafer) in regions of the sample that have historically low defect probabilities when the predicted defect probability exceeds a threshold.

[0092] Now for reference Figure 6 This figure is an example flowchart of method 600 consistent with embodiments of this disclosure. Method 600 is used to generate a dynamic sampling plan for a wafer and to project die losses based on inspection results, assuming a non-uniform defect density or distribution within the wafer. The steps of method 600 can be performed by a computing device, such as... Figure 3 The processor 303 executes the method. It should be understood that the illustrated method 600 can be modified to change the order of the steps and include additional steps. In some embodiments (e.g., in a sampling plan generated using a hybrid method), a non-uniform defect density or distribution can be obtained from the defect probability detected by a static stack or from a prediction based on a calculated defect probability prediction model.

[0093] In step 601, input data is acquired and supplied to the CGI model. The input data may correspond to metrology information collected from one or more images of a first wafer and a second wafer, which are acquired via wafer processing during HVM. In some embodiments, the input data may correspond to metrology information collected from one or more images of a first layer and a second layer of the same wafer. In some embodiments, the wafer may be manufactured under constant manufacturing conditions (e.g., lithography focus, dose conditions, etc.). The input data may include predetermined wafer region definitions and sampling budget distributions. The metrology information may include, but is not limited to, necking, line retraction, line thinning, critical dimensions, edge placement, overlap (e.g., overlay between wafer layers), resist top loss, resist undercut, missing defects, and bridging defects on the wafer.

[0094] In step 602, an estimated defect probability for each die on the first wafer is calculated based on the input data for the first wafer. This calculation may be based on identified defects in the input data and is affected by the quality of the input data. This calculation may be performed by a processor (e.g., Figure 3 The processor 303 in the chip executes the CGI model, which can apply the CGI model to the first chip.

[0095] In step 603, the estimated defective die probabilities for all dies on the first wafer are sorted. The estimated defective die probabilities can be sorted on a per-wafer region basis, such that for each wafer region, the top N... i The top N highest estimated probability of defective die i One die is considered. As mentioned above, N i It is the sampling budget for each chip region.

[0096] In step 604, based on the wafer region definition determined in step 603 and the first N for each wafer region... i For each die, a sampling plan is generated for the first wafer.

[0097] In step 605, the generated sampling plan for the first wafer is used to guide the inspection tool during the inspection of the first wafer. The inspection tool collects the inspection results of the first wafer based on one or more predicted defect areas identified by the sampling plan. In step 606, the CGI model projects the die loss for the first wafer based on the inspection results collected in step 605 and according to Equations 3 and 4.

[0098] In some embodiments, the generated sampling plan can be used to modify the processing parameters of tools in manufacturing (e.g., parameters of a scanner, parameters of an etcher, etc.) to provide feedback or feedforward in the manufacturing process, thereby mitigating identified defects.

[0099] In step 607, based on the input data for the second wafer, an estimated probability of a defective die for each die on the second wafer is calculated. This calculation can be performed by one or more processors (e.g., Figure 3 The processors (303) in the process execute the CGI model, which can apply the CGI model to the second wafer. The input data for the second wafer is as described in step 601 above, and may include wafer region definition and sampling budget distribution for the second wafer. The estimated defective die probabilities for all dies on the second wafer can be sorted by each wafer region, a sampling plan based on the sorted estimated defective die probabilities can be generated, and die loss can be projected by repeating steps 603 to 606 but for the second wafer.

[0100] In some embodiments, when a region of the wafer is known to be prone to defects, a sampling plan can be used to modify the processing parameters of the tools used in manufacturing (e.g., parameters of the scanner (such as focus dose), parameters of the etcher, etc.) to compensate for the defect-prone regions.

[0101] In step 608, once fully processed at the end of wafer processing, probe test results can be acquired for both the first and second wafers. In some embodiments, probe test results can be acquired for either the first or second wafer during various steps of wafer processing (e.g., after development, after etching, etc.). In step 609, R... 2 The correlation score is evaluated by comparing the actual defective die results (e.g., actual die loss) for the first and second wafers with the defective die probabilities (e.g., projected die loss) estimated as described above.

[0102] It should be understood that method 600 can provide a dynamic sampling plan, which, compared to conventional methods, can guide the inspection tool to areas on the die that may contain a higher concentration of potential defects. Additionally, method 600 can provide a more robust method for projecting die losses at the end of the wafer processing stage. In some embodiments, method 600 can provide a more robust method for projecting die losses after various stages of wafer processing (e.g., after development, after etching, etc.). Therefore, the die losses predicted by method 600 can better match actual results and are comparable to the R-values ​​of conventional methods. 2 Compared to the correlation score, the obtained R 2 The correlation score can be improved. In some embodiments, method 600 can compensate for and mitigate die loss by, for example, generating sampling plans that can be used to modify the processing parameters of the tools used in manufacturing (e.g., scanner parameters (such as focus dose), etcher parameters, etc.).

[0103] In some embodiments of this disclosure, constraints solely derived from dynamic sampling schemes (such as generating unstable baselines and reduced resolution and accuracy of model predictions) can be mitigated by using a hybrid sampling scheme. In some embodiments, the hybrid sampling scheme may use a static sampling scheme (e.g., Figure 4 Method 400 Figure 5 Both the wafer 501 and the dynamic sampling plan described above for method 600, thereby taking into account the non-uniform defect density or distribution within the wafer, improve the resolution and accuracy of the model, and maintain a stable baseline by sampling the wafer at locations historically prone to defects (e.g., sampling the wafer at locations historically prone to defects or already shown to be defective). For example, the static sampling plan portion of generating the hybrid method may include generating a baseline sampling plan based on historical inspection data. In some embodiments, the dynamic sampling plan portion of generating the hybrid method may include generating an anomaly sampling plan based on manufacturing data and computational models (e.g., scanner recipes based on computational lithography models, including scanner resolution enhancement techniques such as optical proximity correction).

[0104] Now for reference Figure 7 , Figure 7 This is an example flowchart of method 700, consistent with embodiments of this disclosure, for generating a dynamic sampling plan for a wafer without requiring a predetermined sampling budget distribution for each wafer region. The steps of method 700 can be generated by a computing device (e.g., Figure 3 The process is executed by the processor 303 in the process. It should be understood that the method 700 shown can be modified to change the order of the steps and to include additional steps.

[0105] In step 701, input data is acquired and supplied to the CGI model. The input data may correspond to metrological information collected from one or more images of a first and second wafer, acquired during HVM processing. In some embodiments, the input data may correspond to metrological information collected from one or more images of a first layer of the wafer and a second layer of the same wafer. In some embodiments, the wafer may be manufactured under constant manufacturing conditions (e.g., lithography focus, dosing conditions, etc.). The input data may include predetermined wafer region definitions. The metrological information may include, but is not limited to: necking, line retraction, line thinning, critical dimensions, edge placement, overlap (e.g., overlay between wafer layers), resist top loss, resist undercut, missing defects, and bridging defects on the wafer.

[0106] In step 702, an estimated defect probability for each die on the first wafer is calculated based on the input data for the first wafer. This calculation may be based on identified defects in the input data and is affected by the quality of the input data. This calculation may be performed by a processor (e.g., Figure 3 The processor 303 in the chip executes the CGI model, which can apply the CGI model to the first chip.

[0107] In step 703, a sampling budget is allocated for each region on the first wafer based on the estimated defective die probability for each wafer region. The calculation performed in step 703 can be as follows: (Equation 5) (Equation 6)

[0108] In equation 5, This represents the sampling budget for region i on the chip. This represents the sampling budget for the entire wafer. Therefore, the sampling budget for a region on the wafer can be determined by multiplying the total wafer sampling budget by the ratio of the sum of defective die probabilities in the wafer region to the sum of defective die probabilities in the entire wafer. In Equation 6, This indicates the total number of dies per wafer. The overall wafer sampling rate is a number from 0 to 1 and represents the percentage of dies on the wafer that can be sampled for inspection.

[0109] In step 704, a sampling plan for the first wafer is generated based on the wafer region definition and the distributed sampling budget for each wafer region calculated in step 703.

[0110] In step 705, the generated sampling plan for the first wafer is used to guide the inspection of the first wafer using an inspection tool. For example, the generated sampling plan can be used to guide the inspection tool during the inspection of the first wafer. The inspection tool collects inspection results of the first wafer based on one or more predicted defect areas identified by the sampling plan. In step 706, the CGI model projects die loss for the first wafer based on the inspection results collected in step 705. Die loss projection can be performed via Equations 3 and 4.

[0111] In step 707, based on the input data for the second wafer, an estimated defect probability for each die on the second wafer is calculated. This calculation can be performed by a processor (e.g., Figure 3The processor 303 executes the process, which can apply the CGI model to the second wafer. The input data for the second wafer is as described in step 701 above, and may include wafer region definition for the second wafer and a total sampling budget. The sampling budget can be allocated for each wafer region, a sampling plan based on the estimated defect probability can be generated, and die loss can be projected by repeating steps 703 to 706 but for the second wafer.

[0112] In step 708, once fully processed at the end of wafer processing, probe test results can be obtained for both the first and second wafers. In some embodiments, probe test results can be obtained for either the first or second wafer during various steps of wafer processing (e.g., after development, after etching, etc.). In step 709, R... 2 The correlation score is evaluated by comparing the actual defective die results (e.g., actual die loss) for the first and second wafers with the estimated defective die probabilities (e.g., projected die loss) as described above.

[0113] It should be understood that, compared to conventional methods, Method 700 can provide a sampling plan that allocates a larger percentage of the total sampling budget to wafer regions identified as containing a higher concentration of potentially defective dies. Therefore, the estimated defective die probability map may better match the true results and has a higher R-value than conventional methods. 2 Compared to the correlation score, the obtained R 2 The correlation score can be improved. In some embodiments, method 700 can compensate for and mitigate die loss by, for example, generating a sampling plan that can be used to modify the processing parameters of the tooling in manufacturing (e.g., scanner parameters (such as focus dose), etcher parameters, etc.).

[0114] In some embodiments of this disclosure, constraints solely derived from dynamic sampling schemes (such as generating unstable baselines and reduced resolution and accuracy of model predictions) can be mitigated by using a hybrid sampling scheme. In some embodiments, the hybrid sampling scheme may use a static sampling scheme (e.g., Figure 4 Method 400 Figure 5Both the wafer 501 and the dynamic sampling plan described above for method 700, thereby taking into account the non-uniform defect density or distribution within the wafer, improve the resolution and accuracy of the model, and maintain a stable baseline by sampling the wafer at locations historically prone to defects (e.g., sampling the wafer at locations historically prone to defects or already shown to be defective). For example, the static sampling plan portion of generating the hybrid method may include generating a baseline sampling plan based on historical inspection data. In some embodiments, the dynamic sampling plan portion of generating the hybrid method may include generating an anomaly sampling plan based on manufacturing data and computational models (e.g., scanner recipes based on computational lithography models, including scanner resolution enhancement techniques such as optical proximity correction).

[0115] For reference Figure 8 The figure is an example sampling plan or estimated defective die probability mapping generated by method 700, consistent with embodiments of this disclosure. Figure 8 Corresponding to wafer 801, wafer 801 includes die 802. Each die 802 is represented as a square outlined in black on wafer 801. As described above, method 700 is defined using a predetermined wafer region, therefore Figure 8 The estimated defective die probability mapping can include, for example, Figure 5 The definition and number of identical wafer regions. It should be understood that... Figure 8 For illustrative purposes only, and the wafer region can be of any shape or size, and the number of wafer regions is not limited in this respect. Figure 8 Represented as a gradient image, where darker colors indicate a higher probability of defective dies, and lighter colors indicate a lower probability of defective dies. The three wafer regions are... Figure 8 The diagram is shown, where dashed line 803 represents the boundary of the first wafer region between the first wafer region and the second wafer region, and dashed line 804 represents the boundary of the second wafer region between the second wafer region and the third wafer region. The second wafer region (e.g., the region between dashed lines 803 and 804) exhibits the darkest color and thus indicates the wafer region with the highest probability of defective dies. According to method 700 ( Figure 7 The generated sampling plan allocates a larger proportion of the total sampling budget to the second region, thus directing the inspection tool more towards the second wafer region than other wafer regions. Because method 700 can optimize the sampling budget allocation for each wafer region while maintaining the predetermined total sampling budget for each wafer, therefore... Figure 8 The estimated probability mapping of defective spools can show the probability of defects being targeted. Figure 5 The generated estimated defect die probability map is compared with the defect die probability for each different wafer region. Therefore, Figure 8This can demonstrate an improved sampling plan or more accurate die loss projection, which is achieved by following method 700 ( Figure 7 A sample budget distribution for each wafer region is generated to optimize the sample budget distribution for wafer inspection while maintaining the predetermined wafer region limits and the total sample budget for each wafer.

[0116] In some embodiments of this disclosure, by using a hybrid sampling scheme, constraints derived solely from a dynamic sampling scheme, such as generating an unstable baseline and reduced resolution and accuracy of model predictions, are mitigated. In some embodiments, the hybrid sampling scheme may use a static sampling scheme (e.g., Figure 4 Method 400 Figure 5 Both the wafer 501 and the dynamic sampling plan for wafer 801 as described above take into account the non-uniform defect density or distribution within the wafer, thereby improving the resolution and accuracy of the model, and maintaining a stable baseline by sampling the wafer at locations historically with wafer defects (e.g., locations historically prone to defects or already shown to be defective). For example, the static sampling plan portion of generating the hybrid method may include generating a baseline sampling plan based on historical inspection data. In some embodiments, the dynamic sampling plan portion of generating the hybrid method may include generating an anomaly sampling plan based on manufacturing data and computational models (e.g., scanner recipes based on computational lithography models, including scanner resolution enhancement techniques such as optical proximity correction).

[0117] For reference Figure 9 This figure is an example flowchart of method 900 consistent with embodiments of this disclosure, for generating a sampling plan for a wafer without predefined wafer region definitions and sampling budget distributions for each wafer region. The steps of method 900 can be performed by a computing device (e.g., Figure 3 The processor 303 executes the procedure. It should be understood that the illustrated method 900 can be modified to change the order of the steps and to include additional steps.

[0118] In step 901, input data is acquired and supplied to the CGI model. This input data may correspond to metrology information collected from one or more images of a first and second wafer, acquired during HVM via wafer processing. In some embodiments, the input data may correspond to metrology information collected from one or more images of a first layer of the acquired wafer and a second layer of the same wafer. Wafer processing and metrology information can be as described above. However, the input data does not require predetermined wafer region definitions and sampling budget distributions for each wafer region.

[0119] In step 902, based on the input data for the first wafer, an estimated probability of a defective die for each die on the first wafer is calculated. This calculation may be based on defects identified in the input data and is affected by the quality of the input data. This calculation may be performed by a processor (e.g., Figure 3 The processor 303 in the chip executes the CGI model, which can apply the CGI model to the first chip.

[0120] In step 903, a defect die probability map is generated for the first wafer by compiling the defect die probabilities as described above. In step 904, the boundaries of the wafer region are evaluated to improve the uniformity of the defect die probability density on the defect die probability map. The uniformity of the defect die probability density can be improved by grouping the first die on the wafer with second dies exhibiting similar defect die probabilities. Step 904 can be performed in two alternative steps. Step 904_1 can be performed by applying a sampling plan generated from the CGI in step 903 and performing an image segmentation technique, which may include, but is not limited to, graph cutting, Otsu's algorithm, edge-based segmentation, threshold-based segmentation, region-based segmentation, cluster-based segmentation, watershed segmentation, semantic segmentation, instance segmentation, panoptic segmentation, and other methods for dividing the image into subgroups. The resulting image segmentation result can define die regions on the wafer with improved non-uniformity of defect die probability density. For example, Figure 8 The estimated defect die probability map or sampling plan shown can correspond to the map or sampling plan generated in step 903. Instead of defining the wafer region boundaries as previously described, the sampling budget distribution for each defined wafer region is optimized, and the resulting estimated defect die probability map is adjusted accordingly. Step 904_1 applies the wafer region boundaries to the estimated defect die probability map based on the radial distribution of the defect die probabilities. Therefore, dies on the wafer can be grouped more evenly within the wafer region.

[0121] Alternatively, in step 904_2, the boundary of the wafer region is determined by integrating the estimated defect die probability map with respect to the radial distance to generate a cumulative defect die probability map. The wafer region boundary can be evaluated by a uniform slope or a region of variation in the cumulative defect die probability. Therefore, the evaluated wafer region can include dies on the wafer with similar defect die probabilities, and improves the uniformity of the defect die probability density on the generated defect die probability map.

[0122] In step 905, a sampling plan with the evaluated wafer region boundaries is used to guide the inspection of the first wafer using an inspection tool. For example, this sampling plan can be used to guide the inspection tool during the inspection of the first wafer. In step 906, the CGI model projects die loss for the first wafer based on the inspection results collected in step 905. Die loss projection can be performed via Equations 3 and 4.

[0123] In step 907, based on the input data for the second wafer, an estimated defect probability for each die on the second wafer is calculated. A sampling plan based on the estimated defect probabilities can be generated, wafer regions can be evaluated, and die losses are projected relative to the second wafer by repeating steps 903 to 906. In step 908, once fully processed at the end of wafer processing, probe test results can be obtained for both the first and second wafers. In some embodiments, probe test results are obtained for either the first or second wafer during various steps of wafer processing (e.g., after development, after etching, etc.). In step 909, R... 2 The correlation score is evaluated by comparing the actual defective die results (e.g., actual die loss) for the first and second wafers with the estimated defective die probabilities (e.g., projected die loss) as described above.

[0124] It should be understood that Method 900 can provide a sampling scheme with increased versatility for different wafers. The wafer area evaluated by Method 900 can guide the inspection tool to areas with a higher probability of defective dies, areas that may have been excluded from the predetermined and constant wafer area defined by conventional methods.

[0125] In some embodiments of this disclosure, constraints solely derived from dynamic sampling schemes (such as generating unstable baselines and reduced resolution and accuracy of model predictions) can be improved by using a hybrid sampling scheme. In some embodiments, the hybrid sampling scheme can use a static sampling scheme (e.g., Figure 4 Method 400 Figure 5Both the wafer 501 and the dynamic sampling plan described above for method 900, thereby taking into account the non-uniform defect density or distribution within the wafer, improve the resolution and accuracy of the model, and maintain a stable baseline by sampling the wafer at locations historically prone to defects (e.g., sampling the wafer at locations historically prone to defects or already shown to be defective). For example, the static sampling plan portion of generating the hybrid method may include generating a baseline sampling plan based on historical inspection data. In some embodiments, the dynamic sampling plan portion of generating the hybrid method may include generating an anomaly sampling plan based on manufacturing data and computational models (e.g., scanner recipes based on computational lithography models, including scanner resolution enhancement techniques such as optical proximity correction).

[0126] Now refer to embodiments consistent with this disclosure. Figure 10A and Figure 10B , Figure 10A and Figure 10B These are example estimated defect die probability maps and example cumulative defect die probability charts used to evaluate wafer region boundaries. Figure 10A Step 903 of method 900 can be illustrated (see...) Figure 9 ).like Figure 10A As shown, the defect die probability map of wafer 1001 may include a first probability boundary 1002 and a second probability boundary 1003, which represent the difference in defect die probabilities. For example, the first probability boundary 1002 illustrates the boundary between regions with a higher defect die probability from wafer 1001 (e.g., illustrated as gray) and regions with a lower defect die probability from wafer 1001 (e.g., illustrated as white). The same can be observed for the second probability boundary 1003. The radial distance 1004 is illustrated as starting from the center of wafer 1001, extending through the first probability boundary 1002, then through the second probability boundary 1003, and finally reaching the edge of wafer 1001 (e.g., the radius of wafer 1001).

[0127] Now for reference Figure 10B This figure is an example consistent with embodiments of the present disclosure, demonstrating the evaluation of wafer region definition by integrating a defect die probability map of the wafer relative to radial distance. Figure 10B This can correspond to step 904_2 of method 900 (see...) Figure 9 ). Figure 10B The chart shown can be viewed through... Figure 10A The defect die probability map of wafer 1001 is obtained by integrating with respect to the radial distance 1004. Therefore, Figure 10B This represents the cumulative defect die probability 1005 of wafer 1001 based on a radial distance 1004. From Figure 10BStarting from the origin, the dashed lines from left to right represent the first probability boundary 1002, then the second probability boundary 1003, and the edge of the wafer 1001. Since the radial distance 1004 begins at the center of the wafer 1001, the cumulative defect die probability 1005 starts from 0 and increases with the radial distance 1004. The radial distance between the origin and the first probability boundary 1002 can correspond to a first wafer region 1006, which can correspond to... Figure 10A The gray area is surrounded by the first probability boundary 1002. The same situation can be observed for the second wafer region 1007 and the third wafer region 1008. According to... Figure 10A Because the first wafer region 1006 has a high defect concentration or density, it exhibits a steep slope in the plotted cumulative defect die probability. The same situation was observed for the third wafer region 1008. Because the second wafer region 1007... Figure 10A It exhibits a lower probability density of defective dies, therefore Figure 10B The slope is lower in the corresponding part. Figure 10B The difference in slope within each region can be used to evaluate the wafer region definition for wafer 1001. In some embodiments, the wafer region can be defined such that the defect die probability density is uniform within that wafer region. For example, as Figure 10B As shown, this corresponds to the slope of the plotted cumulative defect die probability remaining constant throughout the wafer region. The wafer region boundary can then be applied to a defect die probability map at the corresponding radial distance (e.g., Figure 8 (Wafer region boundary 803 and wafer region boundary 804 in the text).

[0128] For reference Figure 11 The figure is an example flowchart of method 1100, consistent with embodiments of this disclosure, for projecting R based on die loss. 2 The correlation score directly optimizes the wafer region constraint and sampling budget distribution. Method 1100 can optimize the die loss projection R based on the wafer training set, using parameterized wafer region constraints and sampling budget variables for each wafer region as optimization variables. 2 Relevance score. Method 1100 can be used in R. 2 The correlation score is performed after the wafer has been inspected using an inspection tool based on a sampling plan generated by CGI and has undergone probing tests to obtain accurate results. This is because the correlation score obtained for the wafer... 2The correlation score is used to guide the optimization of parameterized wafer region constraints and sampling budget distribution variables; therefore, this wafer can be referred to as a "training wafer." Method 1100 can also be performed without predetermined wafer region constraints and sampling budget distributions for each wafer region. The steps of Method 1100 can be performed by a computing device (e.g., Figure 3 The processor 303 executes the procedure. It should be understood that the illustrated method 1100 can be modified to change the order of the steps and include additional steps.

[0129] In step 1101, input data is supplied to the CGI model. The input data may be probe test results and images of the training chip acquired via chip processing, containing the metrological information described above.

[0130] In step 1102, the wafer region definition and the sampling budget for each wafer region are parameterized for the training wafer. For example, the wafer region definition can be parameterized, where the wafer contains two wafer region variables. These parameterized variables can be r1 and r2, where r1 is the radial distance from the center of the wafer to the boundary of the first wafer region, and r2 is the radial distance from the center of the wafer to the boundary of the second wafer region. Given this definition, r1 is constrained to be smaller than r2, and 0. <r1、r2<r max , where r max r is the maximum radial distance from the center of the wafer to the edge of the wafer. max It can be 150 mm. It should be understood that the third wafer region is composed of r2 and r... max The radial distance between them is limited. It should also be understood that a wafer may contain fewer or more than three wafer regions. The sampling budget for each wafer region can be parameterized as variables N1, N2, and N3, where N1 corresponds to the sampling budget for the first wafer region, N2 corresponds to the sampling budget for the second wafer region, and N3 corresponds to the sampling budget for the third wafer region. N1, N2, and N3 can be constrained such that the sampling budget for a wafer region cannot exceed the total number of dies in that wafer region, and N1 + N2 + N3 = N budget , where N budget It is a predetermined total sampling budget for the wafer being inspected.

[0131] In step 1103, the parameterized wafer region variables and the sampling budget for each parameterized wafer region variable are optimized to maximize R. 2 Correlation score. This optimization can be performed using any constrained global optimization technique that uses a forward solver to map parameterized wafer region variables, or the sampling budget of each parameterized wafer region variable, to the defect die loss R based on the training wafer. 2Relevance score. Constrained global optimization techniques may include, but are not limited to, Bayesian optimization, coordinate descent, adaptive coordinate descent, Cuckoo search, Beetle antenna search, data-based online nonlinear extremum search, evolutionary strategies, genetic algorithms, multi-level coordinate search algorithms, Nelder-Mead methods, particle swarm optimization, pattern search, stochastic search, simulated annealing, stochastic optimization, subgradient methods, or any other derivative-free optimization algorithm. Step 1103 can be repeated until the above parameterized variables are co-optimized to obtain the maximum R. 2 Relevance score.

[0132] In step 1104, the co-optimized parameterized wafer regions and sampling budget variables for each wafer region are used to generate a sampling plan. In step 1105, the generated sampling plan is applied to the first and second wafers in the test set to guide the inspection tool during the inspection of the first and second wafers in the test set. Compared to the sampling plan used to guide the inspection tool for training the wafers before method 1100 was implemented, the updated sampling plan can indicate different wafer region boundaries and sampling budget distributions for each wafer region.

[0133] In step 1106, the inspection results collected for the first and second wafers in the test set are used to project the die loss for the first and second wafers in the test set. Die loss projection can be performed via Equations 3 and 4. In step 1107, after wafer processing is completed, probe test results are collected for the first and second wafers in the test set to obtain the actual die loss. In step 1108, R is verified. 2 Relevance scores were evaluated. R was validated. 2 Correlation score and initial R of method 1100 2 Compare the relevance scores. If the validation R... 2 The correlation score compared to the initial R 2 If the correlation score is high, the parameterized wafer region and the sampling budget distribution variables of each wafer region can be applied to the wafer for subsequent wafer processing.

[0134] It should be understood that Method 1100 can provide an optimization-based approach to generate optimal fixed sampling schedule settings (e.g., wafer region constraints or sampling budget distribution), which has versatility for predicting the increase of defective dies on different wafers with improved accuracy. It should also be understood that the optimized parameterized wafer region constraints and sampling budget constraints determined from Method 700 or Method 900 can be applied as initial guesses in Method 1100. This can reduce the time and computational costs associated with the optimization of Method 1100.

[0135] Referring now to Table 1, which shows the R values ​​of three wafer datasets determined by methods 600 and 700 of this disclosure relative to conventional methods. 2 The correlation score is improved. Specifically, each dataset includes batches of more than 100 wafers, where sampling plans are generated according to methods 600 and 700 of this disclosure to guide the inspection tool. Projected die losses are calculated, and probe test results are obtained for a portion of the wafers in the batch of dataset 1; while projected die loss calculations are performed, and probe test results are obtained for each wafer in datasets 2 and 3. It should be understood that for both methods 600 and 700 (e.g., assuming non-uniform defect density or distribution), die losses are projected using equations 3 and 4. 2 The correlation scores were determined as described above, and it was found that for each wafer dataset, when Method 600 or Method 700 was applied instead of the traditional method, R... 2 The relevance score was improved. Compared to traditional methods, R² improved when Method 600 was applied across all three datasets. 2 The improved correlation score indicates the benefit of assuming a non-uniform defect density or distribution in the die loss projection. Compared to Method 600, when Method 700 is applied, the R-values ​​for datasets 2 and 3 are significantly higher. 2 The correlation score showed further improvement. Therefore, in addition to assuming a non-uniform defect density or distribution in the die loss projection, when the model-based sampled budget distribution is applied, R... 2 The relevance score can be further improved.

[0136] Table 1. R-values ​​of conventional methods and methods 600 and 700 in this disclosure 2 Quantification of correlation score comparison.

[0137] The benefits provided by the embodiments of this disclosure can be that, using a CGI model that requires no input variables, the R-value of the actual die loss versus the projected die loss can be obtained. 2 The correlation score is improved. In some embodiments, this disclosure can provide a method for projecting die losses without assuming that the defect density or distribution is uniform within the wafer region, and improves R... 2 Correlation score. In some embodiments, the sampling budget distribution defined for the wafer or wafer region can be optimized to improve R... 2 Relevance score. In some embodiments, an optimization-based model is provided, which can further improve R... 2Relevance score. Some embodiments of this disclosure can provide methods for improving the performance and versatility of CGI models to guide wafer inspection. Some embodiments of this disclosure can provide methods for improving defect inspection accuracy and defect-free wafer yield throughout HVM.

[0138] In some embodiments of this disclosure, by using a hybrid sampling scheme, constraints derived solely from a dynamic sampling scheme, such as the generation of unstable baselines and reduced model prediction resolution and accuracy, can be improved. In some embodiments, the hybrid sampling scheme may use a static sampling scheme (e.g., Figure 4 Method 400 Figure 5 The method 1100 employs a dynamic sampling plan as described above, taking into account non-uniform defect density or distribution within the wafer, improving model resolution and accuracy, and maintaining a stable baseline by sampling the wafer at locations historically prone to defects (e.g., sampling locations historically prone to defects or already shown to be defective). For example, the static sampling plan portion of generating the hybrid method may include generating a baseline sampling plan based on historical inspection data. In some embodiments, the dynamic sampling plan portion of generating the hybrid method may include generating an anomaly sampling plan based on manufacturing data and computational models (e.g., scanner recipes based on computational lithography models, including scanner resolution enhancement techniques such as optical proximity correction).

[0139] Now for reference Figure 12 The figure illustrates exemplary sampling schemes 1210, 1220, and 1230 for a wafer consistent with embodiments of this disclosure.

[0140] In some embodiments, sampling plan 1210 may display a static sampling plan for wafers 1201, 1202, 1203, 1204, 1205, and 1206 (e.g., using...). Figure 4 Method 400 is generated, corresponding to Figure 5 (Wafer 501 in the figure). As shown in the sampling plan 1210, wafers 1201, 1202, 1203, 1204, 1205, and 1206 include uniform sampling regions 1211 and 1212. In some embodiments, sampling regions 1211 and 1212 may correspond to regions of the wafer that have historically had wafer defects (e.g., regions of the wafer that have historically been prone to defects or have been shown to have defects).

[0141] In some embodiments, sampling plan 1220 may display a dynamic sampling plan for wafers 1201, 1202, 1203, 1204, 1205, and 1206 (e.g., using...). Figure 6 Method 600 Figure 7Method 700 (corresponding to) Figure 8 (chip 801) Figure 9 Method 900 (corresponding to) Figure 10A The chip 1001 corresponds to Figure 10B (Charts) Figure 11 Method 1100 is generated. As shown in sampling plan 1220, wafers 1201, 1202, 1203, 1204, 1205, and 1206 include non-uniform sampling regions (e.g., sampling regions 1221 and 1222 of wafer 1201). That is, the sampling regions of wafers 1201, 1202, 1203, 1204, 1205, and 1206 vary from wafer to wafer due to differences in the input data (e.g., manufacturing data of individual wafers) fed into the computational model to generate the dynamic sampling plan.

[0142] In some embodiments, certain sampling regions of the dynamic sampling scheme 1220 (e.g., sampling region 1223 of wafer 1203 and sampling region 1224 of wafer 1206) may correspond to regions that have historically not had wafer defects (e.g., regions of wafers that have historically not been prone to defects or have not been shown to have defects).

[0143] In some embodiments, sampling plan 1230 may display a hybrid sampling plan generated based on static sampling plan 1210 and dynamic sampling plan 1220. As shown in hybrid sampling plan 1230, sampling regions 1211 and 1212 are included for each of wafers 1201, 1202, 1203, 1204, 1205, and 1206.

[0144] In some embodiments, the dynamic sampling plan portion of the hybrid sampling plan 1230 may include only dies with a defective die probability higher than a certain threshold (e.g., sampling regions of the dynamic sampling plan 1220 located outside the static sampling plan 1210 and higher than the threshold). For example, the hybrid sampling plan 1230 may include sampling regions 1223 and 1224 of the static sampling plan 1210 and the dynamic sampling plan 1220 (e.g., the defective die probability corresponding to sampling regions 1223 and 1224 may be higher than the threshold).

[0145] Now for reference Figure 13 The figure illustrates exemplary metrology sampling schemes 1310 and 1320 for a wafer consistent with embodiments of this disclosure.

[0146] In some embodiments, sampling plan 1310 may correspond to a typical metrological sampling plan to obtain input data (e.g., manufacturing data) for generating a dynamic sampling plan (e.g., using...). Figure 6 Method 600 Figure 7 Method 700 (corresponding to) Figure 8 (chip 801) Figure 9 Method 900 (corresponding to) Figure 10A Chip 1001 in the middle, corresponding to Figure 10B (Charts) Figure 11 Method 1100 and Figure 12 The dynamic sampling plan 1220 was generated.

[0147] In the embodiments of this disclosure for generating a hybrid sampling plan, due to the static sampling plan (e.g., Figure 12 A static sampling plan 1210 is applied, and sampling plan 1310 may be an inefficient distribution of the sampling budget. Therefore, in some embodiments, the sampling budget can be redistributed to improve the accuracy of the dynamic sampling plan portion of the hybrid sampling plan. For example, sampling plan 1320 can be generated. In some embodiments, sampling plan 1320 can be a modification of an existing metrological sampling plan (e.g., a modification of sampling plan 1310). As shown in sampling plans 1310 and 1320, a sampling area (e.g., sampling area 1312) can be redistributed from an area corresponding to the static sampling plan portion to an area corresponding to the dynamic sampling plan portion (e.g., redistributed to sampling area 1322, an area with a historically low defect probability) to improve the accuracy of the dynamic sampling plan portion.

[0148] When using a hybrid sampling plan (e.g., Figure 12 In some embodiments of the sampling plan 1230, the sampling budget ratio of the wafer can be allocated based on real-time demand and historical data to the dies that will be sampled using a static sampling plan and the dies that will be sampled using a dynamic sampling plan (e.g., the number of dies per wafer that will be sampled using static sampling and the number of dies that will be sampled using dynamic sampling can be adjusted). In some embodiments, the dynamic sampling plan of the hybrid sampling plan can be based on dynamic sampling optimization using a fixed sampling budget for each wafer or each region (e.g., a region of the wafer, a quadrant of the wafer, a concentric circle region of the wafer, etc.).

[0149] Figure 14 A hybrid sampling scheme consistent with embodiments of this disclosure is shown (e.g., Figure 12 Example of a static sampling plan portion 1400 (sampling plan 1230 in the sample plan). In some embodiments, in addition to the CGI-generated dynamic sampling plan portion of the hybrid sampling plan, a fixed die location 1410 in the static sampling plan portion 1400 can be selected for inspection. Advantageously, this option allows targeted sampling of areas known or suspected of being problematic based on experience (e.g., historical data).

[0150] Figure 15A hybrid sampling scheme consistent with embodiments of this disclosure is shown (e.g., Figure 12 A schematic diagram of the example static sampling plan portion of the sampling plan 1230 is shown in Figure 1500.

[0151] In some embodiments, maps 1510, 1520, and 1530 can be generated based on historical defect data across multiple wafers. For example, each of maps 1510, 1520, and 1530 can correspond to a different wafer. Maps 1510, 1520, and 1530 can represent the defect probability for each die on the wafer. For example, points 1512, 1522, and 1532 can represent dies on the wafer that are “failed” (e.g., may be defective), while points 1514, 1524, and 1534 can represent dies on the wafer that are “passed” (e.g., unlikely to be defective).

[0152] The system can use Equation 7 to generate mapping map 1540, which can represent the mapping map of stacked probe wafers. That is, Equation 7 can be used to average mapping maps 1510, 1520, and 1530 to generate mapping map 1540. (Equation 7) in This can represent the number of wafers (e.g., the number of wafers corresponding to maps 1510, 1520, and 1530), while This can represent the defect probability result (e.g., "failure" or "pass") of the die at coordinates (x, y) for a wafer mapping (e.g., mappings 1510, 1520, and 1530). According to Equation 7, The probability of stacking and detecting individual chips at coordinates (x, y) can be achieved by targeting... The defect probability results for each die of a wafer at coordinate (x, y) are summed to calculate the defect probability. Map 1540 can be generated by calculating the stack detection probability of dies for various wafers at each coordinate (x, y) using Equation 7.

[0153] Mapping map 1540 can be used to generate the static sampling portion of a hybrid sampling plan. In some embodiments, mapping map 1540 can be used to generate the static sampling portion of a hybrid sampling plan by determining fixed sampling locations on mapping map 1540 based on the highest defect probability. In some embodiments, the static sampling portion of the hybrid sampling plan can be generated by determining different regions of mapping map 1540 (e.g., quadrants of mapping map 1540, concentric rings of mapping map 1540, etc.) to ensure more strategic coverage of the wafer.

[0154] Similar to Figure 15In some embodiments, instead of using a stacked probe map (e.g., map 1540) to generate the static sampling plan portion of the hybrid sampling plan, a wafer map can be used to generate the static sampling plan portion. For example, each die in the wafer map can correspond to historical sampling frequency data. In some embodiments, each die in the wafer map can correspond to the probability that the die at that location will be sampled.

[0155] Based on the wafer mapping map, the static sampling plan portion of the hybrid sampling plan can be generated. For example, the static sampling plan portion can target historically unsampled or least sampled regions of the wafer based on a probability map of past sampling data. Advantageously, this method aims to explore and resolve regions with higher uncertainty on the wafer.

[0156] The system can use Equation 8 to generate a stacked wafer mapping map. (Equation 8) in It can represent the number of wafers (e.g., the number of wafers corresponding to a wafer map), and This can represent the sampling probability result of the die at coordinates (x, y) on the wafer map (e.g., the die is likely to be sampled, the die is unlikely to be sampled, etc.). According to Equation 8, The stacking sampling probability of each chip at coordinates (x, y) can be obtained by targeting... The wafer map is calculated by summing the sampling probabilities of each die at coordinates (x, y) for each wafer. The wafer map can be generated by calculating the stacked sampling probabilities of the dies at each coordinate (x, y) for various wafers using Equation 8.

[0157] In some embodiments, the projected die loss can be calculated based on a hybrid sampling plan approach. For example, based on Equation 9, static or fixed sampling probabilities can be combined with defect probabilities generated by CGI (based on a dynamic sampling plan) to generate a more accurate and comprehensive risk assessment. (Equation 9).

[0158] The hybrid sampling probability for the die at coordinate (x,y) (e.g., the probability that the die at coordinate (x,y) will fail or be defective in a hybrid sampling plan) can be determined based on a CGI model prediction probability (the probability that the die at coordinate (x,y) will fail or be defective in the dynamic sampling portion) and a stacking detection probability (e.g., Equation 7) or a stacking sampling probability (e.g., Equation 8). The dynamic sampling rate and the fixed sampling rate can be the ratio of dies in the sampling budget (e.g., the ratio of dies under dynamic sampling to the ratio of dies under static sampling).

[0159] Equation 10 can be used to determine the projected die loss: (Equation 10). The projected die loss can be calculated based on the number of defective dies captured, the total number of dies inspected, and a scaling factor (e.g., determined by the mixed sampling probability of Equation 9). In some embodiments, the system (e.g., Figure 2A and Figure 2B Controller 109, Figure 3 The processor 303 can use the sampling plan of the disclosed embodiments to guide the sampling inspection of the sample, use the inspection results of the sample (e.g., using Equation 10) to calculate the projected die loss, obtain the detection test results for the sample, and evaluate R by comparing the detection test results with the projected die loss. 2 Relevance score.

[0160] Embodiments of this disclosure describing a hybrid sampling scheme advantageously result in an increased defect detection rate. This is achieved through strategic static sampling (e.g., Figure 14 and Figure 15 Combined with a dynamic, data-driven sampling schedule, the hybrid sampling schedule targets defects more effectively across the wafer and can also predict projected die losses with greater accuracy.

[0161] Embodiments of this disclosure describing hybrid sampling schemes advantageously result in improved adaptability and coverage. For example, embodiments of this disclosure provide flexibility that allows for customized inspection strategies to adapt to new and evolving defect patterns, which significantly improves coverage. Embodiments of this disclosure increase throughput by focusing on areas of the wafer that are less likely to be defective.

[0162] Embodiments of this disclosure that describe a hybrid sampling scheme provide enhanced robustness of the model by integrating a wider range of datasets and multiple sampling strategies, thereby improving the overall predictive power and reliability of the model.

[0163] Now for reference Figure 16 The figure is an example flowchart of method 1400, which is consistent with an embodiment of the present disclosure, for generating a hybrid sampling plan for a wafer.

[0164] In step 1601, the system (e.g., Figure 3 The processor 303 can generate a static sampling plan to determine a baseline for inspection (e.g., generating a baseline sampling plan based on historical inspection data). In some embodiments, the static sampling plan may include a predetermined region of the wafer. For example, step 1601 may be performed as described above for... Figure 4 Method 400 Figure 5 Chip 501, Figure 12Static sampling plan 1210 Figure 14 Static sampling plan part 1400, Figure 15 The diagram 1500 and the embodiments described in the above diagram are executed.

[0165] In step 1602, the system may generate a dynamic sampling plan to identify anomalous events (e.g., generating an anomalous event sampling plan based on manufacturing data and a computational model). In some embodiments, generating a dynamic sampling plan may include providing wafer-specific input data to a defect probability prediction model and determining the defect die probability for a region of the wafer from the defect probability prediction model. For example, step 1602 may be performed as described above for… Figure 6 Method 600 Figure 7 Method 700 Figure 8 801 chip Figure 9 Method 900 Figure 10A Chip 1001 Figure 10B Charts, Figure 11 Method 1100 or Figure 12 The dynamic sampling plan 1220 was executed.

[0166] In step 1603, the system can apply a static sampling plan. For example, step 1603 can be performed according to the above-described approach for... Figure 4 Method 400 Figure 5 Chip 501, or Figure 12 Static sampling plan 1210 Figure 14 Static sampling plan part 1400, Figure 15 The diagram 1500 and the embodiments described in the above diagram are executed.

[0167] In step 1604, when the predicted defect probability in a region of the sample with a historically low defect probability exceeds a threshold, the system can apply a dynamic sampling plan by triggering additional sampling. For example, step 1604 can be performed as described above for... Figure 6 Method 600 Figure 7 Method 700 Figure 8 801 chip Figure 9 Method 900 Figure 10A Chip 1001 Figure 10B Charts, Figure 11 Method 1100 or Figure 12 The dynamic sampling plan 1220 was executed.

[0168] A non-transitory computer-readable medium may be provided, which can store information for use with a controller (e.g., Figure 1 Controller 109 in Figure 2A Controller 109 Figure 2A The processor of the controller 109) executes, among other things, image inspection, image acquisition, platform positioning, beam focusing, electric field adjustment, beam bending, converging lens adjustment, activation of charged particle sources, and beam deflection; and stores instructions for the lithography projection apparatus (e.g., Figure 3 The photolithography projection apparatus 301 and the inspection tools (e.g., Figure 3 The processor of the inspection tool 302 executes instructions to determine the input data of the sample. Figure 6 Method 600, Execution Figure 7 Method 700, Execution Figure 9 Method 900, Method 1100 of Figure 1100, Method 1600 of Figure 1600, and other executable functions related to modeling and optimizing wafer region definitions or sampling budget distributions for each wafer region are used for inspection during HVM. Common forms of non-transitory media include, for example, floppy disks, flexible disks, hard disks, solid-state drives, magnetic tapes, or any other magnetic data storage media, optical disc read-only memory (CD-ROM), any other optical data storage media, any physical media with a perforated pattern, random access memory (RAM), programmable read-only memory (PROM) and erasable programmable read-only memory (EPROM), flash EPROM or any other flash memory, non-volatile random access memory (NVRAM), caches, registers, any other memory chips or cards, and their networked versions.

[0169] These embodiments may also be described using the following terms:

[0170] 1. A method for generating a sampling plan for an inspection tool, the method comprising:

[0171] Provide wafer-specific input data to the defect probability prediction model;

[0172] The wafer is divided into multiple wafer regions with dies;

[0173] The defect probability of each wafer region is determined based on the defect probability prediction model.

[0174] At least one die is selected from each of the plurality of wafer regions using the determined defect die probability; and

[0175] A sampling plan for the wafer is generated based on the selected die.

[0176] 2. The method according to Clause 1, wherein the input data includes an image containing metrological information of the wafer.

[0177] 3. The method according to Clause 1 or 2, wherein the input data includes predetermined wafer region definitions and sampling budgets for each wafer region.

[0178] 4. The method according to Clause 3, wherein selecting at least one die from each of the plurality of wafer regions using the determined defective die probability further comprises:

[0179] The defect die probabilities for each identified wafer region are sorted; and

[0180] Based on the determined ranking of the defective die probabilities, a number of dies are selected for each of the plurality of wafer regions, wherein the number of dies is less than or equal to the sampling budget for the corresponding wafer region.

[0181] 5. The method according to any one of clauses 1 to 4 further includes:

[0182] The sampling plan is used to guide the wafer inspection of the wafer;

[0183] The inspection results of the wafer are used to calculate the projected die loss;

[0184] Obtain the detection test results for the wafer; and

[0185] R is evaluated by comparing the detection test results with the projected die loss. 2 Relevance score.

[0186] 6. The method according to Clause 5, wherein the projected die loss is calculated by assuming a non-uniform defect density or distribution in the wafer.

[0187] 7. The method according to any one of Clauses 1 to 6, wherein the inspection tool is a scanning charged particle microscope or an optical tool.

[0188] 8. The method according to any one of Clauses 1 to 7, wherein the calculated defect probability prediction model is a calculated guided inspection model.

[0189] 9. A method for optimizing a sampling plan for an inspection tool, the method comprising:

[0190] Provide wafer-specific input data to the computational defect probability prediction model; and

[0191] A sampling budget is allocated for the region based on a comparison between the expected number of defective dies for a region of the wafer and the expected number of defective dies for the wafer.

[0192] The expected number of defective dies for the region is the sum of predicted defective die probabilities for the region, and the expected number of defective dies for the wafer is the sum of predicted defective die probabilities for the wafer; and

[0193] The predicted defect die probability for the region and the predicted defect die probability for the wafer are obtained from the defect probability prediction model.

[0194] 10. The method according to Clause 9, wherein the input data includes an image containing metrological information of the wafer.

[0195] 11. The method according to Clause 9 or 10, wherein the input data includes a predetermined wafer region definition and a sampling budget for the wafer.

[0196] 12. The method according to any one of clauses 9 to 11 further comprises:

[0197] Generate a sampling plan to guide the wafer inspection of the wafer;

[0198] The inspection results of the wafer are used to calculate the projected die loss;

[0199] Obtain the detection test results for the wafer; and

[0200] R is evaluated by comparing the detection test results with the projected die loss. 2 Relevance score.

[0201] 13. The method according to any one of Clauses 9 to 12, wherein the inspection tool is a scanning charged particle microscope or an optical tool.

[0202] 14. The method according to any one of Clauses 9 to 13, wherein the calculated defect probability prediction model is a calculated guided inspection model.

[0203] 15. A method for optimizing a sampling plan for an inspection tool, the method comprising:

[0204] Provide wafer-specific input data to the defect probability prediction model;

[0205] The defect probability of each die for the wafer is determined based on the defect probability prediction model.

[0206] Generate a sampling plan;

[0207] The wafer region is evaluated based on the defective die probability for each die of the wafer.

[0208] The sampling budget distribution for each wafer region under evaluation is assessed; and

[0209] The sampling plan, which includes the evaluated wafer region and the sampling budget distribution, is used to guide the inspection of the wafer.

[0210] 16. The method according to Clause 15, wherein the input data includes an image containing metrological information of the wafer.

[0211] 17. The method according to Clause 15 or 16, wherein the input data includes a predetermined sampling budget for the wafer.

[0212] 18. The method according to any one of Clauses 15 to 17, wherein the wafer region is evaluated by integrating the calculated probability of the defective die for each die of the wafer with respect to a radial direction on the wafer.

[0213] 19. The method according to any one of Clauses 15 to 17, wherein the wafer region is evaluated by image segmentation of the calculated probability of the defective die for each die of the wafer.

[0214] 20. The method according to any one of clauses 15 to 19 further comprises:

[0215] The inspection results of the wafer are used to calculate the projected die loss;

[0216] Obtain the detection test results for the wafer; and

[0217] R is evaluated by comparing the detection test results with the projected die loss. 2 Relevance score.

[0218] 21. The method according to any one of Clauses 15 to 20, wherein the inspection tool is a scanning charged particle microscope or an optical tool.

[0219] 22. The method according to any one of Clauses 15 to 21, wherein the calculated defect probability prediction model is a calculated guided inspection model.

[0220] 23. A method for optimizing a sampling plan for an inspection tool, the method comprising:

[0221] Provide wafer-specific input data to the defect probability prediction model;

[0222] The wafer region is defined and the sampling budget for the wafer region is parameterized, wherein the parameterized wafer region definition and the parameterized sampling budget for the wafer region have specific constraints; and

[0223] The parameterized wafer region definition and the parameterized sampling budget for the wafer region are optimized according to the specific constraints to maximize the projection value.

[0224] 24. The method according to Clause 23, wherein the input data includes the detection test results of the wafer.

[0225] 25. The method according to clause 23 or 24, wherein the input data includes R 2 Relevance score.

[0226] 26. The method according to any one of Clauses 23 to 25, wherein the wafer region is parameterized using a first variable and a second variable.

[0227] 27. The method according to Clause 26, wherein the first variable is r1 and the second variable is r2, wherein r1 is the radial distance from the center of the wafer to the boundary of the first wafer region, and wherein r2 is the radial distance from the center of the wafer to the boundary of the second wafer region.

[0228] 28. The method according to Clause 27, wherein the constraints on the first variable and the second variable include 0 <r1,r2<r max , where r max The radius of the wafer is given.

[0229] 29. The method according to clause 27 or 28, wherein the constraints on the first variable and the second variable include r1. <r2。

[0230] 30. The method according to any one of clauses 23 to 29, wherein the sampling budget for a wafer region on the wafer is parameterized using a first variable, a second variable, and a third variable.

[0231] 31. The method according to Clause 30, wherein the first variable is N1, the second variable is N2, and the third variable is N3, wherein N1 is a sampling budget for a first wafer region, wherein N2 is a sampling budget for a second wafer region, and wherein N3 is a sampling budget for a third wafer region.

[0232] 32. The method according to Clause 31, wherein the constraints on N1, N2, and N3 include N1 + N2 + N3 = N budget , where Nbudget This is the total sampling budget for the wafer.

[0233] 33. The method according to clause 31 or 32, wherein N1, N2 and N3 are respectively less than the total number of dies in the first wafer region, the second wafer region and the third wafer region.

[0234] 34. The method according to any one of clauses 23 to 33, wherein optimizing the parameterized wafer region definition and the parameterized sampling budget for the wafer region comprises: using constrained global optimization techniques.

[0235] 35. The method according to Clause 34, wherein the constrained global optimization technique is a derivativeless optimization algorithm.

[0236] 36. The method according to any one of clauses 23 to 35, wherein the projection value is generated by optimizing the parameterized wafer region definition and the parameterized sampling budget for the wafer region. 2 Relevance score.

[0237] 37. The method according to any one of clauses 23 to 36 further comprises:

[0238] Generate a sampling plan to guide the wafer inspection of the second wafer;

[0239] The inspection results of the second wafer are used to calculate the projected die loss;

[0240] Obtain the detection test results for the second wafer; and

[0241] Evaluation of R 2 Relevance score.

[0242] 38. The method according to any one of clauses 23 to 37, wherein the inspection tool is a scanning charged particle microscope or an optical tool.

[0243] 39. The method according to any one of Clauses 23 to 38, wherein the calculated defect probability prediction model is a calculated guided inspection model.

[0244] 40. An apparatus for generating a sampling plan for inspection tools, comprising:

[0245] Memory, storing instruction sets; and

[0246] At least one processor is configured to execute the set of instructions to cause the device to perform operations, the operations including:

[0247] Provide wafer-specific input data to the defect probability prediction model;

[0248] The wafer is divided into multiple wafer regions with dies;

[0249] The defect probability of each wafer region is determined based on the defect probability prediction model.

[0250] At least one die is selected from each of the plurality of wafer regions using the determined defect die probability; and

[0251] A sampling plan for the wafer is generated based on the selected die.

[0252] 41. The apparatus according to Clause 40, wherein the input data includes an image containing metrological information of the wafer.

[0253] 42. The apparatus according to clause 40 or 41, wherein the input data includes predetermined wafer region definitions and sampling budgets for each wafer region.

[0254] 43. The apparatus according to clause 42, wherein the determined defect die probability used to select at least one die from each of the plurality of wafer regions further comprises:

[0255] The determined defect die probabilities for each wafer for each wafer region are sorted; and,

[0256] Based on the determined ranking of the defective die probabilities, a number of dies are selected for each of the plurality of wafer regions, wherein the number of dies is less than or equal to the sampling budget for the corresponding wafer region.

[0257] 44. The apparatus according to any one of clauses 40 to 43, wherein said operation further comprises:

[0258] The sampling plan is used to guide the inspection of the wafer;

[0259] The inspection results of the wafer are used to calculate the projected die loss;

[0260] Obtain the detection test results for the wafer; and

[0261] R is evaluated by comparing the detection test results with the projected die loss. 2 Relevance score.

[0262] 45. The apparatus according to Clause 44, wherein the projected die loss is calculated by assuming a non-uniform defect density or distribution in the wafer.

[0263] 46. ​​The apparatus according to any one of clauses 40 to 45, wherein the inspection tool is a scanning charged particle microscope or an optical tool.

[0264] 47. The apparatus according to any one of clauses 40 to 46, wherein the calculated defect probability prediction model is a calculated guided inspection model.

[0265] 48. An apparatus for optimizing an inspection tool sampling plan, comprising:

[0266] Memory, storing instruction sets; and

[0267] At least one processor is configured to execute the set of instructions to cause the device to perform operations, the operations including:

[0268] Provide wafer-specific input data to the computational defect probability prediction model; and

[0269] A sampling budget is allocated for the region of the wafer based on a comparison between the expected number of defective dies for a region of the wafer and the expected number of defective dies for the wafer.

[0270] The expected number of defective dies for the region is the sum of predicted defective die probabilities for the region, and the expected number of defective dies for the wafer is the sum of predicted defective die probabilities for the wafer; and

[0271] The predicted defect die probability for the region and the predicted defect die probability for the wafer are obtained from the defect probability prediction model.

[0272] 49. The apparatus according to Clause 48, wherein the input data includes an image containing metrological information of the wafer.

[0273] 50. The apparatus according to clause 48 or 49, wherein the input data includes a predetermined wafer region definition and a sampling budget for the wafer.

[0274] 51. The apparatus according to any one of clauses 48 to 50, wherein said operation further comprises:

[0275] Generate a sampling plan to guide the wafer inspection of the wafer;

[0276] The inspection results of the wafer are used to calculate the projected die loss;

[0277] Obtain the detection test results for the wafer; and

[0278] R is evaluated by comparing the detection test results with the projected die loss. 2 Relevance score.

[0279] 52. The apparatus according to any one of clauses 48 to 51, wherein the inspection tool is a scanning charged particle microscope or an optical tool.

[0280] 53. The apparatus according to any one of clauses 48 to 52, wherein the calculated defect probability prediction model is a calculated guided inspection model.

[0281] 54. An apparatus for optimizing an inspection tool sampling plan, comprising:

[0282] Memory, storing instruction sets; and

[0283] At least one processor is configured to execute the set of instructions to cause the device to perform operations, the operations including:

[0284] Provide wafer-specific input data to the defect probability prediction model;

[0285] The defect probability for each die of the wafer is determined based on the defect probability prediction model.

[0286] Generate a sampling plan;

[0287] The wafer region is evaluated based on the defect probability for each die of the wafer;

[0288] The sampling budget distribution for each wafer region under evaluation is assessed; and

[0289] The inspection of the wafer is guided by the sampling plan, which includes the evaluated wafer region and the sampling budget distribution.

[0290] 55. The apparatus according to Clause 54, wherein the input data includes an image containing metrological information of the wafer.

[0291] 56. The apparatus according to clause 54 or 55, wherein the input data includes a predetermined sampling budget for the wafer.

[0292] 57. The apparatus according to any one of clauses 54 to 56, wherein the wafer region is evaluated by integrating the calculated probability of defective dies for each die of the wafer with respect to a radial direction on the wafer.

[0293] 58. The apparatus according to any one of clauses 54 to 56, wherein the wafer region is evaluated by image segmentation of the generated defect die probability map of the wafer.

[0294] 59. The apparatus according to any one of clauses 54 to 58, wherein said operation further comprises:

[0295] The inspection results of the wafer are used to calculate the projected die loss;

[0296] Obtain the detection test results for the wafer; and

[0297] R is evaluated by comparing the detection test results with the projected die loss. 2 Relevance score.

[0298] 60. The apparatus according to any one of clauses 54 to 59, wherein the inspection tool is a scanning charged particle microscope or an optical tool.

[0299] 61. The apparatus according to any one of clauses 54 to 60, wherein the calculated defect probability prediction model is a calculated guided inspection model.

[0300] 62. An apparatus for optimizing an inspection tool sampling plan, comprising:

[0301] Memory, storing instruction sets; and

[0302] At least one processor is configured to execute the set of instructions to cause the device to perform operations, the operations including:

[0303] Provide wafer-specific input data to the defect probability prediction model;

[0304] The wafer region is defined and the sampling budget for the wafer region is parameterized, wherein the parameterized wafer region definition and the parameterized sampling budget for the wafer region have specific constraints; and

[0305] The parameterized wafer region definition and the parameterized sampling budget for the wafer region are optimized according to the specific constraints to maximize the projection value.

[0306] 63. The apparatus according to Clause 62, wherein the input data includes the detection test results of the wafer.

[0307] 64. The apparatus according to clause 62 or 63, wherein the input data includes R 2 Relevance score.

[0308] 65. The apparatus according to any one of clauses 62 to 64, wherein the wafer region is parameterized using a first variable and a second variable.

[0309] 66. The apparatus according to Clause 65, wherein the first variable is r1 and the second variable is r2, wherein r1 is the radial distance from the center of the wafer to the boundary of the first wafer region, and wherein r2 is the radial distance from the center of the wafer to the boundary of the second wafer region.

[0310] 67. The apparatus according to clause 66, wherein the constraints on the first variable and the second variable include 0 <r1,r2<r max , where r max The radius of the wafer is given.

[0311] 68. The apparatus according to clause 66 or 67, wherein the constraints on the first variable and the second variable include r1. <r2。

[0312] 69. The apparatus according to any one of clauses 62 to 68, wherein the sampling budget for a wafer region on the wafer is parameterized using a first variable, a second variable, and a third variable.

[0313] 70. The apparatus according to claim 69, wherein the first variable is N1, the second variable is N2, and the third variable is N3, wherein N1 is a sampling budget for a first wafer region, wherein N2 is a sampling budget for a second wafer region, and wherein N3 is a sampling budget for a third wafer region.

[0314] 71. The apparatus according to Clause 70, wherein the constraints on N1, N2, and N3 include N1 + N2 + N3 = N budget , where N budget This is the total sampling budget for the wafer.

[0315] 72. The apparatus according to clause 70 or 71, wherein N1, N2 and N3 are each less than the total number of dies in the first wafer region, the second wafer region and the third wafer region.

[0316] 73. The apparatus according to any one of clauses 62 to 72, wherein optimizing the parameterized wafer region definition and the parameterized sampling budget for the wafer region includes: using constrained global optimization techniques.

[0317] 74. The apparatus according to Clause 73, wherein the constrained global optimization technique is a derivativeless optimization algorithm.

[0318] 75. The apparatus according to any one of clauses 62 to 74, wherein the projection value is generated by optimizing the parameterized wafer region definition and the parameterized sampling budget for the wafer region. 2Relevance score.

[0319] 76. The apparatus according to any one of clauses 62 to 75, wherein said operation further comprises:

[0320] Generate a sampling plan to guide the wafer inspection of the second wafer;

[0321] The inspection results of the second wafer are used to calculate the projected die loss;

[0322] Obtain the detection test results for the second wafer; and

[0323] Evaluation of R 2 Relevance score.

[0324] 77. The apparatus according to any one of clauses 62 to 76, wherein the inspection tool is a scanning charged particle microscope or an optical tool.

[0325] 78. The method according to any one of clauses 62 to 77, wherein the calculated defect probability prediction model is a calculated guided inspection model.

[0326] 79. A non-transitory computer-readable medium comprising a set of instructions executable by one or more processors of a computing device to cause the computing device to perform operations for generating an inspection tool sampling plan, the operations including:

[0327] Provide wafer-specific input data to the defect probability prediction model;

[0328] The wafer is divided into multiple wafer regions with dies;

[0329] The defect probability of each wafer region is determined based on the defect probability prediction model.

[0330] At least one die is selected from each of the plurality of wafer regions using the determined defect die probability; and

[0331] A sampling plan for the wafer is generated based on the selected die.

[0332] 80. The non-transitory computer-readable medium according to Clause 79, wherein the input data includes an image containing metrological information of the wafer.

[0333] 81. The non-transitory computer-readable medium according to Clause 79 or 80, wherein the input data includes predetermined wafer region definitions and sampling budgets for each wafer region.

[0334] 82. The non-transitory computer-readable medium according to Clause 81, wherein selecting at least one die from each of the plurality of wafer regions using the determined defect die probability further comprises:

[0335] The determined defect die probabilities for each die in each wafer region are sorted; and

[0336] Based on the determined ranking of the defective die probabilities, a number of dies are selected for each of the plurality of wafer regions, wherein the number of dies is less than or equal to the sampling budget for the corresponding wafer region.

[0337] 83. The non-transitory computer-readable medium according to any one of clauses 79 to 82, wherein said operation further comprises:

[0338] The sampling plan is used to guide the wafer inspection of the wafer;

[0339] The inspection results of the wafer are used to calculate the projected die loss;

[0340] Obtain the detection test results for the wafer; and

[0341] R is evaluated by comparing the detection test results with the projected die loss. 2 Relevance score.

[0342] 84. The non-transitory computer-readable medium as described in Clause 83, wherein the projected die loss is calculated by assuming a non-uniform defect density or distribution in the wafer.

[0343] 85. A non-transitory computer-readable medium according to any one of Clauses 79 to 82, wherein the inspection tool is a scanning charged particle microscope or an optical tool.

[0344] 86. The non-transitory computer-readable medium according to any one of Clauses 79 to 85, wherein the computational defect probability prediction model is a computational guided inspection model.

[0345] 87. A non-transitory computer-readable medium comprising a set of instructions executable by one or more processors of a computing device to cause the computing device to perform operations for optimizing a sampling plan for an inspection tool, the operations including:

[0346] Provide wafer-specific input data to the computational defect probability prediction model; and

[0347] A sampling budget is allocated for the region based on a comparison between the expected number of defective dies for a region of the wafer and the expected number of defective dies for the wafer.

[0348] The expected number of defective dies for the region is the sum of predicted defective die probabilities for the region, and the expected number of defective dies for the wafer is the sum of predicted defective die probabilities for the wafer; and

[0349] The predicted defect die probability for the region and the predicted defect die probability for the wafer are obtained from the defect probability prediction model.

[0350] 88. The non-transitory computer-readable medium as described in Clause 87, wherein the input data includes an image containing metrological information of the wafer.

[0351] 89. A non-transitory computer-readable medium as described in Clause 87 or 88, wherein the input data includes a predetermined wafer region definition and a sampling budget for the wafer.

[0352] 90. A non-transitory computer-readable medium according to any one of clauses 87 to 89, wherein said operation further comprises:

[0353] Generate a sampling plan to guide the wafer inspection of the wafer;

[0354] The inspection results of the wafer are used to calculate the projected die loss;

[0355] Obtain the detection test results for the wafer; and

[0356] R is evaluated by comparing the detection test results with the projected die loss. 2 Relevance score.

[0357] 91. A non-transitory computer-readable medium according to any one of Clauses 87 to 90, wherein the inspection tool is a scanning charged particle microscope or an optical tool.

[0358] 92. The non-transitory computer-readable medium according to any one of clauses 87 to 91, wherein the computational defect probability prediction model is a computational guided inspection model.

[0359] 93. A non-transitory computer-readable medium comprising a set of instructions executable by one or more processors of a computing device to cause the computing device to perform operations for optimizing a sampling plan for an inspection tool, the operations including:

[0360] Provide wafer-specific input data to the defect probability prediction model;

[0361] The defect probability for each die of the wafer is determined based on the defect probability prediction model.

[0362] Generate a sampling plan;

[0363] The wafer region is evaluated based on the defect probability for each die of the wafer;

[0364] The sampling budget distribution for each wafer region under evaluation is assessed; and

[0365] The inspection of the wafer is guided by the sampling plan, which includes the evaluated wafer region and the evaluated sampling budget distribution.

[0366] 94. The non-transitory computer-readable medium according to Clause 93, wherein the input data includes an image containing metrological information of the wafer.

[0367] 95. A non-transitory computer-readable medium according to clause 93 or 94, wherein the input data includes a predetermined sampling budget for the wafer.

[0368] 96. A nontransitory computer-readable medium according to any one of clauses 93 to 95, wherein the wafer region is evaluated by integrating the calculated probability of a defective die for each die of the wafer with respect to a radial direction on the wafer.

[0369] 97. A nontransitory computer-readable medium according to any one of clauses 93 to 95, wherein the wafer region is evaluated by image segmentation of the generated defect die probability map of the wafer.

[0370] 98. A non-transitory computer-readable medium according to any one of clauses 93 to 97, wherein said operation further comprises:

[0371] The inspection results of the wafer are used to calculate the projected die loss;

[0372] Obtain the detection test results for the wafer; and

[0373] R is evaluated by comparing the detection test results with the projected die loss. 2 Relevance score.

[0374] 99. A non-transitory computer-readable medium according to any one of clauses 93 to 98, wherein the inspection tool is a scanning charged particle microscope or an optical tool.

[0375] 100. A non-transitory computer-readable medium according to any one of clauses 93 to 99, wherein the computational defect probability prediction model is a computational guided inspection model.

[0376] 101. A non-transitory computer-readable medium comprising a set of instructions executable by one or more processors of a computing device to cause the computing device to perform operations for optimizing a sampling plan for an inspection tool, the operations including:

[0377] Provide wafer-specific input data to the defect probability prediction model;

[0378] The wafer region is defined and the sampling budget for the wafer region is parameterized, wherein the parameterized wafer region definition and the parameterized sampling budget for the wafer region have specific constraints; and

[0379] The parameterized wafer region definition and the parameterized sampling budget for the wafer region are optimized according to the specific constraints to maximize the projection value.

[0380] 102. The non-transitory computer-readable medium as described in Clause 101, wherein the input data includes the detection test results of the wafer.

[0381] 103. The non-transitory computer-readable medium according to clause 101 or 102, wherein the input data includes R 2 Relevance score.

[0382] 104. A non-transitory computer-readable medium according to any one of clauses 101 to 103, wherein the wafer region is parameterized using a first variable and a second variable.

[0383] 105. A non-transitory computer-readable medium according to Clause 104, wherein the first variable is r1 and the second variable is r2, wherein r1 is the radial distance from the center of the wafer to the boundary of the first wafer region, and wherein r2 is the radial distance from the center of the wafer to the boundary of the second wafer region.

[0384] 106. The non-transitory computer-readable medium according to Clause 105, wherein the constraints on the first variable and the second variable include 0 <r1,r2<r max , where r max The radius of the wafer is given.

[0385] 107. A non-transitory computer-readable medium according to clause 105 or 106, wherein the constraints with respect to the first variable and the second variable include r1. <r2。

[0386] 108. A non-transitory computer-readable medium according to any one of clauses 101 to 107, wherein the sampling budget for a wafer region on the wafer is parameterized using a first variable, a second variable, and a third variable.

[0387] 109. The non-transitory computer-readable medium according to Clause 108, wherein the first variable is N1, the second variable is N2, and the third variable is N3, wherein N1 is a sampling budget for a first wafer region, wherein N2 is a sampling budget for a second wafer region, and wherein N3 is a sampling budget for a third wafer region.

[0388] 110. A non-transitory computer-readable medium as described in Clause 109, wherein the constraints for N1, N2, and N3 include N1 + N2 + N3 = N budget , where N budget This is the total sampling budget for the wafer.

[0389] 111. The non-transitory computer-readable medium according to clause 109 or 110, wherein N1, N2, and N3 are each less than the total number of dies in the first wafer region, the second wafer region, and the third wafer region.

[0390] 112. The non-transitory computer-readable medium according to any one of clauses 101 to 111, wherein optimizing the parameterized wafer region definition and the parameterized sampling budget for the wafer region includes: using constrained global optimization techniques.

[0391] 113. The non-transitory computer-readable medium as described in Clause 112, wherein the constrained global optimization technique is a derivativeless optimization algorithm.

[0392] 114. A non-transitory computer-readable medium according to any one of clauses 101 to 113, wherein the projection value is generated by optimizing the parameterized wafer region definition and the parameterized sampling budget for the wafer region. 2 Relevance score.

[0393] 115. A non-transitory computer-readable medium according to any one of clauses 101 to 114, wherein said operation further comprises:

[0394] Generate a sampling plan to guide the wafer inspection of the second wafer;

[0395] The inspection results of the second wafer are used to calculate the projected die loss;

[0396] Obtain the detection test results for the second wafer; and

[0397] Evaluation of R 2 Relevance score.

[0398] 116. The non-transitory computer-readable medium according to any one of clauses 101 to 115, wherein the inspection tool is a scanning charged particle microscope or an optical tool.

[0399] 117. A non-transitory computer-readable medium according to any one of clauses 101 to 116, wherein the computational defect probability prediction model is a computational guided inspection model.

[0400] 118. A system for generating a sampling plan for an inspection tool using a computational model, the system comprising:

[0401] One or more processors are configured to execute instructions to cause the system to perform:

[0402] Provide wafer-specific input data to the defect probability prediction model;

[0403] The wafer is divided into multiple wafer regions with dies;

[0404] The defect probability of each wafer region is determined based on the defect probability prediction model.

[0405] At least one die is selected from each of the plurality of wafer regions using the determined defect die probability; and

[0406] A sampling plan for the wafer is generated based on the selected die.

[0407] 119. The method according to any one of clauses 1 to 8, wherein the probability of the defective die of the selected die is higher than a threshold.

[0408] 120. The method according to any one of clauses 1 to 8 or 119, wherein the selected die includes dies of the wafer that are excluded from the static sampling schedule of the wafer.

[0409] 121. The method according to Clause 120, wherein the probability of a defective die of the selected die is less than the probability of a defective die of the dies included in the static sampling plan.

[0410] 122. The method according to any one of clauses 120 to 121, wherein the static sampling schedule of the wafer includes a predetermined region of the wafer.

[0411] 123. The method according to Clause 122, wherein the predetermined region of the wafer is based on historical defect die data of one or more wafers.

[0412] 124. A method for generating a sampling plan for an inspection tool, the method comprising: Generate a static sampling plan to determine the baseline to be used for inspection; Generate a dynamic sampling plan to identify anomalous events; Apply the static sampling plan; and When the predicted defect probability in a region of the sample with a historically low defect probability exceeds a threshold, the dynamic sampling plan is applied by triggering additional sampling. 125. The method according to Clause 124, wherein the static sampling plan is generated based on historical detection data of multiple samples. 126. The method according to Clause 125, wherein the historical detection data includes core defect data of the plurality of samples during inspection. 127. The method according to any one of clauses 125 to 126, wherein generating the static sampling plan comprises: Based on the historical detection data of the multiple samples, a probability estimation mapping is generated by averaging the historical detection data; and The static sampling plan is generated based on the generated probability estimation mapping. 128. The method according to any one of clauses 124 to 127, wherein applying the static sampling plan includes: inspecting the sample in areas corresponding to historically high defect probabilities. 129. The method according to any one of clauses 124 to 128, wherein the dynamic sampling plan is generated based on a trained computational model. 130. The method according to Clause 129, wherein the trained computational model is a computational guided inspection model. 131. The method according to any one of clauses 129 to 130, wherein generating the dynamic sampling plan comprises: The manufacturing data of the sample is fed into the trained computational model; A probability estimate of generating the sample; and The probability estimate is then converted into the dynamic sampling plan. 132. The method according to Clause 131, wherein the manufacturing data includes metrological data corresponding to the manufacture of the sample. 133. The method according to Clause 132, wherein the metrological data includes one or more of the following: necking, line retraction, line thinning, critical dimensions, edge placement, overlap, resist top loss, resist undercut, missing defects, or bridging defects of the integrated circuit structure on the sample. 134. The method according to any one of clauses 124 to 133 further includes: generating a metrological sampling plan or modifying an existing metrological sampling plan to obtain manufacturing data from areas of the sample with historically low defect probabilities. 135. The method according to any one of clauses 124 to 134, further comprising: The sampling plan is used to guide sample inspection; The test results of the sample are used to calculate the projected die loss; Obtain the detection test results for the sample; and R is evaluated by comparing the detection test results with the projected die loss. 2 Relevance score.

[0413] 136. The method according to any one of clauses 124 to 135, wherein the inspection tool of the inspection tool sampling plan is a scanning charged particle microscope or an optical tool.

[0414] 137. A method for defect detection using a computationally guided inspection sampling plan, comprising:

[0415] A baseline sampling plan is generated based on historical inspection data;

[0416] An anomaly sampling plan is generated based on manufacturing data and computational models;

[0417] Apply the baseline sampling plan to the samples; and

[0418] The anomaly sampling plan is applied to the sample when the predicted defect probability in a region of the sample with a historically low defect probability exceeds a threshold.

[0419] 138. A method for generating a sampling plan for an inspection tool, the method comprising:

[0420] Provide wafer-specific input data to the defect probability prediction model;

[0421] The defect die probability for the first region of the wafer is determined according to the defect probability prediction model; and

[0422] A sampling plan for the wafer is generated based on the determined defect die probability for the first region of the wafer and based on a predetermined second region of the wafer.

[0423] 139. The method according to Clause 138, wherein the defective die probability of the first region of the wafer is less than the defective die probability of the second region of the wafer.

[0424] 140. The method according to any one of clauses 138 to 139, wherein the defect die probability of the first region of the wafer is higher than a threshold.

[0425] 141. The method according to any one of Clauses 138 to 140, wherein the second region of the wafer is determined based on historical defect die data of one or more wafers.

[0426] 142. The method according to any one of clauses 138 to 141, wherein the input data includes an image containing metrological information of the wafer.

[0427] 143. The method according to any one of clauses 138 to 142, wherein the input data includes predetermined wafer region definitions and a sampling budget for each region of the wafer.

[0428] 144. The method according to any one of clauses 138 to 143 further comprises:

[0429] The sampling plan is used to guide the wafer inspection;

[0430] The inspection results of the wafer are used to calculate the projected die loss;

[0431] Obtain the detection test results for the wafer; and

[0432] R is evaluated by comparing the detection test results with the projected die loss. 2 Relevance score.

[0433] 145. The method according to Clause 144, wherein the projected die loss is calculated by assuming a non-uniform defect density or distribution in the wafer.

[0434] 146. The method according to Clause 145, wherein the non-uniform defect density or distribution is obtained from a static stacking detection defect probability estimate or from a prediction of the computational defect probability prediction model.

[0435] 147. The method according to any one of clauses 138 to 146, wherein the inspection tool is a scanning charged particle microscope or an optical tool.

[0436] 148. The method according to any one of clauses 138 to 147, wherein the calculated defect probability prediction model is a calculated guided inspection model.

[0437] 149. The apparatus according to any one of clauses 40-47, wherein the probability of the defective die of the selected die is higher than a threshold.

[0438] 150. The apparatus according to any one of clauses 40-47 or 149, wherein the selected die includes dies of the wafer excluded from the static sampling schedule of the wafer.

[0439] 151. The apparatus according to Clause 150, wherein the probability of a defective die of the selected die is less than the probability of a defective die of the dies included in the static sampling scheme.

[0440] 152. The apparatus according to any one of clauses 150 to 151, wherein the static sampling schedule of the wafer includes a predetermined region of the wafer.

[0441] 153. The apparatus according to Clause 152, wherein the predetermined region of the wafer is based on historical defect die data of one or more wafers.

[0442] 154. A non-transitory computer-readable medium according to any one of clauses 79 to 86, wherein the probability of the defective die of the selected die is higher than a threshold.

[0443] 155. A non-transitory computer-readable medium according to any one of clauses 79 to 86 or 154, wherein the selected die includes dies of the wafer excluded from the static sampling schedule of the wafer.

[0444] 156. The non-transitory computer-readable medium according to Clause 155, wherein the probability of a defective die of the selected die is less than the probability of a defective die of the dies included in the static sampling scheme.

[0445] 157. A non-transitory computer-readable medium according to any one of clauses 155 to 156, wherein the static sampling scheme of the wafer includes a predetermined region of the wafer.

[0446] 158. The non-transitory computer-readable medium as described in Clause 157, wherein the predetermined region of the wafer is based on historical defect die data of one or more wafers.

[0447] 159. The method according to Clause 137, wherein the baseline sampling plan is generated based on historical detection data of multiple samples.

[0448] 160. The method according to Clause 159, wherein the historical detection data includes core defect data of the plurality of samples during inspection.

[0449] 161. The method according to any one of clauses 159 to 160, wherein generating the baseline sampling plan comprises: Based on the historical detection data of the multiple samples, a probability estimation mapping is generated by averaging the historical detection data; and

[0450] The baseline sampling plan is generated based on the generated probability estimation map.

[0451] 162. The method according to any one of Clauses 137 or 159 to 161, wherein applying the baseline sampling plan includes: inspecting the sample in areas corresponding to historically high defect probabilities.

[0452] 163. The method according to any one of Clauses 137 or 159 to 162, wherein the generation of the anomaly sampling plan is based on a trained computational model.

[0453] 164. The method according to Clause 163, wherein the trained computational model is a computational guided inspection model.

[0454] 165. The method according to any one of clauses 163 to 164, wherein generating the anomaly sampling plan comprises:

[0455] The manufacturing data of the sample is fed into the trained computational model;

[0456] A probability estimate of generating the sample; and

[0457] The probability estimate is converted into the anomalous event sampling plan.

[0458] 166. The method according to Clause 165, wherein the manufacturing data includes metrological data corresponding to the manufacture of the sample.

[0459] 167. The method according to Clause 166, wherein the metrological data includes one or more of the following: necking, line retraction, line thinning, critical dimensions, edge placement, overlap, resist top loss, resist undercut, missing defects, or bridging defects of the integrated circuit structure on the sample.

[0460] 168. The method according to any one of Clauses 137 or 159 to 167 further includes: generating a metrological sampling plan or modifying an existing metrological sampling plan to obtain manufacturing data from areas of the sample with historically low defect probabilities.

[0461] 169. The method according to any one of clauses 137 or 159 to 168, further comprising:

[0462] The sampling plan is used to guide the sampling and inspection of samples;

[0463] The test results of the sample are used to calculate the projected die loss;

[0464] Obtain the detection test results for the sample; and

[0465] R is evaluated by comparing the detection test results with the projected die loss. 2 Relevance score.

[0466] 170. The method according to any one of Clauses 137 or 159 to 169, wherein the inspection tool of the inspection tool sampling plan is a scanning charged particle microscope or an optical tool.

[0467] 171. An apparatus for generating an inspection tool sampling plan, the apparatus comprising:

[0468] Memory, storing instruction sets; and

[0469] At least one processor is configured to execute the set of instructions to cause the device to perform operations, the operations including: Generate a static sampling plan to determine the baseline to be used for inspection; Generate a dynamic sampling plan to identify anomalous events; Apply the static sampling plan; and When the predicted defect probability in a region of the sample with a historically low defect probability exceeds a threshold, the dynamic sampling plan is applied by triggering additional sampling. 172. The apparatus according to Clause 171, wherein the static sampling plan is generated based on historical detection data of multiple samples. 173. The apparatus according to Clause 172, wherein the historical detection data includes core defect data of the plurality of samples during inspection. 174. The apparatus according to any one of clauses 172 to 173, wherein generating the static sampling plan comprises: Based on the historical detection data of the multiple samples, a probability estimation mapping is generated by averaging the historical detection data; and The static sampling plan is generated based on the generated probability estimation mapping. 175. The apparatus according to any one of clauses 171 to 174, wherein applying the static sampling plan includes: inspecting the sample in areas corresponding to historically high defect probabilities. 176. The apparatus according to any one of clauses 171 to 175, wherein the dynamic sampling plan is generated based on a trained computational model. 177. The apparatus according to Clause 176, wherein the trained computational model is a computational guided inspection model. 178. The apparatus according to any one of clauses 176 to 177, wherein generating the dynamic sampling plan comprises: The manufacturing data of the sample is fed into the trained computational model; A probability estimate of generating the sample; and The probability estimate is then converted into the dynamic sampling plan. 179. The apparatus according to Clause 178, wherein the manufacturing data includes metrological data corresponding to the manufacture of the sample. 180. The apparatus according to Clause 179, wherein the metrological data includes one or more of the following: necking, line retraction, line thinning, critical dimensions, edge placement, overlap, resist top loss, resist undercut, missing defects, or bridging defects of the integrated circuit structure on the sample. 181. The apparatus according to any one of clauses 171 to 180 further includes: generating a metrological sampling plan or modifying an existing metrological sampling plan to obtain manufacturing data from regions of the sample that have historically low defect probabilities. 182. The apparatus according to any one of clauses 171 to 181, further comprising: The sampling plan is used to guide sample inspection; The test results of the sample are used to calculate the projected die loss; Obtain the detection test results for the sample; and R is evaluated by comparing the detection test results with the projected die loss. 2 Relevance score.

[0470] 183. The apparatus according to any one of clauses 171 to 182, wherein the inspection tool of the inspection tool sampling plan is a scanning charged particle microscope or an optical tool.

[0471] 184. An apparatus for defect detection using a computationally guided inspection sampling plan, comprising:

[0472] Memory, storing instruction sets; and

[0473] At least one processor is configured to execute the set of instructions to cause the device to perform operations, the operations including:

[0474] A baseline sampling plan is generated based on historical inspection data;

[0475] An anomaly sampling plan is generated based on manufacturing data and computational models;

[0476] Apply the baseline sampling plan to the samples; and

[0477] The anomaly sampling plan is applied to the sample when the predicted defect probability in a region of the sample with a historically low defect probability exceeds a threshold. 185. The apparatus according to Clause 184, wherein the baseline sampling plan is generated based on historical detection data of multiple samples. 186. The apparatus according to Clause 185, wherein the historical detection data includes core defect data of the plurality of samples during inspection. 187. The apparatus according to any one of clauses 185 to 186, wherein generating the baseline sampling plan comprises: Based on the historical detection data of the multiple samples, a probability estimation mapping is generated by averaging the historical detection data; and The baseline sampling plan is generated based on the generated probability estimation map. 188. The apparatus according to any one of clauses 184 to 187, wherein applying the baseline sampling plan includes: inspecting the sample in areas corresponding to historically high defect probabilities. 189. The apparatus according to any one of clauses 184 to 188, wherein the generation of the anomaly sampling plan is based on a trained computational model. 190. The apparatus according to Clause 189, wherein the trained computational model is a computational guided inspection model. 191. The apparatus according to any one of clauses 189 to 190, wherein generating the anomalous event sampling plan comprises: The manufacturing data of the sample is fed into the trained computational model; A probability estimate of generating the sample; and The probability estimate is converted into the anomalous event sampling plan. 192. The apparatus according to Clause 191, wherein the manufacturing data includes metrological data corresponding to the manufacture of the sample. 193. The apparatus according to Clause 192, wherein the metrological data includes one or more of the following: necking, line retraction, line thinning, critical dimensions, edge placement, overlap, resist top loss, resist undercut, missing defects, or bridging defects of the integrated circuit structure on the sample. 194. The apparatus according to any one of clauses 184 to 193 further includes: generating a metrological sampling plan or modifying an existing metrological sampling plan to obtain manufacturing data from regions of the sample that have historically low defect probabilities. 195. The apparatus according to any one of clauses 184 to 194, further comprising: The sampling plan is used to guide sample inspection; The test results of the sample are used to calculate the projected die loss; Obtain the detection test results for the sample; and R is evaluated by comparing the detection test results with the projected die loss. 2 Relevance score.

[0478] 196. The apparatus according to any one of clauses 184 to 195, wherein the inspection tool of the inspection tool sampling plan is a scanning charged particle microscope or an optical tool.

[0479] 197. An apparatus for generating an inspection tool sampling plan, the apparatus comprising:

[0480] Memory, storing instruction sets; and

[0481] At least one processor is configured to execute the set of instructions to cause the device to perform operations, the operations including:

[0482] Provide wafer-specific input data to the defect probability prediction model;

[0483] The defect die probability for the first region of the wafer is determined according to the defect probability prediction model; and

[0484] A sampling plan for the wafer is generated based on the determined defect die probability for the first region of the wafer and based on a predetermined second region of the wafer.

[0485] 198. The apparatus according to Clause 197, wherein the defective die probability of the first region of the wafer is less than the defective die probability of the second region of the wafer.

[0486] 199. The apparatus according to any one of clauses 197 to 198, wherein the probability of the defective die in the first region of the wafer is higher than a threshold.

[0487] 200. The apparatus according to any one of clauses 197 to 199, wherein the second region of the wafer is determined based on historical defect die data of one or more wafers.

[0488] 201. The apparatus according to any one of clauses 197 to 200, wherein the input data includes an image containing metrological information of the wafer.

[0489] 202. The apparatus according to any one of clauses 197 to 201, wherein the input data includes predetermined wafer region definitions and a sampling budget for each region of the wafer.

[0490] 203. The apparatus according to any one of clauses 197 to 202, further comprising:

[0491] The sampling plan is used to guide the wafer inspection;

[0492] The inspection results of the wafer are used to calculate the projected die loss;

[0493] Obtain the detection test results for the wafer; and

[0494] R is evaluated by comparing the detection test results with the projected die loss. 2 Relevance score.

[0495] 204. The apparatus according to clause 203, wherein the projected die loss is calculated by assuming a non-uniform defect density or distribution in the wafer.

[0496] 205. The apparatus according to clause 204, wherein the non-uniform defect density or distribution is obtained from a static stacking detection defect probability estimate or from a prediction of the computational defect probability prediction model.

[0497] 206. The apparatus according to any one of clauses 197 to 205, wherein the inspection tool is a scanning charged particle microscope or an optical tool.

[0498] 207. The apparatus according to any one of clauses 197 to 206, wherein the calculated defect probability prediction model is a calculated guided inspection model.

[0499] 208. A non-transitory computer-readable medium comprising a set of instructions executable by one or more processors of a computing device to cause the computing device to perform operations for generating an inspection tool sampling plan, the operations including: Generate a static sampling plan to determine the baseline to be used for inspection; Generate a dynamic sampling plan to identify anomalous events; Apply the static sampling plan; and When the predicted defect probability in a region of the sample with a historically low defect probability exceeds a threshold, the dynamic sampling plan is applied by triggering additional sampling. 209. The non-transitory computer-readable medium as described in Clause 208, wherein the static sampling plan is generated based on historical detection data of multiple samples. 210. The non-transitory computer-readable medium as described in Clause 209, wherein the historical detection data includes die defect data of the plurality of samples during inspection. 211. A non-transitory computer-readable medium according to any one of clauses 209 to 210, wherein generating the static sampling plan comprises: Based on the historical detection data of the multiple samples, a probability estimation mapping is generated by averaging the historical detection data; and The static sampling plan is generated based on the generated probability estimation mapping. 212. A non-transitory computer-readable medium according to any one of clauses 208 to 211, wherein applying the static sampling plan includes: inspecting the sample in areas corresponding to historically high defect probabilities. 213. A non-transitory computer-readable medium according to any one of clauses 208 to 212, wherein the dynamic sampling plan is generated based on a trained computational model. 214. The non-transitory computer-readable medium as described in Clause 213, wherein the trained computational model is a computational guidance check model. 215. A non-transitory computer-readable medium according to any one of clauses 213 to 214, wherein generating the dynamic sampling plan comprises: The manufacturing data of the sample is fed into the trained computational model; A probability estimate of generating the sample; and The probability estimate is then converted into the dynamic sampling plan. 216. The non-transitory computer-readable medium as described in Clause 215, wherein the manufacturing data includes metrological data corresponding to the manufacture of the sample. 217. The non-transitory computer-readable medium as described in Clause 216, wherein the metrological data includes one or more of the following: necking, line retraction, line thinning, critical dimensions, edge placement, overlap, resist top loss, resist undercut, missing defects, or bridging defects of an integrated circuit structure on the sample. 218. A nontransitory computer-readable medium according to any one of clauses 208 to 217, wherein the set of instructions is executable by one or more processors of a computing device to cause the computing device to further perform: generating a metrological sampling plan or modifying an existing metrological sampling plan to obtain manufacturing data from regions of a sample having a historically low probability of defects. 219. A non-transitory computer-readable medium according to any one of clauses 208 to 218, wherein the set of instructions is executable by one or more processors of a computing device to cause the computing device to further perform: The sampling plan is used to guide sample inspection; The test results of the sample are used to calculate the projected die loss; Obtain the detection test results for the sample; and R is evaluated by comparing the detection test results with the projected die loss. 2 Relevance score.

[0500] 220. The non-transitory computer-readable medium according to any one of clauses 208 to 219, wherein the inspection tool of the inspection tool sampling plan is a scanning charged particle microscope or an optical tool.

[0501] 221. A non-transitory computer-readable medium comprising a set of instructions executable by one or more processors of a computing device to cause the computing device to perform operations for defect detection using a computationally guided inspection sampling plan, the operations comprising:

[0502] A baseline sampling plan is generated based on historical inspection data;

[0503] An anomaly sampling plan is generated based on manufacturing data and computational models;

[0504] Apply the baseline sampling plan to the samples; and

[0505] The anomaly sampling plan is applied to the sample when the predicted defect probability in a region of the sample with a historically low defect probability exceeds a threshold. 222. The non-transitory computer-readable medium as described in Clause 221, wherein the baseline sampling plan is generated based on historical probe data from multiple samples. 223. The non-transitory computer-readable medium as described in Clause 222, wherein the historical detection data includes die defect data of the plurality of samples during inspection. 224. A non-transitory computer-readable medium according to any one of clauses 222 to 223, wherein generating the baseline sampling plan comprises: Based on the historical detection data of the multiple samples, a probability estimation mapping is generated by averaging the historical detection data; and The baseline sampling plan is generated based on the generated probability estimation map. 225. A non-transitory computer-readable medium according to any one of clauses 221 to 224, wherein applying the baseline sampling scheme includes: inspecting the sample in areas corresponding to historically high defect probabilities. 226. A non-transitory computer-readable medium according to any one of clauses 221 to 225, wherein the generation of the anomaly sampling plan is based on a trained computational model. 227. The non-transitory computer-readable medium as described in Clause 226, wherein the trained computational model is a computational guidance check model. 228. A non-transitory computer-readable medium according to any one of clauses 226 to 227, wherein generating the anomaly sampling plan comprises: The manufacturing data of the sample is fed into the trained computational model; A probability estimate of generating the sample; and The probability estimate is converted into the anomalous event sampling plan. 229. The non-transitory computer-readable medium as described in Clause 228, wherein the manufacturing data includes metrological data corresponding to the manufacture of the sample. 230. The non-transitory computer-readable medium as described in Clause 229, wherein the metrological data includes one or more of the following: necking, line retraction, line thinning, critical dimensions, edge placement, overlap, resist top loss, resist undercut, missing defects, or bridging defects of an integrated circuit structure on the sample. 231. A nontransitory computer-readable medium according to any one of clauses 221 to 230, wherein the set of instructions is executable by one or more processors of a computing device to cause the computing device to further perform: generating a metrological sampling plan or modifying an existing metrological sampling plan to obtain manufacturing data from regions of a sample having a historically low probability of defects. 232. A non-transitory computer-readable medium according to any one of clauses 221 to 231, wherein the set of instructions is executable by one or more processors of a computing device to cause the computing device to further perform: The sampling plan is used to guide sample inspection; The test results of the sample are used to calculate the projected die loss; Obtain the detection test results for the sample; and R is evaluated by comparing the detection test results with the projected die loss. 2 Relevance score.

[0506] 233. The non-transitory computer-readable medium according to any one of clauses 221 to 232, wherein the inspection tool of the inspection tool sampling plan is a scanning charged particle microscope or an optical tool.

[0507] 234. A non-transitory computer-readable medium comprising a set of instructions executable by one or more processors of a computing device to cause the computing device to perform operations for generating an inspection tool sampling plan, the operations including:

[0508] Provide wafer-specific input data to the defect probability prediction model;

[0509] The defect die probability for the first region of the wafer is determined according to the defect probability prediction model; and

[0510] A sampling plan for the wafer is generated based on the determined defect die probability for the first region of the wafer and based on a predetermined second region of the wafer.

[0511] 235. The non-transitory computer-readable medium according to Clause 234, wherein the probability of a defective die in the first region of the wafer is less than the probability of a defective die in the second region of the wafer.

[0512] 236. A non-transitory computer-readable medium according to any one of clauses 234 to 235, wherein the probability of the defective die in the first region of the wafer is higher than a threshold.

[0513] 237. A non-transitory computer-readable medium according to any one of clauses 234 to 236, wherein the second region of the wafer is determined based on historical defect die data of one or more wafers.

[0514] 238. A non-transitory computer-readable medium according to any one of clauses 234 to 237, wherein the input data includes an image containing metrological information of the wafer.

[0515] 239. A non-transitory computer-readable medium according to any one of clauses 234 to 238, wherein the input data includes predetermined wafer region definitions and a sampling budget for each region of the wafer.

[0516] 240. A non-transitory computer-readable medium according to any one of clauses 234 to 239, wherein the set of instructions is executable by one or more processors of a computing device to cause the computing device to further perform:

[0517] The sampling plan is used to guide the wafer inspection;

[0518] The inspection results of the wafer are used to calculate the projected die loss;

[0519] Obtain the detection test results for the wafer; and

[0520] R is evaluated by comparing the detection test results with the projected die loss. 2 Relevance score.

[0521] 241. The non-transitory computer-readable medium according to Clause 240, wherein the projected die loss is calculated by assuming a non-uniform defect density or distribution in the wafer.

[0522] 242. The non-transitory computer-readable medium according to Clause 241, wherein the non-uniform defect density or distribution is obtained from a static stacking defect probability estimate or from a prediction of the computational defect probability prediction model.

[0523] 243. The non-transitory computer-readable medium according to any one of clauses 234 to 242, wherein the inspection tool is a scanning charged particle microscope or an optical tool.

[0524] 244. The non-transitory computer-readable medium according to any one of clauses 234 to 243, wherein the computational defect probability prediction model is a computational guided inspection model.

[0525] 245. The method according to any one of Clauses 1 to 8 or 119 to 123, further comprising: adjusting manufacturing process parameters based on the determined defect die probability to mitigate defect-prone areas of the wafer.

[0526] 246. The method according to any one of Clause 245, wherein the manufacturing process parameters include any one or more parameters of the scanner formulation or the etcher formulation.

[0527] 247. The apparatus according to any one of clauses 40 to 47 or 149 to 53, wherein the set of instructions is executable by at least one processor such that the apparatus further performs: adjusting manufacturing process parameters based on the determined defect die probability to mitigate defect-prone areas of the wafer.

[0528] 248. The apparatus according to Clause 247, wherein the manufacturing process parameters include any or more parameters of the scanner formulation or the etcher formulation.

[0529] 249. A nontransitory computer-readable medium according to any one of clauses 79 to 86 or 154 to 158, wherein the set of instructions is executable by one or more processors of a computing device to cause the computing device to further perform: adjusting manufacturing process parameters based on the determined probability of the defective die to mitigate defective areas of the wafer.

[0530] 250. The non-transitory computer-readable medium according to Clause 249, wherein the manufacturing process parameters include any or more parameters of a scanner formulation or an etcher formulation.

[0531] 251. The method according to any one of clauses 124 to 136 further comprises: adjusting manufacturing process parameters based on the predicted defect probability to mitigate defect-prone areas of the sample.

[0532] 252. The method according to Clause 251, wherein the manufacturing process parameters include any or more parameters of the scanner formulation or the etcher formulation.

[0533] 253. The method according to any one of clauses 137 or 159 to 170 further comprises: adjusting manufacturing process parameters based on the predicted defect probability to mitigate defect-prone areas of the sample.

[0534] 254. The method according to Clause 253, wherein the manufacturing process parameters include any or more parameters of the scanner formulation or the etcher formulation.

[0535] 255. The method according to any one of clauses 138 to 148 further comprises: adjusting manufacturing process parameters based on the determined defect probability to mitigate defect-prone areas of the sample.

[0536] 256. The method according to Clause 253, wherein the manufacturing process parameters include any or more parameters of the scanner formulation or the etcher formulation.

[0537] 257. The apparatus according to any one of clauses 171 to 183 further comprises: adjusting manufacturing process parameters based on the predicted defect probability to mitigate defect-prone areas of the sample.

[0538] 258. The apparatus according to Clause 257, wherein the manufacturing process parameters include any or more parameters of the scanner formulation or the etcher formulation.

[0539] 259. The apparatus according to any one of clauses 184 to 196 further comprises: adjusting manufacturing process parameters based on the predicted defect probability to mitigate defect-prone areas of the sample.

[0540] 260. The apparatus according to Clause 259, wherein the manufacturing process parameters include any or more parameters of the scanner formulation or the etcher formulation.

[0541] 261. The apparatus according to any one of clauses 197 to 207, further comprising: adjusting manufacturing process parameters based on the determined defect probability to mitigate defect-prone areas of the sample.

[0542] 262. The apparatus according to Clause 261, wherein the manufacturing process parameters include any or more parameters of the scanner formulation or the etcher formulation.

[0543] 263. A nontransitory computer-readable medium according to any one of Clauses 208 to 220, wherein the set of instructions is executable by one or more processors of a computing device to cause the computing device to further perform: adjusting manufacturing process parameters based on the predicted defect probability to mitigate defect-prone areas of the wafer.

[0544] 264. The non-transitory computer-readable medium as described in Clause 263, wherein the manufacturing process parameters include any or more parameters of a scanner formulation or an etcher formulation.

[0545] 265. A nontransitory computer-readable medium according to any one of clauses 221 to 233, wherein the set of instructions is executable by one or more processors of a computing device to cause the computing device to further perform: adjusting manufacturing process parameters based on the predicted defect probability to mitigate defect-prone areas of the wafer.

[0546] 266. The non-transitory computer-readable medium as described in Clause 265, wherein the manufacturing process parameters include any or more parameters of a scanner formulation or an etcher formulation.

[0547] 267. A nontransitory computer-readable medium according to any one of clauses 234 to 244, wherein the set of instructions is executable by one or more processors of a computing device to cause the computing device to further perform: adjusting manufacturing process parameters based on the determined probability of the defective die to mitigate defect-prone areas of the wafer.

[0548] 268. The non-transitory computer-readable medium as described in Clause 267, wherein the manufacturing process parameters include any or more parameters of a scanner formulation or an etcher formulation.

[0549] 269. The method according to any one of clauses 124 to 136, 251 or 252, wherein the static sampling schedule is generated based on the sampling budget ratio of the wafer.

[0550] 270. The method according to Clause 269, wherein the sampling budget ratio of the wafer includes the allocation of dies to be sampled by the static sampling plan and the allocation of dies to be sampled by the dynamic sampling plan.

[0551] 271. The method according to any one of clauses 124 to 136, 251, 252, 269 or 270, wherein generating the static sampling plan includes: selecting a fixed die location of the wafer to be inspected.

[0552] 272. The method according to any one of clauses 124 to 136, 251, 252 or 269 to 271, wherein generating the static sampling plan comprises: generating a stacked probe wafer mapping map.

[0553] 273. The method according to Clause 272, wherein the stacked probe wafer map includes multiple defect probability results corresponding to dies on the wafer.

[0554] 274. The method according to Clause 273, wherein the plurality of defect probability results indicate the probability that the die contains a defect.

[0555] 275. The method according to any one of clauses 272 to 274, wherein generating the stacked probe wafer map comprises: averaging historical defect data of a plurality of wafers.

[0556] 276. The method according to any one of clauses 124 to 136, 251, 252 or 269 to 271, wherein generating the static sampling plan comprises: generating a stacked sampling wafer mapping map.

[0557] 277. The method according to Clause 276, wherein the stacked sampled wafer map includes multiple defect probability results corresponding to dies on the wafer.

[0558] 278. The method according to Clause 277, wherein the plurality of sampling probability results indicate the probability of whether the die will be sampled.

[0559] 279. The method according to any one of clauses 276 to 278, wherein generating the stacked sampled wafer map comprises: averaging historical sampled data from a plurality of wafers.

[0560] 280. The method according to any one of Clauses 135 to 136, wherein the predicted die loss is calculated based on the predicted defect probability of the static sampling plan, the predicted defect probability of the dynamic sampling plan, the sampling rate of the static sampling plan, and the sampling rate of the dynamic sampling plan.

[0561] 281. The method according to any one of clauses 137, 159 to 170, 253 or 254, wherein the baseline sampling schedule is generated based on the sampling budget ratio of the wafer.

[0562] 282. The method according to Clause 281, wherein the sampling budget ratio of the wafer includes the allocation of dies to be sampled via the baseline sampling plan and the allocation of dies to be sampled via the anomaly sampling plan.

[0563] 283. The method according to any one of clauses 137, 159 to 170, 253, 254, 281 or 282, wherein generating the baseline sampling plan includes: selecting a fixed die location of the wafer to be inspected.

[0564] 284. The method according to any one of clauses 137, 159 to 170, 253, 254 or 281 to 283, wherein generating the baseline sampling plan comprises: generating a stacked probe wafer mapping map.

[0565] 285. The method according to Clause 284, wherein the stacked probe wafer map includes multiple defect probability results corresponding to dies on the wafer.

[0566] 286. The method according to Clause 285, wherein the plurality of defect probability results indicate the probability that the die contains a defect.

[0567] 287. The method according to any one of clauses 284 to 286, wherein generating the stacked probe wafer map comprises: averaging historical defect data of a plurality of wafers.

[0568] 288. The method according to any one of clauses 137, 159 to 170, 253, 254 or 281 to 283, wherein generating the baseline sampling plan comprises: generating a stacked sampling wafer map.

[0569] 289. The method according to Clause 288, wherein the stacked sampled wafer map includes multiple defect probability results corresponding to dies on the wafer.

[0570] 290. The method according to Clause 289, wherein the plurality of sampling probability results indicate the probability of whether the die will be sampled.

[0571] 291. The method according to any one of clauses 288 to 290, wherein generating the stacked sampled wafer map comprises: averaging historical sampled data of a plurality of wafers.

[0572] 292. The method according to any one of Clauses 169 to 170, wherein the predicted die loss is calculated based on the predicted defect probability of the baseline sampling plan, the predicted defect probability of the dynamic sampling plan, the sampling rate of the baseline sampling plan, and the sampling rate of the dynamic sampling plan.

[0573] 293. A system for generating sampling plans for inspection tools, comprising:

[0574] Memory, storing instruction sets; and

[0575] One or more processors are configured to execute the set of instructions to cause the system to perform any one of clauses 269 to 279.

[0576] 294. A system for defect detection using a computationally guided inspection sampling plan, comprising:

[0577] Memory, storing instruction sets; and

[0578] One or more processors are configured to execute the set of instructions to cause the system to perform any one of the provisions 280 to 292.

[0579] 295. A non-transitory computer-readable medium storing a set of instructions executable by at least one processor of a computing device to cause the computing device to perform a method for generating an inspection tool sampling plan according to any one of clauses 269 to 279.

[0580] 296. A non-transitory computer-readable medium storing a set of instructions executable by at least one processor of a computing device to cause the computing device to perform a method for defect detection using a computationally guided inspection sampling plan, as described in any one of claims 280 to 292.

[0581] The block diagrams shown illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer hardware or software products according to various exemplary embodiments of this disclosure. In this regard, each block in the diagram may represent some arithmetic or logical operation, which can be implemented using hardware such as electronic circuits. A block may also represent a module, segment, or code portion including one or more executable instructions for implementing a specified logical function. It should be understood that in some alternative implementations, the functions indicated in the blocks may not occur in the order shown in the diagram. For example, two blocks shown consecutively may be executed or implemented substantially concurrently, or the two blocks may sometimes be executed in reverse order, depending on the functions involved. Some blocks may also be omitted. It should also be understood that each block and combination of blocks in the block diagram may be implemented by a system based on dedicated hardware that performs the specified function or action, or by a combination of dedicated hardware and computer instructions.

[0582] It should be understood that the embodiments of this disclosure are not limited to the specific structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from the scope of this disclosure. This disclosure has been described in conjunction with various embodiments, and other embodiments will be apparent to those skilled in the art upon consideration of practice of the techniques disclosed herein. This specification and the embodiments are intended to be illustrative only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A non-transitory computer-readable medium storing a set of instructions executable by at least one processor of a computing device to cause the computing device to perform operations for generating an inspection tool sampling plan, the operations including: Generate a static sampling plan to determine the baseline to be used for inspection; Generate a dynamic sampling plan to identify anomalous events; Apply the static sampling plan; as well as When the predicted defect probability in a region of the sample with a historically low defect probability exceeds a threshold, the dynamic sampling plan is applied by triggering additional sampling.

2. The non-transitory computer-readable medium of claim 1, wherein the static sampling plan is generated based on historical detection data of multiple samples.

3. The non-transitory computer-readable medium according to claim 2, wherein the historical detection data includes die defect data of the plurality of samples during inspection.

4. The non-transitory computer-readable medium of claim 2, wherein generating the static sampling plan comprises: Based on the historical detection data of the multiple samples, a probability estimation mapping is generated by averaging the historical detection data. as well as The static sampling plan is generated based on the generated probability estimation mapping.

5. The non-transitory computer-readable medium of claim 1, wherein applying the static sampling scheme comprises: The sample was examined in areas that corresponded to historically high defect probabilities.

6. The non-transitory computer-readable medium of claim 1, wherein the dynamic sampling plan is generated based on a trained computational model.

7. The non-transitory computer-readable medium of claim 6, wherein the trained computational model is a computational guidance check model.

8. The non-transitory computer-readable medium of claim 6, wherein generating the dynamic sampling plan comprises: The manufacturing data of the sample is fed into the trained computational model; A probability estimate of generating the sample; as well as The probability estimate is then converted into the dynamic sampling plan.

9. The non-transitory computer-readable medium of claim 8, wherein the manufacturing data includes metrological data corresponding to the manufacture of the sample.

10. The non-transitory computer-readable medium of claim 9, wherein the metrological data includes one or more of the following: necking, line retraction, line thinning, critical dimensions, edge placement, overlap, resist top loss, resist undercut, missing defects, or bridging defects of the integrated circuit structure on the sample.

11. The non-transitory computer-readable medium of claim 1, wherein the operation further comprises: Generate a metrological sampling plan or modify an existing metrological sampling plan to obtain manufacturing data from areas of the sample that have historically low defect probabilities.

12. The non-transitory computer-readable medium of claim 1, wherein the operation further comprises: The sampling plan is used to guide sample inspection; The test results of the sample are used to calculate the projected die loss; Obtain the detection test results for the sample; as well as R is evaluated by comparing the detection test results with the projected die loss. 2 Relevance score.

13. The non-transitory computer-readable medium of claim 1, wherein the inspection tool of the inspection tool sampling plan is a scanning charged particle microscope or an optical tool.

14. A system for generating a sampling plan for an inspection tool, the system comprising: A memory, wherein the memory stores a set of instructions; as well as One or more processors, the one or more processors being configured to execute the instruction set to cause the system to perform operations, the operations including: Generate a static sampling plan to determine the baseline to be used for inspection; Generate a dynamic sampling plan to identify anomalous events; Apply the static sampling plan; and When the predicted defect probability in a region of the sample with a historically low defect probability exceeds a threshold, the dynamic sampling plan is applied by triggering additional sampling.

15. A method for generating a sampling plan for an inspection tool, the method comprising: Generate a static sampling plan to determine the baseline to be used for inspection; Generate a dynamic sampling plan to identify anomalous events; Apply the static sampling plan; as well as When the predicted defect probability in a region of the sample with a historically low defect probability exceeds a threshold, the dynamic sampling plan is applied by triggering additional sampling.

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