Molding compound layer in semiconductor package

Abstract

Various embodiments of an integrated circuit (IC) die package are disclosed. The IC die package includes an IC die, an interposer structure electrically connected to the IC die, a first bonding structure, a second bonding structure, and a molding compound layer. The first bonding structure includes a first dielectric layer disposed on the IC die and a first conductive plug disposed in the first dielectric layer. The second bonding structure includes a second dielectric layer disposed on the interposer structure and a second conductive plug disposed in the second dielectric layer. The molding compound layer includes a molding region and a molding cavity.

Description

Cross-references to related applications

[0001] This disclosure claims priority to U.S. Patent Application No. 18 / 348,934, filed July 7, 2023, entitled “Molding Compound Layers in Semiconductor Packages,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor packaging, and more specifically to molding compound layers in integrated circuit (IC) die packaging. Background Technology

[0003] IC die packaging may include two or more IC dies (e.g., system-on-a-chip (SOC), logic die, and / or memory die) mounted on a package substrate. Power and signal connections between IC dies are made through wiring layers. Two or more IC dies may be bonded to the wiring layers using a hybrid bonding structure and may be encapsulated in a molding compound layer. The molding compound layer provides mechanical rigidity and environmental protection to the two or more IC dies against moisture and handling damage. Summary of the Invention

[0004] Various embodiments of a molding compound layer having a cavity in an IC die package are disclosed. In some embodiments, a structure includes an IC die, an interposer structure electrically connected to the IC die, a first bonding structure, a second bonding structure, and a molding compound layer. The first bonding structure includes a first dielectric layer disposed on the IC die and a first conductive plug disposed in the first dielectric layer. The second bonding structure includes a second dielectric layer disposed on the interposer structure and a second conductive plug disposed in the second dielectric layer. The molding compound layer includes a molding region and a cavity.

[0005] In some embodiments, an IC die package includes: a wiring layer; a first IC die and a second IC die disposed on the wiring layer; a first bonding structure and a second bonding structure disposed on the first IC die and the second IC die, respectively; a third bonding structure bonded to the first bonding structure and the second bonding structure and disposed on the wiring layer; and an encapsulation layer configured to surround the first IC die and the second IC die. The wiring layer includes conductors and vias. The encapsulation layer includes a molded region and a recessed opening located within the molded region.

[0006] In some embodiments, a method for manufacturing an IC die package having a molding compound layer includes: forming a first structure having a first bonding structure on the IC die; forming a second structure having a second bonding structure on an interposer structure; performing a bonding process between the first and second bonding structures to form a bonding structure; placing the bonding structure in a component region between a top mold forming structure and a bottom mold forming structure of a molding system; and performing a molding process in the molding system to form a molding compound layer having a molding region and a cavity surrounding the bonding structure. The placement of the bonding structure includes aligning a protruding structure of the top mold forming structure with a portion of the second bonding structure that does not overlap with the first bonding structure. Attached Figure Description

[0007] When with attachment Figure 1 To better understand the various aspects of this disclosure, please refer to the following detailed description.

[0008] Figure 1 A cross-sectional view of a molding compound layer with a cavity in an IC die package according to some embodiments is illustrated.

[0009] Figure 2 A cross-sectional view of a molding compound layer with a cavity is illustrated in another IC die package according to some embodiments.

[0010] Figure 3 A cross-sectional view of a molding compound layer with a cavity is illustrated in another IC die package according to some embodiments.

[0011] Figure 4 This is a flowchart of a method for manufacturing an IC die package having a molding compound layer with a cavity, according to some implementation schemes.

[0012] Figure 5 A cross-sectional view of an IC die package at a stage of its manufacturing process, according to some implementation schemes, is shown.

[0013] Figure 6 A cross-sectional view of an IC die package at a stage of its manufacturing process, according to some implementation schemes, is shown.

[0014] Figure 7 A cross-sectional view of an IC die package at a stage of its manufacturing process, according to some implementation schemes, is shown.

[0015] Figure 8 A cross-sectional view of an IC die package at a stage of its manufacturing process, according to some implementation schemes, is shown.

[0016] Figure 9A cross-sectional view of an IC die package at a stage of its manufacturing process, according to some implementation schemes, is shown.

[0017] Figure 10 A cross-sectional view of an IC die package at a stage of its manufacturing process, according to some implementation schemes, is shown.

[0018] Figure 11 A cross-sectional view of an IC die package at a stage of its manufacturing process, according to some implementation schemes, is shown.

[0019] Figure 12 A cross-sectional view of an IC die package at a stage of its manufacturing process, according to some implementation schemes, is shown.

[0020] Figure 13 A cross-sectional view of an IC die package at a stage of its manufacturing process, according to some implementation schemes, is shown.

[0021] Figure 14 A cross-sectional view of an IC die package at a stage of its manufacturing process, according to some implementation schemes, is shown.

[0022] Figure 15 A cross-sectional view of an IC die package at a stage of its manufacturing process, according to some implementation schemes, is shown.

[0023] Figure 16 A cross-sectional view of an IC die package having a molding compound layer with a cavity, according to some embodiments, is shown at a stage of its manufacturing process.

[0024] Figure 17 A cross-sectional view of an IC die package having a molding compound layer with a cavity, according to some embodiments, is shown at a stage of its manufacturing process.

[0025] Figure 18 A cross-sectional view of an IC die package having a molding compound layer with a cavity, according to some embodiments, is shown at a stage of its manufacturing process.

[0026] Figure 19 A cross-sectional view of an IC die package having a molding compound layer with a cavity, according to some embodiments, is shown at a stage of its manufacturing process.

[0027] Figure 20 Exemplary systems or devices, according to some embodiments, may include different IC die packages having a molding compound layer with a cavity.

[0028] Exemplary embodiments will now be described with reference to the accompanying drawings. In the drawings, similar reference numerals generally denote the same, functionally similar, and / or structurally similar elements. Unless otherwise stated, the discussion of elements with the same annotations applies to each other. Detailed Implementation

[0029] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. To simplify this disclosure, specific examples of the components and arrangements are described below. These are merely examples and are not intended to be limiting. For example, in the following description, the process for forming a first feature over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features, such that the first and second features are not in direct contact. As used herein, forming a first feature over a second feature means that the first feature is formed in direct contact with the second feature. Additionally, in various examples, this disclosure may repeat reference numerals and / or letters. Such repetition, in itself, does not prescribe a relationship between the various embodiments and / or configurations discussed.

[0030] Spatial terms, such as “below,” “under,” “lower,” “above,” and “upper,” are used herein for descriptive convenience to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the accompanying drawings. Spatial terms are intended to cover different orientations during the use or operation of the device other than those depicted in the drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial descriptors used herein shall be interpreted accordingly.

[0031] It should be noted that the use of terms such as "an embodiment," "an embodiment," "an exemplary embodiment," or "exemplary" in the specification indicates that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when describing a specific feature, structure, or characteristic in conjunction with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the scope of knowledge of those skilled in the art.

[0032] It should be understood that the wording or terminology used herein is for illustrative purposes and not for limitation, and that the terminology or terminology used herein shall be interpreted by those skilled in the art in accordance with the teachings herein.

[0033] In some implementations, the terms "about" and "substantially" may indicate a value of a given quantity that varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of that value). These values ​​are merely examples and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of a value as interpreted by one of skill in the art in accordance with the teachings herein.

[0034] An IC die (also known as an "IC chip") may comprise an assembly of layers with different functionalities, such as interconnect structures, power distribution networks, logic chips, memory chips, etc. An IC die package (also known as a "semiconductor package") may comprise multiple IC dies disposed on and electrically connected to a wiring layer having an interposer structure, and these multiple IC dies may be disposed on and electrically connected to a package substrate. The wiring layer and package substrate may provide electrical connections (also known as "signal transmission paths" or "metal wiring") between IC dies on the same wiring layer and / or between IC dies on different wiring layers.

[0035] The IC die can be bonded to a wiring layer in a hybrid bonding process using top and bottom hybrid bonding structures. Each top hybrid bonding structure can be disposed on and electrically connected to an interconnect structure of the IC die. The bottom hybrid bonding structure can be disposed on and electrically connected to a metal line in the wiring layer. Each of the top and bottom hybrid bonding structures may include a dielectric layer and conductive structures disposed within the dielectric layer. During the hybrid bonding process, the top surface of the top hybrid bonding structure (also referred to as the "bonding surface") can be contacted with the top surface of the bottom hybrid bonding structure to form a fusion bond (e.g., oxide-to-oxide bonding) between the dielectric layers and a metal bond (e.g., copper-to-copper bonding) between the conductive structures.

[0036] Each IC die in an IC die, along with its top hybrid bonding structure, may be surrounded by a molding compound layer (e.g., a polymer material layer). The space between adjacent IC dies and adjacent hybrid bonding structures may be filled with the molding compound layer. The molding compound layer may be directly disposed on the sidewalls of the IC die and the top hybrid bonding structure, as well as on the top surface of the bottom hybrid bonding structure. The interface between the molding compound layer and the bottom hybrid bonding structure may be substantially coplanar with the hybrid bonding interface between the top and bottom hybrid bonding structures. The molding compound layer provides mechanical stability and environmental protection for the IC die and hybrid bonding structure.

[0037] One of the challenges in manufacturing reliable IC die packages is preventing delamination at the hybrid bonding interface due to stress induced by the molding compound layer during IC die package manufacturing and / or reliability testing. The molding compound layer can have a higher coefficient of thermal expansion than the materials of the IC die and / or hybrid bonding structure. Therefore, during the high-temperature processes performed in IC die package manufacturing and / or reliability testing, the molding compound layer can have greater thermal expansion than the IC die and / or hybrid bonding structure. Since the molding compound layer is located adjacent to the hybrid bonding interface without any space available for thermal expansion, this difference in thermal expansion can cause peel stress at the hybrid bonding interface at the edges of the IC die. The molding compound layer is constrained by the IC die on the sides, by the bottom hybrid bonding structure on the bottom side, and by the carrier on the top side.

[0038] To address the aforementioned challenges, this invention provides an example molding compound layer having cavities in an IC die package and an example method for forming the example molding compound layer. In some embodiments, each IC die in the IC die package, together with the top hybrid bonding structure, may be surrounded by a molding compound layer having one or more cavities. In some embodiments, one or more cavities may be disposed between adjacent IC dies and between adjacent top hybrid bonding structures. In some embodiments, one or more cavities may have a U-shaped or any suitable geometric cross-sectional profile. One or more cavities may reduce the total molding compound volume, thereby eliminating or reducing peel stress caused by thermal expansion at the hybrid bonding interface.

[0039] In some embodiments, a molding compound layer having one or more cavities can be formed in a molding system (e.g., a transfer molding system) using molding processes (e.g., transfer molding or compression molding). The molding system may include a bottom mold-forming structure and a top mold-forming structure. The top mold-forming structure may include one or more protruding structures that can create indentations in the molding compound layer to form one or more cavities. Therefore, the cross-sectional profile of the one or more cavities may resemble the cross-sectional profile of the one or more protruding structures. By using one or more protruding structures to form one or more cavities during the molding process, the formation of one or more cavities can be achieved during the manufacturing process of an IC die package without increasing the manufacturing time and cost of the IC die package.

[0040] Figure 1A cross-sectional view of an IC die package 100 (also referred to as "IC chip package 100") according to some embodiments is illustrated. In some embodiments, the IC die package 100 may include (i) a die layer 102, (ii) a wiring layer 104, (iii) a bonding layer 106, (iv) a molding compound layer 108 (also referred to as "encapsulation layer 108"), and (v) a conductive bonding structure 110. In some embodiments, the die layer 102 may include one or more IC dies 112, each IC die including high-performance IC dies such as SoC dies, microcontroller unit (MCU) dies, microprocessor unit (MPU) dies, accelerated processing unit (APU) dies, central processing unit (CPU) dies, graphics processing unit (GPU) dies, and combinations thereof. Although two IC dies 112 are shown in the die layer 102, any number of IC dies 112 may be included in the die layer 102. In some embodiments, adjacent IC dies 112 may be separated from each other by a distance D1 of approximately 50µm to approximately 70µm. In some embodiments, IC dies 112 may include interconnect structures 114 that electrically connect devices (not shown) in IC dies 112 to underlying wiring layers 104 via bonding layer 106. In some embodiments, IC dies 112 may be electrically connected to each other via bonding layer 106 and wiring layers 104. In some embodiments, die layers 102 may be electrically connected to upper die layers or other components (not shown) of the IC die package 100 via a redistribution layer (not shown) or a bonding layer similar to bonding layer 106.

[0041] In some embodiments, wiring layer 104 may include an interposer structure having (i) a semiconductor substrate 104A, (ii) a conductive via 104B disposed in the semiconductor substrate 104A, (iii) a dielectric layer 104C disposed on the semiconductor substrate 104A, (iv) a metal line 104D disposed in the dielectric layer 104C, and (v) a metal via 104E disposed in the dielectric layer 104C. In some embodiments, semiconductor substrate 104A may include a silicon substrate. In some embodiments, conductive via 104B may include a metal (such as copper and aluminum), a metal alloy (such as a copper alloy and an aluminum alloy), or a combination thereof. In some embodiments, dielectric layer 104C may include a stack of dielectric layers. In some embodiments, wiring layer 104 may be electrically bonded to an underlying package substrate (not shown) via conductive bonding structure 110. In some embodiments, each conductive bonding structure in conductive bonding structure 110 may include a copper (Cu) bump 110A and a solder bump 110B. The packaging substrate can be disposed on a circuit board (not shown) and electrically connected to the circuit board, and the IC die package 100 can be electrically connected to an external device through the circuit board.

[0042] In some embodiments, the bonding layer 106 may include one or more first hybrid bonding structures 116 (also referred to as "top hybrid bonding structure 116") and second hybrid bonding structures 118 (also referred to as "bottom hybrid bonding structure 118"). The bottom surface of each first hybrid bonding structure 116 may be disposed on and electrically connected to the interconnect structure 114 of the corresponding IC die 112. The top surface (also referred to as "bonding surface") of each first hybrid bonding structure 116 may be disposed on and bonded to the top surface of the second hybrid bonding structure 118 via hybrid bonding, as described in detail below. The interface between the first hybrid bonding structure 116 and the second hybrid bonding structure 118 may be referred to as "hybrid bonding interface 117". As discussed in detail below, the bonding reliability between the first hybrid bonding structure 116 and the second hybrid bonding structure 118 can be improved by using the molding compound layer 108 to reduce the risk of delamination between the first hybrid bonding structure 116 and the second hybrid bonding structure 118 at the hybrid bonding interface 117.

[0043] In some embodiments, each first hybrid bonding structure 116 may include a first dielectric layer 116A and one or more first conductive structures 116B disposed within the first dielectric layer 116A. Although three first conductive structures 116B are shown in each first hybrid bonding structure 116, any number of first conductive structures 116B may be included in the first hybrid bonding structure 116. In some embodiments, the first dielectric layer 116A may include silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), or any other suitable dielectric material. In some embodiments, each first conductive structure 116B may include a first conductive plug 120 and a first liner 122 surrounding the first conductive plug 120. In some embodiments, the first conductive structure 116B may be without a liner (not shown). The top surfaces of the first conductive plug 120 and the first liner 122 may be substantially coplanar with the top surface 116t of the first dielectric layer 116A. In some embodiments, the first conductive plug 120 may include a conductive material such as copper (Cu), cobalt (Co), aluminum (Al), any other suitable conductive material, and combinations thereof. In some embodiments, the first liner 122 may include a conductive material that is the same as or different from the material of the first conductive plug 120. In some embodiments, the first liner 122 may include titanium (Ti), Cu, or other suitable conductive materials.

[0044] In some embodiments, the second hybrid bonding structure 118 may include a second dielectric layer 118A and one or more second conductive structures 118B disposed within the second dielectric layer 118A. Although six second conductive structures 118B are shown in the second hybrid bonding structure 118, any number of second conductive structures 118B may be included in the second hybrid bonding structure 118. In some embodiments, the second dielectric layer 118A may include the same or different dielectric material as the first dielectric layer 116A. In some embodiments, each second conductive structure 118B may include a second conductive plug 124 and a second liner 126 surrounding the second conductive plug 124. In some embodiments, the second conductive structure 118B may be without a liner (not shown). The top surfaces of the second conductive plug 124 and the second liner 126 may be substantially coplanar with the top surface 118t of the second dielectric layer 118A. In some embodiments, the second conductive plug 124 and the second liner 126 may each include the same or different conductive material as the first conductive plug 120 and the first liner 122, respectively.

[0045] The first dielectric layer 116A and the second dielectric layer 118A can be bonded to each other via dielectric-to-dielectric fusion bonding, and the first conductive structure 116B and the second conductive structure 118B can be bonded to each other via metal-to-metal bonding. The dielectric-to-dielectric fusion bonding and metal-to-metal bonding can occur at the hybrid bonding interface 117. In some embodiments, the number of second conductive structures 118B can be equal to the total number of first conductive structures 116B. Each second conductive structure 118B can be bonded to a corresponding first conductive structure 116B.

[0046] In some embodiments, the molding compound layer 108 may surround each IC die 112 and each first hybrid bonding structure 116, and may be disposed on the second hybrid bonding structure 118. In some embodiments, the molding compound layer 108 may include one or more molding regions 108A and a cavity 108B (also referred to as a "recessed opening 108B") disposed in each molding region 108A. In some embodiments, in addition to the molding regions 108A at the periphery of the IC die package 100, the molding regions 108A may be disposed in inter-die regions 119, each inter-die region being located between adjacent IC dies and between adjacent first hybrid bonding structures 116. Although in Figure 1The diagram illustrates an inter-die region 119 having a molded region 108A, but the IC die package 100 may include any number of similar inter-die regions 119 having molded regions 108A between other adjacent IC dies and other adjacent first hybrid bonding structures 116. In some embodiments, the molded region 108A may be directly disposed on the sidewall of the first dielectric layer 116A of the IC die 112 and the first hybrid bonding structure 116. The molded region 108A may also be directly disposed on the top surface 118t of the second dielectric layer 118A of the second hybrid bonding structure 118. In some embodiments, the interface between the molded region 108A and the top surface 118t of the second dielectric layer 118A may be substantially coplanar with the hybrid bonding interface 117. In some embodiments, the molded region 108A may comprise molding compound, epoxy resin, resin, or any other suitable encapsulating material. In some implementations, the volume of the molded region 108A in the inter-die region 119 may be about 10% to about 50% of the volume of the inter-die region 119 to provide sufficient mechanical stability and environmental protection for the IC die 112 and the first hybrid bonding structure 116.

[0047] In some implementations, in addition to the cavity 108B at the periphery of the IC die package 100, the cavity 108B may be located in the inter-die region 119. Although Figure 1 The diagram illustrates an inter-die region 119 with a cavity 108B, but the IC die package 100 may include any number of similar inter-die regions 119 with cavities 108B between other adjacent IC dies and other adjacent first hybrid bonding structures 116. In some embodiments, the cavity 108B may be disposed on the second dielectric layer 118A of the second hybrid bonding structure 118 and may be separated from the top surface 118t of the second dielectric layer 118A by a portion of the molded region 108A. In some embodiments, the cavity 108B may extend below the interface between the IC die and the first hybrid bonding structure 1116. In some embodiments, the cavity 108B may have a U-shaped or any suitable geometry (e.g., rectangular, triangular, etc.) cross-sectional profile. In some embodiments, the volume of the cavity 108B in the inter-die region 119 may be from about 50% to about 90% of the volume of the inter-die region 119. Within this volume range, the cavity 108B reduces the overall thermal expansion of the molding region 108A without causing peel stress at the hybrid bonding interface 117 during the high-temperature processes performed in the manufacturing and / or reliability testing of the IC die package 100. Although all cavities 108B are shown as being located in... Figure 1Of all the molded regions 108A, however one or more molded regions 108A may be cavityless (not shown). In some embodiments, the molded region 108A at the periphery of the IC die package 100 may be cavityless (not shown).

[0048] Figure 2 A cross-sectional view of an IC die package 200 according to some embodiments is illustrated. Unless otherwise stated, the discussion of IC die package 100 applies to IC die package 200. Figure 1 and Figure 2 Discussions of elements with the same annotations apply to each other. In some embodiments, the IC die package 200 may include a molding compound layer 208. Unless otherwise stated, the discussion of molding compound layer 108 applies to molding compound layer 208. In some embodiments, molding compound layer 208 may include one or more molding regions 108A and a plurality of mold cavities 108B disposed in each molding region 108A, such as Figure 2 As shown, instead of as Figure 1 Individual mold cavities 108B in each molding region 108A are shown. In some embodiments, the total volume of the plurality of mold cavities 108B in the inter-die region 119 may be about 50% to about 90% of the volume of the inter-die region 119 to reduce the total stress in the molding region 108A during high-temperature processes performed in the manufacture and / or reliability testing of the IC die package 200. Although in Figure 2 Two cavities 108B are shown in the inter-die region 119, but there may be any number of cavities 108B in each inter-die region 119.

[0049] Figure 3 A cross-sectional view of an IC die package 300 according to some embodiments is illustrated. Unless otherwise stated, the discussion of IC die package 100 applies to IC die package 300. Figure 1 and Figure 3 Discussions of elements with the same annotations apply to each other. In some embodiments, the IC die package 300 may include a molding compound layer 308. Unless otherwise stated, the discussion of molding compound layer 108 applies to molding compound layer 308. In some embodiments, molding compound layer 308 may include one or more molding regions 308A and a mold cavity 308B disposed in each molding region 308A. In some embodiments, with Figure 1 Unlike cavity 108B, cavity 308B can extend to the top surface 118t of the second dielectric layer. In some embodiments, cavity 308B can have a rectangular or any suitable geometric cross-sectional profile. Although in Figure 3A single cavity 308B is shown in the inter-die region 119, but there may be any number of cavities 308B in each inter-die region 119. In some embodiments, the cavity 108B may have a U-shaped or any suitable geometry (e.g., rectangular, triangular, etc.) cross-sectional profile. In some embodiments, the volume of the cavity 308B in each inter-die region 119 may be about 50% to about 90% of the volume of the inter-die region 119 to reduce the stress caused by the molding region 308A during the high-temperature processes performed in the manufacturing and / or reliability testing of the IC die package 300.

[0050] Figure 4 It is used for manufacturing according to some implementation schemes. Figure 1 The flowchart illustrates an example method 400 for manufacturing an IC die package 100. For illustrative purposes, reference will be made to methods used in manufacturing such packages. Figures 5 to 19 The example manufacturing process of the IC die package 100 shown is described below. Figure 4 The operation shown. Figures 5 to 19 This is a cross-sectional view of the IC die package 100 at various manufacturing stages according to some implementation schemes. Depending on the specific application, operations may be performed in different sequences or not at all. It should be noted that method 400 may not produce a complete IC die package 100. Therefore, it should be understood that additional processes may be provided before, during, and after method 400, and only some of these other processes may be briefly described herein. Unless otherwise stated, for... Figure 1 and Figures 5 to 19 Discussions of elements with the same annotations are applicable to each other.

[0051] refer to Figure 4 In operation 405, a first hybrid bonding structure is formed on the IC die. For example, as shown in reference... Figures 5 to 8 As described, a first hybrid bonding structure 116 is formed on the IC die 112. In some embodiments, the formation of the first hybrid bonding structure 116 may include the following sequential operations: (i) depositing a first dielectric layer 116A on the IC die 112, such as... Figure 5 As shown; (ii) Etching the first dielectric layer 116A to form an opening 520 on the interconnect structure 114, as Figure 5 As shown; (iii) a conductive layer 622 of material having a first liner 122 is deposited on the top surface 116t of the first dielectric layer 116A and along the sidewall of the opening 520, as shown. Figure 6 As shown; (iv) A patterned photoresist layer 638 is formed on the conductive layer 622, as shown. Figure 6As shown; (v) using an electroplating process or other suitable conductive material deposition process to deposit a conductive layer 720 of material having the first conductive plug 120 to fill the opening 520 and extend a distance above the top surface 116t of the first dielectric layer 116A, as shown. Figure 7 As shown; (vi) Remove the patterned photoresist layer 638, as Figure 8 As shown; and (vii) performing a chemical mechanical polishing (CMP) process to make the top surfaces of the first conductive plug 120 and the first liner 122 coplanar with the top surface 116t of the first dielectric layer 116A, as shown. Figure 8 As shown. In some embodiments, step (iii) may be omitted to form a first hybrid bonding structure 116 without the first liner 122.

[0052] refer to Figure 4 In operation 410, a second hybrid bonding structure is formed on the wiring layer. For example, as shown in reference... Figures 9 to 12 As described, a second hybrid bonding structure 118 is formed on the wiring layer 104. In some embodiments, the formation of the second hybrid bonding structure 118 may include the following sequential operations: (i) depositing a second dielectric layer 118A on the wiring layer 104, such as... Figure 9 As shown; (ii) Etching the second dielectric layer 124 to form an opening 924 on the metal line 104D, as Figure 9 As shown; (iii) a conductive layer 1026 of material having a second liner 126 is deposited on the top surface 118t of the second dielectric layer 124 and along the sidewall of the opening 1026, as shown. Figure 10 As shown; (iv) A patterned photoresist layer 1038 is formed on the conductive layer 1026, as... Figure 10 As shown; (v) using an electroplating process or other suitable conductive material deposition process to deposit a conductive layer 1124 of material having the second conductive plug 124 to fill the opening 924 and extend a distance above the top surface 118t of the second dielectric layer 118A, as shown. Figure 11 As shown; (vi) Remove the patterned photoresist layer 1038, as... Figure 12 As shown; and (vii) performing a CMP process to make the top surfaces of the second conductive plug 124 and the second liner 126 coplanar with the top surface 118t of the second dielectric layer 118A, as Figure 12 As shown. In some embodiments, step (iii) may be omitted to form a second hybrid bonding structure 118 without the second liner 126. In some embodiments, step 410 may be formed before step 405, and step 415 may be formed after step 405.

[0053] refer to Figure 4In operation 415, a hybrid bonding process is performed between the first hybrid bonding structure and the second hybrid bonding structure. For example, as referenced... Figure 13 As described, a hybrid bonding process is performed between the first hybrid bonding structure 116 and the second hybrid bonding structure 118. In some embodiments, performing the hybrid bonding process may include the following sequential operations: (i) performing an activation process using plasma (e.g., hydrogen plasma) on the top surfaces of the first dielectric layer 116A, the first conductive structure 116B, the second dielectric layer 118A, and the second conductive structure 118B; (ii) aligning the first conductive structure with the corresponding second conductive structure 118B and bringing the top surface 116t of the first dielectric layer 116A into contact with the top surface 118t of the second dielectric layer 118A, such as... Figure 13 As shown, and (iii) at a temperature lower than the melting temperature of the materials of the first conductive plug 120 and the second conductive plug 124. Figure 13 The structure is subjected to annealing process to form Figure 13 The structure. In some embodiments, after alignment in operation (ii), the first conductive structure 116B and the second conductive structure 118B may not be in contact with each other, and an air gap may exist between the first conductive structure 116B and the second conductive structure 118B. The first conductive structure 116B and the second conductive structure 118B may expand and come into contact with each other during the annealing process to form a metal-to-metal molten bond.

[0054] refer to Figure 4 In operation 420, a molding compound layer having a cavity is formed to surround the IC die. For example, as referenced... Figures 14 to 17 As described, a molding compound layer 108 having a molding region 108A and a molding cavity 108B is formed to surround the IC die 112. In some embodiments, such as Figure 14 As shown, a molding compound layer 108 can be formed in the molding system 1400 using a molding process.

[0055] In some embodiments, the molding system 1400 may include a mold forming structure 1430, which may include a top mold forming structure 1430A (also referred to as "top mold sleeve 1430A") and a bottom mold forming structure 1430B (also referred to as "bottom mold sleeve 1430B"). In some embodiments, the molding system 1400 may also include a gate region 1432, a part region 1434, and a venting region 1434 disposed between the top mold forming structure 1430A and the bottom mold forming structure 1430B. In some embodiments, a portion of the top mold forming structure 1430A in the part region 1434 may include a protrusion structure 1438 that may create indentations in the molding compound layer 108 to form a cavity 108B, as discussed in detail below. Therefore, the cross-sectional profile and structural dimensions of the cavity 108B may be similar to the cross-sectional profile and structural dimensions of the protrusion structure 1438.

[0056] The formation of the molding compound layer 108 may include the following sequential operations: (i) applying... Figure 13 The intermediate structure of the IC die package 100 is placed in the component region 1434, such that the protruding structure 1438 can be aligned with and extend into the inter-die region 119, as shown below. Figure 14 As shown, (ii) the fluid molding compound (not shown) is introduced into the part region 1434 through the gate region 1432 until the venting region 1436 is filled, and (iii) a curing process is performed on the fluid molding compound to form the molding compound layer 1508, as shown. Figure 15 As shown, (iv) the top mold forming structure 1430A is removed to expose the molding compound layer 1508, and (v) portions of the molding compound layer 1508 formed in the gate region 1432 and the venting region 1436 are removed to form Figure 16 The molding compound layer 108, and (vi) the .... Figure 16 The molding compound layer 108 undergoes a CMP process to make the top surface 108t of the molding region 108A of the molding compound layer 108 coplanar with the back surface 112b of the IC die 112, such as... Figure 17 As shown. In some implementations, Figure 13 The intermediate structure of the IC die package 100 can be bonded to a carrier substrate (not shown) before being placed in a molding system 1400 for a molding process. The molding system 1400 may include other components, such as clamping structures, reservoirs, and fluid chambers, which are not shown for simplicity.

[0057] refer to Figure 4 In operation 425, a conductive bonding structure is formed on the wiring layer. For example, as shown in the reference... Figure 18 and Figure 19As described, the conductive bonding structure 110 is formed on the wiring layer 104. In some embodiments, the formation of the conductive structure may include the following sequential operations: (i) performing a CMP process or etching process on the semiconductor substrate 104A to expose the bottom surface 104Bs of the conductive via 104B, such as... Figure 18 As shown, and (ii) a conductive bonding structure 110 is formed on the bottom surface 104Bs, as Figure 19 As shown.

[0058] Figure 20 This may be an illustration of an exemplary system or device that may include the disclosed embodiments. System or device 2000 may be implemented in a wide range of ways in conjunction with one or more of the disclosed embodiments. For example, system or device 2000 may be implemented in one or more of a desktop computer 2010, a laptop computer 2020, a tablet computer 2030, a cellular or mobile phone 2040, and a television 2050 (or a set-top box communicating with a television).

[0059] Furthermore, the system or device 2000 may be implemented in a wearable device 2060 such as a smartwatch or a health monitoring device. In some implementations, a smartwatch may have different functions, such as access to email, cellular services, and calendar functions. The wearable device 2060 may also perform health monitoring functions, such as monitoring the user's vital signs and performing epidemiological functions (e.g., contact tracing and providing communications to emergency medical services). The wearable device 2060 may be worn around the user's neck, implanted in the user's body, glasses or helmets designed to provide computer-generated reality experiences (e.g., augmented and / or virtual reality), any other suitable wearable device, and combinations thereof.

[0060] Furthermore, system or device 2000 may be implemented in a server computer system (such as a dedicated server) or in shared hardware implementing cloud-based services 2070. System or device 2000 may be implemented in other electronic devices, such as home electronic devices 2080, including refrigerators, thermostats, security cameras, and other suitable home electronic devices. The interconnection of such devices may be referred to as the “Internet of Things” (IoT). System or device 2000 may also be implemented in various modes of transportation 2090, such as as part of vehicle control systems, navigation systems, and / or entertainment systems. Figure 20 The systems and devices illustrated herein are merely examples and are not intended to limit future applications of the disclosed embodiments. Other example systems and devices that can implement the disclosed embodiments include portable gaming devices, music players, data storage devices, and drones.

[0061] It should be understood that the detailed description portion, and not a summary of the disclosure portion, is intended to be used for interpreting the claims. The summary of the disclosure portion may set forth one or more, but not all, possible embodiments of this disclosure as contemplated by the inventor, and therefore is not intended to limit the appended claims in any way.

[0062] Unless otherwise stated, the specific embodiments are not intended to limit the scope of the claims drafted based on the disclosure of this form, even where only a single example is described with respect to a particular feature. Therefore, the disclosed embodiments are intended to be illustrative rather than restrictive, without any statement to the contrary. This application is intended to cover such alternative, modified, and equivalent forms, as will be apparent to those skilled in the art who benefit from this disclosure.

[0063] The foregoing disclosure outlines the features of several embodiments, thereby enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or realize the same advantages of the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure.

Claims

1. A structure comprising: Integrated circuit (IC) die; An interposer structure, wherein the interposer structure is electrically connected to the IC die; A first bonding structure, comprising: A first dielectric layer is disposed on the IC die; and A first conductive plug is disposed in the first dielectric layer; A second bonding structure is bonded to the first bonding structure, wherein the second bonding structure includes: A second dielectric layer is disposed on the intermediate layer structure; and A second conductive plug, wherein the second conductive plug is disposed in the second dielectric layer; and A molding compound layer disposed on the second bonding structure, wherein the molding compound layer includes a molding area and a mold cavity.

2. The structure according to claim 1, wherein the molding compound layer surrounds the IC die and the first bonding structure.

3. The structure according to claim 1, wherein the molding region is directly disposed on the sidewall of the IC die and the first dielectric layer.

4. The structure according to claim 1, wherein the molding region and the mold cavity are disposed on the portion of the second bonding structure that does not overlap with the first bonding structure.

5. The structure according to claim 1, wherein the cavity extends below the interface between the IC die and the first bonding structure.

6. The structure of claim 1, wherein the mold cavity extends to the surface portion of the second bonding structure that does not overlap with the first bonding structure.

7. The structure according to claim 1, wherein the mold cavity includes a U-shaped cross-sectional profile.

8. The structure according to claim 1, wherein the mold cavity includes a first mold cavity and a second mold cavity disposed in the molding region.

9. The structure of claim 1, wherein the interface between the molding region and the second bonding structure and the interface between the first bonding structure and the second bonding structure are substantially coplanar.

10. The structure according to claim 1, wherein the top surface of the molded region is substantially coplanar with the back surface of the IC die.

11. An integrated circuit (IC) die package, the integrated circuit (IC) die package comprising: A wiring layer, the wiring layer including conductors and vias; The first IC die and the second IC die are disposed on the wiring layer; A first bonding structure and a second bonding structure are respectively disposed on the first IC die and the second IC die; A third bonding structure is bonded to the first bonding structure and the second bonding structure and disposed on the wiring layer; and An encapsulation layer is configured to surround the first IC die and the second IC die, wherein the encapsulation layer includes a molded region and a recessed opening located in the molded region.

12. The IC die package according to claim 11, wherein the recessed opening is disposed between the first IC die and the second IC die.

13. The IC die package according to claim 11, wherein the recessed opening is disposed between the first bonding structure and the second bonding structure.

14. The IC die package according to claim 11, wherein the recessed opening is disposed on the portion of the third bonding structure that does not overlap with the first bonding structure and the second bonding structure.

15. The IC die package of claim 11, wherein the surface portion of the third bonding structure that does not overlap with the first bonding structure and the second bonding structure is exposed in the recessed opening.

16. The IC die package of claim 11, wherein the recessed opening extends below the interface between the first IC die and the first bonding structure.

17. A method, the method comprising: A first structure including a first bonding structure is formed on an integrated circuit (IC) die; A second structure, including a second bonding structure, is formed on the intermediate layer structure; A bonding process is performed between the first bonding structure and the second bonding structure to form a bonding structure; The bonding structure is placed in a component region between a top mold forming structure and a bottom mold forming structure of a molding system, wherein placing the bonding structure includes aligning a protruding structure of the top mold forming structure with a portion of the second bonding structure that does not overlap with the first bonding structure; as well as A molding process is performed in the molding system to form a molding compound layer that surrounds the bonding structure, including the molding area and the mold cavity.

18. The method of claim 17, wherein performing the molding process includes forming the mold cavity having the cross-sectional profile of the protruding structure.

19. The method of claim 17, wherein performing the molding process comprises: Introduce the fluid molding compound into the component region; as well as The fluid molding compound is cured to form the molding compound layer.

20. The method of claim 17, wherein performing the molding process includes performing a polishing process on the molding compound layer to make the top surface of the molding region coplanar with the back surface of the IC die.

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