Mask assembly and method of manufacturing a mask assembly

Abstract

The invention relates to a mask assembly and a method of manufacturing the same. The method comprises the following steps: providing a wafer; forming a first inorganic layer on the wafer; forming a second inorganic layer on the first inorganic layer; etching the wafer to form a cell opening; forming a photosensitive layer on a rear surface of the first inorganic layer exposed through the cell opening; etching the photosensitive layer to form a plurality of photosensitive openings; isotropically etching the first inorganic layer to form a plurality of first openings overlapping the plurality of photosensitive openings; and anisotropically etching the second inorganic layer to form a plurality of second openings overlapping the plurality of first openings.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2024-0143682, filed on October 21, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to mask assemblies and methods of manufacturing mask assemblies. More specifically, this disclosure relates to methods of manufacturing mask assemblies for use in deposition processes. Background Technology

[0004] Display devices typically include pixels, and each pixel may include driving elements such as transistors and display elements such as organic light-emitting diodes.

[0005] Display elements can be formed by stacking electrodes and light-emitting patterns on a substrate.

[0006] A process can be performed using a mask assembly with openings defined therethrough to form a light-emitting pattern. The light-emitting pattern is formed corresponding to the area exposed through the openings of the mask assembly. The light-emitting pattern is formed on the target substrate according to the shape and position of the openings of the mask assembly. Summary of the Invention

[0007] This disclosure provides a method for manufacturing a mask assembly that allows the side surfaces defining the opening of the mask assembly to have selected angles.

[0008] This disclosure provides a mask assembly that can prevent or reduce the occurrence of shadow areas caused by uneven thickness formation of deposition patterns during a process of depositing deposition material on a target substrate.

[0009] Embodiments of the present invention provide a method for manufacturing a mask assembly. In such an embodiment, the method includes: providing a wafer; forming a first inorganic layer on the wafer; forming a second inorganic layer on the first inorganic layer; etching the wafer to form cell openings; forming a photosensitive layer on a rear surface of the first inorganic layer exposed through the cell openings; etching the photosensitive layer to form a plurality of photosensitive openings; isotropically etching the first inorganic layer to form a plurality of first openings overlapping the plurality of photosensitive openings; and anisotropically etching the second inorganic layer to form a plurality of second openings overlapping the plurality of first openings.

[0010] In one embodiment, forming a plurality of first openings may include wet etching of the first inorganic layer along a direction from the rear surface of the first inorganic layer to the upper surface of the first inorganic layer.

[0011] In an embodiment, forming a plurality of second openings may include dry etching the second inorganic layer along a direction from the rear surface of the second inorganic layer to the upper surface of the second inorganic layer.

[0012] In an embodiment, forming the first inorganic layer may include depositing silicon oxide (SiO2) on the upper surface of the wafer using a chemical vapor deposition (CVD) process. x ) and aluminum oxide (AlO x One of them.

[0013] In an embodiment, forming the second inorganic layer may include depositing silicon nitride (SiN) on the upper surface of the first inorganic layer using a chemical vapor deposition (CVD) process. x ).

[0014] In an embodiment, forming a plurality of first openings may include etching a portion of the rear surface of the first inorganic layer through the plurality of photosensitive openings in a direction from the rear surface of the first inorganic layer to the upper surface of the first inorganic layer.

[0015] In one embodiment, forming a plurality of second openings may include etching a portion of the rear surface of the second inorganic layer exposed through a plurality of first openings in a direction from the rear surface of the second inorganic layer to the upper surface of the second inorganic layer.

[0016] In some embodiments, the method may further include removing the photosensitive layer.

[0017] In one embodiment, removing the photosensitive layer may include wet stripping of the photosensitive layer.

[0018] In an embodiment, after the plurality of first openings are formed and before the photosensitive layer is removed, each of the plurality of side surfaces of the first inorganic layer defining the plurality of first openings may have an undercut shape when viewed in cross-section.

[0019] In one embodiment, forming the cell opening may include wet etching the wafer in a direction from the back surface of the wafer to the top surface of the wafer.

[0020] In an embodiment, when viewed in cross-section, the cell opening may have a width that decreases in the direction from the back surface of the wafer to the top surface of the wafer.

[0021] In an embodiment, the first inorganic layer may have a thickness greater than or equal to about 100 nanometers (nm) and less than or equal to about 2 micrometers (μm), and the second inorganic layer may have a thickness greater than or equal to about 5 nm and less than or equal to about 50 nm.

[0022] Embodiments of the present invention provide a mask assembly, comprising: a wafer having a plurality of cell openings defined therethrough; a first inorganic layer disposed on the wafer and having a plurality of first openings completely penetrating an upper surface and a rear surface of the first inorganic layer; and a second inorganic layer disposed on the first inorganic layer and having a plurality of second openings defined therethrough and overlapping the plurality of first openings. In such an embodiment, each of the plurality of first openings has a width that decreases in the direction from the rear surface of the first inorganic layer to the upper surface of the first inorganic layer.

[0023] In an embodiment, the first inorganic layer may have a thickness greater than that of the second inorganic layer.

[0024] In an embodiment, the first inorganic layer may have a thickness greater than or equal to about 100 nm and less than or equal to about 2 μm.

[0025] In an embodiment, the second inorganic layer may have a thickness greater than or equal to about 5 nm and less than or equal to about 50 nm.

[0026] In an embodiment, when viewed in a plan view, each of the plurality of unit openings may overlap with a plurality of first openings and a plurality of second openings.

[0027] In this embodiment, the wafer may include silicon, and the first inorganic layer may include silicon oxide (SiO2). x ) and aluminum oxide (AlO x One of the following, and the second inorganic layer includes silicon nitride (SiN). x ).

[0028] In one embodiment, each of the plurality of cell openings can completely penetrate the wafer in the thickness direction, and when viewed in cross-section, each of the plurality of cell openings can have a width that decreases in the direction from the back surface of the wafer to the top surface of the wafer.

[0029] In an embodiment, when viewed in a plan view, the plurality of second openings may be spaced apart from each other.

[0030] In the embodiments, the first inorganic layer may have a single-layer structure, and the second inorganic layer may have a multi-layer structure.

[0031] According to embodiments of the present invention, in a mask assembly manufactured by a method for manufacturing a mask assembly (i.e., a method for manufacturing a mask assembly), the occurrence of shadowed areas where the deposited material is deposited at an uneven thickness is reduced.

[0032] According to embodiments of the present invention, the manufacturing method of the mask assembly is simplified, and the cost and time consumption in the manufacturing process are reduced.

[0033] According to embodiments of the present invention, when a mask manufactured according to the mask assembly manufacturing method is used in the deposition process, the yield and reliability of the deposition process are improved. Furthermore, the resolution, brightness, and lifespan of the display device manufactured by the deposition process are also improved. Attached Figure Description

[0034] Figure 1 This is a perspective view illustrating an electronic device according to an embodiment of the present disclosure.

[0035] Figure 2 This is a view showing an electronic device in use according to an embodiment of the present disclosure.

[0036] Figure 3 This is an exploded perspective view showing an electronic device according to an embodiment of the present disclosure.

[0037] Figure 4 This is a cross-sectional view showing a deposition apparatus according to an embodiment of the present disclosure.

[0038] Figure 5 This is a plan view illustrating a mask assembly according to an embodiment of the present disclosure.

[0039] Figure 6 It is shown Figure 5 A magnified plan view of region AA'.

[0040] Figure 7A It shows along Figure 6 A cross-sectional view of the mask assembly taken by line I-I'.

[0041] Figure 7B It shows along Figure 6 A cross-sectional view of the mask assembly taken from line II-II'.

[0042] Figure 7C It shows along Figure 6 A cross-sectional view of the mask assembly taken from line III-III'.

[0043] Figure 8A This is a view showing a portion of a deposition process using a mask assembly according to a comparative example.

[0044] Figure 8B It is shown Figure 8A Enlarged cross-sectional view of region BB'.

[0045] Figure 8C This is a view illustrating a portion of a deposition process using a mask assembly according to an embodiment of the present disclosure.

[0046] Figure 9 This is a flowchart illustrating a method for manufacturing a mask assembly according to an embodiment of the present disclosure.

[0047] Figures 10A to 10J This is a cross-sectional view of a method for manufacturing a mask assembly according to an embodiment of the present disclosure.

[0048] Figure 11 This is a cross-sectional view showing a mask assembly according to an embodiment of the present disclosure.

[0049] Figure 12 This is a cross-sectional view showing a mask assembly according to an embodiment of the present disclosure.

[0050] Figure 13 It shows the use Figure 5 The diagram shows a plan view of the display panel manufactured by the mask assembly shown.

[0051] Figure 14 It is shown Figure 13 The image shows a cross-sectional view of one pixel.

[0052] Figure 15 It is shown by Figure 4 A view of the deposition process performed by the deposition equipment shown. Detailed Implementation

[0053] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be exhaustive and complete, and will fully convey the scope of the invention to those skilled in the art.

[0054] It will be understood that when an element is referred to as being "on" another element, the element may be directly on the other element, or there may be an intermediary element between the element and the other element. Conversely, when an element is referred to as being "directly on" another element, there is no intermediary element.

[0055] In this disclosure, it will be understood that when an element or layer is referred to as being “connected to” or “coupled to” another element or layer, the element or layer may be directly connected to or directly coupled to the other element or layer, or there may be an intermediary element or layer.

[0056] The same reference numerals always refer to the same elements. In the accompanying drawings, the thickness, proportions, and size of parts are exaggerated for the purpose of effective description of the technical content.

[0057] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, areas, layers, and / or segments, these elements, components, areas, layers, and / or segments should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or segment from another. Therefore, without departing from the teachings herein, “first element,” “first component,” “first area,” “first layer,” or “first segment” discussed below may be referred to as “second element,” “second component,” “second area,” “second layer,” or “second segment.”

[0058] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, “a,” “an,” “the,” and “at least one” do not indicate a limitation on quantity and are intended to include both the singular and the plural. Thus, a reference to “an element” in the claims followed by a reference to “the element” includes one element and multiple elements. For example, unless the context clearly indicates otherwise, “an element” has the same meaning as “at least one element.” “At least one” should not be construed as limited to “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that, when used in this specification, the terms “comprising” and / or “including” or “having” and / or “possessing” indicate the presence of the stated features, areas, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components and / or groups thereof.

[0059] Furthermore, relative terms such as “below” or “bottom” and “above” or “top” may be used herein to describe the relationship between one element and another as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the relative terms are intended to cover different orientations of the device. For example, if the device is flipped in one of the drawings, an element described as being “below” the other element will subsequently be oriented to be “above” the other element. Thus, depending on the specific orientation of the drawing, the term “below” can cover both “below” and “above” orientations. Similarly, if the device is flipped in one of the drawings, an element described as being “below” or “under” the other element will subsequently be oriented to be “above” the other element. Thus, the terms “below” or “under” can cover both “above” and “below” orientations.

[0060] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, “about” or “approximately” includes the stated value and means within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art. For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0061] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that, unless expressly defined herein, terms (such as those defined in general dictionaries) should be interpreted as having meanings consistent with their meanings in the context of the relevant field and will not be interpreted in an idealized or overly formalized sense.

[0062] The embodiments are described herein with reference to cross-sectional views of schematic diagrams as idealized embodiments. Therefore, variations in the shapes illustrated will be expected due to factors such as manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but will include deviations in shape due to factors such as manufacturing. For example, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0063] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0064] Figure 1 This is a perspective view illustrating an electronic device according to an embodiment of the present disclosure. Figure 2 This is a view showing an electronic device in use according to an embodiment of the present disclosure. Figure 3 This is an exploded perspective view showing an electronic device according to an embodiment of the present disclosure.

[0065] Reference Figures 1 to 3 Embodiments of the electronic device HMD can be activated in response to an electrical signal. The electronic device HMD can be a mobile phone (e.g., a foldable mobile phone), a laptop computer, a television, a tablet computer, a vehicle navigation unit, a gaming unit, or a wearable unit. Wearable units can be devices worn on a user's body and can include a head-mounted display for implementing extended reality (XR) content.

[0066] Figure 1A head-mounted display is shown as an embodiment of an electronic device HMD. In such an embodiment, the electronic device HMD can be a display device worn on the user's head. The electronic device HMD can provide images while obstructing the user's field of vision of the actual environment. Users US wearing electronic device HMDs can find it easier to immerse themselves in virtual reality.

[0067] An electronic device HMD may include a body section HS, a strip section STR, a pad section PP, and a display panel DP. Although not shown in the accompanying drawings, an electronic device HMD may include various sensors and cameras.

[0068] The main body HS can be worn on the head of the user US. The main body HS can house a display panel DP for displaying images and an accelerometer (not shown). The accelerometer can detect the movement of the user US and can send signals to the display panel DP. Therefore, the display panel DP can provide images in response to changes in the user US's gaze. Thus, the user US can experience virtual reality that is very similar to real life.

[0069] In addition to the components described above, the main body HS may also house components with various functions. The main body HS may be referred to as a housing or casing. In an embodiment, a control unit (not shown) may be additionally placed on the exterior of the main body HS to adjust settings such as volume or screen brightness. The control unit may be provided as a physical button or a touch sensor. Furthermore, the main body HS may house a proximity sensor (not shown) to determine whether the user US is wearing the electronic device HMD. The main body HS may also include an external display panel.

[0070] The main body HS may include the main body portion HS-1 and the covering portion HS-2. Figure 3 An embodiment with a structure in which the main body portion HS-1 and the cover portion HS-2 are separate is shown as a representative example; however, this disclosure should not be limited thereto or thereby restricted. In another embodiment, for example, the main body portion HS-1 may be provided integrally with the cover portion HS-2 as an indivisible part of a single whole, and the main body portion HS-1 and the cover portion HS-2 may not be separate from each other.

[0071] Display panels (DPs) can be positioned between the main body portion HS-1 and the cover portion HS-2. Each of the multiple display panels (DPs) can display an image through the display area DA. Figure 3The present invention illustrates an embodiment in which the left-eye and right-eye images are provided separately by display panels (DPs), however, this disclosure should not be limited thereto or thereby restricted. In another embodiment, for example, the left-eye and right-eye images may be displayed by a single display panel. Multiple display panels (DPs) may be driven by separate drivers; however, this disclosure should not be limited thereto or thereby restricted. According to an embodiment, multiple display panels (DPs) may be driven by a single driver.

[0072] Display panel DP can generate an image corresponding to the image data input to display panel DP. Each of the plurality of display panels DP can be an organic light-emitting display panel, an inorganic light-emitting display panel, an organic-inorganic light-emitting display panel, a quantum dot display panel, a micro light-emitting diode (LED) display panel, a nano LED display panel, or a liquid crystal display panel. In the following description, for ease of description, embodiments in which the display panel DP is an organic light-emitting display panel will be described primarily, but this disclosure should not be limited to organic light-emitting display panels.

[0073] The strap section STR can be coupled to the main body section HS to allow the main body section HS to be easily worn on the user US. The strap section STR may include a main strap STR1 and an upper strap STR2.

[0074] The main strap STR1 can be worn around the circumference of the user's head (US). The main strap STR1 secures the main body (HS) to the user (US), allowing it to fit snugly against the head. The upper strap STR2 connects the main body (HS) to the main strap STR1 along the upper part of the user's head. The upper strap STR2 effectively prevents the main body (HS) from slipping down. Furthermore, the upper strap STR2 improves the user's wearing comfort by distributing the load on the main body (HS).

[0075] Figure 1 The embodiments shown are representative examples of structures in which the lengths of the main band STR1 and the upper band STR2 are adjustable; however, this disclosure should not be limited thereto or thereby restricted. In another embodiment, for example, the main band STR1 and the upper band STR2 may be elastic, and the adjustable length portions of the main band STR1 and the upper band STR2 may be omitted.

[0076] Apart from Figure 1 and Figure 2 Besides the shape disclosed herein, the strap STR can be modified into various shapes, as long as the strap STR allows the main body HS to be fixed to the user US. In the embodiment, the upper strap STR2 can be omitted. Furthermore, according to the embodiment, the strap STR can be modified into various shapes (such as a helmet coupled to the main body HS or an eyeglass temple coupled to the main body HS).

[0077] The pad portion PP can be disposed between the main body portion HS and the user's head portion US. The pad portion PP can be formed of a material that is easily deformable into different shapes. In embodiments, the pad portion PP may include a polymer resin (e.g., polyurethane, polycarbonate, polypropylene, and polyethylene) or a sponge molded by foaming a rubber latex, polyurethane-based material, or acrylic-based material; however, this disclosure should not be limited thereto or thereby restricted.

[0078] The padding portion PP allows the main body portion HS to fit securely to the user US, thus improving the wearing comfort of the user US. The padding portion PP can be detached from the main body portion HS. According to an embodiment, the padding portion PP can be omitted.

[0079] An optical system OL can be disposed in the main body portion HS-1 of the main body portion HS. The optical system OL can magnify the image provided by the display panel DP. Each of the plurality of display panels DP can display an image on a third direction DR3 through a display area DA parallel to a first direction DR1 and a second direction DR2 intersecting the first direction DR1. The optical system OL can be spaced apart from the display panel DP on the third direction DR3. The optical system OL can be positioned between the display panel DP and the user's eye US. The optical system OL can include a right-eye optical system OL_R and a left-eye optical system OL_L. The left-eye optical system OL_L can provide a magnified image to the left pupil of the user US, and the right-eye optical system OL_R can provide a magnified image to the right pupil of the user US.

[0080] The left-eye optical system OL_L and the right-eye optical system OL_R can be spaced apart from each other in the first direction DR1. The distance between the right-eye optical system OL_R and the left-eye optical system OL_L can be adjusted to correspond to the distance between the user's two eyes. In addition, the distance between the optical system OL and the display panel DP can be adjusted according to the user's visual acuity.

[0081] The optical system OL can be a convex aspherical lens. In embodiments, for example, the optical system OL can be a pancake lens, but it should not be limited thereto. In such an embodiment, each of the left-eye optical system OL_L and the right-eye optical system OL_R includes one lens; however, this disclosure should not be limited thereto. In another embodiment, each of the left-eye optical system OL_L and the right-eye optical system OL_R may include multiple lenses.

[0082] In such an embodiment, since the display panel DP is located very close to the user's (US) eyes, it is expected to have a higher resolution compared to a conventional display panel. According to embodiments of the method for manufacturing a mask assembly of this disclosure, a mask assembly MA (refer to) can be provided having a structure that maintains deposition reliability even during the manufacturing process of a high-resolution display panel. Figure 4 The mask assembly MA (see below) will be described in detail. Figure 4 The structural characteristics of the mask assembly and each process of the mask assembly manufacturing method.

[0083] Figure 4 This is a cross-sectional view showing a deposition apparatus according to an embodiment of the present disclosure.

[0084] According to embodiments of the present disclosure, the deposition apparatus DD can be used to form, as described later, the components included in the display panel DP (refer to...). Figure 13 One or more functional layers in ). In an embodiment, for example, the deposition device DD can be used to perform functions for the display panel DP (refer to Figure 13 EML of depositional patterns (refer to) Figure 15 ) deposition process.

[0085] Reference Figure 4 Embodiments of a deposition apparatus DD may include a cavity CB, a stationary unit PU, a deposition unit EU, a mask assembly MA, and a stage ST. The deposition apparatus DD may also include additional mechanical equipment to enable an inline system.

[0086] The cavity CB may include a bottom surface, a top surface, and sidewalls connecting the bottom surface and the top surface (or connecting between the bottom surface and the top surface) to provide internal space within the cavity CB. The bottom surface of the cavity CB may be substantially parallel to a plane defined by a first direction DR1 and a second direction DR2, and the normal direction of the bottom surface of the cavity CB may be substantially parallel to a third direction DR3. In this disclosure, the expression "when viewed in a plane" or "when viewed in a plan view" may be defined based on a surface parallel to the plane defined by the first direction DR1 and the second direction DR2, and may mean when viewed on a third direction DR3 perpendicular to the plane defined by the first direction DR1 and the second direction DR2.

[0087] The fixed unit PU, deposition unit EU, mask assembly MA, and stage ST can be placed inside the cavity CB. Additionally, the target substrate M-SUB can be placed inside the cavity CB.

[0088] The cavity CB can provide a closed (or sealed) space. Therefore, the deposition conditions inside the cavity CB can be set to a vacuum state.

[0089] Although not shown in the accompanying drawings, the cavity CB may include one or more doors. The cavity CB can be opened or closed through the doors. The mask assembly MA and the target substrate M-SUB can enter and exit through the doors provided in the cavity CB.

[0090] The fixing unit PU can be placed above the deposition unit EU within the cavity CB. The fixing unit PU can be used to attach the mask assembly MA to the target substrate M-SUB. Figure 4 An embodiment with a structure in which the mask assembly MA contacts the target substrate M-SUB is shown as a representative example. However, this disclosure should not be limited thereto or thereby restricted, and the mask assembly MA may be spaced apart from the target substrate M-SUB without contacting it.

[0091] The fixing unit PU may include a magnetic material to hold the mask assembly MA to the target substrate M-SUB. According to an embodiment, the fixing unit PU may include an electrostatic chuck. The fixing unit PU can apply an attractive force to the mask assembly MA to effectively prevent the mask assembly MA from sagging due to gravity.

[0092] Although not shown in the accompanying drawings, the holding unit PU may also include a clamping portion to hold the target substrate M-SUB. The clamping portion can be used to keep the target substrate M-SUB stationary during the deposition process (i.e., to hold the target substrate M-SUB in a fixed position). In embodiments, for example, the clamping portion may be defined as a groove to which the target substrate M-SUB is detachably coupled.

[0093] The target substrate M-SUB can be a processing target on which a deposition material DM is deposited. In an embodiment, for example, the target substrate M-SUB may include a support substrate and a substrate BL disposed on the support substrate and connected to the base substrate (see reference). Figure 15 The corresponding synthetic resin layer. The support substrate can be located in the display panel DP (refer to...). Figure 13 The later stages of the manufacturing process are removed. Depending on the component formed by the deposition process, the target substrate M-SUB may include a display panel DP (see reference). Figure 13 The formation of ) in the matrix substrate BL (refer to Figure 15 Some components on ).

[0094] The deposition unit EU can be placed in the cavity CB to face the stationary unit PU. The deposition unit EU may include a space containing the deposition material DM and one or more nozzles for spraying the deposition material DM. Figure 4 An embodiment showing a deposition unit EU comprising three nozzles is presented as a representative example; however, this disclosure should not be limited thereto or thereby restricted.

[0095] The deposited material DM can include inorganic, metallic, or organic materials capable of sublimation or evaporation. The deposited material DM can be patterned and deposited on the target substrate M-SUB using a mask assembly MA.

[0096] A mask assembly MA can be disposed on a stage ST. The mask assembly MA can be disposed between a deposition unit EU and a target substrate M-SUB. In an embodiment, for example, the mask assembly MA can be fixed to the stage ST and can be attached to and detached from the stage ST. The upper surface of the mask assembly MA can face the target substrate M-SUB.

[0097] The mask assembly MA allows the deposition material DM to be deposited in a pattern on the target substrate M-SUB. The mask assembly MA also allows the deposition material DM to selectively pass through specific areas of the mask assembly MA.

[0098] The mask assembly MA may include a wafer WF, a first inorganic layer INL1, and a second inorganic layer INL2.

[0099] Wafer WF can include silicon (Si).

[0100] Cell openings S-OP can be defined (e.g., through) the upper surface WU and the rear surface WB of the wafer WF. Multiple cell openings S-OP can be provided. Figure 4 An embodiment in which two unit openings S-OP are defined in a mask assembly MA is shown as a representative example.

[0101] Each of the multiple unit openings S-OP completely penetrates the wafer WF (or is completely defined or formed through the wafer WF) in the thickness direction (i.e., third direction DR3) of the mask assembly MA.

[0102] The first inorganic layer INL1 can be disposed on the wafer WF. In an embodiment, for example, the first inorganic layer INL1 can be disposed on the upper surface WU of the wafer WF. The first inorganic layer INL1 can be in direct contact with the upper surface WU of the wafer WF.

[0103] The first inorganic layer INL1 may include a material suitable for isotropic etching. The first inorganic layer INL1 may also include a material suitable for wet etching. In an embodiment, for example, the first inorganic layer INL1 may include silicon oxide (SiO2). x ) or aluminum oxide (AlO x ).

[0104] The first inorganic layer, INL1, can have a single-layer structure.

[0105] The first inorganic layer, INL1, can be formed using a chemical vapor deposition (CVD) process. This will be described later.

[0106] The first opening OP1 may be defined by the first inorganic layer INL1 in the thickness direction. The first opening OP1 may be defined by the upper surface I1U and the rear surface I1B of the first inorganic layer INL1 (e.g., it may completely penetrate the upper surface I1U and the rear surface I1B of the first inorganic layer INL1). When viewed in a plane (or when viewed in a plan view or in a third-direction DR3), the first opening OP1 may overlap with the cell opening S-OP. Figure 4 An embodiment with a structure in which five first openings OP1 overlap with each unit opening S-OP is shown as a representative example.

[0107] The second inorganic layer INL2 can be disposed on the first inorganic layer INL1. In an embodiment, for example, the second inorganic layer INL2 can be disposed on the upper surface I1U of the first inorganic layer INL1. The second inorganic layer INL2 can be in direct contact with the upper surface I1U of the first inorganic layer INL1.

[0108] The second inorganic layer INL2 can be formed on the upper surface of the first inorganic layer INL1.

[0109] The second inorganic layer INL2 may include a material suitable for anisotropic etching. The second inorganic layer INL2 may include a material suitable for dry etching. In an embodiment, for example, the second inorganic layer INL2 may include silicon nitride (SiN). x The second inorganic layer, INL2, can be formed by chemical vapor deposition (CVD). This will be described later.

[0110] The second inorganic layer, INL2, can have a multilayer structure.

[0111] The second opening OP2 can be defined in the thickness direction by the second inorganic layer INL2. When viewed in a plane or in a plan view, the second opening OP2 can overlap with the first opening OP1. The second opening OP2 can also overlap with the element opening S-OP. Figure 4 An embodiment with a structure in which five second openings OP2 overlap with each unit opening S-OP is shown as a representative example.

[0112] The deposited material DM can pass through the cell opening S-OP, the first opening OP1, and the second opening OP2, and can be blocked in other areas. That is, the deposited material DM can selectively pass through the mask assembly MA and can be deposited as a pattern on the target substrate M-SUB.

[0113] When viewed in a plane, the first opening OP1 can overlap with the unit opening S-OP. The unit opening S-OP can define the area where the deposition pattern is formed on the target substrate M-SUB.

[0114] After passing through the unit opening S-OP, the first opening OP1, and the second opening OP2, the deposited material DM can be formed on the deposition surface of the target substrate M-SUB as a deposition pattern corresponding to the first opening OP1. This will be described later.

[0115] The ST can be positioned between the deposition unit EU and the stationary unit PU. The ST can be placed outside the path of the deposition material DM supplied from the deposition unit EU toward the target substrate M-SUB.

[0116] The stage ST can support the mask assembly MA. The stage ST can provide a mounting surface on which the mask assembly MA is mounted. The mounting surface can be substantially parallel to the first direction DR1 and the second direction DR2. The mounting surface of the stage ST can be substantially parallel to the bottom of the cavity CB.

[0117] Figure 5 This is a plan view illustrating a mask assembly according to an embodiment of the present disclosure.

[0118] Reference Figure 5 When viewed in a plane or in a plan view, embodiments of the mask assembly MA may have a circular shape; however, this disclosure should not be limited thereto or thereby restricted. In embodiments, for example, the mask assembly MA may have a polygonal shape.

[0119] The mask assembly MA may include a cell region CA and a peripheral region NCA surrounding the cell region CA when viewed in a plane.

[0120] The element region CA can be connected to the element opening S-OP (see reference). Figure 4 )correspond. Figure 5 An embodiment showing forty-eight cell regions CA arranged in the first direction DR1 and the second direction DR2 is illustrated as a representative example, but this disclosure should not be limited thereto or thereby restricted. The arrangement and number of cell regions CA can be related to... Figure 5 The arrangement and quantity shown may differ from those shown. Figure 5 Various modifications were made to the arrangement and quantity shown.

[0121] When viewed in a plane, the second opening OP2 can be defined within a cell region CA. The second opening OP2 can be arranged in each of the plurality of cell regions CA and can be spaced apart from each other in each of the plurality of cell regions CA. In an embodiment, for example, the second opening OP2 is arranged in each cell region CA on the first direction DR1 and the second direction DR2. However, this disclosure should not be limited thereto or thereby restricted. The second opening OP2 can be defined as being formed on the target substrate M-SUB (refer to...). Figure 4 EML of deposition patterns in ) (refer to) Figure 15 )correspond.

[0122] Figure 6 It is shown Figure 5 A magnified plan view of region AA'. Figures 7A to 7C It is shown Figure 6 A cross-sectional view of the mask assembly.

[0123] In the following text, reference will be made to Figure 6 as well as Figures 7A to 7C Describe the structural characteristics of the mask assembly MA.

[0124] Figure 6 An embodiment is shown in which each of the second openings OP2 has a circular shape when viewed in a plane. However, the shape of the second openings OP2 when viewed in a plane should not be limited to a circular shape. In another embodiment, for example, each of the second openings OP2 may have a polygonal shape when viewed in a plane.

[0125] Figure 6 An embodiment of a structure having twenty second openings OP2 arranged in a first direction DR1 and a second direction DR2 is shown; however, this is merely an example and this disclosure should not be limited thereto or thereby restricted.

[0126] For ease of illustration and description, Figures 7A to 7C An embodiment is shown having a structure in which the second inorganic layer INL2 is disposed at the lowest position and the first inorganic layer INL1 and the wafer WF are stacked on the third-direction DR3. That is, Figures 7A to 7C The mask component MA shown can be relative to Figure 4 The mask component MA described herein is flipped vertically. However, for ease of explanation, in the following description, based on... Figure 4 The mask assembly MA shown is used to define the terms "upper surface" and "rear surface" for components in the mask assembly MA.

[0127] Figure 7A It shows along Figure 6 A cross-sectional view of the mask assembly taken by line I-I'.

[0128] Reference Figure 7A In an embodiment of the mask assembly MA, the width SW of each of the plurality of cell openings S-OPs may decrease in the direction from the rear surface WB of the wafer WF to the upper surface WU of the wafer WF. In an embodiment, for example, the width SW of each of the plurality of cell openings S-OPs may gradually decrease in the direction from the rear surface WB of the wafer WF to the upper surface WU of the wafer WF.

[0129] The first opening OP1 may have a width OW1 that decreases in the direction from the rear surface I1B to the upper surface I1U of the first inorganic layer INL1. In an embodiment, for example, the width OW1 of the first opening OP1 may gradually decrease in the direction from the rear surface I1B to the upper surface I1U. Figure 7A An embodiment of a structure having a side surface of each of a plurality of first openings OP1 defined in a first inorganic layer INL1 that is a curved surface is shown as a representative example. However, this disclosure should not be limited thereto or thereby restricted.

[0130] When viewed in a plane, the first opening OP1 can overlap with the second opening OP2.

[0131] The second opening OP2 may have a constant width OW2. The width OW2 of the second opening OP2 may be constant on the third direction DR3. However, this disclosure should not be limited to or restricted by this, and will be described later.

[0132] The first inorganic layer INL1 may have a thickness TH1 greater than the thickness TH2 of the second inorganic layer INL2. In an embodiment, for example, the thickness TH1 of the first inorganic layer INL1 may be greater than or equal to about 100 nanometers (nm) and less than or equal to about 2 micrometers (μm). In an embodiment, for example, the thickness TH2 of the second inorganic layer INL2 may be greater than or equal to about 5 nm and less than or equal to about 50 nm.

[0133] Figure 7B It shows along Figure 6 A cross-sectional view of the mask assembly taken from line II-II'.

[0134] Reference Figure 7B In an embodiment of the mask assembly MA, the cell opening S-OP may be defined, and the first opening OP1 and the second opening OP2 may not be defined.

[0135] The rear surface I1B of the first inorganic layer INL1 can be exposed through the cell opening S-OP.

[0136] The second inorganic layer INL2 can be covered by the first inorganic layer INL1 and therefore can be left unexposed.

[0137] Figure 7C It shows along Figure 6 A cross-sectional view of the mask assembly taken from line III-III'.

[0138] Reference Figure 7C In embodiments of the mask assembly MA, the cell opening S-OP (see reference) may not be limited. Figure 7A ), First opening OP1 (refer to) Figure 7A ) and the second opening OP2 (refer to Figure 7A ).

[0139] Therefore, the first inorganic layer INL1 can be covered by wafer WF.

[0140] The second inorganic layer INL2 can be covered by the first inorganic layer INL1 and the wafer WF.

[0141] Figure 8A This is a view showing a portion of a deposition process using a mask assembly according to a comparative example. Figure 8B It is shown Figure 8A Enlarged cross-sectional view of region BB'. Figure 8C This is a view illustrating a portion of a deposition process using a mask assembly according to an embodiment of the present disclosure.

[0142] In the following text, reference will be made to Figures 8A to 8C The mask assembly according to embodiments of the present disclosure will be described in more detail.

[0143] Figure 8A The process of forming a deposited pattern EML on a target substrate M-SUB using a mask assembly according to a comparative example is illustrated. For ease of illustration and description, Figure 8A The diagram shows a configuration in which the first nozzle NZ-L and the second nozzle NZ-R are spaced apart from each other in the first direction DR1, and the deposition equipment is omitted (see reference). Figure 4 Other components of the deposition equipment (DD).

[0144] Reference Figure 8A The deposited material discharged from the first nozzle NZ-L or the second nozzle NZ-R (refer to...) Figure 4 The deposited material (DM) can be provided into the opening OP defined by the shadow mask SM-O.

[0145] However, due to the deposition material DM (reference) Figure 4 A portion of the material may not be supplied to DR3 in parallel with third parties, therefore, based on the deposited material DM (refer to...). Figure 4 The angle provided may result in a shaded area SA in the deposited pattern EML. In this disclosure, the shaded area SA may refer to an area in the deposited pattern EML where no material has been deposited to the normal thickness.

[0146] Reference Figure 8B When viewed in cross-section, the side surface of the defined opening OP of the shadow mask SM-O in the mask assembly of the comparative example can be parallel to the third direction DR3. Therefore, a shadowed region SA may appear in the deposition process using the shadow mask SM-O.

[0147] In the following description, for ease of description, the deposited material DM (refer to) discharged from the first nozzle NZ-L can be referred to as... Figure 4 The path at one end of the defined shaded area SA is called the first path DM-L, and the deposited material DM (refer to) can be discharged from the second nozzle NZ-R. Figure 4 The path at the other end of the shaded area SA is called the second path DM-R.

[0148] The shaded area SA can correspond to the area between the end point of the first path DM-L and the end point of the second path DM-R.

[0149] The shadow region SA can be divided into an inner shadow region I-SA and an outer shadow region O-SA relative to an imaginary line extending from the side surface of the defining opening OP of the shadow mask SM-O.

[0150] Reference Figure 8C According to embodiments of the present disclosure, a shadow mask SM may include a first inorganic layer INL1 and a second inorganic layer INL2.

[0151] Since the first opening OP1 is defined by the first inorganic layer INL1, the amount of deposited material DM can be reduced (see reference). Figure 4 The area blocked by the rear surface of the shadow mask SM. Therefore, a second modified path DM-R' can be defined in a deposition process using the shadow mask SM according to an embodiment of the present disclosure.

[0152] In such an embodiment, compared with the reference Figure 8B Compared to the described shadow mask SM-O, since the shadow mask SM also includes a second inorganic layer INL2, the deposited material DM (refer to...) Figure 4 The area blocked by the shadow mask SM can be increased. Therefore, the first modified path DM-L' can be defined in the deposition process using the shadow mask SM according to embodiments of the present disclosure.

[0153] In a shadow mask SM according to an embodiment of the present disclosure, the shadow region SA' may be defined by a first modification path DM-L' and a second modification path DM-R'.

[0154] For ease of illustration and description, Figure 8C In the middle, refer to Figure 8B The first path DM-L and the second path DM-R are depicted as dashed arrows that intersect each other.

[0155] According to the embodiment, based on the first modification path DM-L' and the second modification path DM-R', and compared with the inner shadow area I-SA of the comparison example (refer to...), Figure 8B Compared to the example, the inner shadow region I-SA' can be reduced, and compared to the outer shadow region O-SA (see comparison example) Figure 8B Compared to the previous method, the outer shadow region O-SA' can be reduced.

[0156] Therefore, compared with the reference Figure 8B The shaded area SA described (refer to) Figure 8B Compared to ), the shaded area SA' can be reduced.

[0157] That is, according to the embodiments of this disclosure, the mask assembly MA (refer to...) Figure 4 This can effectively prevent or significantly reduce the occurrence of shadowed areas (SA'). Furthermore, the normal depositional area (LSA) can be enlarged.

[0158] In other words, due to the mask assembly MA (refer to) according to embodiments of this disclosure Figure 4 The process includes a first inorganic layer INL1 and a second inorganic layer INL2, which improves the yield and reliability of the deposition process. Therefore, the resolution, brightness, and lifespan of display devices manufactured via the deposition process can be improved.

[0159] Due to the mask assembly MA (refer to) according to embodiments of the present disclosure Figure 4 This includes settings at the wafer WF (reference) Figure 4 Both the first inorganic layer INL1 and the second inorganic layer INL2 on the mask assembly can improve bending strength due to the inorganic layers. Therefore, the bending strength of the mask assembly MA (refer to) can be significantly reduced. Figure 4 It can reduce distortion and effectively prevent the appearance of shadow areas SA'.

[0160] Figure 9 This is a flowchart illustrating a method for manufacturing a mask assembly according to an embodiment of the present disclosure.

[0161] Reference Figure 9 A method for manufacturing a mask assembly according to an embodiment of the present disclosure includes: providing a wafer (S100); forming a first inorganic layer on the wafer (S200); forming a second inorganic layer on the first inorganic layer (S300); etching the wafer to form a cell opening (S400); forming a photosensitive layer on the rear surface of the first inorganic layer exposed through the cell opening (S500); etching the photosensitive layer to form a photosensitive opening (S600); isotropically etching the first inorganic layer to form a first opening overlapping the photosensitive opening (S700, hereinafter, S700 may be referred to as "forming the first opening"); and anisotropically etching the second inorganic layer to form a second opening overlapping the first opening (S800, hereinafter, S800 may be referred to as "forming the second opening").

[0162] The method for manufacturing a mask assembly according to an embodiment of the present disclosure may further include removing the photosensitive layer (S900).

[0163] Figures 10A to 10J This is a cross-sectional view of a method for manufacturing a mask assembly according to an embodiment of the present disclosure.

[0164] In the following text, for ease of description, the mask assembly MA in the pre-completion state during the manufacturing process of the mask assembly MA will be referred to as the preliminary mask P-MA.

[0165] Reference Figure 10A In an embodiment of the method for manufacturing a mask assembly, the provision of a wafer WF (S100, see reference) can be performed. Figure 9 ).

[0166] Although not shown in the accompanying drawings, the wafer WF according to an embodiment may have a circular shape. The wafer WF may include silicon (Si).

[0167] Then, refer to Figure 10B In an embodiment of the mask assembly manufacturing method, the formation of a first inorganic layer INL1 on the wafer WF (S200, see reference) can be performed. Figure 9 ).

[0168] The first inorganic layer INL1 can be formed on the upper surface WU of the wafer WF.

[0169] The first inorganic layer, INL1, can be formed by depositing a material via chemical vapor deposition (CVD).

[0170] The deposition material used to form the first inorganic layer INL1 can be a material suitable for isotropic etching.

[0171] The deposition material used to form the first inorganic layer INL1 can be a material suitable for wet etching. In an embodiment, for example, the deposition material used to form the first inorganic layer INL1 may include silicon oxide (SiO2). x ) or aluminum oxide (AlO x ).

[0172] Reference Figure 10C In an embodiment of the mask assembly manufacturing method, forming a second inorganic layer INL2 on the first inorganic layer INL1 can be performed (S300, see reference). Figure 9 ).

[0173] The second inorganic layer INL2 can be formed on the upper surface I1U of the first inorganic layer INL1.

[0174] The second inorganic layer, INL2, can be formed by depositing material via chemical vapor deposition (CAD) process.

[0175] The deposition material used to form the second inorganic layer INL2 can be a material suitable for anisotropic etching.

[0176] The deposition material used to form the second inorganic layer INL2 can be a material suitable for dry etching. The second inorganic layer INL2 may comprise a different material than the first inorganic layer INL1. In embodiments, for example, the deposition material used to form the second inorganic layer INL2 may include silicon nitride (SiN). x ).

[0177] The thickness TH1 of the first inorganic layer INL1 can be greater than the thickness TH2 of the second inorganic layer INL2. In an embodiment, for example, the thickness TH1 of the first inorganic layer INL1 can be greater than or equal to about 100 nm and less than or equal to about 2 μm. In an embodiment, for example, the thickness TH2 of the second inorganic layer INL2 can be greater than or equal to about 5 nm and less than or equal to about 50 nm.

[0178] For ease of illustration and explanation, Figures 10D to 10J An embodiment is shown having a structure in which the second inorganic layer INL2 is disposed at the lowest position and the first inorganic layer INL1 and the wafer WF are stacked on the third-direction DR3. That is, Figures 10D to 10J The mask assembly shown (i.e., Figures 10D to 10I The initial mask P-MA and Figure 10J The mask component (MA) in the middle can be relative to Figure 4 The mask component MA described herein is flipped vertically. However, for ease of description, the following description is based on... Figure 4 The mask component MA shown is used to define Figures 10D to 10I The initial mask P-MA and Figure 10J The terms "upper surface" and "rear surface" are used for components in the mask assembly MA.

[0179] Reference Figure 10D In an embodiment of the mask assembly manufacturing method, wafer etching (WF) can be performed to form cell openings (S-OP) (S400, see reference). Figure 9 ).

[0180] The wafer WF can be etched along the direction from the rear surface WB to the upper surface WU. In an embodiment, for example, the wafer WF can be anisotropically etched along the direction from the rear surface WB to the upper surface WU.

[0181] Forming unit openings (S-OP) can include wet-etched wafers (WF).

[0182] However, when performing a wet etching process to etch a wafer (WF) to form a cell opening (S-OP, S400, see reference)... Figure 9 In the process, at least a portion of the wafer WF can be etched by an etching solution on the first direction DR1, the second direction DR2, and the third direction DR3.

[0183] However, the etching rate of the wafer WF in the third direction DR3 can be greater than the etching rate of the wafer WF in the first direction DR1 and the second direction DR2. Therefore, when viewed in cross-section, the side surface WS of the defining cell opening S-OP of the wafer WF can have a reverse tapering shape.

[0184] Reference Figure 10E and Figure 10F In an embodiment of the mask assembly manufacturing method, a photosensitive layer PR (S500, see reference) can be formed on the rear surface I1B exposed through the unit opening S-OP of the first inorganic layer INL1. Figure 9 ) and etch the photosensitive layer PR to form the photosensitive opening P-OP (S600, reference) Figure 9 ).

[0185] The photosensitive layer PR may include a photosensitive material. The photosensitive layer PR can be formed by coating the photosensitive material onto the back surface I1B of the first inorganic layer INL1 via a spin coating process or an inkjet process.

[0186] Figure 10E and Figure 10F Examples of photosensitive materials that are negative photoresists are shown as representative examples. However, this disclosure should not be limited thereto or thereby restricted, and the photosensitive material may also be a positive photoresist.

[0187] The photosensitive layer PR is etched to form the photosensitive opening P-OP by placing the light opening M-OP above the preliminary mask P-MA through the light mask PM defined by it and irradiating the photosensitive layer PR with light LE through the light opening M-OP of the light mask PM. (S600, see reference) Figure 9 ).

[0188] Reference Figure 10G and Figure 10H In an embodiment of the method for manufacturing a mask assembly, forming a first opening OP1 (S700, see reference) can be performed. Figure 9 ). Figure 10H yes Figure 10G A magnified view of region CC'.

[0189] Forming the first opening OP1 (S700, reference) Figure 9 This may include isotropic etching of the first inorganic layer INL1. In an embodiment, for example, a first opening OP1 is formed (S700, see reference). Figure 9 This may include wet etching of the first inorganic layer INL1 along the direction from the rear surface I1B of the first inorganic layer INL1 to the upper surface I1U.

[0190] Forming the first opening (S700, see reference) Figure 9This may include etching the portion of the rear surface I1B of the first inorganic layer INL1 exposed through the photosensitive opening P-OP along a direction from the rear surface I1B of the first inorganic layer INL1 to the upper surface I1U of the first inorganic layer INL1.

[0191] When viewed in a plane, the first opening OP1 can overlap with the photosensitive opening P-OP.

[0192] In such an embodiment, since the first opening OP1 is formed by isotropically etching the first inorganic layer INL1, the width OW1 of the first opening OP1 can be larger than the width TW of the photosensitive opening P-OP that overlaps with the first opening OP1.

[0193] Therefore, when viewed in the cross-section, the first opening OP1 (S700, reference) is formed. Figure 9 After that, the photosensitive layer PR (S900, see reference) is removed. Figure 9 Prior to this, each of the plurality of side surfaces I1S of the first inorganic layer INL1 defining the first opening OP1 and the photosensitive layer PR may have an undercut shape.

[0194] In other words, when viewed in a plane, the side surface of the photosensitive layer PR that defines the photosensitive opening P-OP can protrude partially in a direction toward the center of the first opening OP1. In this disclosure, the protruding portion of the photosensitive layer PR can be referred to as the tip portion TP.

[0195] The first opening OP1 may be formed having a width OW1 that decreases in the direction from the rear surface I1B of the first inorganic layer INL1 to the upper surface I1U. In an embodiment, for example, when viewed in cross-section, the side surface I1S of the first inorganic layer INL1 defining each of the plurality of first openings OP1 may have a curved shape; however, this disclosure should not be limited thereto or thereby restricted.

[0196] A portion of the second inorganic layer INL2 can be exposed without being covered by the first inorganic layer INL1. The rear surface I2B of the second inorganic layer INL2 can be exposed through the first opening OP1. Therefore, the first inorganic layer INL1 can be used as a mask to form the second opening OP2 (see reference). Figure 10I This will be described later.

[0197] Reference Figure 10I In an embodiment of the method for manufacturing a mask assembly, forming a second opening OP2 (S800, see reference) can be performed. Figure 9 ).

[0198] Forming the second opening OP2 (S800, reference) Figure 9 This may include anisotropic etching of the second inorganic layer INL2.

[0199] Forming the second opening OP2 (S800) may include etching the portion of the rear surface I2B of the second inorganic layer INL2 exposed through the first opening OP1 along a direction from the rear surface I2B of the second inorganic layer INL2 to the upper surface I2U of the second inorganic layer INL2.

[0200] In an embodiment, for example, a second opening OP2 is formed (S800, see reference). Figure 9 This may include dry etching of the second inorganic layer INL2 along the direction from the rear surface I2B of the second inorganic layer INL2 to the upper surface I2U of the second inorganic layer INL2.

[0201] In forming the second opening OP2 (S800, refer to...) Figure 9 ), due to the formation of the first opening OP1 (S700, refer to Figure 9 The photosensitive layer PR with the photosensitive opening P-OP used in the ) has not been removed, so the photosensitive layer PR can be used to form the second opening OP2.

[0202] In other words, according to an embodiment of the mask assembly manufacturing method, both the first opening OP1 and the second opening OP2 can be formed using a photosensitive layer PR and a photosensitive opening P-OP defined by the photosensitive layer PR. Therefore, the time and cost of manufacturing additional masks can be reduced.

[0203] Reference Figure 10J In an embodiment of the method for manufacturing a mask assembly, the removal of the photosensitive layer (PR) can be performed (see reference). Figure 10I )(S900, refer to Figure 9 ).

[0204] Remove photosensitive layer PR (reference) Figure 10I )(S900, refer to Figure 9 This may include wet stripping of the photosensitive layer PR. However, this disclosure should not be limited thereto or thereby restricted. In embodiments, for example, the photosensitive layer PR may be dry stripped.

[0205] Figure 11 This is a cross-sectional view showing a mask assembly according to an embodiment of the present disclosure.

[0206] exist Figure 11 In the figures, the same / similar reference numerals indicate Figures 4 to 10J The same / similar elements in the text will be omitted, and therefore any repeated detailed descriptions of the same / similar elements will be omitted.

[0207] Reference Figure 11 According to the embodiment, the mask assembly MA-1 may include a wafer WF, a first inorganic layer INL1 and a second inorganic layer INL2-1.

[0208] The second opening OP2-1 may be defined by the second inorganic layer INL2-1. The second opening OP2-1 may have a width OW2-1 that decreases in the direction from the rear surface I2B of the second inorganic layer INL2-1 to the upper surface I2U of the second inorganic layer INL2-1. In an embodiment, for example, the width OW2-1 of the second opening OP2-1 may gradually decrease in the direction from the rear surface I2B of the second inorganic layer INL2-1 to the upper surface I2U of the second inorganic layer INL2-1.

[0209] When viewed in cross-section, the side surface I2S of the second inorganic layer INL2-1 defining the second opening OP2-1 can be tilted in the direction between the first direction DR1 and the third direction DR3.

[0210] Figure 12 This is a cross-sectional view showing a mask assembly according to an embodiment of the present disclosure.

[0211] exist Figure 12 In the figures, the same / similar reference numerals indicate Figures 4 to 10J The same / similar elements in the text will be omitted, and therefore any repeated detailed descriptions of the same / similar elements will be omitted.

[0212] Reference Figure 12 According to the embodiment, the mask assembly MA-2 may include a wafer WF, a first inorganic layer INL1-1 and a second inorganic layer INL2.

[0213] The first opening OP1-1 may be defined by the first inorganic layer INL1-1. The first opening OP1-1 may have a width OW1-1 that decreases in the direction from the rear surface I1B of the first inorganic layer INL1-1 to the upper surface I1U of the first inorganic layer INL1-1. In an embodiment, for example, the width OW1-1 of the first opening OP1-1 may gradually decrease in the direction from the rear surface I1B of the first inorganic layer INL1-1 to the upper surface I1U of the first inorganic layer INL1-1.

[0214] When viewed from the cross section, the side surface I1S-1 of the first inorganic layer INL1-1 defining the first opening OP1-1 can be a plane inclined in the direction between the first direction DR1 and the third direction DR3.

[0215] Figure 12 An embodiment showing a structure in which the side surface I1S-1 of the first inorganic layer INL1-1 defining the first opening OP1-1 is flat is shown as a representative example; however, this disclosure should not be limited thereto or thereby restricted. In embodiments, for example, the side surface I1S-1 of the first inorganic layer INL1-1 defining the first opening OP1-1 may include curved surfaces and flat surfaces.

[0216] Figure 13 It shows the use Figure 5 The diagram shows a plan view of the display panel manufactured by the mask assembly shown. Figure 14 It is shown Figure 13 The image shows a cross-sectional view of one pixel. Figure 15 It is shown by Figure 4 A view of the deposition process performed by the deposition equipment shown.

[0217] Figure 13 It shows the use Figure 5 The diagram shows a plan view of the display panel manufactured by the mask assembly shown.

[0218] Reference Figure 13 An embodiment of the display panel DP may have a rectangular shape defined by a short side extending in a first direction DR1 and a long side extending in a second direction DR2; however, the shape of the display panel DP should not be limited thereto or thereby restricted. The display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA.

[0219] The display panel DP can be a light-emitting display panel. The display panel DP can be an organic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel can include organic light-emitting materials. The light-emitting layer of a quantum dot light-emitting display panel can include quantum dots or quantum rods. In the following description, embodiments where the display panel DP is an organic light-emitting display panel will be used as representative examples.

[0220] The display panel DP may include multiple pixels PX, multiple scan lines SL1 to SLm, multiple data lines DL1 to DLn, multiple transmit lines EL1 to ELm, a first control line CSL1 and a second control line CSL2, a first power line PLL1 and a second power line PLL2, a connection line CNL, and multiple pads PD. Each of “m” and “n” is a natural number greater than 0.

[0221] Pixels (PX) can be arranged in the display area (DA). Scan driver (SDV) and transmit driver (EDV) can each be located in a non-display area (NDA) adjacent to the long side of the display panel (DP). Data driver (DDV) can be located in a non-display area (NDA) adjacent to one of the short sides of the display panel (DP). When viewed in a plane, the data driver (DDV) can be positioned adjacent to the bottom edge of the display panel (DP).

[0222] Scan lines SL1 to SLm can extend along the first direction DR1 and can be connected to the pixel PX and the scan driver SDV. Data lines DL1 to DLn can extend along the second direction DR2 and can be connected to the pixel PX and the data driver DDV. Transmit lines EL1 to ELm can extend along the first direction DR1 and can be connected to the pixel PX and the transmit driver EDV.

[0223] The first power line PLL1 may extend along the second direction DR2 and may be disposed in the non-display area NDA. The first power line PLL1 may be disposed between the display area DA and the transmit driver EDV; however, it should not be limited thereto or restricted by this. According to an embodiment, the first power line PLL1 may be disposed between the display area DA and the scan driver SDV.

[0224] The connecting line CNL can extend along the first direction DR1 and can be arranged along the second direction DR2. The connecting line CNL can be connected to the first power line PLL1 and the pixel PX. A first voltage can be applied to the pixel PX through the first power line PLL1 and the connecting line CNL connected to the first power line PLL1.

[0225] The second power line PLL2 can be located in the non-display area NDA. The second power line PLL2 can extend along the long side of the display panel DP and the other short side of the display panel DP where the data driver DDV is not located. The second power line PLL2 can be located outside the scan driver SDV and the transmit driver EDV.

[0226] Although not shown in the accompanying drawings, the second power line PLL2 can extend to the display area DA and can be connected to the pixel PX. A second voltage having a lower level than the first voltage can be applied to the pixel PX through the second power line PLL2.

[0227] When viewed in a plane, the first control line CSL1 can be connected to the scan driver SDV and can extend towards the lower end of the display panel DP. When viewed in a plane, the second control line CSL2 can be connected to the transmit driver EDV and can extend towards the lower end of the display panel DP. The data driver DDV can be positioned between the first control line CSL1 and the second control line CSL2.

[0228] The pad PD can be set on the display panel DP. The pad PD can be set closer to the lower end of the display panel DP than the data driver DDV. The data driver DDV, the first power line PLL1, the second power line PLL2, the first control line CSL1, and the second control line CSL2 can be connected to the pad PD. Data lines DL1 to DLn can be connected to the data driver DDV, and the data driver DDV can be connected to the pad PD corresponding to the data lines DL1 to DLn.

[0229] The light-emitting element of the display panel DP can be made of Figure 5 The unit area CA shown is formed. The unit area corresponding to the display panel DP can be defined in the target substrate M-SUB (see reference). Figure 4 In this process, when the light-emitting element is formed in a unit area, the unit area can be divided. As a result, it is possible to manufacture... Figure 13 The display panel DP shown is shown.

[0230] Although not shown in the accompanying drawings, the timing controller that controls the operation of the scan driver SDV, data driver DDV, and transmit driver EDV, as well as the voltage generator that generates the first and second voltages, can be mounted on a printed circuit board. The timing controller and voltage generator can be connected to their respective pads PD via the printed circuit board.

[0231] The scan driver SDV generates multiple scan signals, which are applied to pixel PX via scan lines SL1 to SLm. The data driver DDV generates multiple data voltages, which are applied to pixel PX via data lines DL1 to DLn. The transmit driver EDV generates multiple transmit signals, which are applied to pixel PX via transmit lines EL1 to ELm.

[0232] Pixel PX can receive data voltage in response to a scan signal. Pixel PX can emit light with a brightness corresponding to the data voltage in response to a transmit signal, and therefore, an image can be displayed. The emission time of pixel PX can be controlled by the transmit signal.

[0233] The aforementioned lines may include data lines DL1 to DLn. The pads connected to the aforementioned lines may include... Figure 13 The pad PD is shown in the figure. The display panel DP, where the luminescent layer of pixel PX is not formed, can be defined as the aforementioned target substrate M-SUB (see reference). Figure 4 ).

[0234] Figure 14 It is shown Figure 13 The image shows a cross-sectional view of one pixel.

[0235] An embodiment of the pixel PX can be disposed on a substrate BL and can include a transistor TR and a light-emitting element OLED. The transistor TR and the light-emitting element OLED of the pixel PX can be connected to data lines DL1 to DLn and a first power line PLL1 and a second power line PLL2. The transistor TR and the light-emitting element OLED of the pixel PX can be connected to the pad PD via data lines DL1 to DLn and the first power line PLL1 and the second power line PLL2.

[0236] An OLED (Light Emitting Diode) may include a first electrode AE, a second electrode CE, a hole control layer HCL, an electron control layer ECL, and a deposited pattern EML. In an embodiment, the deposited pattern EML may be referred to as the light-emitting layer EML. The first electrode AE ​​may be an anode electrode, and the second electrode CE may be a cathode electrode.

[0237] The transistor TR and the light-emitting element OLED can be disposed on the substrate BL. In an embodiment, for example, a transistor TR is shown; however, the pixel PX may include multiple transistors and at least one capacitor to drive the light-emitting element OLED.

[0238] The display area DA may include a light-emitting area PA corresponding to a pixel PX and a non-light-emitting area NPA surrounding the light-emitting area PA. The light-emitting element OLED may be disposed in the light-emitting area PA.

[0239] The substrate BL may include a flexible plastic substrate. In an embodiment, for example, the substrate BL may include transparent polyimide (PI). A buffer layer BFL may be disposed on the substrate BL, and the buffer layer BFL may be an inorganic layer.

[0240] Semiconductor patterns can be disposed on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon; however, it should not be limited to or restricted by this. According to embodiments, the semiconductor pattern may include amorphous silicon or metal oxide.

[0241] Semiconductor patterns can be doped with N-type or P-type dopants. Semiconductor patterns can include highly doped and lightly doped regions. The highly doped region can have a higher conductivity than the lightly doped region and can essentially serve as the source electrode (SD) and drain electrode (DD) of the transistor TR. The lightly doped region can essentially correspond to the active region (AD) (or channel region) of the transistor TR.

[0242] The source electrode SD, active region AD, and drain electrode DD of transistor TR can be formed from a semiconductor pattern. A first insulating layer 10 can be disposed on the semiconductor pattern. The gate electrode GD of transistor TR can be disposed on the first insulating layer 10. A second insulating layer 20 can be disposed on the gate electrode GD. A third insulating layer 30 can be disposed on the second insulating layer 20.

[0243] The connecting electrodes CNE1 and CNE2 can be disposed between the transistor TR and the light-emitting element OLED to connect the transistor TR to the light-emitting element OLED. The connecting electrodes CNE1 and CNE2 may include a first connecting electrode CNE1 and a second connecting electrode CNE2.

[0244] The first connecting electrode CNE1 can be disposed on the third insulating layer 30 and can be connected to the wire pattern SCL via a first contact hole CNT-1 defined by the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30. Figure 14 In the diagram, the line pattern SCL is spaced apart from the drain electrode DD, but the line pattern SCL can be connected to the drain electrode DD in the plan view. The line pattern SCL can extend from the drain electrode DD in the plan view. The line pattern SCL and the drain electrode DD can be made of the same material. A fourth insulating layer 40 can be disposed on the first connecting electrode CNE1. A fifth insulating layer 50 can be disposed on the fourth insulating layer 40.

[0245] The second connecting electrode CNE2 can be disposed on the fourth insulating layer 40. The second connecting electrode CNE2 can be connected to the first connecting electrode CNE1 via the second contact hole CNT-2 defined by the fourth insulating layer 40. The fifth insulating layer 50 can be disposed on the second connecting electrode CNE2. Each of the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40, and the fifth insulating layer 50 can be an inorganic layer or an organic layer.

[0246] A first electrode AE ​​can be disposed on a fifth insulating layer 50. The first electrode AE ​​can be connected to a second connecting electrode CNE2 via a third contact hole CNT-3 defined through the fifth insulating layer 50. A pixel defining layer PDL can be disposed on the first electrode AE ​​and the fifth insulating layer 50 to expose a portion of the first electrode AE. An opening PX_OP can be defined by the pixel defining layer PDL to expose a portion of the first electrode AE.

[0247] The hole control layer (HCL) can be disposed on the first electrode (AE) and the pixel definition layer (PDL). The HCL can also be commonly disposed in the light-emitting region (PA) and the non-light-emitting region (NPA). The HCL may include a hole transport layer and a hole injection layer.

[0248] The luminescent layer (EML) can be disposed on the hole control layer (HCL). The EML can be disposed in the region corresponding to the opening (PX_OP). The EML can include organic and / or inorganic materials. The EML can generate light with one of the following colors: red, green, and blue.

[0249] The electronic control layer (ECL) can be disposed on the light-emitting layer (EML) and the hole control layer (HCL). The ECL can be commonly disposed in the light-emitting region (PA) and the non-light-emitting region (NPA). The ECL may include an electron transport layer and an electron injection layer.

[0250] The second electrode CE can be disposed on the electronic control layer ECL. The second electrode CE can be commonly distributed throughout the pixel PX.

[0251] A thin-film encapsulation layer (TFE) can be disposed on the light-emitting element (OLED). The TFE can also be disposed on the second electrode (CE) to cover the pixel (PX). The TFE can include at least two inorganic layers and an organic layer disposed between the inorganic layers. The inorganic layers protect the pixel (PX) from moisture and oxygen. The organic layers protect the pixel (PX) from foreign substances such as dust particles.

[0252] A first voltage can be applied to the first electrode AE ​​via transistor TR, and a second voltage having a lower level than the first voltage can be applied to the second electrode CE. Holes and electrons injected into the light-emitting layer EML can recombine to generate excitons, and the light-emitting element OLED can emit light by excitons returning (transitioning) from the excited state to the ground state.

[0253] Figure 15 It is shown by Figure 4 A view of the deposition process performed by the deposition equipment shown.

[0254] Reference Figure 15 The components from the substrate BL to the hole control layer HCL can be connected to... Figure 4 The target substrate M-SUB shown corresponds to this.

[0255] Mask component MA (reference) Figure 4 The mask assembly (MA) can be configured to face the target substrate M-SUB. However, for illustrative purposes, only the portion included in the mask assembly (see reference 100000) is shown. Figure 4 It is part of the shadow mask SM in ) and other parts are omitted.

[0256] Mask component MA (reference) Figure 4 (It can be set to be close to the target substrate M-SUB).

[0257] The deposition material DM can be provided onto the target substrate M-SUB through the first opening OP1 and the second opening OP2. The luminescent layer EML can be formed on the target substrate M-SUB through the deposition material DM.

[0258] According to an embodiment of the method for manufacturing a mask assembly, a mask assembly MA capable of reducing the occurrence of shadow areas can be manufactured (see reference). Figure 4 ).

[0259] Furthermore, according to an embodiment of the method for manufacturing a mask assembly, the mask assembly MA (refer to...) can be simplified. Figure 4 This manufacturing process can reduce manufacturing time and costs.

[0260] When using a mask assembly MA (refer to) manufactured by a method for manufacturing a mask assembly according to embodiments of the present disclosure... Figure 4 When using deposition processes, the yield and reliability of the deposition process can be improved. Therefore, the quality of DP (display devices manufactured via deposition processes) can be improved. Figure 13 (Resolution, brightness, and lifespan)

[0261] This invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be exhaustive and complete, and will fully convey the concept of the invention to those skilled in the art.

[0262] Although the invention has been specifically shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A method for manufacturing a mask assembly, wherein, The method includes: Provide wafers; A first inorganic layer is formed on the wafer; A second inorganic layer is formed on the first inorganic layer; The wafer is etched to form cell openings; A photosensitive layer is formed on the rear surface of the first inorganic layer exposed through the unit opening; Etch the photosensitive layer to form multiple photosensitive openings; Isotropic etching of the first inorganic layer to form a plurality of first openings overlapping the plurality of photosensitive openings; and The second inorganic layer is anisotropically etched to form a plurality of second openings that overlap with the plurality of first openings.

2. The method according to claim 1, wherein, The formation of the plurality of first openings includes wet etching of the first inorganic layer along a direction from the rear surface of the first inorganic layer to the upper surface of the first inorganic layer.

3. The method according to claim 1, wherein, The formation of the plurality of second openings includes dry etching of the second inorganic layer along a direction from the rear surface of the second inorganic layer to the upper surface of the second inorganic layer.

4. The method according to claim 1, wherein, The formation of the first inorganic layer includes depositing one of silicon oxide and aluminum oxide on the upper surface of the wafer using a chemical vapor deposition process, and The formation of the second inorganic layer includes depositing silicon nitride on the upper surface of the first inorganic layer by a chemical vapor deposition process.

5. The method according to claim 1, wherein, The formation of the plurality of first openings includes etching the portion of the rear surface of the first inorganic layer exposed through the plurality of photosensitive openings in a direction from the rear surface of the first inorganic layer to the upper surface of the first inorganic layer.

6. The method according to claim 1, wherein, The formation of the plurality of second openings includes etching the portion of the rear surface of the second inorganic layer exposed through the plurality of first openings in a direction from the rear surface of the second inorganic layer to the upper surface of the second inorganic layer.

7. The method according to claim 1, wherein, The method also includes removing the photosensitive layer.

8. The method according to claim 7, wherein, The removal of the photosensitive layer includes wet stripping of the photosensitive layer.

9. The method according to claim 7, wherein, After the formation of the plurality of first openings and before the removal of the photosensitive layer, each of the plurality of side surfaces of the first inorganic layer defining the plurality of first openings has an undercut shape when viewed in cross-section.

10. The method according to claim 1, wherein, The formation of the cell opening includes wet etching the wafer in a direction from the rear surface of the wafer to the upper surface of the wafer, and when viewed in cross-section, the cell opening has a width that decreases in the direction from the rear surface of the wafer to the upper surface of the wafer.

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