Probe card for chip testing, testing system, method, equipment and medium

Abstract

The invention provides a probe card for chip testing, a testing system, a testing method, equipment and a medium. The probe card includes: a circuit board; the switching substrate is connected with the circuit board; the probe part is configured to place a unit to be tested, the unit to be tested comprises at least one bare chip to be tested on the wafer, the bare chip to be tested comprises a physical layer, and the physical layer comprises a data transmitting end and a data receiving end; the first switching module is connected with the physical layer, and the first switching module is connected with a first external bare chip used for external function testing of the to-be-tested bare chip and a first terminal resistor unit used for external loopback testing of the to-be-tested bare chip; therefore, the first switching module is switched and connected between the first external bare crystal and the first terminal resistor unit. According to the invention, the chip which fails due to the problem of the bare chip to be tested can be screened out in advance in the wafer test stage, the test coverage rate of a chip interface is improved, the yield of packaged finished products is improved, and the problem of high packaging cost can be solved.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a probe card, test system, method, apparatus, and storage medium for chip testing. Background Technology

[0002] Chip testing refers to the inspection of a chip's functionality, performance, reliability, and stability. Testing chips can fully and quantitatively reflect various indicators of each chip, from its structure and function to its electrical characteristics. It can detect defective chips, thereby ensuring chip yield and production efficiency.

[0003] Chip testing includes wafer probing (CP) testing and final test (FT) testing after packaging. Only products that pass CP testing and FT testing can be shipped and delivered normally.

[0004] CP (Content Probe) testing generally refers to using a probe card connected to the chip's pins to test the performance and functionality of the chip on the wafer. FT (Firmware Test) testing is typically performed as a final test on the chip after downstream processes such as dicing, bonding, packaging, and aging. This is because processes like packaging may damage parts of the chip's circuitry, necessitating FT testing to select qualified finished products. Performing CP and FT testing on chips provides timely and effective feedback on product yield, reduces packaging costs, and ensures the quality of products leaving the factory. Summary of the Invention

[0005] At least one embodiment of this disclosure provides a probe card for chip testing, comprising: a circuit board; an adapter substrate connected to the circuit board; a probe section configured to place a unit under test (DUT), wherein the DUT includes at least one bare die of a chip under test on a wafer, the bare die of the chip under test includes a physical layer and the physical layer includes a data transmitting end and a data receiving end; and a first switching module connected to the physical layer, wherein the first switching module is respectively connected to a first external bare die for external functional testing of the bare die of the chip under test and a first terminating resistor unit for external loopback testing of the bare die of the chip under test, so that the first switching module switches between the first external bare die and the first terminating resistor unit.

[0006] At least one embodiment of this disclosure provides a testing system including a probe card as in any of the examples above, wherein the testing system further includes a testing machine connected to the circuit board of the probe card.

[0007] At least one embodiment of this disclosure also provides a test method for chip testing, comprising: triggering a test command and acquiring test data based on an acquired probe card for testing a unit under test (DUT), wherein the DUT includes at least one bare die of a chip under test on a wafer, the bare die of the chip under test includes a physical layer and the physical layer includes a data transmitter and a data receiver; switching between external loopback testing and external functional testing of the bare die of the chip under test in response to the test command; transmitting the test data to a first terminating resistor unit through the data transmitter in response to the external loopback testing, and acquiring response data corresponding to the test data through the data receiver to obtain a test result; and transmitting the test data to a first external bare die through the data transmitter in response to the external functional testing, and acquiring response data corresponding to the test data through the data receiver to obtain a test result.

[0008] At least one embodiment of this disclosure provides an electronic device, including a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, it implements a test method as in any of the examples above.

[0009] At least one embodiment of this disclosure provides a computer-readable storage medium, wherein a computer program is stored within the storage medium, and when executed by a processor, the computer program implements a test method as described in any of the above examples. Attached Figure Description

[0010] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0011] Figure 1 This is a schematic diagram illustrating the composition of a probe card provided in some embodiments of this disclosure;

[0012] Figure 2 This is a schematic diagram of a probe card for chip testing provided in some embodiments of this disclosure;

[0013] Figure 3 A schematic diagram of a probe card for chip testing provided for other embodiments of this disclosure;

[0014] Figure 4 A test process flowchart provided for some embodiments of this disclosure;

[0015] Figure 5 This is a schematic diagram of the composition of a test system provided in some embodiments of this disclosure;

[0016] Figure 6 A flowchart illustrating a test method for chip testing provided for some embodiments of this disclosure;

[0017] Figure 7 This diagram illustrates an implementation method for probe cards and wafer testing, provided for some embodiments of this disclosure.

[0018] Figure 8 This is a schematic diagram of the structure of an electronic device provided in at least one embodiment of the present disclosure. Detailed Implementation

[0019] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0020] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0021] The term "comprising" and its variations as used herein are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below. It should be noted that the concepts of "first", "second", etc., used in this disclosure are only used to distinguish different devices, modules, or units, and are not intended to limit the order of functions performed by these devices, modules, or units or their interdependencies. It should be noted that the modifications "a" and "a plurality" used in this disclosure are illustrative and not restrictive, and those skilled in the art should understand that unless explicitly indicated in the context, they should be understood as "one or more". The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of these messages or information.

[0022] Currently, in CP testing, the wafer under test is placed on a probe card, which contains fixed probes. During testing, all test procedures are transmitted to the wafer via these probes. The probes can input various signals to the die on the wafer and can also capture the output from the die. After testing each die, the probe station moves to the next die to continue testing other dies, thus screening out defective chips before packaging.

[0023] This research reveals that, due to limitations in test hardware, CP testing typically only performs internal loopback testing on the die under test (e.g., a DDR die, where DDR refers to Double Data Rate Synchronous Dynamic Random Access Memory), failing to test external loopback testing or external functional tests requiring connection to external dies. This results in low CP test coverage. To address this issue, FT testing is currently required to increase coverage. However, this approach still requires improving chip yield and may lead to high packaging costs and limited test speeds.

[0024] At least one embodiment of this disclosure provides a probe card for chip testing, comprising: a circuit board; an adapter substrate connected to the circuit board; a probe section configured to place a unit under test (DUT), wherein the DUT includes at least one bare die of a chip under test on a wafer, the bare die of the chip under test includes a physical layer and the physical layer includes a data transmitting end and a data receiving end; and a first switching module connected to the physical layer, wherein the first switching module is respectively connected to a first external bare die for external functional testing of the bare die of the chip under test and a first terminating resistor unit for external loopback testing of the bare die of the chip under test, so that the first switching module switches between the first external bare die and the first terminating resistor unit.

[0025] At least one embodiment of this disclosure also provides a testing system including the probe card as described above, the testing system further including a testing machine, and the testing machine being connected to the circuit board of the probe card.

[0026] The probe card of the above embodiments of this disclosure can not only realize internal loopback testing in the CP testing phase, but also realize external loopback testing of the test object and external functional testing of the test object with external dies in the CP phase. The embodiments of this disclosure can screen out chips that fail due to problems with the bare die under test in advance in the CP testing phase, improve chip interface test coverage and improve the yield of the packaged finished product (i.e., FT yield), and also solve the problem of high packaging costs.

[0027] In some embodiments of this disclosure, some terms are defined as follows:

[0028] PCIE: Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard.

[0029] DDR SDRAM: Double Data Rate Synchronous Dynamic Random Access Memory, commonly referred to as DDR; DDR stands for Double Data Rate, and SDRAM stands for Synchronous Dynamic Random Access Memory; for example, in this article, DDR refers to Double Data Rate Synchronous Dynamic Random Access Memory.

[0030] MIPI: Mobile Industry Processor Interface, is an open standard developed for mobile application processors.

[0031] SERDES: Serializer / Deserializer, short for SERializer / DESerializer. It is a mainstream time-division multiplexing, point-to-point serial communication technology.

[0032] Die: refers to a wafer particle, die, bare die, or bare chip, which is an unpackaged chip at the wafer level.

[0033] Chip Probing Test (CP test): This refers to wafer testing. CP testing involves using probes to poke the chip pins to test the performance and functionality of the chips on the wafer.

[0034] Final Test: Also known as FT test. FT test is usually the final test performed on a chip after subsequent processes such as dicing, bonding, packaging, and aging.

[0035] Loopback Test: Also known as loopback test, it refers to the process where a signal sent from a communication device returns (loops back) to its original location. It can determine whether the device is operating normally or identify failed nodes in the network.

[0036] The embodiments and examples of this disclosure will now be described in detail with reference to the accompanying drawings.

[0037] Figure 1 This is a schematic diagram illustrating the composition of a probe card provided in some embodiments of this disclosure. Figure 2 This is a schematic diagram of a probe card for chip testing provided in some embodiments of this disclosure.

[0038] For example, such as Figure 1As shown, embodiments of this disclosure provide a probe card 100 for chip testing. The probe card 100 is test hardware for CP testing of a chip, and the test object for CP testing is a chip die.

[0039] For example, such as Figure 1 As shown, the probe card 100 includes a circuit board 110, an adapter substrate 120, a probe section 130, and a first switching module 140. The adapter substrate 120 is connected to the circuit board 110, and the probe section 130 is configured to place a device under test (DUT) 200, which includes at least one bare die 200a (or simply die under test) on a wafer.

[0040] For example, circuit board 110 is a printed circuit board (PCB), that is, circuit board 110 is a probe card PCB. In this article, circuit board 110 can be simply referred to as PCB board 110.

[0041] For example, the adapter substrate 120 refers to an interface or substrate, and thus, the adapter substrate 120 can also be called a carrier board or substrate. For example, the adapter substrate 120 can be an MLO (Multi Layer Organic), which can be fixed to the PCB by ball bonding or conductive adhesive. The MLO is like a scaled-down version of the PCB. The MLO is different from the circuit board 110 and is thinner than the circuit board 110.

[0042] For example, such as Figure 1 As shown, the probe section 130 includes a probe head 131 and probes 132. The probe section 130 can be mounted on the adapter substrate 120. The probes 132 are fixed by the probe head 131. The probes 132 are used to contact or connect to each die 200a of the chip under test on the wafer. For example, in the CP testing phase, one die 200 is one chip. Of course, this is merely exemplary and is not a limitation of the embodiments of this disclosure.

[0043] For example, such as Figure 1 and Figure 2 As shown, the bare die 200a of the chip under test includes a physical layer 210 (PHY), and the physical layer 210 includes a data transmitter 211 and a data receiver 212.

[0044] For example, in Figure 2In this example, physical layer 210 can also be called port physical layer. Physical layer 210 can send and receive corresponding data frames. The first switching module 140 is connected to physical layer 210. The first switching module 140 is connected to the first external die 150 for functional testing (also called external functional testing) of die 200a under test and the first terminating resistor unit 160 for external loopback testing of die 200a under test, so that the first switching module 140 switches between the first external die 150 and the first terminating resistor unit 160.

[0045] The probe cards in some embodiments of this disclosure can be used for chip interface testing, improving coverage of tests such as DDR interfaces in CP testing. For example, in Figure 2 In the example, physical layer 210 can be a high-speed physical layer interface, which can be understood as a module integrating the functions of a physical layer port and a high-speed I / O interface. Of course, this is merely exemplary and not a limitation of the embodiments of this disclosure; for example, the relationship between the physical layer port and the high-speed I / O interface could also be... Figure 3 The situation is illustrated below.

[0046] The probe card of the above embodiments of this disclosure can not only realize internal loopback testing in the CP testing phase, but also realize external loopback testing of the die under test and external functional testing (also referred to as functional testing in this document) when the die under test is connected to a die in the CP testing phase. The embodiments of this disclosure can screen out chips that fail due to problems with the die under test in advance in the CP testing phase, and the failed chips are not packaged, thereby improving the chip interface test coverage and FT yield, and also solving the problem of high packaging costs.

[0047] In the embodiments of this disclosure, the self-testing form of loopback testing can help test the physical links of integrated circuit chips. Loopback testing is generally divided into internal loopback testing and external loopback testing. Internal loopback testing in the embodiments of this disclosure refers to forming a loopback path inside the device under test (DUT) without passing through the outside of the chip. External loopback testing in the embodiments of this disclosure refers to the test signal passing through the outside of the DUT and returning to the inside of the DUT to form a corresponding loopback path. For example, in the embodiments of this disclosure, an external loopback test path is formed through an externally connected terminating resistor.

[0048] In some examples, when the die under test 200a includes a die under test for Double Data Rate Synchronous Dynamic Random Access Memory (DRAM) (also referred to as the DDR die under test), embodiments of this disclosure can test the DDR external loopback during the CP test phase, thereby overcoming the problem that the CP test in existing solutions cannot test the DDR external loopback. Furthermore, embodiments of this disclosure can also test the external functionalities of externally connected DDR chips during the CP test phase, thereby overcoming the problem that the CP test in existing solutions cannot test the external functionalities of externally connected DDR chips.

[0049] For the sake of clarity and conciseness, many examples in this disclosure use DDR chips as the test object and DDR test items as examples for illustration. However, the embodiments of this disclosure do not limit the chip type of the test object or the test item category. For example, it can also be a scenario of testing MIPI or PCIe. The specific technical solutions and effects can be similarly referred to the scenario of testing DDR. The embodiments of this disclosure will not be exhaustive or elaborated here.

[0050] In the embodiments of this disclosure, taking DDR as an example, the test signal can pass through the outside of the DDR Die 200a under test, for example, through a DDR Die connected externally relative to the DDR under test, and return to the inside of the DDR Die 200a, thereby completing the external function test of the DDR. For example, in the case of external function testing, after the data is written to the external DDR chip, it can be saved, and the data can be read from the external DDR chip at intervals (e.g., ten minutes), without the need for real-time data reading. In contrast, for external loopback testing with a terminating resistor, real-time data reading and writing are required.

[0051] In some examples, a signal connection can be established between the data transmitter 211 and the data receiver 212, thereby enabling internal loopback testing of the bare die 200a under test. For example, Figure 2 The dashed arrow in the box containing 200a shows the path of the internal loopback test.

[0052] For example, such as Figure 2 As shown, the die under test 200a may further include a control unit 220, which is connected to the physical layer 210 and configured to generate test data to implement the aforementioned internal loopback test, external functional test, and external loopback test. In the embodiments of this disclosure, the external functional test and external loopback test of the die under test 200a can be collectively referred to as the external test of the die under test.

[0053] The embodiments of this disclosure can perform internal loopback, external loopback, and external functional tests during CP testing. Some embodiments of this disclosure, by setting external functional tests and external loopback tests, such as those for DDR, to be performed first during the CP phase, can screen out all DDR external functional defective chips in advance during the CP phase and can also check for process problems in DDR external functional defective chips. In the embodiments of this disclosure, after problematic chips are screened out through CP testing, these chips will not be packaged, thus reducing packaging costs. Therefore, the embodiments of this disclosure not only overcome the limitations of existing solutions in terms of testing functionality but also improve chip interface test coverage and chip yield, while avoiding unnecessary packaging costs.

[0054] For example, such as Figure 2 As shown, the control unit 220 includes a pattern generator 221 and an error detector 222. The pattern generator 221 can generate data for testing, and this generated data can be regarded as test data. The error detector 222 can determine the test result based on the received signal. For example, the error detector 222 can compare the received signal with a reference signal to determine the detection result. For example, the error detector 222 compares the received signal A1 with the test data B1 generated by the pattern generator 221 to determine whether they are consistent. If they are consistent, the test result is that the test passes; if they are inconsistent, the test result is that the test fails. Of course, this is merely an example and is not a limitation of the embodiments of this disclosure. It can be freely set according to the actual situation, and will not be elaborated here.

[0055] For example, such as Figure 1 and Figure 2 As shown, in the embodiments of this disclosure, the first external die 150 refers to a die that is an external component or structure relative to the die 200a of the chip under test (DUT), and the first external die 150 corresponds to the die 200a of the DUT, thereby enabling the testing of external functional aspects of the die 200a. For example, if the die 200a of the DUT is a DDR die, then the first external die 150 is an external DDR die. As another example, if the die 200a of the DUT is a PCIe die, then the first external die 150 is an external PCIe die. Yet another example, if the die 200a of the DUT is a Serdes die, then the first external die 150 is an external Serdes die. For example, the first switching module 140 in the embodiments of this disclosure can also be a switching die corresponding to the die 200a of the chip under test. For example, if the die 200a of the chip under test is a DDR die, then the first switching module 140 is a switching die for DDR testing (which can be referred to as DDR Switch Die). Other cases are similar and will not be described in detail here.

[0056] The embodiments disclosed herein can be used not only to test DDR, but also extended to other modules under test and IP (Intellectual Property) modules. For example, similar methods can be used to test MIPIDie, PCIE Die, SerDes Die, etc. Of course, this is merely exemplary and is not a limitation of the embodiments disclosed herein.

[0057] In some examples, if the die 200a under test includes a first die under test for double data rate synchronous dynamic random access memory (i.e., the DDR die under test), the first external die 150 includes a second die for double data rate synchronous dynamic random access memory class that matches the first die under test (i.e., the external DDR die), and the first switching module 140 is the corresponding DDR switching die (i.e., the DDR switch die). In other examples, the die under test 200a includes a third die under test, for example, the third die under test is configured as a die for at least one of a mobile industry processor interface, a high-speed serial computer expansion bus interface, and a serial / deserializer (such as a MIPI die, PCIE die, or Serdes die). The first external die 150 includes a fourth die (such as an external MIPI die, PCIE die, or Serdes die) of at least one of a mobile industry processor interface, a high-speed serial computer expansion bus interface, and a serial / deserializer that matches the first die under test. The first switching module 140 is a corresponding switching die (such as a MIPI switch die, PCIE switch die, or Serdes switch die). Of course, the above are merely exemplary and are not intended to limit the embodiments of this disclosure. Any integrated circuit chip with a physical layer and control unit as described in the examples is acceptable, and further enumeration is not required.

[0058] The embodiments disclosed herein can not only improve chip interface test coverage and chip yield, but also have strong scalability.

[0059] Figure 3 This is a schematic diagram of a probe card for chip testing, provided for other embodiments of this disclosure.

[0060] For example, such as Figure 3 As shown, compared to Figure 2 Example, Figure 3 It may also include a high-speed I / O interface module 230, which is connected between the first switching module 140 and the physical layer 210. Figure 3 For the other parts of the example, please refer to the relevant... Figure 2 The examples will not be repeated here.

[0061] like Figure 2 As shown, the first terminating resistor unit 160 in the embodiments of this disclosure refers to a terminating resistor, such as a 50-ohm terminating resistor. It should be noted that the first terminating resistor unit 160 can be a resistive element or a resistive circuit. The embodiments of this disclosure do not limit this, as long as it can realize the use of the terminating resistor to achieve external loopback testing. It will not be exhaustively described here.

[0062] For example, such as Figure 2 As shown, for external loopback testing during the CP phase, the bare die 200a of the chip under test in this embodiment can transmit test data to the first terminating resistor unit 160 via the data transmitter 211, and obtain response data corresponding to the test data via the data receiver 212 to obtain the corresponding test results. For example, as Figure 2 As shown, for external functional testing during the CP phase, the die 200a under test of this embodiment transmits test data to the first external die 150 through the data transmitter 211, and obtains response data corresponding to the test data through the data receiver 212 to obtain the corresponding test results.

[0063] In some examples, at least one of the first external bare die 150, the first terminating resistor unit 160, and the first switching module 140 may be disposed on the adapter substrate 120. For example, as Figure 1 and Figure 2 As shown, the first external bare die 150, the first terminating resistor unit 160 and the first switching module 140 are all disposed on the adapter substrate 120.

[0064] In embodiments of this disclosure, the first switching module 140 is placed in the adapter substrate 120. The first switching module 140 can be switched to the first terminating resistor unit 160 (for example, the first terminating resistor unit 160 can also be placed in the adapter substrate 120). This results in a short connection distance between the first terminating resistor unit and the die under test (DUT), leading to excellent signal integrity (SI) and significantly improving the test speed. This allows the tests in embodiments of this disclosure to meet product specifications. Alternatively, embodiments of this disclosure can also place the first external die 150 in the adapter substrate 120. This results in a short connection distance between the first external die 150 and the DUT, excellent signal integrity, and significantly improved test speed. Furthermore, based on the good signal integrity, full-speed functional tests (such as DDR full-speed functional tests) and external loopback tests (such as DDR external loopback tests) can be run.

[0065] Compared to existing solutions that use FT testing for external loopback testing of chips, resulting in poor signal integrity and test rates that often fail to meet product specifications, the adapter substrate 120 of the present disclosure is designed to improve signal integrity. The CP test hardware has excellent signal integrity and strong scalability.

[0066] Based on some embodiments of the probe card disclosed herein, a scheme for testing the signal integrity of CP testing hardware is provided. In some examples, at least one of the first switching module 140, the first external die 150, and the first terminating resistor unit 160 is disposed on the surface of the adapter substrate 120. For example, as Figure 1 and Figure 2 As shown, the first switching module 140, the first external bare die 150, and the first terminating resistor unit 160 are all disposed on the surface of the adapter substrate 120.

[0067] Therefore, the embodiments of this disclosure, by placing the added first switching module 140, first external bare die 150, and first terminating resistor unit 160 on the surface of the adapter substrate 120, are highly feasible and more conducive to improving signal integrity.

[0068] It should be noted that the embodiments of this disclosure do not limit which specific side of the surface of the adapter substrate 120 each of the first switching module 140, the first external bare die 150, and the first terminating resistor unit 160 is located on; this can be determined according to the actual situation. Figure 1 The positions and arrangements shown in the illustrations are merely schematic and exemplary, and are not intended to limit the embodiments of this disclosure.

[0069] In some examples, at least one of the first switching module 140, the first external die 150, and the first terminating resistor unit 160 is connected to the surface of the adapter substrate 120 via a ball-and-point connection. For example, as... Figure 1 As shown, the ball-point connections between the various components can be referenced. Figure 1 As shown at various spheres, such as between the first external bare die 150 and the adapter substrate 120, between the first switching module 140 and the adapter substrate 120, or between the circuit board 110 and the adapter substrate 120, etc. Of course, this is merely exemplary and is not a limitation of the embodiments of this disclosure. It can be determined according to the actual situation, and will not be elaborated here.

[0070] The embodiments of this disclosure achieve the connection between two corresponding structures by connecting balls, which is convenient to operate and provides better contact and connection effects.

[0071] In some examples, at least one of the first switching module 140, the first external die 150, and the first terminating resistor unit 160 is soldered onto the adapter substrate 120.

[0072] The embodiments of this disclosure improve signal integrity by soldering auxiliary test components (for example, DDR switch die, DDR die, or terminating resistor) onto the adapter substrate 120.

[0073] For example, such as Figure 1 As shown, at least one embodiment of this disclosure provides a testing system that includes not only any of the probe cards 100 described above, but also a testing machine 300 connected to the circuit board 110 of the probe card 100. For example, the testing machine 300 may be an Automatic Test Equipment (ATE). Thus, embodiments of this disclosure perform CP testing on the ATE's platform, thereby identifying chips that fail externally during the CP stage.

[0074] It should be noted that the specific implementation and technical effects of the testing system in the embodiments of this disclosure can be referred to the description of the probe card above, and will not be repeated here.

[0075] Figure 4 This is a test process flowchart provided for some embodiments of this disclosure.

[0076] For example, such as Figure 4 As shown, the test process for chip testing in some embodiments of this disclosure includes steps S1 to S5.

[0077] Step S1: Obtain a wafer, wherein the wafer includes one or more bare dies of the chip under test (also referred to as the die under test).

[0078] Step S2: Perform CP test on each Die to be tested; In step S2, the Die to be tested in CP test is the Die.

[0079] Step S3: After the CP test of the Die is completed, the Die is packaged to obtain the packaged chip.

[0080] Step S4: Perform FT test on the Chip; In step S4, the object to be tested in the FT test is the Chip that has been packaged.

[0081] Step S5, chip sorting, to achieve high-quality product shipment. For example, in step S5, chip sorting refers to the process of classifying chips according to their performance parameters and placing them into different chip boxes. Chip sorting is an important step in the semiconductor manufacturing process, ensuring that the performance and quality of the chips meet expectations, and also providing suitable product selection for different application scenarios.

[0082] In some examples, taking the DDR Die as an example, the CP test in step S2 includes DDR internal loopback test, DDR external loopback test and DDR external function test.

[0083] The test process of the embodiments of this disclosure can realize internal loopback testing and external testing in the CP stage, improve chip interface test coverage and chip yield, and avoid unnecessary packaging costs.

[0084] In some examples, the test process for chip testing in embodiments of this disclosure can omit step S4 after the internal loopback test and external test of the CP stage have been completed. This can significantly reduce packaging costs. For example, step S4 can be omitted in scenarios where the packaging process is mature or superior. Of course, this is merely exemplary and not a limitation of the embodiments of this disclosure. It can be adjusted according to actual conditions, and will not be exhaustively described here.

[0085] Figure 5 This is a schematic diagram illustrating the composition of a testing system provided in some embodiments of this disclosure.

[0086] For example, such as Figure 5 As shown, the test system of this disclosure embodiment further includes: a finished product test module 400 for post-packaging finished product testing (FT testing), the finished product test module 400 including a test load board 410 and a test socket 420. The test socket 420 is provided with a method for placing the target chip under test 500 (i.e., Figure 4 The test pin 421 of the Chip shown is the target chip 500, which is the chip after the unit under test 200 has been packaged.

[0087] For example, such as Figure 5 As shown, the test load board 410 is equipped with a second switching module 430, a second external chip 440 for functional testing (i.e., external functional testing) of the target chip under test 500, and a second terminating resistor unit (not shown) for external loopback testing of the target chip under test 500. The second switching module 430 is connected to the second external chip 440 and the second terminating resistor unit respectively, so that the second switching module 430 switches between the second external chip 440 and the second terminating resistor unit.

[0088] The embodiments of this disclosure can not only realize internal loopback testing (and / or external loopback testing and external functional testing of bare die) in the CP testing stage, but also realize external loopback, internal loopback and external functional testing of packaged chips in the FT testing stage, which can effectively reduce the failure rate and improve chip yield, and has a wider range of applications.

[0089] It should be noted that, for the FT test in the embodiments of this disclosure, it can not only use the above-mentioned setting of the second switching module 430 to connect the second external chip 440 or the second terminating resistor unit to realize the external function test or the external loopback test, but also use only the second terminating resistor unit connected on the test load board 410 to realize the external loopback test, or use only the second external chip 440 connected on the test load board 410 to realize the external function test. The embodiments of this disclosure do not limit this, and can be selected according to the actual situation, which will not be elaborated here.

[0090] For example, in embodiments of this disclosure, the second external chip 440 refers to a chip that is an external component or structure relative to the target chip under test 500, and the second external chip 440 corresponds to the target chip under test 500. For example, if the target chip under test 500 is a DDR chip, then the second external chip 440 is an external DDR chip. As another example, if the target chip under test 500 is a PCIe chip, then the second external chip 440 is an external PCIe chip. Yet another example, if the target chip under test 500 is a SerDes chip, then the second external chip 440 is an external SerDes chip. For instance, the second switching module 430 in embodiments of this disclosure can also be a switching chip corresponding to the target chip under test 500. For example, if the target chip under test 500 is a DDR chip, then the second switching module 430 is a switching chip for DDR testing (which can be denoted as a DDRSwitch Chip), and other cases are similar, and will not be elaborated further here.

[0091] In some examples, at least one of the second switching module 430, the second external chip 440, and the second terminating resistor unit is disposed on the surface of the test load board 410. For example, as Figure 5 As shown, the second switching module 430, the second external chip 440, and the second terminating resistor unit are all disposed on the surface of the test load board 410. Thus, for FT testing, the embodiment of this disclosure exhibits excellent signal integrity, increased test speed, and good achievement of product specifications.

[0092] It should be noted that in the embodiments of this disclosure, the testing system may include more or fewer modules, and the connection relationship between the modules is not limited and can be determined according to actual needs. The specific configuration of each module is not limited. For details on the specific implementation methods and technical effects of the testing system, please refer to the relevant content of the probe card provided in the above embodiments of this disclosure, which will not be repeated here.

[0093] The modules in the above embodiments can be configured as software, hardware, firmware, or any combination thereof to perform specific functions. For example, these modules may correspond to dedicated integrated circuits, pure software code, or modules combining software and hardware. It should be noted that although the test system is divided into modules for performing corresponding processes in the above description, those skilled in the art will understand that the processes performed by each module can also be performed without any specific module division or clear boundaries between modules.

[0094] Figure 6 This is a flowchart illustrating a test method for chip testing provided for some embodiments of this disclosure.

[0095] For example, such as Figure 6 As shown, at least one embodiment of this disclosure provides a test method for chip testing that includes steps T1 to T3.

[0096] T1. Based on the probe card already acquired for testing the unit under test, trigger the test command and acquire the test data. The unit under test includes the bare die of the chip under test on the wafer. The bare die of the chip under test includes a physical layer, and the physical layer includes a data transmitter and a data receiver.

[0097] T2. In response to test commands, switch between external loopback testing for the die under test and external functional testing for the die under test.

[0098] T3. In response to an external loopback test, the die under test transmits test data to the first terminating resistor unit through the data transmitter and obtains response data corresponding to the test data through the data receiver to obtain the test result; and, in response to an external functional test, the die under test transmits test data to the first external die through the data transmitter and obtains response data corresponding to the test data through the data receiver to obtain the test result.

[0099] The embodiments of this disclosure can screen out problematic chips, such as DDR chips, at the CP stage, so that these problematic chips do not need to be packaged, thus solving the problem of high packaging costs. Furthermore, the embodiments of this disclosure can show the true yield of DDR and the true wafer map of DDR during the CP test at the CP stage, thereby analyzing the cause of failure, improving the wafer manufacturing process, reducing the failure rate, and increasing the chip yield.

[0100] The testing methods of the embodiments of this disclosure are implemented through testing software, which includes multiple test items. For example, DDR test items are one type of all test items; that is, the testing software of the embodiments of this disclosure may include DDR test items. In some examples, the DDR test items include DDR internal loopback testing, DDR external loopback testing, and DDR external function testing for connecting external DDR chips. For DDR internal loopback testing, no testing hardware or signal integrity metrics of the testing hardware are required, while for DDR external loopback testing and DDR external function testing, signal integrity metrics of the testing hardware are required. For example, the testing methods in some embodiments of this disclosure are methods capable of testing high-speed signals during the CP testing phase.

[0101] In some examples, the testing method of embodiments of this disclosure further includes the following process or steps: in response to an internal loopback test for the bare die of the chip under test, obtaining test results based on test data and through a signal connection between a data transmitter and a data receiver.

[0102] The testing method of the embodiments of this disclosure can test internal loopback, external loopback, and external functional tests during CP testing.

[0103] In some examples, in response to a die under test including a first die under test for double-rate synchronous dynamic random access memory, the die under test transmits test data to a first external die via a data transmitter, including: the first die under test transmitting test data to a second die of a double-rate synchronous dynamic random access memory class matched with the first die under test via a data transmitter.

[0104] In some examples, in response to a third die under test (DUT) including at least one of a mobile industry processor interface, a high-speed serial computer expansion bus interface, and a serializer / deserializer, the DUT transmits test data to a first external die via a data transmitter, including: the third DUT transmitting test data via a data transmitter to a fourth die of at least one of a mobile industry processor interface, a high-speed serial computer expansion bus interface, and a serializer / deserializer that is matched to the third DUT.

[0105] The embodiments disclosed herein can not only improve chip interface test coverage and chip yield, but also have strong scalability.

[0106] It should be noted that the specific implementation and technical effects of the test method for chip testing in the embodiments of this disclosure can be referred to the description of the probe card and test system above, and will not be repeated here.

[0107] Figure 7This diagram illustrates an implementation method for probe cards and wafer testing, provided in some embodiments of this disclosure. It should be noted that, for clarity and conciseness, [the following text is omitted as it is not part of the main text]. Figure 7 This explanation primarily uses DDR as an example for testing, but the embodiments disclosed herein are not limited to DDR. Figure 7 The method shown still applies to MIPI, PCIe, or SerDes, etc., and will not be elaborated here.

[0108] For example, such as Figure 7 As shown in some embodiments of this disclosure, a method for acquiring a probe card includes the following steps:

[0109] Step Q1: Design the probe section.

[0110] Step Q2: Fabricate the probe section, which includes a probe head and a probe.

[0111] Step Q3: Design the adapter board (e.g., MLO).

[0112] Step Q4: Process and manufacture the adapter substrate.

[0113] Step Q5: Solder the first external bare die (e.g., DDR die) to the adapter substrate.

[0114] Step Q6: Solder the first switching module (e.g., DDR Switch Die) to the adapter substrate.

[0115] Step Q7: Complete the entire fabrication of the adapter substrate.

[0116] Step Q8: Design the probe card PCB.

[0117] Step Q9: Fabricate the circuit board for the probe card.

[0118] Step Q10: Solder the adapter substrate to the circuit board of the probe card.

[0119] Step Q11: Assemble the probe section and the circuit board.

[0120] Step Q12: Complete the fabrication of the probe card.

[0121] In some examples, such as when DDR is the test object, embodiments of this disclosure will include DDR-related schematics and PCB layout designs during the design process of the adapter substrate. For example, the PCB layout design includes DDR-related internal interconnections. For example, the PCB layout design includes the placement locations of the DDR die and DDR switch die. For example, the PCB layout design includes the placement location of the first terminating resistor unit (e.g., a 50-ohm resistor). Of course, this is merely exemplary and not a limitation of the embodiments of this disclosure.

[0122] It should be noted that flowcharts are used in some embodiments of this disclosure to illustrate the steps of the method according to embodiments of this disclosure. It should be understood that the preceding or following steps are not necessarily performed in precise order. Instead, various steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes, or one or more steps can be removed from these processes.

[0123] by Figure 7 For example, this disclosure does not limit the order of the various processes or steps in this example. For instance, the embodiments of this disclosure do not limit the order of steps Q1, Q3, and Q8. For example, any one of these three can be executed as the first step. Of course, this is merely exemplary and is not a limitation on the embodiments of this disclosure.

[0124] For example, such as Figure 7 As shown in some embodiments of this disclosure, a method for implementing CP testing based on a probe card is provided, including the following steps:

[0125] Step Q13: After completing the fabrication of the probe card, install the probe card on the testing machine.

[0126] Step Q14: Develop software on the test machine to test the bare die of the chip under test (such as DDR, MIPI, PCIe or SerDes bare die).

[0127] Step Q15: Perform a CP test to obtain the corresponding test results.

[0128] Based on the probe card already obtained, the embodiments of this disclosure also require the development of related supporting test software for DDR external test items (DDR external loopback test and external function test of external DDR chips) to achieve CP test.

[0129] The following is for reference. Figure 8The diagram illustrates a structural schematic of an electronic device (e.g., a terminal device or a server) 600 suitable for implementing embodiments of the present disclosure. The terminal device in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 8 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0130] like Figure 8 As shown, electronic device 600 may include a processing device (e.g., a central processing unit, a graphics processor, etc.) 601, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 602 or a program loaded from storage device 606 into random access memory (RAM) 603. RAM 603 also stores various programs and data required for the operation of electronic device 600. Processing device 601, ROM 602, and RAM 603 are interconnected via bus 604. Input / output (I / O) interface 605 is also connected to bus 604.

[0131] Typically, the following devices can be connected to I / O interface 605: input devices 606 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 607 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 606 including, for example, magnetic tapes, hard disks, etc.; and communication devices 609. Communication device 609 allows electronic device 600 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 8 An electronic device 600 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0132] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication device 609, or installed from storage device 606, or installed from ROM 602. When the computer program is executed by processing device 601, it performs the functions defined in the methods of embodiments of this disclosure.

[0133] It should be noted that the computer-readable medium described in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0134] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol, such as HTTP (Hypertext Transfer Protocol), and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0135] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0136] The aforementioned computer-readable medium carries one or more programs that, when executed by the electronic device, cause the electronic device to: trigger test instructions and acquire test data based on an acquired probe card for testing the unit under test (DUT), wherein the DUT includes a bare die of a chip under test on a wafer, the bare die of the chip under test includes a physical layer, and the physical layer includes a data transmitter and a data receiver; in response to the test instructions, switch between external loopback testing and external functional testing of the bare die of the chip under test; in response to the external loopback testing, the bare die of the chip under test transmits test data to a first terminating resistor unit through the data transmitter and acquires response data corresponding to the test data through the data receiver to obtain test results; and in response to the external functional testing, the bare die of the chip under test transmits test data to a first external bare die through the data transmitter and acquires response data corresponding to the test data through the data receiver to obtain test results.

[0137] Computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof, including but not limited to object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0138] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0139] The units described in the embodiments of this disclosure can be implemented in software or in hardware. The name of a unit does not necessarily limit the unit itself; for example, the first switching module can also be described as "a module for switching between the first external bare die and the first terminating resistor unit".

[0140] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), and so on.

[0141] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0142] According to one or more embodiments of this disclosure, [Example 1] provides a probe card for chip testing, comprising: a circuit board; an adapter substrate connected to the circuit board; a probe section configured to place a unit under test (DUT), wherein the DUT includes at least one bare die of a chip under test on a wafer, the bare die of the chip under test includes a physical layer and the physical layer includes a data transmitting end and a data receiving end; a first switching module connected to the physical layer, wherein the first switching module is respectively connected to a first external bare die for external functional testing of the bare die of the chip under test and a first terminating resistor unit for external loopback testing of the bare die of the chip under test, so that the first switching module switches between the first external bare die and the first terminating resistor unit.

[0143] According to one or more embodiments of this disclosure, Example 2 provides a probe card similar to that of Example 1, wherein at least one of a first external bare die, a first terminating resistor unit, and a first switching module is disposed on an adapter substrate.

[0144] According to one or more embodiments of this disclosure, Example 3 provides a probe card similar to that of Example 2, wherein at least one of a first switching module, a first external die, and a first terminating resistor unit is disposed on the surface of the adapter substrate.

[0145] According to one or more embodiments of this disclosure, Example 4 provides a probe card similar to Example 3, wherein at least one of a first switching module, a first external die, and a first terminating resistor unit is connected to the surface of the adapter substrate via a ball-and-point connection.

[0146] According to one or more embodiments of this disclosure, Example 5 provides a probe card similar to that of Example 1, wherein at least one of a first switching module, a first external bare die, and a first terminating resistor unit is soldered onto an adapter substrate.

[0147] According to one or more embodiments of this disclosure, Example Six provides a probe card similar to that of Example One, wherein a data transmitter and a data receiver are signal-connected to enable internal loopback testing of the die under test; the die under test also includes a control unit, wherein the control unit is connected to the physical layer and configured to generate test data to enable internal loopback testing, external functional testing, and external loopback testing.

[0148] According to one or more embodiments of this disclosure, Example 7 provides a probe card of Example 1, wherein the die under test includes a first die under test for a double-rate synchronous dynamic random access memory, the first external die includes a second die of a double-rate synchronous dynamic random access memory class that matches the first die under test, and the first switching module is a switching die.

[0149] According to one or more embodiments of this disclosure, Example 8 provides a probe card of Example 1, wherein the die under test includes a third die under test, the third die under test being configured as a die for at least one of a mobile industry processor interface, a high-speed serial computer expansion bus interface, and a serial / deserializer, the first external die includes a fourth die of at least one of a mobile industry processor interface, a high-speed serial computer expansion bus interface, and a serial / deserializer that matches the third die under test, and the first switching module is a switching die.

[0150] According to one or more embodiments of this disclosure, [Example Nine] provides a testing system including the probe card of Example One, wherein the testing system further includes a testing machine connected to the circuit board of the probe card.

[0151] According to one or more embodiments of this disclosure, Example 10 provides the test system of Example 9, which further includes a finished product test module for testing the packaged finished product. The finished product test module includes a test load board and a test socket. The test socket is provided with test probes for placing a target chip under test. The target chip under test is the chip after the unit under test has been packaged.

[0152] According to one or more embodiments of this disclosure, Example 11 provides a test system of Example 10, wherein a test load board is provided with a second switching module, a second external chip for external functional testing of the target chip under test, and a second terminating resistor unit for external loopback testing of the target chip under test, wherein the second switching module is connected to the second external chip and the second terminating resistor unit respectively, so that the second switching module switches between the second external chip and the second terminating resistor unit.

[0153] According to one or more embodiments of this disclosure, Example Twelve provides a test system of Example Eleven, wherein at least one of a second switching module, a second external chip, and a second terminating resistor unit is disposed on the surface of a test load board.

[0154] According to one or more embodiments of this disclosure, [Example Thirteen] provides a test method for chip testing, comprising: triggering a test command based on an acquired probe card for testing a unit under test (DUT), and acquiring test data, wherein the DUT includes a bare die of a chip under test on a wafer, the bare die of the chip under test includes a physical layer, and the physical layer includes a data transmitter and a data receiver; in response to the test command, switching between an external loopback test for the bare die of the chip under test and an external functional test for the bare die of the chip under test; in response to the external loopback test, the bare die of the chip under test transmits test data to a first terminating resistor unit through the data transmitter, and acquires response data corresponding to the test data through the data receiver to obtain a test result; and in response to the external functional test, the bare die of the chip under test transmits test data to a first external bare die through the data transmitter, and acquires response data corresponding to the test data through the data receiver to obtain a test result.

[0155] According to one or more embodiments of this disclosure, Example Fourteen provides a test method similar to Example Thirteen, which further includes: in response to an internal loopback test for a bare die of a chip under test, acquiring test results based on test data and through a signal connection between a data transmitter and a data receiver.

[0156] According to one or more embodiments of this disclosure, Example XV provides a test method of Example XIII, wherein, in response to a die under test including a first die under test for a double-rate synchronous dynamic random access memory, the die under test transmits test data to a first external die via a data transmitter, including: the first die under test transmitting test data to a second die of a double-rate synchronous dynamic random access memory class matched with the first die under test via the data transmitter.

[0157] According to one or more embodiments of this disclosure, Example Sixteen provides a test method of Example Thirteen, wherein, in response to a third die under test including at least one of a mobile industry processor interface, a high-speed serial computer expansion bus interface, and a serializer / deserializer, the die under test transmits test data to a first external die via a data transmitter, including: the third die under test transmitting test data to a fourth die of at least one of a mobile industry processor interface, a high-speed serial computer expansion bus interface, and a serializer / deserializer that is matched with the third die under test via a data transmitter.

[0158] According to one or more embodiments of this disclosure, [Example Seventeen] provides an electronic device including: a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, it implements the test method in Example Thirteen.

[0159] According to one or more embodiments of this disclosure, [Example 18] provides a computer-readable storage medium, wherein the storage medium stores a computer program that, when executed by a processor, implements the test method in Example 13.

[0160] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0161] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0162] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A probe card for chip testing, comprising: Circuit board; An adapter substrate is connected to the circuit board. The probe section is configured to place a unit under test (DUT), wherein the DUT includes at least one bare die of a chip under test on a wafer, the bare die of the chip under test includes a physical layer and the physical layer includes a data transmitting end and a data receiving end; A first switching module is connected to the physical layer. The first switching module is connected to a first external die for external functional testing of the die under test and a first terminating resistor unit for external loopback testing of the die under test, so that the first switching module can switch between the first external die and the first terminating resistor unit.

2. The probe card as described in claim 1, wherein, At least one of the first external bare die, the first terminating resistor unit, and the first switching module is disposed on the adapter substrate.

3. The probe card as described in claim 2, wherein, At least one of the first switching module, the first external bare die, and the first terminating resistor unit is disposed on the surface of the adapter substrate.

4. The probe card as described in claim 3, wherein, At least one of the first switching module, the first external bare die, and the first terminating resistor unit is connected to the surface of the adapter substrate via a ball point.

5. The probe card as described in claim 1, wherein... At least one of the first switching module, the first external bare die, and the first terminating resistor unit is soldered onto the adapter substrate.

6. The probe card as described in claim 1, wherein, The data transmitting end and the data receiving end are connected by a signal to realize the internal loopback test of the bare die of the chip under test; The bare die of the chip under test also includes a control unit, wherein the control unit is connected to the physical layer and configured to generate test data to realize the internal loopback test, the external functional test and the external loopback test.

7. The probe card as described in any one of claims 1 to 6, wherein, The die under test includes a first die under test for a double-rate synchronous dynamic random access memory (DRAM), the first external die includes a second die of a DRAM class that matches the first die under test, and the first switching module is a switching die.

8. The probe card as described in any one of claims 1 to 6, wherein, The die under test includes a third die under test, which is configured as a die for at least one of a mobile industry processor interface, a high-speed serial computer expansion bus interface, and a serial / deserializer. The first external die includes a fourth die that matches the third die under test and is of at least one of a mobile industry processor interface, a high-speed serial computer expansion bus interface, and a serial / deserializer. The first switching module is a switching die.

9. A testing system comprising a probe card as described in any one of claims 1 to 8, wherein, The testing system also includes a testing machine, which is connected to the circuit board of the probe card.

10. The testing system of claim 9, further comprising: A finished product testing module used for testing the packaged finished product, wherein... The finished product testing module includes a test load board and a test socket. The test socket is provided with test probes for placing the target chip under test. The target chip under test is the chip after the unit under test has been packaged.

11. The testing system as described in claim 10, wherein, The test load board is provided with a second switching module, a second external chip for external functional testing of the target chip under test, and a second terminating resistor unit for external loopback testing of the target chip under test. The second switching module is connected to the second external chip and the second terminating resistor unit respectively, so that the second switching module can switch between the second external chip and the second terminating resistor unit.

12. The testing system as described in claim 11, wherein, At least one of the second switching module, the second external chip, and the second terminating resistor unit is disposed on the surface of the test load board.

13. A test method for chip testing, comprising: Based on the probe card already acquired for testing the unit under test, a test command is triggered to acquire test data. The unit under test includes at least one bare die of a chip under test on a wafer. The bare die of the chip under test includes a physical layer, and the physical layer includes a data transmitter and a data receiver. In response to the test command, a switching selection is made between external loopback testing for the die under test and external functional testing for the die under test; In response to the external loopback test, the die under test transmits the test data to the first terminating resistor unit through the data transmitting end, and obtains response data corresponding to the test data through the data receiving end to obtain the test result; and in response to the external functional test, the die under test transmits the test data to the first external die through the data transmitting end, and obtains response data corresponding to the test data through the data receiving end to obtain the test result.

14. The test method as described in claim 13, further comprising: In response to the internal loopback test for the bare die of the chip under test, the test result is obtained based on the test data and through the signal connection between the data transmitter and the data receiver.

15. The test method as described in claim 13, wherein, In response to the chip under test (DUT) including a first DUT for a double-data-rate synchronous dynamic random access memory (DRAM), the DUT transmits the test data to the first external DUT via the data transmitter, including: The first die under test transmits the test data to a second die of a double-rate synchronous dynamic random access memory class that matches the first die under test via the data transmitting terminal.

16. The test method as described in claim 13, wherein, In response to the chip under test (DUT) including a third DUT for at least one of a mobile industry processor interface, a high-speed serial computer expansion bus interface, and a serial / deserializer, the DUT transmits the test data to a first external DUT through the data transmitting end, including: The third die under test transmits the test data through the data transmitting end to a fourth die of at least one of the following types: mobile industry processor interface, high-speed serial computer expansion bus interface, and serial / deserializer, which are compatible with the third die under test.

17. An electronic device comprising: Processor and memory, The memory stores a computer program, which, when executed by the processor, implements the test method according to any one of claims 13 to 16.

18. A computer-readable storage medium, wherein, The storage medium stores a computer program, which, when executed by a processor, implements the test method according to any one of claims 13 to 16.

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