Virtual memory data processing method of computing equipment and related equipment

Abstract

According to the virtual memory data processing method of the computing device and the related device, the computing device comprises a plurality of computing modules, each computing module is associated with an independent three-dimensional stacked dynamic random access memory, and the method comprises the steps that in response to a virtual memory reservation request, the virtual memory reservation request is executed; determining a reserved virtual address field corresponding to the virtual memory reservation request in the virtual address space, and generating a virtual address pointer pointing to the reserved virtual address field; in response to the physical memory creation request, acquiring a memory size parameter and an allocation strategy parameter corresponding to the physical memory creation request; determining a target physical memory set from the plurality of three-dimensional stacked dynamic random access memories based on the allocation strategy parameter, allocating a physical memory page corresponding to the memory size parameter, and generating a physical memory handle based on the physical memory page; the mapping relation between the virtual address pointer and the physical memory handle is established, and the overall execution efficiency of the computing device when the computing device executes the compute-intensive task is improved.

Description

Technical Field

[0001] This application relates to the field of computational data processing technology, and in particular to virtual memory data processing methods and related equipment for computing devices. Background Technology

[0002] With the rapid development of artificial intelligence, especially large-scale language models, the demand for memory bandwidth in computing systems is increasing exponentially. Traditional two-dimensional planar storage architectures have gradually become a bottleneck limiting the release of computing power. To break through this "memory wall," three-dimensional dynamic random access memory (3D-DRAM) technology has emerged. It uses through-silicon vias (TSVs) to vertically stack high-density storage cells directly on computing modules (such as computing chips, clusters, or units), forming a highly integrated near-memory computing architecture. This architecture not only significantly shortens signal transmission paths and reduces power consumption but also provides ultra-high data transfer bandwidth far exceeding that of traditional video memory, making it the core storage form for next-generation high-performance graphics processing units (GPUs) and artificial intelligence (AI) accelerators.

[0003] However, in this decentralized 3D stacked architecture, limited by physical wiring density and interconnect power consumption, it is usually difficult to implement a fully meshed global crossbar within the chip. This results in physical memory resources being divided into multiple independent entities attached to specific computing modules. In related technologies, general virtual memory management mechanisms typically assume that physical memory is flat and uniformly accessed, often allocating it continuously at the device-wide granularity. This lacks awareness of the underlying physical topology, which can easily lead to computing tasks being scheduled to the 3D stacked dynamic random access memory of one computing module, while the required data is allocated to the 3D stacked dynamic random access memory of another computing module. This results in frequent high-latency cross-module remote access, causing congestion in the chip's internal interconnect channels and negating the high bandwidth advantage of the 3D stacked dynamic random access memory. Consequently, existing computing devices configured with 3D stacked dynamic random access memory still have relatively low overall execution efficiency for computationally intensive tasks. Summary of the Invention

[0004] This application provides a virtual memory data processing method and related equipment for computing devices, which can improve the overall execution efficiency of computing devices configured with three-dimensional stacked dynamic random access memory when performing computationally intensive tasks.

[0005] To achieve the above objectives, a first aspect of this application proposes a virtual memory data processing method for a computing device, wherein the computing device includes multiple computing modules, each computing module being associated with an independent three-dimensional stacked dynamic random access memory, and the method includes:

[0006] In response to a virtual memory reservation request, a reserved virtual address segment corresponding to the virtual memory reservation request is determined in the virtual address space, and a virtual address pointer pointing to the reserved virtual address segment is generated;

[0007] In response to a physical memory creation request, obtain the memory size parameters and allocation strategy parameters corresponding to the physical memory creation request;

[0008] Based on the allocation strategy parameters, a target physical memory set is determined from the plurality of three-dimensional stacked dynamic random access memories, and physical memory pages corresponding to the memory size parameters are allocated in the target physical memory set. Then, a physical memory handle is generated based on the location information of the physical memory pages.

[0009] Establish a mapping relationship between the reserved virtual address segment pointed to by the virtual address pointer and the physical memory page in the physical memory handle.

[0010] In some embodiments, determining a target physical memory set from the plurality of three-dimensional stacked dynamic random access memories based on the allocation strategy parameters, and allocating physical memory pages corresponding to the memory size parameters in the target physical memory set, includes:

[0011] When the allocation strategy parameter is a single local strategy, the target module identifier is determined from the physical memory creation request;

[0012] Based on the target module identifier, the target three-dimensional stacked dynamic random access memory is determined from the three-dimensional stacked dynamic random access memory associated with the plurality of computing modules;

[0013] When the number of remaining free pages in the target three-dimensional stacked dynamic random access memory is not less than the number of required pages corresponding to the memory size parameter, the target three-dimensional stacked dynamic random access memory is used as the target physical memory set.

[0014] Select the remaining free pages corresponding to the required number of pages from the target physical memory set as the physical memory pages.

[0015] In some embodiments, determining a target physical memory set from the plurality of three-dimensional stacked dynamic random access memories based on the allocation strategy parameters, and allocating physical memory pages corresponding to the memory size parameters in the target physical memory set, includes:

[0016] When the allocation strategy parameter is a global distribution strategy, the three-dimensional stacked dynamic random access memory associated with the multiple computing modules is determined as the target physical memory set;

[0017] Based on the required number of pages corresponding to the memory size parameters, calculate the average number of pages that each of the three-dimensional stacked dynamic random access memories in the target physical memory set needs to share;

[0018] For each of the three-dimensional stacked dynamic random access memories in the target physical memory set, the remaining free pages corresponding to the average number of pages are selected as the physical memory pages.

[0019] In some embodiments, determining a target physical memory set from the plurality of three-dimensional stacked dynamic random access memories based on the allocation strategy parameters, and allocating physical memory pages corresponding to the memory size parameters in the target physical memory set, includes:

[0020] When the allocation strategy parameter is a group distribution strategy, the group mask information corresponding to the physical memory creation request is determined;

[0021] Based on the grouping mask information, a subset of computing modules is selected from the plurality of computing modules;

[0022] The three-dimensional stacked dynamic random access memory associated with the subset of computing modules is used as the target physical memory set;

[0023] The physical memory pages required for the memory size parameters are evenly distributed among the multiple three-dimensional stacked dynamic random access memories contained in the target physical memory set.

[0024] In some embodiments, the packet mask information is used to indicate computing modules that are determined to be operating normally, and the step of filtering a subset of computing modules from the plurality of computing modules based on the packet mask information includes:

[0025] Determine the bits identified as usable in the block mask information;

[0026] The calculation module corresponding to the bit is selected as the subset of calculation modules.

[0027] In some embodiments, generating a physical memory handle based on the location information of the physical memory page includes:

[0028] A physical page mapping table is generated based on the number of entries corresponding to the memory size parameters;

[0029] Add the physical location information of all the physical memory pages to the physical page mapping table;

[0030] The physical memory handle is generated based on the index pointing to the physical page mapping table.

[0031] In some embodiments, establishing the mapping relationship between the reserved virtual address segment pointed to by the virtual address pointer and the physical memory page in the physical memory handle includes:

[0032] Based on the physical memory handle, read at least one physical location information recorded in the physical page mapping table;

[0033] The system iterates through multiple consecutive virtual pages pointed to by the virtual address pointers and sequentially establishes a one-to-one mapping entry between each virtual page and the physical location information in the physical page mapping table, so that the consecutive virtual address space is discretely mapped to the target physical memory set.

[0034] In some embodiments, the computing module is any one of a computing chip, a computing cluster, or a computing unit.

[0035] To achieve the above objectives, a second aspect of this application provides a virtual memory data processing method for a computing device, the computing device comprising multiple computing modules, each computing module being associated with an independent three-dimensional stacked dynamic random access memory, the system comprising:

[0036] The virtual reservation module is used to respond to a virtual memory reservation request by determining the reserved virtual address segment corresponding to the virtual memory reservation request in the virtual address space and generating a virtual address pointer pointing to the reserved virtual address segment.

[0037] The physical creation module is used to respond to a physical memory creation request by obtaining the memory size parameters and allocation strategy parameters corresponding to the physical memory creation request.

[0038] The physical handle generation module is used to determine a target physical memory set from the plurality of three-dimensional stacked dynamic random access memories based on the allocation strategy parameters, allocate physical memory pages corresponding to the memory size parameters in the target physical memory set, and then generate a physical memory handle based on the location information of the physical memory pages.

[0039] The mapping execution module is used to establish a mapping relationship between the reserved virtual address segment pointed to by the virtual address pointer and the physical memory page in the physical memory handle.

[0040] To achieve the above objectives, a third aspect of this application provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the virtual memory data processing method for computing devices as described in the first aspect.

[0041] To achieve the above objectives, a fourth aspect of the present application provides a storage medium, which is a computer-readable storage medium storing a computer program that, when executed by a processor, implements the virtual memory data processing method of the computing device described in the first aspect.

[0042] The virtual memory data processing method and related apparatus for a computing device proposed in this application include multiple computing modules, each associated with an independent three-dimensional stacked dynamic random access memory. The method includes: first, in response to a virtual memory reservation request, determining a reserved virtual address segment corresponding to the virtual memory reservation request in the virtual address space, and generating a virtual address pointer pointing to the reserved virtual address segment; then, in response to a physical memory creation request, obtaining memory size parameters and allocation strategy parameters corresponding to the physical memory creation request; subsequently, based on the allocation strategy parameters, determining a target physical memory set from multiple three-dimensional stacked dynamic random access memories, allocating physical memory pages corresponding to the memory size parameters in the target physical memory set, and generating a physical memory handle based on the location information of the physical memory pages; finally, establishing a mapping relationship between the reserved virtual address segment pointed to by the virtual address pointer and the physical memory page in the physical memory handle. This application decouples the virtual address reservation process from the physical memory creation process and introduces allocation strategy parameters during the physical memory creation stage. Unlike the assumption of flat and uniform access in traditional general virtual memory management mechanisms, the solution provided in this application can perceive the underlying physical topology under the architecture without global cross switches. According to the strategy parameters, it accurately locks the data in the target physical memory set associated with the target computing module, and realizes flexible mapping between discrete physical pages and continuous virtual addresses through physical memory handles. This topology-aware allocation mechanism effectively avoids high-latency cross-module remote access caused by computing tasks and their required data being in different computing modules, thereby significantly reducing the risk of congestion in the internal interconnect channels of the chip, fully releasing the high bandwidth and low power consumption advantages of the three-dimensional stacked dynamic random access memory, and greatly improving the overall data throughput and execution efficiency of computing devices when performing computationally intensive tasks.

[0043] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description

[0044] Figure 1 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application.

[0045] Figure 2 This is a schematic diagram of the structure of a computing device based on computing chips, provided in another embodiment of this application.

[0046] Figure 3 This is a flowchart of a virtual memory data processing method for a computing device provided in another embodiment of this application.

[0047] Figure 4 This is a flowchart illustrating the physical memory page determination process under a single local strategy, provided in another embodiment of this application.

[0048] Figure 5 This is a schematic diagram illustrating the determination and mapping of physical memory pages corresponding to a single local strategy, provided in another embodiment of this application.

[0049] Figure 6 This is a flowchart of a physical memory page determination process under a global distribution strategy, provided in another embodiment of this application.

[0050] Figure 7 This is a schematic diagram illustrating the determination and mapping of physical memory pages corresponding to a global distribution strategy provided in another embodiment of this application.

[0051] Figure 8 This is a flowchart of physical memory page determination under a group distribution strategy provided in another embodiment of this application.

[0052] Figure 9 yes Figure 8 The flowchart for step 802.

[0053] Figure 10 This is a schematic diagram illustrating the determination and mapping of physical memory pages corresponding to a group distribution strategy provided in another embodiment of this application.

[0054] Figure 11 This is a flowchart illustrating the generation of a physical memory handle, provided in another embodiment of this application.

[0055] Figure 12 This is a schematic diagram of generating a physical memory handle according to another embodiment of this application.

[0056] Figure 13This is a flowchart illustrating the generation of a mapping relationship, provided in another embodiment of this application.

[0057] Figure 14 This is a schematic diagram illustrating the generation of a mapping relationship provided in another embodiment of this application.

[0058] Figure 15 This is a schematic diagram of the structure of a virtual memory data processing method for a computing device provided in another embodiment of this application.

[0059] Figure 16 This is a schematic diagram of the hardware structure of an electronic device provided in another embodiment of this application. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0061] It should be noted that although functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0063] With the rapid development of artificial intelligence, especially large-scale language models, the demand for memory bandwidth in computing systems is increasing exponentially. Traditional two-dimensional planar storage architectures have gradually become a bottleneck limiting the release of computing power. To break through this "memory wall," three-dimensional dynamic random access memory (3D-DRAM) technology has emerged. It uses through-silicon vias (TSVs) to vertically stack high-density storage cells directly on computing modules (such as computing chips, clusters, or units), forming a highly integrated near-memory computing architecture. This architecture not only significantly shortens signal transmission paths and reduces power consumption but also provides ultra-high data transfer bandwidth far exceeding that of traditional video memory, making it the core storage form for next-generation high-performance graphics processing units (GPUs) and artificial intelligence (AI) accelerators.

[0064] However, in this decentralized 3D stacked architecture, limited by physical wiring density and interconnect power consumption, it is usually difficult to implement a fully meshed global crossbar within the chip. This results in physical memory resources being divided into multiple independent entities attached to specific computing modules. In related technologies, general virtual memory management mechanisms typically assume that physical memory is flat and uniformly accessed, often allocating it continuously at the device-wide granularity. This lacks awareness of the underlying physical topology, which can easily lead to computing tasks being scheduled to the 3D stacked dynamic random access memory of one computing module, while the required data is allocated to the 3D stacked dynamic random access memory of another computing module. This results in frequent high-latency cross-module remote access, causing congestion in the chip's internal interconnect channels and negating the high bandwidth advantage of the 3D stacked dynamic random access memory. Consequently, existing computing devices configured with 3D stacked dynamic random access memory still have relatively low overall execution efficiency for computationally intensive tasks.

[0065] To improve the overall execution efficiency of computing devices configured with 3D stacked dynamic random access memory (DRAM) during computationally intensive tasks, this application decouples the virtual address reservation process from the physical memory creation process and introduces allocation strategy parameters during the physical memory creation stage. Unlike the flat and uniform access memory allocation assumption in traditional general virtual memory management mechanisms, the solution provided in this application can perceive the underlying physical topology under a global cross-switch architecture. Based on the strategy parameters, it accurately locks data into the target physical memory set associated with the target computing module and achieves flexible mapping between discrete physical pages and contiguous virtual addresses through physical memory handles. This topology-aware allocation mechanism effectively avoids high-latency cross-module remote access caused by computing tasks and their required data being located in different computing modules, thereby significantly reducing the risk of congestion in the chip's internal interconnect channels. It fully leverages the high bandwidth and low power consumption advantages of 3D stacked DRAM, and significantly improves the overall data throughput and execution efficiency of computing devices when performing computationally intensive tasks.

[0066] The virtual memory data processing method and related equipment for a computing device provided in the embodiments of this application will be further described below. First, the computing device applying this virtual memory data processing method will be described. (Refer to...) Figure 1 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Figure 1As shown, the computing device of this application adopts a highly integrated near-memory computing architecture based on vertical stacking. Its main body includes multiple parallel computing modules. Each computing module and its vertically stacked independent three-dimensional stacked dynamic random access memory (3D-DRAM) above it form a tightly coupled storage-computing unit pair, forming a physically discrete local storage resource layout.

[0067] Figure 1 The dashed box surrounding 3D-DRAM, labeled "Virtual Memory," schematically illustrates that although physical memory is distributed across various computing modules, logically the system presents and manages these resources to the user through a unified virtual address space. Furthermore, multiple computing modules establish communication connections through an underlying interconnect network, which carries control signaling and necessary data transmission between modules, thereby supporting the collaborative computing capabilities of the entire device in the absence of hardware constraints such as a global crossbar.

[0068] It is understandable that, such as Figure 1 The “computing module” shown is a general abstract concept defined according to the hardware architecture hierarchy, used to refer to the smallest physical computing unit with independent local three-dimensional stacked dynamic random access memory (3D-DRAM). Depending on the coverage of the chip’s internal interconnect network and the integration level of the manufacturing process, the computing module can be represented by physical entities of various granularities, as shown in the following three examples.

[0069] In the first example, the compute module can be a compute die. This is a larger hardware granularity, typically referring to an independent silicon die within a package. In this architecture, a three-dimensional stacked dynamic random access memory is directly stacked on top of the entire compute die, and all compute clusters and units within that die share this local storage resource. Here, the "single local policy" of virtual memory management locks data onto a specific die, while cross-die access is treated as remote access.

[0070] In the second example, the computing module can be a computing cluster. This is an intermediate granularity between a core and a unit; a computing core typically contains multiple computing clusters. In this architecture, the hardware design further subdivides and physically binds the 3D stacked dynamic random access memory to each computing cluster, allowing multiple computing units within the same cluster to share the cluster's local memory, while accessing the memory of other clusters within the same core requires traversing the on-chip interconnect network. This granularity provides finer bandwidth isolation than the core-level isolation.

[0071] In the third example, the computing module can be a computing unit (such as a streaming multiprocessor (SM) in a graphics processing unit (GPU) or a core in an artificial intelligence (AI) chip). This is the smallest hardware granularity. In this architecture, each independent computing unit has its own dedicated three-dimensional stacked dynamic random access memory stacked vertically on top, achieving ultimate "near-memory computing." Here, the memory allocation strategy can precisely control where data is stored next to a specific computing core, thereby minimizing memory access latency.

[0072] In this embodiment, the computing module can be configured in any of a variety of forms according to real-time requirements, providing a general memory management architecture with broad adaptability to the underlying hardware topology. Regardless of whether the underlying hardware chooses a larger chip-level sharing due to the size of the crossbar, or chooses a tiny unit-level dedicated memory to pursue ultimate bandwidth, the virtual memory management method described later in this application can be adapted through a unified "computing module identifier," thereby maintaining the consistency and compatibility of the software interface across different chip design generations and product specifications.

[0073] Reference Figure 2 This is a schematic diagram of the structure of a computing device based on computing chips, provided in an embodiment of this application. Figure 2 As shown, the computing device contains multiple physically independent computing chips. Each computing chip is an independent package or logical subsystem, which further integrates multiple computing units and a local interconnect network to support communication within the chip. In this architecture, each computing unit is vertically stacked with a dedicated three-dimensional stacked dynamic random access memory (3D-DRAM), thus forming multiple high-bandwidth near-memory computing nodes within the chip. At the same time, the computing chips are connected through the device's underlying global interconnect network, thereby ensuring low-latency local memory access within a single chip while supporting system-level data interaction and collaborative computing across chips through a two-level interconnect architecture.

[0074] Based on the computing device provided above, the virtual memory data processing method applied to this computing device will be further described below. References provided in this application Figure 3 This is an optional flowchart of a virtual memory data processing method for a computing device provided in an embodiment of this application. Figure 3 The method may include, but is not limited to, steps 301 to 304. It is also understood that this embodiment... Figure 3The order of steps 301 to 304 is not specifically limited. The order of steps can be adjusted or some steps can be reduced or added according to actual needs.

[0075] Step 301: In response to the virtual memory reservation request, determine the reserved virtual address segment corresponding to the virtual memory reservation request in the virtual address space, and generate a virtual address pointer pointing to the reserved virtual address segment.

[0076] Step 301 will be described in detail below.

[0077] In some embodiments, when a computing device responds to a virtual memory reservation request, it first determines the reserved virtual address segment corresponding to the virtual memory reservation request in the virtual address space and generates a virtual address pointer pointing to the reserved virtual address segment. Here, the virtual address space refers to a unified, contiguous logical addressing range presented by the system to the user program. It can be understood that the physical storage resources corresponding to these contiguous virtual address spaces may be distributed across different computing modules.

[0078] Understandably, virtual memory reservation requests are typically triggered by function calls like VirtualMemReserve(size, &ptr), which carry the critical memory size parameter (i.e., size in the code). At this stage, the computing device's memory management unit or the operating system kernel first parses the request to confirm that the application intends to request a contiguous logical address space in the current process context. At this point, no actual allocation or occupation of physical memory is involved; the request is merely a logical "placeholder" declaration.

[0079] Then, in response to the request, the computing device begins scanning and searching for free regions in the virtual address space of the current process. The system calculates the required address span based on the memory size parameters, searching within the vast virtual address space (e.g., several terabytes in a 64-bit system) for a contiguous address region that meets the size requirement and is not yet occupied by other resources. Once a suitable region is found, the computing device marks it as "reserved" in the kernel's data structures (such as a Virtual Address Descriptor (VAD) tree or a linked list of memory descriptors), thus determining a reserved virtual address segment. This operation is equivalent to marking a piece of land on a logical map to prevent subsequent memory allocation requests from accidentally overwriting or using this address range.

[0080] Once the address segment is locked, the computing device acquires the starting logical address of that segment and encapsulates it as a virtual address pointer (such as a code ptr). This pointer, as a 64-bit or 32-bit memory address value, is returned to the application by the computing device as the return value of a function call or as a pointer parameter. This virtual address pointer is the only entry point for the application to subsequently access this memory block and is also the key anchor connecting the logical and physical views in subsequent steps (such as generating a physical memory handle or establishing the final mapping). At this point, although the application already holds a valid pointer, directly reading or writing to this pointer will trigger a page fault because a physical mapping has not yet been established.

[0081] Step 302: In response to the physical memory creation request, obtain the memory size parameters and allocation strategy parameters corresponding to the physical memory creation request.

[0082] Step 302 will be described in detail below.

[0083] In some embodiments, subsequently, in response to a physical memory creation request, the computing device obtains the memory size parameters and allocation strategy parameters corresponding to the physical memory creation request. The memory size parameters define the required size of the physical memory (e.g., the number of bytes or pages), while the allocation strategy parameters are the core control variables of this scheme, used to indicate how the physical memory should be distributed in the underlying hardware topology.

[0084] Understandably, a physical memory creation request is typically manifested as a specific Application Programming Interface (API) function call (such as LocalMemCreate), the purpose of which is to explicitly express to the operating system the application's specific needs for underlying hardware storage resources. At this point, the computing device parses the data packet or parameter list carried by the request to extract the control information necessary for the subsequent allocation process, namely the memory size parameters and allocation strategy parameters. These two parameters together constitute the specific parameters for hardware resource allocation.

[0085] The computing device then first identifies and obtains memory size parameters (such as code size) from the physical memory creation request. This parameter is a quantifiable value used to precisely define the amount of storage space required by the application's current task, typically expressed in bytes. After obtaining this parameter, the computing device usually combines it with the computing device's page size to convert it into a specific number of physical pages (Page Count). This value determines how many free storage units the computing device needs to lock in the underlying three-dimensional stacked dynamic random access memory, forming the basis for resource quantification.

[0086] In some embodiments, the computing device synchronously extracts key allocation policy parameters (corresponding to policy enumeration values ​​in the code, such as SINGLE, ALL, or GROUP) from physical memory creation requests. These parameters act as "routing instructions," instructing the computing device on how to organize physical resources. For example, the parameter might specify a single local policy prioritizing low latency or a globally distributed policy prioritizing high bandwidth. In some cases (such as group distribution policies), the acquisition of this parameter may also involve reading auxiliary parameters (such as localMemID or groupMask). Based on these policy instructions, the computing device decides whether to concentrate physical pages on a single node or distribute them across multiple nodes.

[0087] Step 303: Based on the allocation strategy parameters, determine the target physical memory set from multiple three-dimensional stacked dynamic random access memories, allocate physical memory pages corresponding to the memory size parameters in the target physical memory set, and then generate physical memory handles based on the location information of the physical memory pages.

[0088] Step 303 will be described in detail below.

[0089] In some embodiments, further, based on the obtained allocation strategy parameters, a target physical memory set is determined from multiple three-dimensional stacked dynamic random access memories, and physical memory pages corresponding to memory size parameters are allocated in the target physical memory set. Then, physical memory handles are generated based on the location information of the physical memory pages. During this process, the computing device filters multiple three-dimensional stacked dynamic random access memories connected internally to determine the target physical memory set according to the specific instructions of the strategy parameters (such as single local, global distribution, or group distribution). This defines the legal physical hardware boundary of this memory allocation operation, ensuring that subsequent data storage strictly adheres to the performance model set by the application (such as low latency or high bandwidth).

[0090] After determining the hardware set, the computing device performs a specific capacity allocation operation, which involves allocating physical memory pages corresponding to the memory size parameters within the target physical memory set. The computing device first converts the memory size parameters (number of bytes) into the required number of physical pages, and then searches for free resources in one or more memories contained in the target physical memory set. The computing device checks the bitmap or free list of each memory, deducts the corresponding physical memory page quota, and marks these pages as "occupied." It is worth noting that, depending on the strategy, these physical pages may be concentrated in the same memory chip or evenly distributed across multiple memory chips in an interleaved manner, but logically they all serve the same allocation request.

[0091] Next, to shield the upper layers from the complex physical distribution details of the lower layers, the computing device performs an abstraction and encapsulation operation, namely, generating physical memory handles based on the location information of physical memory pages. The computing device constructs a physical page mapping table in kernel space, recording the hardware addresses (i.e., location information) of all physical memory pages allocated in the above steps in sequence. At this point, although the physical resources are in place, a connection has not yet been established with the virtual address. The computing device generates an opaque identifier pointing to this mapping table, i.e., a physical memory handle, and returns it to the caller. This handle becomes the sole credential for subsequent operations of this set of physical resources by the user-space program.

[0092] The following section will further describe the determination of the target physical memory set and the allocation of physical memory pages for different allocation strategy parameters.

[0093] Reference Figure 4 Based on the allocation strategy parameters, a target physical memory set is determined from multiple three-dimensional stacked dynamic random access memories, and physical memory pages corresponding to memory size parameters are allocated in the target physical memory set, including the following steps 401 to 404.

[0094] Step 401: When the allocation strategy parameter is a single local strategy, determine the target module identifier from the physical memory creation request.

[0095] Step 402: Based on the target module identifier, determine the target three-dimensional stacked dynamic random access memory from the three-dimensional stacked dynamic random access memory associated with multiple computing modules.

[0096] Step 403: When the number of remaining free pages in the target 3D stacked dynamic random access memory is not less than the required number of pages corresponding to the memory size parameter, the target 3D stacked dynamic random access memory is used as the target physical memory set.

[0097] Step 404: Select the remaining free pages corresponding to the required number of pages from the target physical memory set as physical memory pages.

[0098] Steps 401 to 404 are described in detail below.

[0099] In some embodiments, the step of determining the target physical memory set based on allocation policy parameters first requires identifying the specific memory allocation mode. When the system recognizes that the allocation policy parameter is set to a single local policy (corresponding to the code "single"), it means that the memory allocation mechanism will prioritize the utilization of local resources to reduce access latency. In this scenario, the system responds to the received physical memory creation request by parsing the data packet or instruction field it carries, and extracting a clear target module identifier. Here, the single local policy refers to a rule that forces or prioritizes the allocation of memory on the local hardware node to which the computing task belongs, aiming to avoid performance losses caused by cross-node communication; while the target module identifier is a logical or physical ID used to uniquely identify the computing unit (such as a CPU core, GPU, or specific accelerator) that initiates the memory request, which is a key index for subsequent hardware resource location.

[0100] After identifying the target module identifier, a hardware resource mapping and location operation is performed. Specifically, based on the target module identifier, a search is conducted within a pre-built hardware topology to precisely locate the target 3D-DRAM that has a direct coupling or affiliation relationship with the target module identifier from among the 3D-DRAMs associated with multiple computing modules. Through this step, the computing device can accurately direct logical computing requests to the physically nearest and fastest high-performance storage hardware, achieving precise matching between logical requests and physical hardware.

[0101] After identifying the specific hardware object, resource availability needs to be assessed to ensure the feasibility of allocation. At this point, the computing device reads the target 3D stacked dynamic random access memory's status register or resource management table in real time to obtain its remaining free pages and compares this value with the required number of pages calculated based on memory size parameters. If the result shows that the remaining free pages are not less than the required number of pages, it indicates that the memory has sufficient capacity to handle the task, and the computing device then formally confirms the target 3D stacked dynamic random access memory as the target physical memory set. Here, the memory size parameter refers to the size of the memory space requested by the user or application (e.g., 1GB), while the required number of pages is the physical number of pages calculated by dividing this size by the system page size. This step effectively constitutes an "admission check" mechanism before memory allocation.

[0102] After completing the resource locking and set determination, the computing device will perform the final physical resource allocation. Specifically, from the determined target physical memory set, according to a preset addressing algorithm (such as low address priority, contiguous address priority, etc.), the device will precisely select the number of remaining free pages equal to the required number of pages from the available address space, and mark these selected pages as occupied, thus delivering them as the final physical memory pages to the requesting end. This process completes the physical mapping from the logical memory set to the specific physical pages. As the smallest unit of memory management by the operating system, the physical address of a physical memory page will be recorded and a mapping relationship established with its virtual address, allowing the computing module to directly read and write it.

[0103] Reference Figure 5 This is a schematic diagram illustrating the determination and mapping of physical memory pages corresponding to a single local strategy provided in an embodiment of this application. For example... Figure 5 As shown in the attached figure, this diagram illustrates the mapping from virtual addresses to physical addresses when the allocation policy parameter is configured as a single local policy (i.e., Policy=SINGLE). Figure 5 The horizontal bar at the top center represents a sequence of consecutive virtual memory page numbers requested by the application (e.g., from 102 to 109), which corresponds to the memory size parameter carried in the physical memory creation request. The computing device calculates the required number of pages (i.e., 8 pages) based on this size parameter and prepares this contiguous virtual address space at the logical level, waiting to establish a mapping relationship with the underlying physical hardware resources.

[0104] Figure 5 The four vertical pillars at the bottom center (labeled LM0, LM1, LM2, and LM3) represent multiple three-dimensional stacked dynamic random access memories (DRAMs) in the computing device. At this point, the computing device first parses the target module identifier (also known as the Local Memory Identifier, or localMemID) in the request, and based on this target module identifier, precisely determines LM1 as the target three-dimensional stacked DRAM from these four candidate memories. For example... Figure 5 As shown, the other memories (LM0, LM2, LM3) were not selected in this allocation process, and their internal storage units did not participate in the mapping of this specific set of virtual pages. This intuitively reflects the core constraint of the "single local" strategy, that is, data is forcibly confined to a single physical storage node.

[0105] Then, the specific internal allocation process for the target three-dimensional stacked dynamic random access memory (LM1) is further performed, such as... Figure 5As indicated by the middle arrow pointing to the internal squares of LM1, the computing device first confirms that the current number of remaining free pages in LM1 meets the requirements, and then selects specific remaining free pages from the physical address space of LM1 (such as...). Figure 5 The diagram shows squares filled with numbers such as 102, 103, 104, etc. It's important to note that these selected physical pages don't necessarily have contiguous physical addresses (for example, they may occupy indices 1, 2, 3, and 5 in the diagram), but they all belong to the same target physical memory set. Once allocated, these physical pages become the physical memory pages shown in the diagram, and a one-to-one mapping path is established between them and the virtual memory page numbers (102-109) above them through page table entries (PTEs).

[0106] Through steps 401 to 404 above, a strong coupling allocation of computing and storage resources is achieved by implementing a "single local strategy". The solution of this application maximizes the use of the high bandwidth and low latency characteristics of 3D-DRAM by strictly limiting the allocation to the three-dimensional stacked dynamic random access memory associated with the target computing module, and avoids communication bottlenecks caused by cross-node or cross-chip access. At the same time, by comparing the remaining free pages with the required pages in advance, allocation failures caused by resource fragmentation or insufficiency are effectively prevented, ensuring the determinism and high efficiency of memory services in high-performance computing scenarios. It is particularly suitable for application scenarios such as artificial intelligence training or high-frequency trading that are extremely sensitive to memory access speed.

[0107] Reference Figure 6 Based on the allocation strategy parameters, a target physical memory set is determined from multiple three-dimensional stacked dynamic random access memories, and physical memory pages corresponding to memory size parameters are allocated in the target physical memory set, including the following steps 601 to 603.

[0108] Step 601: When the allocation strategy parameter is a global distribution strategy, the three-dimensional stacked dynamic random access memory associated with multiple computing modules is determined as the target physical memory set.

[0109] Step 602: Based on the required number of pages corresponding to the memory size parameter, calculate the average number of pages required for each three-dimensional stacked dynamic random access memory in the target physical memory set.

[0110] Step 603: For each three-dimensional stacked dynamic random access memory of the target physical memory set, select the remaining free pages corresponding to the average number of pages as physical memory pages.

[0111] Steps 601 to 603 are described in detail below.

[0112] In some embodiments, when the allocation strategy parameter is detected to be set to a global distribution strategy, it means that the computing device is no longer limited to the resource utilization of a single node, but optimizes overall performance through a cross-node resource scheduling mechanism. In this case, the computing device will consider all three-dimensional stacked dynamic random access memory (3D-DRAM) that are associated with multiple computing modules, and determine them as a whole as the target physical memory set. Here, the global distribution strategy refers to a rule aimed at utilizing all available storage nodes within the computing device for parallel data carrying, and the target physical memory set at this time essentially constitutes a globally shared physical storage resource pool, laying the hardware foundation for subsequent large-scale parallel access.

[0113] After determining the resource pool containing multiple storage devices, the computing device needs to perform quantitative allocation calculations of resources based on the task scale. Specifically, the computing device calculates the total number of pages required for the task based on the memory size parameters carried in the physical memory creation request. Then, it divides this total by the total number of 3D stacked dynamic random access memories (DRAMs) included in the target physical memory set to calculate the average number of pages that each memory node should handle. This step essentially performs a static load balancing algorithm (interleaving), ensuring that each hardware node bears equal or similar storage pressure by evenly distributing the total data demand, thus preventing a single memory node from becoming a bottleneck due to excessive load.

[0114] In some embodiments, based on the calculated sharing ratio, the computing device will perform specific physical page locking and allocation operations. For each 3D stacked dynamic random access memory (DRAM) in the target physical memory set, the computing device searches within its respective address space, selects a number of remaining free pages equal to the average number of pages, and combines these pages, which are distributed across different hardware, into a unified physical memory page delivered to the user. This means that although logically the user obtains a contiguous virtual memory space, physically, this space is actually interwoven from multiple memory segments distributed across different 3D stacked DRAMs, thus completing the discretization mapping of physical addresses.

[0115] Reference Figure 7 This is a schematic diagram illustrating the determination and mapping of physical memory pages corresponding to a global distribution strategy provided in an embodiment of this application. For example... Figure 7 The diagram illustrates the specific architecture of the virtual address to physical address mapping when the allocation policy parameter is configured as a global distribution policy (i.e., Policy=ALL). Figure 7The horizontal bar at the top represents a contiguous range of virtual memory page numbers (e.g., from 102 to 109) requested by the user program, corresponding to the memory size parameters included in the physical memory creation request. The computing device first calculates the total number of pages required for this task as 8 pages based on these size parameters, and reserves corresponding virtual page table entries in the logical address space, preparing to map them onto the underlying physical hardware resources.

[0116] Figure 7 The four vertical pillars at the bottom (labeled LM0, LM1, LM2, and LM3) represent all the three-dimensional stacked dynamic random access memories associated with multiple computing modules within the system. Because the strategy is globally distributed, the computing device no longer selects a single memory, but instead establishes these four storage devices (LM0 to LM3) as the target physical memory set. Subsequently, the computing device performs a division operation based on the total required number of pages (8 pages) and the number of memories within the set (4), calculating that the average number of pages required for each three-dimensional stacked dynamic random access memory is 2 pages.

[0117] Furthermore, Figure 7 The diagram illustrates the specific physical page allocation process based on the above calculation results. For each memory segment from LM0 to LM3, the computing device selects two remaining free pages as physical memory pages. Specifically... Figure 7 As shown: virtual pages 102 and 103 are mapped to LM0 (located at indices 4 and 7 respectively); virtual pages 104 and 105 are mapped to LM1; virtual pages 106 and 107 are mapped to LM2; and virtual pages 108 and 109 are mapped to LM3. This interleaved allocation method ensures that continuous logical data is evenly "spread out" and physically stored across all available hardware nodes.

[0118] Through steps 601 to 603 above, by implementing a "global distribution strategy," uniform and discrete storage of memory data on the system's global hardware resources is achieved. The solution of this application distributes the required number of pages evenly across multiple three-dimensional stacked dynamic random access memories. When the system performs data read and write operations, it can simultaneously activate all memory channels, thereby achieving a significant bandwidth aggregation effect and multiplying the overall throughput of the memory system. This parallel access mechanism not only greatly accelerates the transmission speed of large datasets but also effectively balances the power consumption and thermal load of each storage node, preventing "hot spot" congestion caused by frequent access to a single node. It is particularly suitable for applications with extremely high memory bandwidth requirements, such as scientific computing and big data analysis.

[0119] Reference Figure 8Based on the allocation strategy parameters, a target physical memory set is determined from multiple three-dimensional stacked dynamic random access memories, and physical memory pages corresponding to memory size parameters are allocated in the target physical memory set, including the following steps 801 to 804.

[0120] Step 801: When the allocation strategy parameter is a group distribution strategy, determine the group mask information corresponding to the physical memory creation request.

[0121] Step 802: Based on the group mask information, select a subset of computing modules from multiple computing modules.

[0122] Steps 801 to 802 are described in detail below.

[0123] In some embodiments, when the computing device detects that the allocation policy parameter is set to a group distribution policy, it indicates that the current memory allocation is neither limited to a private mode on a single node nor generalized to a shared mode across the entire computing device, but rather adopts a local sharing mode that lies between the two. At this time, the computing device responds to the physical memory creation request by parsing the control fields carried within it, extracting and determining the group mask information. Here, the group distribution policy refers to a mechanism that divides hardware resources into several logical or physical groups for management. The group mask information is typically a set of binary bit strings or specific logical identifiers used to precisely indicate the specific range of hardware groups that the current task is authorized to use or requests to use; it is a key index for subsequent resource filtering.

[0124] Once the mask data used to define the resource scope is obtained, the computing device performs a logical filtering operation on the computing resources. Specifically, based on the grouped mask information, the computing device traverses or matches multiple available computing modules in the current computing device. By performing logical operations (such as bitwise AND operations) or table lookups between the mask information and the identifiers of the computing modules, the computing device removes modules that do not meet the mask requirements from the global computing resource pool, thereby filtering out a specific subset of computing modules. This step essentially defines a specific "computing domain" at the logical level, ensuring that subsequent memory allocation is limited to this specific hardware sub-scope, achieving logical isolation of hardware resources, as described below.

[0125] Reference Figure 9 The group mask information is used to indicate the computing modules that are determined to be operating normally. Based on the group mask information, a subset of computing modules is selected from multiple computing modules, including the following steps 901 to 902.

[0126] Step 901: Determine the bits marked as available in the block mask information.

[0127] Step 902: Select the calculation module corresponding to the bit as a subset of calculation modules.

[0128] Steps 901 to 902 are described in detail below.

[0129] In some embodiments, for the step of filtering a subset of computing modules based on group mask information, the computing device first uses the mask information as an indicator of hardware health status. In this scenario, the group mask information is not only used to define logical groups, but also explicitly used to indicate which computing modules in the computing device are determined to be operating normally. This means that the mask information is a dynamic status bitmap generated based on underlying hardware inspection mechanisms (such as Power-On Self-Test or real-time heartbeat detection), designed to remove faulty or maintenance nodes from the full hardware resource pool. In response to a memory creation request, the computing device invokes the group mask information to initiate a logical process of filtering qualified hardware resources from multiple computing modules, ensuring that subsequent memory operations are built on a reliable hardware foundation.

[0130] To interpret the aforementioned status indications, the computing device performs the operation of determining the available bits in the block mask information. Specifically, the computing device reads the mask, which exists as a binary data stream or register value, and scans each bit sequentially. Here, a bit is the smallest unit of measurement for binary information. In this scheme, the index of each bit logically corresponds to a specific computing module in the computing device, and the value of that bit (0 or 1) represents the status attribute of that module. For example, the computing device identifies a bit with a value of "1" as "available," indicating that the corresponding hardware is in normal operating mode; while it identifies a bit with a value of "0" as "unavailable," indicating that the corresponding hardware is faulty, offline, or locked by the computing device.

[0131] Furthermore, based on the parsing results of the binary status bits, the computing device performs the final resource locking operation, that is, selecting the computing modules corresponding to the bits as a subset of computing modules. In this step, the computing device uses a pre-set mapping table to convert the logical locations of those "identified as available" bits into physical hardware IDs. The computing device only includes the computing modules corresponding to these physical IDs in the candidate range for this memory allocation, thereby constructing a subset of computing modules filtered by health status. This subset of computing modules essentially constitutes a dynamically available resource whitelist. Any computing module not included in this subset (i.e., the module corresponding to the unavailable bits) and its associated storage resources will be strictly excluded from this operation.

[0132] Through steps 901 to 902 above, by using group mask information to screen the health status of computing modules, a fault isolation and fault tolerance mechanism at the memory allocation level is realized. The solution of this application effectively prevents data from being stored in the three-dimensional stacked dynamic random access memory associated with the faulty module by dynamically removing nodes with abnormal status before allocating physical memory, thereby avoiding the risk of program crashes or data loss due to hardware failure. At the same time, this bitmap-based screening mechanism has extremely high processing efficiency and can quickly adapt to dynamic changes in the topology of computing devices (such as hot-swapping or dynamic node offline), significantly improving the reliability and availability of large-scale parallel computing devices.

[0133] Step 803: Use the three-dimensional stacked dynamic random access memory associated with the subset of computing modules as the target physical memory set.

[0134] Step 804: Distribute the required physical memory pages evenly among the multiple three-dimensional stacked dynamic random access memories contained in the target physical memory set.

[0135] Steps 803 to 804 are described in detail below.

[0136] After determining the specific range of computing resources, the computing device needs to further map the corresponding storage resource entities. During this process, the computing device identifies the storage devices directly associated with or mounted by each computing module in the subset of computing modules, based on the hardware topology, and uniformly delineates this portion of 3D-DRAM as the target physical memory set. In this process, memory associated with computing modules not included in this subset will be excluded from this allocation. This means that the target physical memory set constitutes a local, intra-group shared storage pool, the physical boundary of which is entirely defined by the aforementioned group mask information, thus establishing a resource isolation wall at the physical level from other groups.

[0137] After locking onto the target storage resource pool, the computing device executes a balanced allocation algorithm within the group. Specifically, this involves evenly distributing the required physical memory pages among the multiple three-dimensional stacked dynamic random access memories (DRAMs) contained in the target physical memory set, based on the total demand calculated using memory size parameters. This process typically involves interleaving contiguous logical address spaces across different memories within the group, ensuring that each memory handles approximately the same amount of data. For example, if there are two memories in the group, data pages might be distributed in an alternating odd-even pattern. Ultimately, these selected physical pages together constitute the physical memory space delivered to the user.

[0138] Reference Figure 10This is a schematic diagram illustrating the determination and mapping of physical memory pages corresponding to a group distribution strategy provided in an embodiment of this application. For example... Figure 10 The diagram illustrates the specific architecture of the virtual address to physical address mapping when the allocation policy parameter is configured as a group distribution policy (i.e., Policy=GROUP). Figure 10 The horizontal bar at the top represents a contiguous range of virtual memory page numbers (e.g., from 102 to 109) requested by the user program, corresponding to the memory size parameters included in the physical memory creation request. The computing device first calculates the total number of pages required for this task as 8 pages based on these size parameters, and reserves corresponding virtual page table entries in the logical address space, preparing to map them to the selected underlying physical hardware resources.

[0139] Figure 10 The four vertical pillars at the bottom (labeled LM0, LM1, LM2, and LM3) represent the three-dimensional stacked dynamic random access memory associated with multiple computing modules in the computing device. The computing device first parses the block mask information carried in the request (e.g., "0x3", its binary representation is 0011). The computing device identifies the lower two bits of the mask as "1" (indicating availability), thereby selecting the corresponding LM0 and LM1 as a subset of computing modules and determining their associated memory as the target physical memory set. For example... Figure 10 As shown, LM2 and LM3 (corresponding to the high-order bits of the binary number 0) that are not selected by the mask remain blank and do not participate in this memory allocation. This intuitively reflects the logical isolation of hardware resources based on the mask.

[0140] also, Figure 10 The diagram illustrates the resource balancing operation performed within a defined group. The computing device calculates an average of 4 pages per memory location based on the total required number of pages (8 pages) and the number of available memory locations in the target physical memory set (2 locations, LM0 and LM1). The computing device then selects four remaining free pages from LM0 and LM1 as physical memory pages. Virtual page numbers 102 to 105 are mapped to different physical locations in LM0 (e.g., indices 2, 3, 6, and 9), while virtual page numbers 106 to 109 are mapped to different physical locations in LM1 (e.g., indices 0, 4, 6, and 7). This allocation ensures that data is evenly distributed within the selected "groups."

[0141] Through steps 801 to 804 above, the "group distribution strategy" enables flexible scheduling of memory resources within specific hardware groups. This application's solution, by introducing group mask information, allows computing devices to flexibly define the "granularity" of memory allocation. This achieves parallel access to multiple three-dimensional stacked dynamic random access memories within a group, resulting in higher bandwidth (partial bandwidth aggregation effect) than a single local strategy. Furthermore, by limiting the allocation to a subset of computing modules, it avoids the bus contention issues that might arise with a global distribution strategy. This strategy is particularly suitable for multi-tenant environments or scenarios requiring the execution of multiple independent parallel tasks, providing effective resource isolation and interference suppression while ensuring high performance.

[0142] The following section will further describe how to generate a physical memory handle.

[0143] Reference Figure 11 The process of generating a physical memory handle based on the location information of the physical memory page includes the following steps 1101 to 1103.

[0144] Step 1101: Generate a physical page mapping table based on the number of entries corresponding to the memory size parameter.

[0145] Step 1102: Add the physical location information of all physical memory pages to the physical page mapping table.

[0146] Step 1103: Generate a physical memory handle based on the index pointing to the physical page mapping table.

[0147] Steps 1101 to 1103 are described in detail below.

[0148] In some embodiments, the process of generating physical memory handles based on the location information of physical memory pages first requires constructing a basic data structure to carry the address mapping relationship. The computing device generates a physical page mapping table based on the number of entries corresponding to the memory size parameters. Specifically, the computing device first parses the memory size parameters (e.g., the total number of bytes requested) in the user-initiated physical memory creation request and divides them by the computing device's default page size to calculate the required number of entries. Subsequently, the computing device dynamically allocates a contiguous memory space in kernel space or a specific managed memory region to create an array or linked list structure containing the number of entries, i.e., the physical page mapping table. This physical page mapping table is the core middleware connecting virtual addresses and physical hardware, and each entry reserves space for storing a physical address or page frame number.

[0149] After constructing the empty physical page mapping table, the computing device performs a data filling operation, adding the physical location information of all physical memory pages to the physical page mapping table. During this process, the computing device traverses each physical memory page allocated in the previous steps, reading its corresponding hardware address or physical page frame number; this data constitutes the physical location information. The computing device writes this physical location information one by one into the corresponding index position in the physical page mapping table in logical order. It is understandable that, due to the possibility of a global or group distribution strategy used in the previous steps, these physical memory pages may be physically scattered across different three-dimensional stacked dynamic random access memories, and their physical addresses may be non-contiguous; however, through this filling step, they are organized into a logically continuous sequence in the physical page mapping table, providing a basis for subsequent linear access.

[0150] Once the page mapping table is populated, the computing device needs to generate a credential for the upper-layer application to operate on the resource. This is done by generating a physical memory handle based on an index pointing to the physical page mapping table. This index is a pointer to the starting location of the physical page mapping table in the computing device's memory or a reference to a memory descriptor list (MDL). The computing device encapsulates this index into an opaque identifier, namely the physical memory handle.

[0151] As is understandable, a physical memory handle is an abstract software object that shields user programs from the underlying physical address details and complex hardware topology. When an application subsequently requests to map this physical memory to the virtual address space, it only needs to provide the computing device with this handle, and the computing device can then use the handle to trace back to the corresponding mapping table and find the specific physical page.

[0152] Reference Figure 12 This is a schematic diagram illustrating the generation of a physical memory handle according to an embodiment of this application. Figure 12 As shown, this illustrates the specific data structure states of the computing device in the initial stage of physical memory allocation, where it constructs the physical page mapping table and generates physical memory handles. Figure 12 The three tables at the bottom center correspond to the three different allocation strategies mentioned above (single local, global distribution, and group distribution). In this case, the computing device has completed the locking of physical resources according to the memory size parameters requested by the user and filled the specific physical location information (such as LM1.page1, LM0.page4, etc. shown in the "Physical Address" column of the table) into the mapping table.

[0153] At this stage, the status of the "Virtual Address" column in the table is uniformly displayed as "Undefined". This indicates that only the physical layer resource reservation and handle creation have been completed, and the final MemMap operation has not yet been performed. That is, the projection from the virtual address space to the physical address space has not yet been established, and the physical resources are in an intermediate state of "allocated but not mapped".

[0154] at this time, Figure 12 The left-hand side (Example 1) corresponds to the mapping table structure under a single local strategy. In this scenario, all physical location information recorded in the generated physical page mapping table points to the same three-dimensional stacked dynamic random access memory (LM1). As can be seen, the table entries consecutively record a series of physical page frame numbers located within the same hardware node, from LM1.page1 to LM1.page11. Although the "Virtual Address" column is still "Undefined," this mapping table has already organized physically contiguous or adjacent local resources together. The generated physical memory handle will directly point to this table, preparing for the subsequent mapping of this high-speed local memory to a specific computing task.

[0155] also, Figure 12 The middle section (Example 2) and the right section (Example 3) respectively illustrate the mapping table states under the global distribution strategy and the group distribution strategy. In the middle global strategy example, the physical location information exhibits an alternating jump between LM0 and LM3 (e.g., the first item is LM0.page4, the second is LM0.page7, the third is LM1.page2, etc.), reflecting the discretized distribution of physical pages across the entire computing device. In the right group distribution example, physical pages only alternate between the two specific subsets of computing modules, LM0 and LM1. Although the physical storage locations are highly dispersed, the physical memory handle generated in step 1103 shields this underlying complexity. By pointing to this linearly arranged physical page mapping table, it allows upper-layer applications to manage these discrete hardware resources through a unified credential.

[0156] Through steps 1101 to 1103 above, by establishing a physical page mapping table and generating handles, the abstraction and structuring of physical resource management are achieved. In this application, through the physical page mapping table, the computing device successfully integrates physical memory pages that may be physically discretely distributed on multiple three-dimensional stacked dynamic random access memories into a logically unified resource object. By generating physical memory handles, the computing device establishes a secure resource reference mechanism between kernel mode and user mode, so that applications do not need to directly handle complex physical addressing (especially when multiple non-uniform memory access (NUMA) nodes or stacked memory are involved), but only need to hold a simple handle to achieve efficient management and reuse of high-performance storage resources.

[0157] Step 304: Establish the mapping relationship between the reserved virtual address segment pointed to by the virtual address pointer and the physical memory page in the physical memory handle.

[0158] Step 304 will be described in detail below.

[0159] In some embodiments, the final step involves establishing a mapping between the reserved virtual address segment pointed to by the virtual address pointer and the physical memory page in the physical memory handle. This process (i.e., the Map API call) ultimately binds the logical-layer "pointer" to the physical-layer "handle." At this point, the computing device traverses the virtual pages in the virtual address segment and reads the physical page location information recorded in the handle, filling in the mapping entries one by one in the page table. Through this operation, the originally contiguous virtual address space is transparently and explicitly mapped to a three-dimensional stacked dynamic random access memory that may be discretely distributed among specific computing modules, thus completing the construction of virtualized memory, as described below.

[0160] Reference Figure 13 Establishing a mapping relationship between the reserved virtual address segment pointed to by the virtual address pointer and the physical memory page in the physical memory handle includes the following steps 1301 to 1302.

[0161] Step 1301: Based on the physical memory handle, read at least one record of physical location information from the physical page mapping table.

[0162] Step 1302: Traverse the multiple consecutive virtual pages pointed to by the virtual address pointers, and sequentially establish a one-to-one mapping entry between each virtual page and its physical location information in the physical page mapping table, so that the consecutive virtual address space is discretely mapped to the target physical memory set.

[0163] Steps 1301 to 1302 are described in detail below.

[0164] In some embodiments, for the step of establishing the mapping relationship between the reserved virtual address segment pointed to by the virtual address pointer and the physical memory page in the physical memory handle, a handle-based resource indexing operation is first performed. The computing device reads at least one piece of physical location information recorded in the physical page mapping table based on the physical memory handle. Specifically, the physical memory handle, as an opaque reference identifier, internally encapsulates a pointer to a kernel object or a specific memory description structure; by resolving this handle, the computing device can accurately locate the physical page mapping table, which has been created and populated with physical addresses in the preceding steps. Subsequently, the computing device sequentially extracts pre-allocated hardware address data, i.e., physical location information, from this table. This information represents the physical coordinates of the actual readable and writable three-dimensional stacked dynamic random access memory (DRAM) cells.

[0165] After acquiring physical resource information, the computing device redirects its processing logic to the virtual address space. During this process, the computing device begins traversing multiple consecutive virtual pages pointed to by virtual address pointers. These virtual address pointers are typically returned by memory reservation functions (such as VirtualMemReserve) from user-mode programs, pointing to the beginning of a logically contiguous, linearly arranged virtual address space. The computing device scans this space at page granularity (e.g., 4KB or 2MB), identifying each virtual page awaiting mapping, preparing for subsequent address binding.

[0166] Furthermore, the computing device simultaneously performs address binding operations during the traversal process, that is, sequentially establishing a one-to-one mapping entry between each virtual page and its physical location information in the physical page mapping table. During this process, the computing device fills the currently traversed virtual page number (VPN) into the corresponding "virtual address" field in the physical page mapping table, or updates the computing device's page table entry (PTE) to point to the currently read physical page frame number (PFN). This operation strongly binds the abstract software logical address to the specific hardware physical address, ensuring that when the CPU accesses the virtual page, the memory management unit (MMU) can correctly route the request to the corresponding physical storage unit.

[0167] The ultimate result of the above mapping process is to discretely map a contiguous virtual address space to a target set of physical memory. This means that although from the application's perspective, data is stored in a flat, contiguous buffer, at the physical level, the physical pages constituting this buffer may be scattered and interleaved across multiple different three-dimensional stacked dynamic random access memories through the aforementioned "global distribution strategy" or "group distribution strategy." This mapping method is called "discrete mapping," which successfully shields the complex underlying hardware topology, allowing upper-layer applications to disregard the specific physical distribution of data.

[0168] Through steps 1301 to 1302 above, the combination of handle mechanism and linear traversal mapping achieves efficient decoupling between the memory logical view and physical view. The solution of this application maps continuous virtual pages to discrete physical location information, enabling the computing device to fully utilize the parallel bandwidth advantage of multiple three-dimensional stacked dynamic random access memories at the underlying level while maintaining the simplicity of the application programming model (linear addressing). This mechanism allows user programs to transparently enjoy the high-performance data throughput brought by the underlying multi-channel hardware, just like operating ordinary continuous memory, greatly reducing the development complexity of high-performance computing software.

[0169] Reference Figure 14 This is a schematic diagram illustrating the generation of a mapping relationship provided in an embodiment of this application. For example... Figure 14 The image shows the final view of the physical page map and its corresponding hardware resource status after the computing device calls a memory mapping function (such as MemMap). Figure 14 The bar chart at the top corresponds one-to-one with the three tables below, presenting the mapping results under a single local strategy (Example 1), a global distribution strategy (Example 2), and a group distribution strategy (Example 3), respectively. This is in contrast to the previous stage (i.e., as shown in the previous example). Figure 12 Compared to the physical memory handle generation process shown, Figure 14 The "Virtual Address" column in the table is no longer "Undefined" but is filled with specific virtual page numbers (such as Page 102 to Page 109). This indicates that the traversal mapping operation has been completed, and the computing device has "anchored" the contiguous logical space pointed to by the virtual address pointer to the specific physical hardware.

[0170] like Figure 14 The mapping table structure shown in the lower middle section illustrates how resources managed by physical memory handles are instantiated. Taking the "Global Distribution Strategy" (Example 2) in the middle as an example, the "Physical Address" column in the physical page mapping table retains the previously calculated discrete distribution information (such as LM0.page4, LM0.page7, LM1.page2, etc.). During this process, the computing device sequentially fills the table with consecutive virtual pages (Page102, Page103, Page104...) in a linear order. This process establishes rigid one-to-one mapping entries: Page102 is directed to LM0, while the immediately following Page104 is directed to LM1. This structure intuitively demonstrates the mapping characteristic of "logical continuity, physical discreteness," where the continuous address stream seen by the user program is transparently distributed to different three-dimensional stacked dynamic random access memories at the underlying level.

[0171] The following describes examples of this solution under different strategies.

[0172] The first example describes the process of memory mapping based on a single local strategy. The corresponding code example is shown below.

[0173] User code:

[0174] VirtualMemReserve(size, &ptr);

[0175] LocalMemCreate(*handle, size, policy=SINGLE, localMemID);

[0176] MemMap(ptr, handle, size);

[0177] In this process, the VirtualMemReserve function in the user code first reserves a contiguous region in the logical address space, and the computing device returns a virtual address pointer (ptr) pointing to the beginning of that region. Next, the user initiates a LocalMemCreate call, explicitly passing three key parameters: "8*pageSize" (representing the memory size, i.e., the size of 8 pages requested), an allocation policy parameter set to "SINGLE," and a target module identifier pointing to a specific hardware node (such as "LM1"). This series of instructions explicitly tells the computing device that all subsequent physical resources must and can only come from the specific memory LM1.

[0178] Then, the computing device kernel responds to the above request and executes the @LocalMemCreate logic. The computing device first converts the requested byte size into the required number of pages (i.e., 8 pages) and creates an initial physical page mapping table containing 8 entries. Subsequently, based on the target module identifier (LM1), the computing device excludes other available memory in the device (such as LM0, LM2, LM3) and searches only within the physical address space of the target 3D stacked dynamic random access memory (LM1). The computing device locks 8 specific remaining free pages in LM1 (located at physical locations indices 1, 2, 3, 5, 7, 8, 10, and 11 respectively) and registers this physical location information in the mapping table, generating corresponding physical memory handles.

[0179] The final stage of the process is then triggered by the MemMap function in the user code. The computing device receives the reserved virtual address pointer (ptr) and a handle containing the physical resource, and begins establishing the final mapping. The computing device traverses the consecutive virtual pages numbered 102 to 109 in the virtual address bar, creating a one-to-one page table entry corresponding to each of them and the locked physical pages in LM1. Specifically, virtual page 102 is mapped to physical location 1 in LM1, virtual page 103 is mapped to physical location 2, and so on, until virtual page 109 is mapped to physical location 11. At this point, the "virtual address" field in the mapping table is filled in, and the data path is fully established.

[0180] The second example describes the process of memory mapping based on a globally distributed strategy. The corresponding code example is shown below.

[0181] User code:

[0182] VirtualMemReserve(size, &ptr);

[0183] LocalMemCreate(*handle, size, policy=ALL);

[0184] MemMap(ptr, handle, size);

[0185] In this process, the VirtualMemReserve function in the user code is invoked first, reserving a contiguous region in the logical address space and obtaining a virtual address pointer (ptr). Subsequently, the user initiates a LocalMemCreate call, passing in "8*pageSize" (the total size for requesting 8 pages) representing the memory size parameter and an allocation strategy parameter set to "ALL". This parameter explicitly informs the computing device that the requested physical resources should not be limited to a single node, but should be evenly distributed among all available 3D stacked dynamic random access memories (LM0 to LM3) in the current device.

[0186] Then, the compute device kernel performs a critical load balancing calculation in response to `@LocalMemCreate`. As shown in the code comments, the compute device calculates based on the formula `numPages = size / pageSize / numLMsInDevice`. In this example, the total requirement is 8 pages, and there are 4 available memory locations in the device (`numLMsInDevice = 4`). Therefore, the compute device calculates that the average number of pages to be handled by each 3D stacked dynamic random access memory is 2 pages. Subsequently, the compute device retrieves and locks 2 remaining free pages in each of LM0, LM1, LM2, and LM3, and registers these scattered physical location information into the physical page mapping table, generating corresponding physical memory handles.

[0187] The final mapping is then established by the MemMap function called by the user. The computing device, based on the virtual address pointer (ptr) and handle, sequentially fills the mapping table with a continuous sequence of virtual pages (Page 102 to Page 109). Virtual pages 102 and 103 are mapped to LM0 (located at indices 4 and 7 of LM0, respectively), virtual pages 104 and 105 are mapped to LM1, virtual pages 106 and 107 are mapped to LM2, and virtual pages 108 and 109 are mapped to LM3. This allocation method achieves both logical address continuity and complete physical address discretization.

[0188] The third example describes the process of memory mapping based on a group distribution strategy. The corresponding code example is shown below.

[0189] User code:

[0190] VirtualMemReserve(size, &ptr);

[0191] LocalMemCreate(*handle, size, policy=GROUP, groupMask);

[0192] MemMap(ptr, handle, size);

[0193] In this process, first, the user code executes the VirtualMemReserve function, reserving a contiguous region in the logical address space and obtaining a virtual address pointer (ptr) pointing to the beginning of that region. Next, the user initiates a LocalMemCreate call, explicitly passing in three key control parameters: "size" representing the memory size (corresponding to 8 pages in this example), the allocation strategy parameter set to "GROUP," and the crucial group mask information (groupMask, set to hexadecimal 0x3 in this example). This combination of instructions explicitly tells the computing device that subsequent physical resource allocation should be limited to the specific hardware group specified by the mask.

[0194] In some embodiments, the computing device kernel responds to the above request and executes mask parsing and resource calculation in the @LocalMemCreate logic. The computing device first parses the group mask information 0x3, converts it to binary 0011, and identifies the lowest two bits as "1" (available), thus determining that LM0 and LM1 constitute the subset of computing modules allocated this time, while LM2 and LM3 (corresponding to bit 0) are excluded. Subsequently, the computing device performs load calculation according to the formula numPages = size / pageSize / numLMsInGroup: the total requirement is 8 pages, and the number of effective memory units within the group is 2. Therefore, the average number of pages to be allocated to each 3D stacked dynamic random access memory is calculated to be 4 pages. The computing device then retrieves and locks 4 remaining free pages in LM0 and LM1 respectively, registers these physical location information in the physical page mapping table, and generates corresponding physical memory handles.

[0195] In some embodiments, the final address binding is completed by the MemMap function invoked by the user. The computing device traverses the sequence of virtual pages (Pages 102 to 109) and establishes mapping entries based on the virtual address pointer (ptr) and handle. The first four virtual pages (102 to 105) are mapped to different physical locations in LM0 (e.g., indices 2, 3, 6, and 9), while the last four virtual pages (106 to 109) are mapped to different physical locations in LM1 (e.g., indices 0, 4, 6, and 7).

[0196] By decoupling virtual reservation from physical creation and introducing policy control during the physical allocation phase through steps 301 to 304 above, the management challenges of three-dimensional stacked dynamic random access memory under an architecture without a global crossbar switch are effectively solved. The solution of this application allows the system to be aware of the underlying physical topology and can accurately lock data in the local storage of a specific computing module or module group according to the needs of the computing task, avoiding blind cross-module remote access. Thus, while ensuring the continuity of virtual addresses, the high bandwidth utilization of the three-dimensional stacked memory is maximized and the interconnection latency is reduced.

[0197] This application also provides a virtual memory data processing method for a computing device, which can implement the above-described virtual memory data processing method for a computing device, see reference. Figure 15 The device 1500 includes:

[0198] The virtual reservation module 1510 is used to respond to a virtual memory reservation request by determining the reserved virtual address segment corresponding to the virtual memory reservation request in the virtual address space and generating a virtual address pointer pointing to the reserved virtual address segment.

[0199] The physical creation module 1520 is used to respond to a physical memory creation request by obtaining the memory size parameters and allocation strategy parameters corresponding to the physical memory creation request.

[0200] The physical handle generation module 1530 is used to determine the target physical memory set from multiple three-dimensional stacked dynamic random access memories based on the allocation strategy parameters, allocate physical memory pages corresponding to memory size parameters in the target physical memory set, and then generate physical memory handles based on the location information of the physical memory pages.

[0201] The mapping execution module 1540 is used to establish the mapping relationship between the reserved virtual address segment pointed to by the virtual address pointer and the physical memory page in the physical memory handle.

[0202] In some embodiments, the physical handle generation module 1530 is further configured to:

[0203] When the allocation strategy parameter is a single local strategy, the target module identifier is determined from the physical memory creation request;

[0204] Based on the target module identifier, the target three-dimensional stacked dynamic random access memory is determined from the three-dimensional stacked dynamic random access memory associated with multiple computing modules.

[0205] When the number of remaining free pages in the target 3D stacked dynamic random access memory is not less than the number of required pages corresponding to the memory size parameter, the target 3D stacked dynamic random access memory is used as the target physical memory set.

[0206] Select the remaining free pages corresponding to the required number of pages from the target physical memory set as physical memory pages.

[0207] In some embodiments, the physical handle generation module 1530 is further configured to:

[0208] When the allocation strategy parameter is a global distribution strategy, the three-dimensional stacked dynamic random access memory associated with multiple computing modules is determined as the target physical memory set;

[0209] Based on the required number of pages corresponding to the memory size parameters, calculate the average number of pages that each three-dimensional stacked dynamic random access memory in the target physical memory set needs to share;

[0210] For each three-dimensional stacked dynamic random access memory of the target physical memory set, the remaining free pages corresponding to the average number of pages are selected as physical memory pages.

[0211] In some embodiments, the physical handle generation module 1530 is further configured to:

[0212] When the allocation strategy parameter is a group distribution strategy, the group mask information corresponding to the physical memory creation request is determined.

[0213] Based on the group mask information, a subset of computing modules is selected from multiple computing modules;

[0214] The three-dimensional stacked dynamic random access memory associated with the subset of computing modules is used as the target physical memory set;

[0215] The physical memory pages required for the memory size parameters are evenly distributed among the multiple three-dimensional stacked dynamic random access memories contained in the target physical memory set.

[0216] In some embodiments, the physical handle generation module 1530 is further configured to:

[0217] Identify the available bits in the block mask information;

[0218] The computation modules corresponding to the bits are selected as a subset of computation modules.

[0219] In some embodiments, the physical handle generation module 1530 is further configured to:

[0220] A physical page mapping table is generated based on the number of entries corresponding to the memory size parameters.

[0221] Add the physical location information of all physical memory pages to the physical page mapping table;

[0222] A physical memory handle is generated based on the index pointing to the physical page mapping table.

[0223] In some embodiments, the mapping execution module 1540 is further configured to:

[0224] Based on the physical memory handle, read at least one record of physical location information from the physical page mapping table;

[0225] Traverse multiple consecutive virtual pages pointed to by virtual address pointers, and sequentially establish a one-to-one mapping entry between each virtual page and its physical location information in the physical page mapping table, so that the consecutive virtual address space is discretely mapped to the target physical memory set.

[0226] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, the specific implementation of the virtual memory data processing method of the computing device is basically the same as the specific implementation of the virtual memory data processing method of the computing device described above, and will not be repeated here.

[0227] This application also provides an electronic device, including:

[0228] At least one memory;

[0229] At least one processor;

[0230] At least one program;

[0231] The program is stored in memory, and the processor executes at least one program to implement the virtual memory data processing method of the computing device described above in this application. The electronic device can be any smart terminal, including mobile phones, tablets, personal digital assistants (PDAs), and in-vehicle computers.

[0232] Please see Figure 16 , Figure 16 The hardware structure of an electronic device according to another embodiment is illustrated. The electronic device includes:

[0233] The processor 1601 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application.

[0234] The memory 1602 can be implemented in the form of ROM (Read Only Memory), static storage device, dynamic storage device, or RAM (Random Access Memory). The memory 1602 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 1602, and the processor 1601 calls and executes the virtual memory data processing method of the computing device in the embodiments of this application.

[0235] The input / output interface 1603 is used to implement information input and output;

[0236] The communication interface 1604 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0237] Bus 1605 transmits information between various components of the device (e.g., processor 1601, memory 1602, input / output interface 1603, and communication interface 1604);

[0238] The processor 1601, memory 1602, input / output interface 1603 and communication interface 1604 are connected to each other within the device via bus 1605.

[0239] This application also provides a storage medium, which is a computer-readable storage medium, storing a computer program that, when executed by a processor, implements the virtual memory data processing method of the computing device described above.

[0240] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0241] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0242] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0243] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0244] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0245] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0246] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0247] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. The coupling or direct coupling or communication connection between the shown or discussed units may be through some interfaces, or indirect coupling or communication connection between the apparatus or units, and may be electrical, mechanical, or other forms.

[0248] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0249] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0250] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0251] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A method for processing virtual memory data in a computing device, characterized in that, The computing device includes multiple computing modules, each of which is associated with an independent three-dimensional stacked dynamic random access memory. The method includes: In response to a virtual memory reservation request, a reserved virtual address segment corresponding to the virtual memory reservation request is determined in the virtual address space, and a virtual address pointer pointing to the reserved virtual address segment is generated; In response to a physical memory creation request, obtain the memory size parameters and allocation strategy parameters corresponding to the physical memory creation request; Based on the allocation strategy parameters, a target physical memory set is determined from the plurality of three-dimensional stacked dynamic random access memories, and physical memory pages corresponding to the memory size parameters are allocated in the target physical memory set. Then, a physical memory handle is generated based on the location information of the physical memory pages. Establish a mapping relationship between the reserved virtual address segment pointed to by the virtual address pointer and the physical memory page in the physical memory handle.

2. The virtual memory data processing method for a computing device according to claim 1, characterized in that, The step of determining a target physical memory set from the plurality of three-dimensional stacked dynamic random access memories based on the allocation strategy parameters, and allocating physical memory pages corresponding to the memory size parameters in the target physical memory set, includes: When the allocation strategy parameter is a single local strategy, the target module identifier is determined from the physical memory creation request; Based on the target module identifier, the target three-dimensional stacked dynamic random access memory is determined from the three-dimensional stacked dynamic random access memory associated with the plurality of computing modules; When the number of remaining free pages in the target three-dimensional stacked dynamic random access memory is not less than the number of required pages corresponding to the memory size parameter, the target three-dimensional stacked dynamic random access memory is used as the target physical memory set. Select the remaining free pages corresponding to the required number of pages from the target physical memory set as the physical memory pages.

3. The virtual memory data processing method for a computing device according to claim 1, characterized in that, The step of determining a target physical memory set from the plurality of three-dimensional stacked dynamic random access memories based on the allocation strategy parameters, and allocating physical memory pages corresponding to the memory size parameters in the target physical memory set, includes: When the allocation strategy parameter is a global distribution strategy, the three-dimensional stacked dynamic random access memory associated with the multiple computing modules is determined as the target physical memory set; Based on the required number of pages corresponding to the memory size parameters, calculate the average number of pages that each of the three-dimensional stacked dynamic random access memories in the target physical memory set needs to share; For each of the three-dimensional stacked dynamic random access memories in the target physical memory set, the remaining free pages corresponding to the average number of pages are selected as the physical memory pages.

4. The virtual memory data processing method for a computing device according to claim 1, characterized in that, The step of determining a target physical memory set from the plurality of three-dimensional stacked dynamic random access memories based on the allocation strategy parameters, and allocating physical memory pages corresponding to the memory size parameters in the target physical memory set, includes: When the allocation strategy parameter is a group distribution strategy, the group mask information corresponding to the physical memory creation request is determined; Based on the grouping mask information, a subset of computing modules is selected from the plurality of computing modules; The three-dimensional stacked dynamic random access memory associated with the subset of computing modules is used as the target physical memory set; The physical memory pages required for the memory size parameters are evenly distributed among the multiple three-dimensional stacked dynamic random access memories contained in the target physical memory set.

5. The virtual memory data processing method for a computing device according to claim 4, characterized in that, The group mask information is used to indicate which computing modules are operating normally. The step of selecting a subset of computing modules from the plurality of computing modules based on the group mask information includes: Determine the bits identified as usable in the block mask information; The calculation module corresponding to the bit is selected as the subset of calculation modules.

6. The virtual memory data processing method for a computing device according to claim 1, characterized in that, The step of generating a physical memory handle based on the location information of the physical memory page includes: A physical page mapping table is generated based on the number of entries corresponding to the memory size parameters; Add the physical location information of all the physical memory pages to the physical page mapping table; The physical memory handle is generated based on the index pointing to the physical page mapping table.

7. The virtual memory data processing method for a computing device according to claim 1, characterized in that, The step of establishing the mapping relationship between the reserved virtual address segment pointed to by the virtual address pointer and the physical memory page in the physical memory handle includes: Based on the physical memory handle, read at least one physical location information recorded in the physical page mapping table; The system iterates through multiple consecutive virtual pages pointed to by the virtual address pointers and sequentially establishes a one-to-one mapping entry between each virtual page and the physical location information in the physical page mapping table, so that the consecutive virtual address space is discretely mapped to the target physical memory set.

8. The virtual memory data processing method for a computing device according to claim 1, characterized in that, The computing module can be any one of a computing chip, a computing cluster, or a computing unit.

9. A virtual memory data processing system for a computing device, characterized in that, The computing device includes multiple computing modules, each of which is associated with an independent three-dimensional stacked dynamic random access memory. The system includes: The virtual reservation module is used to respond to a virtual memory reservation request, determine the reserved virtual address segment corresponding to the virtual memory reservation request in the virtual address space, and generate a virtual address pointer pointing to the reserved virtual address segment; The physical creation module is used to respond to a physical memory creation request by obtaining the memory size parameters and allocation strategy parameters corresponding to the physical memory creation request. The physical handle generation module is used to determine a target physical memory set from the plurality of three-dimensional stacked dynamic random access memories based on the allocation strategy parameters, allocate physical memory pages corresponding to the memory size parameters in the target physical memory set, and then generate a physical memory handle based on the location information of the physical memory pages. The mapping execution module is used to establish a mapping relationship between the reserved virtual address segment pointed to by the virtual address pointer and the physical memory page in the physical memory handle.

10. An electronic device, characterized in that, The device includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the virtual memory data processing method of the computing device according to any one of claims 1 to 8.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the virtual memory data processing method of the computing device according to any one of claims 1 to 8.

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