Heterogeneous multi-core instruction set architecture-oriented memory system performance optimization method and device

Abstract

The invention provides a memory system performance optimization method and device oriented to a heterogeneous multi-core instruction set architecture, relates to the technical field of computer systems, and aims to solve the technical problems that an existing data storage system is high in memory overhead and low in memory allocation efficiency. The method comprises: based on an application programming interface, establishing an association relationship between a memory allocator and an instruction set architecture, the association relationship including a first binding relationship between a high-performance memory allocator and a high-performance core, and a second binding relationship between a lightweight energy efficiency memory allocator and an energy efficiency core; in response to a received memory allocation instruction initiated by a current thread, acquiring memory space parameters and task types required by the memory allocation instruction; determining a target core according to the memory space parameter and the task type; according to the target core, determining a target memory allocator by using an association relationship; and allocating the memory according to the target memory allocator.

Description

Technical Field

[0001] This invention relates to the field of computer system technology, and more specifically, to a method and apparatus for optimizing memory system performance for heterogeneous multi-core instruction set architectures. Background Technology

[0002] With the continuous iteration and development of computer technology, traditional instruction set architectures have established extremely high technical barriers, making it very difficult for developers to build application software. In recent years, a new type of open, modular, and customizable instruction set architecture has gradually emerged and developed rapidly, and its related processor systems have been widely used in smart IoT devices, edge computing platforms, and high-performance computing systems. When developing application software based on this instruction set architecture processor, it is usually paired with a related operating system and data storage system to support the upper-layer application in realizing its functions.

[0003] Although some current data storage systems can achieve basic memory allocation using their built-in high-performance memory management components, the following problems still exist:

[0004] (1) Existing data storage systems rely on a single high-performance memory management component, resulting in high memory overhead and reduced memory utilization efficiency.

[0005] (2) The memory allocator of the existing data storage system does not fully consider the hardware characteristics of the multi-core instruction set architecture processor, resulting in low memory allocation efficiency and affecting the overall performance of the data storage system. Summary of the Invention

[0006] In view of this, the present invention provides a method and apparatus for optimizing the performance of memory systems for heterogeneous multi-core instruction set architectures, aiming to solve the technical problems of high memory overhead and low memory allocation efficiency in existing data storage systems.

[0007] One aspect of the present invention provides a method for optimizing memory system performance for heterogeneous multi-core instruction set architectures, comprising: establishing an association between a memory allocator and the instruction set architecture based on an application programming interface (API), wherein the memory allocator includes a first memory allocator and a second memory allocator, and the association includes a first binding relationship between the first memory allocator and a first core, and a second binding relationship between the second memory allocator and a second core; in response to receiving a memory allocation instruction initiated by the current thread, obtaining the memory space parameters and task type required by the memory allocation instruction; determining a target core from the first core and the second core based on the memory space parameters and the task type; determining a target memory allocator from the first memory allocator and the second memory allocator based on the target core and the association; and allocating memory based on the target memory allocator.

[0008] According to an embodiment of the present invention, determining a target core from a first core and a second core based on memory space parameters and task type includes: determining the second core as the target core in response to the memory space parameters and task type meeting preset conditions; and determining the first core as the target core in response to the memory space parameters and task type not meeting preset conditions.

[0009] According to an embodiment of the present invention, allocating memory according to a target memory allocator includes: predicting potential memory requirements within a specified time period based on the historical memory operation characteristics of the current application; and guiding the target memory allocator to allocate memory based on the potential memory requirements.

[0010] According to an embodiment of the present invention, the method further includes: establishing a memory block reuse pool, wherein the reuse pool includes multiple memory blocks, and the lifetime of the multiple memory blocks is <1s; in response to receiving a memory allocation instruction initiated by the current thread, matching the target memory block corresponding to the memory allocation instruction in the reuse pool; and allocating memory according to the target memory block.

[0011] According to an embodiment of the present invention, the reuse pool is configured to automatically adjust the size of the reuse pool capacity based on the reuse rate; wherein, in response to the reuse rate being less than a reuse rate threshold, the reuse pool capacity is reduced, and in response to the reuse rate being greater than the reuse rate threshold, the reuse pool capacity is expanded.

[0012] According to an embodiment of the present invention, the method further includes: establishing a multi-level reclamation strategy; and performing reclamation processing on memory blocks according to the multi-level reclamation strategy, wherein the multi-level reclamation strategy includes a first-level reclamation, a second-level reclamation, and a third-level reclamation; the first-level reclamation represents real-time reclamation of memory blocks after they are released; the second-level reclamation represents reclamation of idle memory blocks within a preset time interval; and the third-level reclamation represents reclamation of idle memory blocks when the system load is lower than a load threshold.

[0013] According to an embodiment of the present invention, the method further includes: in response to a memory allocation instruction requiring the migration of memory blocks between a first core and a second core, performing a migration operation using pre-configured atomic instructions; and in response to the completion of the migration operation, clearing the cache associated with the virtual memory mapping using pre-configured synchronization clearing instructions, and synchronizing the latest memory view.

[0014] Another aspect of the present invention provides a memory system performance optimization device for heterogeneous multi-core instruction set architectures, comprising: an establishment module for establishing an association between a memory allocator and an instruction set architecture based on an application programming interface, wherein the memory allocator includes a first memory allocator and a second memory allocator, and the association includes a first binding relationship between the first memory allocator and a first core, and a second binding relationship between the second memory allocator and a second core; an acquisition module for acquiring memory space parameters and task type required by a memory allocation instruction initiated by a current thread in response to receiving such an instruction; a first determination module for determining a target core from the first core and the second core based on the memory space parameters and the task type; a second determination module for determining a target memory allocator from the first memory allocator and the second memory allocator based on the target core and the association; and an allocation module for allocating memory based on the target memory allocator.

[0015] Another aspect of the present invention provides an electronic device comprising: one or more processors; and a memory for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors cause the one or more processors to implement the method described above.

[0016] Another aspect of the present invention provides a computer-readable storage medium storing computer-executable instructions, which, when executed, are used to implement the method described above.

[0017] Another aspect of the present invention provides a computer program product including computer-executable instructions that, when executed, are used to implement the method described above.

[0018] Compared with the prior art, the memory system performance optimization method and apparatus for heterogeneous multi-core instruction set architectures provided in this invention have at least the following beneficial effects:

[0019] (1) The memory system performance optimization method and apparatus for heterogeneous multi-core instruction set architecture provided in the embodiments of the present invention introduces a hybrid memory allocator at the bottom layer of the data storage system (memory database). At the same time, it proposes a memory allocation mode based on "thread-core-allocator" for the characteristics of heterogeneous multi-core instruction set architecture processors, that is, it establishes a binding relationship between the core and the allocator, overcomes the defects of a single allocator, makes full use of the characteristics of instruction set architecture processors, and improves the efficiency of memory allocation and use.

[0020] (2) The memory system performance optimization method and apparatus for heterogeneous multi-core instruction set architecture provided in the embodiments of the present invention propose a full life cycle optimization management method of memory block "prediction-pre-allocation-reuse-recycling", which greatly improves the overall memory performance. Attached Figure Description

[0021] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0022] Figure 1 A flowchart illustrating a memory system performance optimization method for heterogeneous multi-core instruction set architectures according to an embodiment of the present invention is shown.

[0023] Figure 2 This schematically illustrates a structural block diagram of a memory system performance optimization device for heterogeneous multi-core instruction set architectures according to an embodiment of the present invention.

[0024] Figure 3 The diagram illustrates a block diagram of an electronic device suitable for implementing a memory system performance optimization method for heterogeneous multi-core instruction set architectures according to an embodiment of the present invention. Detailed Implementation

[0025] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0027] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0028] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0029] In the embodiments of this invention, the collection, updating, analysis, processing, use, transmission, provision, disclosure, and storage of data (e.g., including but not limited to user personal information) comply with relevant laws and regulations, are used for legitimate purposes, and do not violate public order and good morals. In particular, necessary measures have been taken to prevent unauthorized access to user personal information data and to maintain the security of user personal information and network security.

[0030] With the continuous iteration and development of computer technology, traditional instruction set architectures have established extremely high technical barriers, making it very difficult for developers to build application software. In recent years, a new type of open, modular, and customizable instruction set architecture has gradually emerged and developed rapidly, and its related processor systems have been widely used in smart IoT devices, edge computing platforms, and high-performance computing systems.

[0031] For example, systems-on-a-chip (SoCs) based on open instruction set architectures have moved from the laboratory to a broad market including smart IoT, edge computing, and high-performance computing. When building application software based on instruction set architecture processors, they are usually paired with relevant operating systems and in-memory databases (such as data storage systems) to support upper-layer applications in implementing their functions.

[0032] Data storage systems address the performance bottlenecks of traditional disk databases under high concurrency or low latency requirements, and can be used as databases, caches, and message brokers, finding widespread application in various scenarios. Memory allocation efficiency is a key factor affecting the performance of data storage systems, typically implemented using high-performance memory management components. However, while these components perform excellently in multi-threaded, large memory block allocation scenarios, they incur significant memory overhead, adding approximately 8%-12% of overhead and reducing memory utilization. Furthermore, these high-performance memory management components lack deep customization and optimization for instruction set architecture and hardware characteristics, resulting in poor platform compatibility and reduced efficiency in memory allocation and deallocation. Therefore, existing data storage systems suffer from the following problems:

[0033] (1) Existing data storage systems rely on a single high-performance memory management component, resulting in high memory overhead and reduced memory utilization efficiency.

[0034] (2) The memory allocator of the existing data storage system does not fully consider the hardware characteristics of the multi-core instruction set architecture processor, resulting in low memory allocation efficiency and affecting the overall performance of the data storage system.

[0035] Based on this, embodiments of the present invention provide a method and apparatus for optimizing the performance of memory systems for heterogeneous multi-core instruction set architectures, aiming to solve the technical problems of high memory overhead and low memory allocation efficiency in existing data storage systems.

[0036] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0037] Figure 1 A flowchart illustrating a memory system performance optimization method for heterogeneous multi-core instruction set architectures according to an embodiment of the present invention is shown.

[0038] like Figure 1 As shown, the memory system performance optimization method for heterogeneous multi-core instruction set architecture in this embodiment may include, for example, operations S1 to S5.

[0039] In operation S1, based on the application programming interface, the association between the memory allocator and the instruction set architecture is established. The memory allocator includes a first memory allocator and a second memory allocator. The association includes a first binding relationship between the first memory allocator and the first core, and a second binding relationship between the second memory allocator and the second core.

[0040] In operation S2, in response to receiving a memory allocation instruction initiated by the current thread, the memory space parameters and task type required by the memory allocation instruction are obtained.

[0041] When operating S3, the target core is determined from the first core and the second core based on memory space parameters and task type.

[0042] In operation S4, based on the target core, the target memory allocator is determined from the first memory allocator and the second memory allocator using the correlation relationship.

[0043] In operation S5, memory is allocated according to the target memory allocator.

[0044] Instruction set architecture processors typically employ a heterogeneous multi-core architecture design. A heterogeneous multi-core processor may include a high-performance core (i.e., the first core) with high processing power and strong processing capabilities, and an energy-efficient core (i.e., the second core) with weaker processing capabilities suitable for single-threaded, single-task applications.

[0045] This embodiment presents a quantitative definition method for high-performance cores and energy-efficient cores. In practical applications, this method can be implemented by establishing a processor core metric submodule at the system level, thus achieving core partitioning. For example, on a typical heterogeneous multi-core instruction set architecture processor, a hardware performance monitoring unit (PMU) can collect microarchitectural metrics for each core, including:

[0046] Computational performance, also known as instructions per clock (IPC) and branch prediction accuracy; cache performance, also known as L1 / L2 cache hit rate and cache line fill latency; and memory bandwidth, also known as local memory controller bandwidth.

[0047] In this embodiment, a processor core that satisfies IPC>2.0 and L2 cache>512KB is defined as a high-performance core (first core), and a processor core that satisfies IPC<1.2 is defined as an energy-efficient core (second core).

[0048] When different processor cores coexist, traditional memory allocation methods using a single memory allocator cannot fully utilize the characteristics of heterogeneous multi-core architectures. To fully leverage the features of heterogeneous multi-core architectures, this embodiment breaks away from the traditional "thread-allocator" memory allocation model and proposes a "thread-core-allocator" model. While retaining the existing first memory allocator (i.e., the high-performance memory allocator) in the data storage system, a second memory allocator (i.e., a lightweight and energy-efficient memory allocator) is introduced.

[0049] The second memory allocator is lightweight and highly efficient for allocating small memory blocks, but it is unsuitable for use in multi-threaded concurrency due to global lock contention issues. By introducing a second memory allocator, combining the advantages of a high-performance and a lightweight, energy-efficient allocator, thread affinity can be set through the operating system's Application Programming Interface (API) to establish a relationship between the memory allocator and the instruction set architecture. Specifically:

[0050] Binding the first memory allocator to the first core (representing the first binding relationship) means binding the high-performance memory allocator to the high-performance core for handling large memory blocks and multi-threaded concurrency, and binding the second memory allocator to the second core (representing the second binding relationship) means binding the lightweight and energy-efficient memory allocator to the energy-efficient core for handling small memory blocks and single-threaded tasks.

[0051] At the implementation level, the underlying calls to a lightweight, energy-efficient memory allocator can be introduced by modifying relevant functions in the data storage system, thus implementing different memory allocator logic. A memory allocator thread pool can be built, and threads using different memory allocators can be fixed to high-performance and energy-efficient cores through extended functions in the thread library, avoiding scheduling turbulence and achieving thread-core binding. Tests show that inter-core switching latency has been reduced by 65%.

[0052] The memory system performance optimization method for heterogeneous multi-core instruction set architecture provided by this invention introduces a hybrid memory allocator to the underlying layer of the data storage system (memory database). At the same time, it proposes a memory allocation mode based on "thread-core-allocator" to take into account the characteristics of heterogeneous multi-core instruction set architecture processors. That is, it establishes a binding relationship between the core and the allocator, overcomes the defects of a single allocator, makes full use of the characteristics of instruction set architecture processors, and improves the efficiency of memory allocation and utilization.

[0053] According to an embodiment of the present invention, operation S2, in response to receiving a memory allocation instruction initiated by the current thread, obtains the memory space parameters and task type required by the memory allocation instruction, for example:

[0054] Before allocating memory, first determine the required memory size and the current task type. The task type may include, for example:

[0055] High-power tasks involving a central processing unit (CPU) or high input / output operations (high I / O tasks).

[0056] According to an embodiment of the present invention, operation S3 determines the target core from the first core and the second core based on memory space parameters and task type, specifically including:

[0057] If the memory space parameters and task type meet the preset conditions, the second core is determined as the target core; if the memory space parameters and task type do not meet the preset conditions, the first core is determined as the target core.

[0058] For example, in this embodiment, when the required space is <1KB or when it is a high IO task, the second core is used as the target core, that is, the energy-efficient core thread is used to perform memory allocation and IO read / write operations.

[0059] In all other cases, the first core is used as the target core, meaning that high-performance cores are used for processing in all other cases.

[0060] For high-performance cores, a load threshold can be set. For example, the load of each core can be checked every 100ms between different high-performance cores. If the load of a core exceeds the load threshold, a "memory block" migration is performed, migrating some memory blocks to the low-load high-performance core to achieve load balancing.

[0061] According to an embodiment of the present invention, operation S4 determines the target memory allocator from the first memory allocator and the second memory allocator based on the target core and using the association relationship, for example:

[0062] Since the association between the memory allocator and the instruction set architecture has been established in advance, once the target core is determined based on the memory space parameters and task type, the target memory allocator that is bound to it can be determined based on the corresponding target core, and then subsequent memory allocation can be carried out based on the target memory allocator.

[0063] According to an embodiment of the present invention, operation S5 allocates memory according to the target memory allocator, which may specifically include:

[0064] Based on the historical memory operation characteristics of the current application, predict the potential memory demand within a specified time period; based on the potential memory demand, guide the target memory allocator to allocate memory.

[0065] In this embodiment, to further improve the efficiency of memory allocation threads, a four-stage intelligent optimization management mechanism for the entire lifecycle of memory blocks, namely "prediction-pre-allocation-reuse-reclaim", is proposed.

[0066] For example, first, a pre-allocation engine is established to implement memory block pre-allocation, specifically:

[0067] Based on the operational history of the data storage system's memory, such as the most recent 1000 records of memory data, the potential memory demand within the next 100ms is predicted using exponential smoothing (with a smoothing constant α = 0.3), as follows:

[0068] If the predicted growth in demand for memory blocks with a space of <1KB exceeds a threshold (e.g., the threshold is set to 20%), then 10 blocks are pre-allocated using a lightweight, energy-efficient memory allocator (retained in the local cache) to avoid real-time allocation latency.

[0069] If the predicted increase in demand for memory blocks with a space of ≥1KB exceeds the threshold, the high-performance memory allocator is invoked to reserve contiguous physical pages to reduce the failure of the TLB, also known as the Translation Lookaside Buffer (TLB).

[0070] When the system memory pressure is greater than 0.7, the pre-allocation coefficient is reduced by 50% to avoid resource waste by dynamically adjusting the pre-allocation trigger conditions.

[0071] According to an embodiment of the present invention, the method may further include, for example:

[0072] Establish a memory block reuse pool, which includes multiple memory blocks, each with a lifespan of less than 1 second; in response to receiving a memory allocation instruction initiated by the current thread, match the target memory block corresponding to the memory allocation instruction in the reuse pool; allocate memory according to the target memory block.

[0073] In this embodiment, memory block reuse pools are further established for memory blocks with short lifecycles to avoid multiple frequent memory allocation operations. For example, eight reuse pools can be established for memory blocks with lifecycles of <1s and sizes of 256B, 512B, 1KB, 2KB, 4KB, 8KB, 16KB, and 32KB, respectively. Each reuse pool is associated with a doubly linked list to accelerate access.

[0074] When freeing memory, if the memory block's lifecycle and size meet the above requirements, it is not actually freed but added to the reuse pool. When allocating memory, it is preferentially obtained from the reuse pool. If a matching memory exists in the reuse pool, i.e., a hit occurs, the allocator call can be skipped. Tests show that this mechanism can reduce latency by 70%.

[0075] According to an embodiment of the present invention, the reuse pool is configured to automatically adjust the size of the reuse pool according to the reuse rate.

[0076] Specifically, in response to a reuse rate less than the reuse rate threshold, the reuse pool capacity is reduced; in response to a reuse rate greater than the reuse rate threshold, the reuse pool capacity is expanded.

[0077] In this embodiment, the capacity of the constructed reuse pool can be adaptively adjusted, for example:

[0078] When the reuse rate (number of reuses / total number of allocations) is less than 30%, the capacity of the reuse pool will be automatically reduced, such as releasing memory blocks that are 1 / 3 of the current size of the reuse pool.

[0079] When the reuse rate is greater than 70%, the reuse pool will be expanded, for example, by increasing the capacity by 20% of the existing capacity.

[0080] According to an embodiment of the present invention, the method may further include, for example:

[0081] Establish a multi-level reclamation strategy; based on the multi-level reclamation strategy, reclaim memory blocks. The multi-level reclamation strategy includes first-level reclamation, second-level reclamation, and third-level reclamation. First-level reclamation means that memory blocks are reclaimed in real time after they are released. Second-level reclamation means that idle memory blocks are reclaimed within a preset time interval. Third-level reclamation means that idle memory blocks are reclaimed when the system load is lower than the load threshold.

[0082] In this embodiment, the low-power characteristics of the instruction set architecture are further combined to design a three-level recycling strategy, as follows:

[0083] Level 1 reclamation (real-time): When releasing a memory block, if it belongs to a lightweight and energy-efficient memory allocator and its size is less than the threshold, it is directly returned to its memory pool; if it belongs to a high-performance memory allocator and is on a high-performance core, thread cache reclamation is triggered.

[0084] Secondary recycling (periodic): Executed every 1 second by the energy efficiency core, it calls the relevant functions of the high-performance memory allocator to clean up the thread cache and merge the free blocks of the lightweight energy efficiency memory allocator (for example, it can use the vector extension instructions of the instruction set architecture to batch mark adjacent blocks).

[0085] Level 3 reclamation (under low load): When the system CPU idle rate is >50%, large page merging is triggered (e.g., merging multiple 4KB pages into a 2MB large page). The page table attributes are modified through specific instructions of the instruction set architecture to improve the TLB hit rate (tests show that the access speed in large page scenarios is improved by 2.3 times).

[0086] Building upon this foundation, fault tolerance and adaptive degradation mechanisms can be established to address potential resource saturation or hardware anomalies in instruction set architecture devices, ensuring the stable operation of the data storage system. The fault tolerance strategy involves monitoring the health of memory allocators, detecting abnormal states in both high-performance and lightweight energy-efficient memory allocators in real time. Health metrics used can include the number of allocation failures, the rate of increase in memory fragmentation, and the percentage of lock contention time.

[0087] When the health of the high-performance memory allocator is less than 60%, for example, if three large memory block allocations fail in a row, the threshold is automatically temporarily increased to the maximum value, such as 16KB, to force small memory blocks to also use the lightweight and energy-efficient memory allocator.

[0088] When the health of the lightweight, energy-efficient memory allocator is less than 60%, for example, when the fragmentation rate is greater than 30%, the "emergency mode" of the high-performance memory allocator is enabled to reduce thread contention.

[0089] The memory system performance optimization method for heterogeneous multi-core instruction set architecture provided by this invention proposes a full lifecycle optimization management method of memory blocks, namely "prediction-pre-allocation-reuse-reclaim", which greatly improves the overall memory performance.

[0090] According to an embodiment of the present invention, the method may further include, for example:

[0091] In response to a memory allocation instruction requiring the migration of memory blocks between the first and second cores, the migration operation is performed using pre-configured atomic instructions; in response to the completion of the migration operation, the cache associated with virtual memory mapping is cleared using pre-configured synchronization clear instructions, and the latest memory view is synchronized.

[0092] In this embodiment, to fully utilize the instruction set characteristics of the instruction set architecture, memory operations were further customized, for example:

[0093] When high-performance cores migrate "memory blocks", it can be done through atomic instructions (address space isolation) of the instruction set architecture to ensure data consistency.

[0094] When performing affinity thread binding, the high-performance memory allocator allocated by the high-performance core can be set to "G=0 (non-global page)" to avoid cache pollution from other cores. Simultaneously, the "Physical Memory Attributes (PMA)" configuration can be enabled for the lightweight energy-efficient memory allocator allocated by the energy-efficient core, mapping it to low-latency static random-access memory (SRAM) (if present), resulting in a measured reduction in access latency from 35ns to 12ns.

[0095] Figure 2 The diagram illustrates a structural block diagram of a memory system performance optimization device for heterogeneous multi-core instruction set architectures according to an embodiment of the present invention.

[0096] like Figure 2 As shown, the memory system performance optimization device 200 for heterogeneous multi-core instruction set architecture according to an embodiment of the present invention includes: an establishment module 210, an acquisition module 220, a first determination module 230, a second determination module 240, and an allocation module 250.

[0097] The establishment module 210 is used to establish the association between the memory allocator and the instruction set architecture based on the application programming interface. The memory allocator includes a first memory allocator and a second memory allocator. The association includes a first binding relationship between the first memory allocator and the first core, and a second binding relationship between the second memory allocator and the second core.

[0098] The acquisition module 220 is used to obtain the memory space parameters and task type required by the memory allocation instruction in response to receiving the memory allocation instruction initiated by the current thread.

[0099] The first determining module 230 is used to determine the target core from the first core and the second core based on memory space parameters and task type.

[0100] The second determining module 240 is used to determine the target memory allocator from the first memory allocator and the second memory allocator based on the target core and using the association relationship.

[0101] The allocation module 250 is used to allocate memory according to the target memory allocator.

[0102] Any one or more of the modules, submodules, units, and subunits according to embodiments of the present invention, or at least part of the functions of any one or more of them, can be implemented in a single module. Any one or more of the modules, submodules, units, and subunits according to embodiments of the present invention can be implemented by being divided into multiple modules. Any one or more of the modules, submodules, units, and subunits according to embodiments of the present invention can be at least partially implemented as hardware circuits, such as field-programmable gate arrays (FPGAs), programmable logic arrays (PLAs), systems-on-a-chip, systems-on-a-substrate, systems-on-package, application-specific integrated circuits (ASICs), or implemented in hardware or firmware by any other reasonable means of integrating or packaging circuits, or implemented in software, hardware, and firmware, or in any suitable combination of any of these three implementation methods. Alternatively, one or more of the modules, submodules, units, and subunits according to embodiments of the present invention can be at least partially implemented as computer program modules, which, when run, can perform corresponding functions.

[0103] For example, any multiple of the establishment module 210, acquisition module 220, first determination module 230, second determination module 240, and allocation module 250 can be combined into one module / unit / subunit, or any one of these modules / units / subunits can be split into multiple modules / units / subunits. Alternatively, at least part of the functionality of one or more of these modules / units / subunits can be combined with at least part of the functionality of other modules / units / subunits and implemented in one module / unit / subunit. According to embodiments of the present invention, at least one of the establishment module 210, acquisition module 220, first determination module 230, second determination module 240, and allocation module 250 can be at least partially implemented as hardware circuitry, such as a field-programmable gate array (FPGA), programmable logic array (PLA), system-on-a-chip, system-on-a-substrate, system-on-package, application-specific integrated circuit (ASIC), or any other reasonable means of integrating or packaging the circuitry, or implemented in software, hardware, or firmware, or in any suitable combination of any of these three implementation methods. Alternatively, at least one of the creation module 210, acquisition module 220, first determination module 230, second determination module 240 and allocation module 250 may be implemented at least partially as a computer program module, which can perform corresponding functions when the computer program module is run.

[0104] It should be noted that the memory system performance optimization device part for heterogeneous multi-core instruction set architecture in the embodiments of the present invention corresponds to the memory system performance optimization method part for heterogeneous multi-core instruction set architecture in the embodiments of the present invention. For a detailed description of the memory system performance optimization device part for heterogeneous multi-core instruction set architecture, please refer to the memory system performance optimization method part for heterogeneous multi-core instruction set architecture, which will not be repeated here.

[0105] Figure 3 The diagram illustrates a block diagram of an electronic device suitable for implementing a memory system performance optimization method for heterogeneous multi-core instruction set architectures according to an embodiment of the present invention. Figure 3 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments of the present invention.

[0106] like Figure 3 As shown, an electronic device 300 according to an embodiment of the present invention includes a processor 301, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 302 or a program loaded from a storage portion 308 into a random access memory (RAM) 303. The processor 301 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 301 may also include onboard memory for caching purposes. The processor 301 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present invention.

[0107] The storage section 308 stores various programs and data required for the operation of the electronic device 300. The processor 301, ROM 302, and storage section 308 are interconnected via bus 304. The processor 301 executes various operations of the method flow according to embodiments of the present invention by executing programs in ROM 302 and / or storage section 308. It should be noted that the programs may also be stored in one or more memories other than ROM 302 and storage section 308. The processor 301 may also execute various operations of the method flow according to embodiments of the present invention by executing programs stored in said one or more memories.

[0108] According to an embodiment of the present invention, the electronic device 300 may further include an input / output (I / O) interface 305, which is also connected to a bus 304. The electronic device 300 may also include one or more of the following components connected to the input / output (I / O) interface 305: an input section 306 including a keyboard, mouse, etc.; an output section 307 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 308 including a hard disk, etc.; and a communication section 309 including a network interface card such as a LAN card, modem, etc. The communication section 309 performs communication processing via a network such as the Internet. A drive 310 is also connected to the input / output (I / O) interface 305 as needed. A removable medium 311, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 310 as needed so that computer programs read from it can be installed into the storage section 308 as needed.

[0109] According to embodiments of the present invention, the method flow according to embodiments of the present invention can be implemented as a computer software program. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a computer-readable storage medium, the computer program containing program code for performing the method shown in the flowchart. In such embodiments, the computer program can be downloaded and installed from a network via communication section 309, and / or installed from removable medium 311. When the computer program is executed by processor 301, it performs the functions defined in the system of the embodiments of the present invention. According to embodiments of the present invention, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0110] The present invention also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of the present invention.

[0111] According to embodiments of the present invention, the computer-readable storage medium may be a non-volatile computer-readable storage medium. Examples include, but are not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In the present invention, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0112] For example, according to embodiments of the present invention, a computer-readable storage medium may include the ROM 302 and / or storage portion 308 described above and / or one or more memories other than ROM 302 and storage portion 308.

[0113] Embodiments of the present invention also include a computer program product comprising a computer program containing program code for performing the methods provided in the embodiments of the present invention. When the computer program product is run on an electronic device, the program code is used to enable the electronic device to implement the methods provided in the embodiments of the present invention.

[0114] When the computer program is executed by the processor 301, it performs the functions defined in the system / apparatus of this embodiment of the invention. According to embodiments of the invention, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0115] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and may be downloaded and installed via communication section 309, and / or installed from removable medium 311. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0116] According to embodiments of the present invention, program code for executing the computer programs provided in the embodiments of the present invention can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0117] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions. Those skilled in the art will understand that the features described in the various embodiments of the present invention can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments of the present invention can be combined and / or combined in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or pairings fall within the scope of this invention.

[0118] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A method for optimizing the performance of memory systems for heterogeneous multi-core instruction set architectures, characterized in that, The instruction set architecture includes a first core and a second core, and the method includes: Based on the application programming interface, an association relationship is established between the memory allocator and the instruction set architecture. The memory allocator includes a first memory allocator and a second memory allocator. The association relationship includes a first binding relationship between the first memory allocator and the first core, and a second binding relationship between the second memory allocator and the second core. In response to receiving a memory allocation instruction initiated by the current thread, obtain the memory space parameters and task type required by the memory allocation instruction; Based on the memory space parameters and the task type, the target core is determined from the first core and the second core; Based on the target core, and using the association relationship, the target memory allocator is determined from the first memory allocator and the second memory allocator; Allocate memory according to the target memory allocator.

2. The method according to claim 1, characterized in that, The step of determining the target core from the first core and the second core based on the memory space parameters and the task type includes: In response to the memory space parameters and the task type meeting preset conditions, the second core is determined to be the target core; In response to the fact that the memory space parameters and the task type do not meet the preset conditions, the first core is determined to be the target core.

3. The method according to claim 1, characterized in that, The step of allocating memory according to the target memory allocator includes: Based on the historical memory operation characteristics of the current application, predict the potential memory demand within a specified time period; Based on the potential memory requirements, the target memory allocator is guided to allocate memory.

4. The method according to claim 1, characterized in that, The method further includes: Establish a memory block reuse pool, wherein the reuse pool includes multiple memory blocks, and the lifetime of the multiple memory blocks is <1 second; In response to receiving a memory allocation instruction initiated by the current thread, a target memory block corresponding to the memory allocation instruction is matched in the reuse pool; Allocate memory based on the target memory block.

5. The method according to claim 4, characterized in that, The reuse pool is configured to automatically adjust its capacity based on the reuse rate. Specifically, in response to the reuse rate being less than a reuse rate threshold, the reuse pool capacity is reduced; in response to the reuse rate being greater than a reuse rate threshold, the reuse pool capacity is expanded.

6. The method according to claim 4, characterized in that, The method further includes: Establish a multi-level recycling strategy; The memory block is reclaimed according to the multi-level reclamation strategy, wherein the multi-level reclamation strategy includes a first-level reclamation, a second-level reclamation, and a third-level reclamation. The first-level reclamation characterizes the real-time reclamation of the memory block after it is released; The second-level reclamation characterizes the reclamation of idle memory blocks within a preset time interval; The third-level reclamation refers to the reclamation of idle memory blocks when the system load is below the load threshold.

7. The method according to claim 1, characterized in that, The method further includes: In response to the memory allocation instruction requiring the migration of memory blocks between the first core and the second core, the migration operation is performed using pre-configured atomic instructions; In response to the completion of the migration operation, the cache associated with the virtual memory mapping is cleared using pre-configured synchronization cleanup instructions, and the latest memory view is synchronized.

8. A memory system performance optimization device for heterogeneous multi-core instruction set architectures, characterized in that, The instruction set architecture includes a first core and a second core, and the device includes: A module is established to establish an association between a memory allocator and an instruction set architecture based on an application programming interface. The memory allocator includes a first memory allocator and a second memory allocator. The association includes a first binding relationship between the first memory allocator and the first core, and a second binding relationship between the second memory allocator and the second core. The acquisition module is used to, in response to receiving a memory allocation instruction initiated by the current thread, acquire the memory space parameters and task type required by the memory allocation instruction; The first determining module is used to determine the target core from the first core and the second core based on the memory space parameters and the task type; The second determining module is used to determine the target memory allocator from the first memory allocator and the second memory allocator based on the target core and the association relationship. The allocation module is used to allocate memory according to the target memory allocator.

9. An electronic device, characterized in that, include: One or more processors; Storage device for storing one or more programs; Wherein, when the one or more programs are executed by the one or more processors, the one or more processors perform the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having executable instructions stored thereon, characterized in that, When executed by the processor, this instruction causes the processor to perform the method according to any one of claims 1 to 7.

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