Storage chip acceleration method and computer readable storage medium

Abstract

The invention discloses a storage chip acceleration method and a computer readable storage medium, the method is applied to a device end, the device end comprises a cache area used for receiving tasks from a host end in communication connection with the device end through a preprocessing task sequence and caching the tasks, and the method comprises the following steps: obtaining a main processing task sequence of the device end and priorities of the tasks included in the main processing task sequence; obtaining a preprocessing task sequence cached by the equipment end and priorities of tasks included in the preprocessing task sequence; the method comprises the following steps: acquiring a pre-sending task state of a host end and a task priority processing state of an equipment end, processing a task in a main processing task sequence of the equipment end according to the priority of the task, and in the processing process, judging whether the pre-sending task state of the host end and the task priority processing state of the equipment end meet a preset rule or not, and determining a resource release mode of the current task and performing resource release. And resource preparation is carried out in advance for the high-priority tasks through the low-priority tasks, so that reasonable utilization of overall resources is realized, and the overall performance of the storage particles is improved.

Description

Technical Field

[0001] This invention relates to the field of storage technology, specifically to a method for accelerating storage chips and a computer-readable storage medium. Background Technology

[0002] The firmware integrated within the eMMC (embedded multimedia card) memory chip performs the core function of flash memory resource management, responsible for key operations such as garbage collection, logical-to-physical address table updates, and bad block management. In normal operating mode, the firmware performs buffer management, garbage collection, and logical-to-physical address table flushing based on the real-time status of the memory chip.

[0003] However, the firmware logic inside existing eMMC storage particles is passive and can only respond to the current task requirements. It cannot plan ahead for upcoming tasks and prepare internal resources for the storage particles. It lacks the ability to predict and prepare the resources required by the task in advance, which cannot improve the parallel processing capability of the storage particles and greatly affects the overall performance of the storage particles. Summary of the Invention

[0004] The main technical problem this invention addresses is how to achieve advance planning and preparation of resources.

[0005] According to a first aspect, one embodiment provides a method for accelerating a memory chip, applied to a device, the device including a cache region, the cache region being used to receive and cache tasks from a host connected to the device via a preprocessed task sequence, the method for accelerating the memory chip includes:

[0006] Obtain the main processing task sequence of the device and the priority of the tasks included in the main processing task sequence, wherein the main processing task sequence represents the task sequence being processed by the device.

[0007] The device acquires the preprocessing task sequence cached on the device and the priorities of the tasks included in the preprocessing task sequence, wherein the preprocessing task sequence represents the sequence of tasks that the device will process in the future.

[0008] The pre-send task status on the host side and the task priority processing status on the device side are obtained. The pre-send task status on the host side indicates whether the host side currently has a pre-processed task to send to the buffer area on the device side. The task priority processing status on the device side indicates whether the task currently being processed by the device side is the lowest priority task in the main processing task sequence.

[0009] The tasks in the main processing task sequence on the device are processed according to their priority. During the processing, the resource release method for the current task is determined and resources are released based on whether the pre-sent task status on the host and the task priority processing status on the device meet the preset rules.

[0010] According to a second aspect, one embodiment provides a computer-readable storage medium storing a computer program that can be executed by a processor to implement the storage chip speed-up method.

[0011] According to the above embodiments, a method for accelerating a memory chip and a computer-readable storage medium configure corresponding priorities for host tasks and the task processing operations involved in each host task based on different application scenarios; and send the task sequence to be executed by the host in a future unit of time, which is pre-stored on the host, to the device in parallel in advance; the device then rationally allocates its internal resources based on the main processing task sequence it is currently processing and the received pre-processing task sequence; when the device executes the main processing task sequence, it adjusts the task execution order according to the waiting time of the lowest priority task in the current main processing task sequence, so as to ensure that high-priority tasks are executed first and avoid excessive waiting of low-priority tasks; when executing low-priority tasks... During the process, resources are prepared in advance for high-priority tasks to be executed in the future; when the main processing task sequence is about to be completed, resources are further prepared in advance based on the highest priority task in the preprocessing task sequence. This solves the problem that the current eMMC passive receiving mode has insufficient processing capabilities, resulting in long response time and poor handling of sudden, large-scale system operations and complex application scenarios. It enables bidirectional communication between the host and the device, thereby enabling the host and the device to communicate and provide early warnings in advance; by preparing resources in advance for high-priority tasks through low-priority tasks, reasonable resource sharing is achieved, and various types of tasks are ensured to consume less resources and be executed in a timely manner, thereby improving the overall performance of storage particles. Attached Figure Description

[0012] Figure 1 This is a flowchart of a method for speeding up memory chips;

[0013] Figure 2 This is a schematic diagram of a multi-task parallel pre-set test system.

[0014] Figure 3 This is a schematic diagram of a management interface generated for a complex application scenario;

[0015] Figure 4 This is a flowchart of task processing when preset rules are not met;

[0016] Figure 5It is a flowchart of task processing when preset rules are met;

[0017] Figure 6 This is a schematic diagram of the hardware logic architecture for eMMC task management. Detailed Implementation

[0018] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0019] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0020] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0021] With the widespread use of eMMC (Embedded Multi Media Card) memory chips in terminal products such as TVs, set-top boxes, tablets, and mobile phones, the requirements for their performance and reliability are becoming increasingly stringent, among which ensuring stable and reliable data is particularly important.

[0022] From a hardware architecture perspective, an eMMC memory chip is actually a miniature embedded system, mainly composed of an ARM CPU as the controller and NAND flash memory for data storage. The ARM CPU is responsible for running the controller software (i.e., firmware), which undertakes the core functions to ensure the reliable use of the NAND flash memory. These functions include bad block management, garbage collection, early warning mechanisms, and performance and lifespan optimization, ensuring the reliable operation of the NAND flash memory.

[0023] In eMMC storage chips, the internal firmware logic directly determines the performance and reliability of the memory. Typically, the firmware autonomously triggers a series of background operations based on the internal state of the storage chip, such as GC (garbage collection) data movement and P / L table flushing. However, because the firmware logic is passively received, it can only respond to the current task requirements and cannot plan ahead for the resource needs of subsequent tasks or prepare the corresponding resources. Furthermore, most existing designs rely on the firmware to independently determine and execute these actions within the storage chip, lacking effective communication with the host. Since the device cannot predict the host's subsequent actions, the firmware cannot prepare the necessary resources in advance. For example, it cannot reserve sufficient receive buffers for future tasks or pre-process valid logical block address (LBA) mappings in the NAND flash memory. This passive communication between the device and host also prevents the device from preparing internal storage resources for future tasks in advance, thus hindering the improvement of the storage chip's parallel processing capabilities. In high-concurrency, high-real-time scenarios, this significantly impacts the overall performance and response speed of eMMC.

[0024] Based on different application scenarios, this invention configures corresponding priorities for host tasks and the task processing operations (i.e., internal resources of the device) involved in each host task; and pre-stores the task sequence to be executed in a future unit of time on the host side, and sends it to the device side (Device-eMMC side) in parallel in advance. The device side makes reasonable allocation of internal resources based on the task sequence it is currently processing (i.e., the main processing task sequence) and the task sequence pre-stored by the host (i.e., the pre-processing task sequence) it receives.

[0025] Specifically, when executing the main processing task sequence on the device side, the task execution order is adjusted according to the waiting time of the lowest priority task in the current main processing task sequence. This ensures that high-priority tasks are executed first, avoids excessive waiting for low-priority tasks, and prepares resources in advance for high-priority tasks to be executed in the future while executing low-priority tasks. When the main processing task sequence is about to be completed (i.e., processing the last task), resources are further prepared in advance according to the highest priority task in the preprocessing task sequence. This changes the current passive receiving mode of eMMC to bidirectional communication between the host and the device, providing early warning and enabling reasonable resource sharing. It solves the problem of untimely communication between the host and the device caused by the existing communication mode, ensuring that various types of tasks consume less resources and are executed in a timely and efficient manner, thereby improving the overall performance of storage particles.

[0026] Please refer to Figure 1 Some embodiments provide a method for accelerating a memory chip, applied to a device. The device includes a cache area for receiving and caching tasks from a host connected in communication with the device via a preprocessed task sequence. The method for accelerating a memory chip includes the following steps:

[0027] Step S100: Obtain the main processing task sequence on the device and the priority of the tasks included in the main processing task sequence, wherein the main processing task sequence represents the task sequence being processed by the device; obtain the preprocessing task sequence cached on the device and the priority of the tasks included in the preprocessing task sequence, wherein the preprocessing task sequence represents the task sequence that the device will process in the future.

[0028] This invention generates complex types of tasks according to actual needs through a multi-task parallel pre-set test system, as shown in the schematic diagram of the device. Figure 2 As shown, it consists of a host-side central processing unit (CPU), DRAM memory, eMMC storage chips (device-side or Device-eMMC side), a socket for placing the eMMC storage chips, NAND flash memory, a universal asynchronous receiver / transmitter (UART), a USB peripheral interface, and a power supply.

[0029] First, the multi-task parallel pre-configuration test system is powered on and initialized. On the PC, the Complex ScenarioGenerator management interface (complex application scenario generation management interface) runs Image software. This software runs on the multi-task generation sub-board within the complex application scenario generation management interface and is used to generate complex task instructions. Then, it is burned (downloaded) to the flash NAND flash memory via UART or USB interface. After burning, the flash NAND flash memory drives the system boot, using the eMMC storage chip connected via a socket as an auxiliary storage disk. After booting, the Host-CPU receives instructions from the management interface and generates corresponding task sequences based on different configuration requirements (or configuration parameters), determining the task type, number of tasks, and the time interval between different task issuances. These are then sent to the eMMC device for processing. The generation conditions for the task sequences can be arbitrarily configured through this complex application scenario generation management interface, conveniently and comprehensively covering the task types that may exist in actual products.

[0030] Among them, the PC-side Complex Scenario Generator generates a management interface (for generating management interfaces for complex application scenarios), such as... Figure 3 As shown, its main functions include: an instruction generation module (Image), which runs the Image software on the multi-task generation subboard to generate complex task instructions; a system configuration module (Configuration), used to configure the multi-task parallel pre-set test system; a host mode configuration module (Host Mode), used to configure the host management mode, such as issuing instructions; a device mode configuration module (Device Mode), used to configure the device management mode, such as the burning mode; an event module, which sets the event type; a priority module, used to configure the priority corresponding to different task types; a performance module, used to compare the performance differences before and after the implementation of the method in this invention; a result module, used to output the complex execution results of multiple types of tasks; and an information output window (Information OutputWindow), used to output and display information.

[0031] This embodiment configures corresponding priorities for different host tasks on the host side (Host-CPU) according to different application scenarios, and sets corresponding priorities for task processing operations required when performing host task processing on the device side (Device-eMMC). Based on the task priority and the priority of task processing operations, resources are prepared in advance for high-priority tasks to ensure that high-priority tasks are executed in a timely and effective manner.

[0032] For example, the priorities of different host tasks on the host side and different task processing operations on the device side are shown in Table 1. The priorities of host tasks are mainly divided into 4 levels. The priorities of all task types are in descending order as HP3, HP2, HP0, and HP1. Among them, configuring system crash, system restart, system emergency event, and system low battery is the highest priority HP3 among all task types, and these tasks are further subdivided into sub-priorities. At this time, the sub-priorities of each task are in descending order as HP34 > HP33 > HP31 > HP32. The priority of configuring system high performance is HP2, and the priority of configuring system idle state is HP1. The priority of configuring sequential write data, sequential read data, random write data, and random read data is HP0, and subdivided into sub-priorities. At this time, the sub-priorities of each task are the same, that is, HP01 = HP02 = HP03 = HP04.

[0033] The host pre-stores its task sequence within a unit time slice T. At this time, the tasks contained in the task sequence are random combinations of tasks with various priorities. At the same time, the host (Host-CPU) also manages the task types and quantities within the unit time slice T in order to make reasonable use of overall resources. Then, the generated task sequence is transmitted to the device (Device-eMMC) in parallel in advance through VendorCMD customized instructions. When generating the task sequence, for multiple tasks of the same priority, they are sorted according to the order in which each task is issued.

[0034] After receiving the parallel task instructions (i.e. Vendor CMD customized instructions) issued by the host, the internal logic of the device classifies and processes the task sequence issued by the host, and schedules the corresponding task processing operations in parallel. This allows for advance management of internal DP0, DP1, DP2, and DP3 resources, so as to prepare buffer resources and / or perform FTL (flash translation layer) management for high-priority tasks in advance, thereby improving task predictability and enhancing parallel processing capabilities.

[0035] This embodiment prioritizes task processing operations on the device side. For example, the priority of task processing operations can be mainly divided into four levels. The priorities of all task processing operations, in descending order, are DP3, DP2, DP0, and DP1. Among these, the priority levels for configuring abnormal states and Program... The priority of NAND (NAND programming) and data DMA (direct memory access) is DP3, and these task processing operations are further subdivided into sub-priorities. At this time, the sub-priorities of each task processing operation are in descending order as DP33 > DP32 > DP31. The priority of CPU scheduling management is configured as DP2. The priorities of P / L flush management (page / block mapping table management), Buffer management, GC management (garbage collection management), and WL management (wear leveling management) are configured as DP0, and subdivided into sub-priorities. At this time, the sub-priorities of each task processing operation are the same, that is, DP01=DP02=DP03=DP04. The priority of IDLE state (standby state) and Sleep state (sleep state) is configured as DP1. At this time, the sub-priorities of each task processing operation are also the same, that is, DP11=DP12.

[0036] Table 1

[0037]

[0038] It should be noted that if there is no main processing task sequence being executed on the device, the preprocessing task sequence in the cache area will be used as the main processing task sequence and the task will be processed directly on the device. If there is a main processing task sequence being executed on the device, the preprocessing task sequence will be processed on the device after the main processing task sequence has been executed. Future tasks (i.e., preprocessing task sequences) are received from the host connected to the device through the preprocessing task sequence and cached.

[0039] Furthermore, the device in this embodiment is equipped with a buffer area to receive and store task sequences pre-stored within a unit time slice T sent by the host. These task sequences are also called pre-processed task sequences. If the previously received pre-processed task sequence has not yet been executed on the device, the device must wait for the previous pre-processed task sequence to be processed before receiving a new pre-processed task sequence. The previous pre-processed task sequence becomes the new main processing task sequence on the device after entering it. Through interactive communication between the host and the device regarding task execution status and available resource status, the host can dynamically adjust the current task type and number based on the communication information, thereby making reasonable use of resources and improving the overall performance of the storage system.

[0040] Step S110: Obtain the pre-send task status on the host side and the task priority processing status on the device side.

[0041] In this embodiment, the pre-sending task status of the host side refers to whether the host side currently has a pre-processed task to send to the cache area of ​​the device side. When the host side has no task to send to the device side, the corresponding host side is in an idle state. At this time, task processing and resource preparation are still required. The idle time is used to prepare the internal resources of the storage particles in advance to cope with sudden situations such as the host side suddenly sending a large number of system operations at a certain time.

[0042] The task priority processing status on the device side refers to whether the task currently being processed by the device side is the lowest priority task in the main processing task sequence. Since the device side prioritizes the execution of high-priority tasks in this embodiment, the execution time of high-priority tasks may exceed expectations due to factors such as insufficient resources. At this time, high-priority tasks need to wait for the corresponding resources to be released before they can continue to execute. In this embodiment, when the execution time of high-priority tasks is too long, the lowest priority task is switched to process them to release resources as soon as possible, so as to ensure the timely execution of high-priority tasks.

[0043] By analyzing the pre-sending task status on the host side and the task priority processing status on the device side, it can be determined which internal logic the device side should prioritize in idle mode. This avoids the lack of advance knowledge of future host tasks, which could prevent the device side from maximizing the performance requirements of complex application scenarios and solves the drawbacks of passive mode on the eMMC storage granular side.

[0044] Step S120: Process the tasks in the main processing task sequence on the device side according to their priority. During the processing, determine the resource release method for the current task and release the resources based on whether the pre-sent task status on the host side and the task priority processing status on the device side meet the preset rules.

[0045] In this embodiment, the resource release method for the current task is determined and resources are released based on whether the pre-sending task status on the host side and the task priority processing status on the device side meet the preset rules. If the preset rules are met, the resource release method for the current task is determined based on the main processing task sequence or the pre-processing task sequence.

[0046] When the host's pre-send task status indicates that a pre-processed task exists to be sent to the device's buffer area, and the device's task priority processing status indicates that the task currently being processed by the device is not the lowest priority task in the main processing task sequence, it is considered that the preset rules are not met. In this case, the priorities of each task in the main processing task sequence are processed in descending order, and during the processing, multiple preset checkpoints are used to determine whether to adjust the execution order of tasks in the main processing task sequence; for example... Figure 4As shown, the task processing when the preset rules are not met includes the following steps:

[0047] Step S1201: Obtain the total execution time based on the theoretical execution time of all tasks contained in the initial main processing task sequence, and determine the time nodes corresponding to a preset number of checkpoints based on the total execution time.

[0048] In some embodiments, the total execution time is obtained based on the theoretical execution time of all tasks included in the current main processing task sequence at the beginning of the device. After obtaining the total execution time, it is divided equally, and each division point corresponds to a checkpoint. For example, if the total execution time is t (e.g., 30s) and the preset number of checkpoints is 3, then the total time t is divided into 3 parts, and the time nodes corresponding to each checkpoint are t / 3, 2t / 3 and t, which are 10s, 20s and 30s respectively.

[0049] Step S1202: Obtain the waiting time of the lowest priority task in the current main processing task sequence.

[0050] Although this embodiment prioritizes the execution of high-priority tasks, it switches to low-priority tasks for processing when their execution time is too long to avoid low-priority tasks waiting excessively. After the current low-priority task finishes execution, it returns to the original execution order to continue processing high-priority tasks. Therefore, during the actual execution of the main processing task sequence, the highest priority task and the lowest priority task are constantly updated, and the waiting time of the lowest priority task in the current main processing task sequence is also updated accordingly.

[0051] Step S1203: For any checkpoint: Obtain the actual execution time of the highest priority task within the time range between the checkpoint and the previous checkpoint, and determine the execution status of the highest priority task within the time range of the checkpoint based on the actual execution time and the preset proportion of the time range corresponding to the checkpoint.

[0052] This embodiment achieves synchronization of task execution status by setting multiple checkpoints and combining them with the longest waiting time to achieve efficient response, thereby avoiding high-priority tasks occupying resources for a long time and causing subsequent tasks to fail to execute. Specifically, if the actual execution time is less than or equal to the time corresponding to the preset percentage of the time range of the checkpoint, the highest priority task corresponding to the checkpoint has been completed within the time range of the checkpoint, and the corresponding execution status is "completed". If the highest priority task corresponding to the checkpoint has not been completed within the time range of the preset percentage of the time range of the checkpoint, the corresponding execution status is "incomplete".

[0053] For example, the preset percentage can be set to 80%. For the first checkpoint (corresponding to 10s), the corresponding time range is 0s to 10s. If the actual execution time of the highest priority task is less than 8s within this time range, that is, the high priority task is completed ahead of schedule, and the corresponding task execution status is completed. If the highest priority task has not been completed by 8s, the corresponding task execution status is incomplete.

[0054] Step S1204: Determine whether to adjust the task execution order based on the execution status and waiting time corresponding to the checkpoint.

[0055] If the execution status is incomplete and the waiting time of the lowest priority task does not exceed the maximum waiting time, there is no need to adjust the task execution order. Continue to execute the highest priority task within the time range corresponding to this checkpoint. If the execution status is complete and the waiting time does not exceed the maximum waiting time, there is no need to adjust the task execution order. Continue to execute the highest priority task that has not yet been executed in the current main processing task sequence. And so on, continue to judge the next checkpoint.

[0056] When the waiting time exceeds the maximum waiting time, the task execution order needs to be adjusted, and the task with the lowest priority in the current main processing task sequence is executed. This ensures that high-priority tasks are executed first, while avoiding excessive waiting for low-priority tasks.

[0057] In this embodiment, by setting multiple checkpoints, the task execution status of the device can be detected in a timely manner. When a high-priority task is completed ahead of schedule (e.g., within 8 seconds), the device can process the next task in a timely manner, avoiding low-priority tasks from blindly waiting for a fixed time slice (i.e., the longest waiting time), thereby maximizing resource utilization.

[0058] When the host-side pre-send task status is "no pre-processing tasks to be sent to the device-side cache area," or when the device-side task priority processing status is "the task currently being processed by the device is the lowest priority task in the main processing task sequence," it is considered that the preset rules are met. The target task requiring resource preparation for the current task is then obtained, and the resource release method for the current task is determined and performed based on the target task. For example... Figure 5 As shown, the task processing when the preset rules are met includes the following steps:

[0059] Step S1211: Obtain the target task that requires the current task to prepare resources.

[0060] This embodiment obtains the target task that requires resource preparation for the current task based on the current main processing task sequence or preprocessing task sequence. When the task execution order needs adjustment, it indicates that the waiting time of the lowest priority task in the current main processing task sequence has exceeded the maximum waiting time, and the lowest priority task needs to be executed. In this embodiment, after the task is completed, the corresponding resources are released, and execution returns to the original execution order. The task that needs to be executed after returning to the original execution order is the task that requires resource preparation in advance by the lowest priority task, i.e., the target task. In this embodiment, the highest priority task within the time range corresponding to the checkpoint or the highest priority task that has not yet been executed in the current main processing task sequence is taken as the target task.

[0061] If the execution status is incomplete, the highest priority task within the time range corresponding to the checkpoint is taken as the target task; if the execution status is completed, the highest priority unexecuted task in the current main processing task sequence is taken as the target task.

[0062] Alternatively, when the device is currently executing the last task in the main processing task sequence and the preprocessing task sequence is not an empty set, the task with the highest priority in the preprocessing task sequence is obtained and that task is taken as the target task.

[0063] For example, suppose that in the original execution order, after obtaining the execution status of a high-priority task A, the waiting time of the lowest-priority task B in the current main processing task sequence exceeds the maximum waiting time. At this time, task B is forcibly executed, and then the execution order is returned to continue after task B is completed. If the execution status of task A is incomplete, task A needs to be executed again after returning to the original execution order; if the execution status of task A is completed, the next task of task A needs to be executed after returning to the original execution order. Since the task sequence is sorted according to priority, and for tasks of the same priority, they are sorted according to the order in which they were issued, the next task of task A is actually the highest-priority task that has not been executed in the current main processing task sequence.

[0064] When the device is currently executing the last task in the main processing task sequence, which is also the lowest priority task in the current main processing task sequence, it is necessary to prepare resources in advance for the next task (or future task). At this time, the next task is the highest priority task in the preprocessing task sequence. This enables low-priority tasks to prepare resources in advance for high-priority tasks and changes the passive receiving mode of the eMMC device to bidirectional communication between the host and the device, realizing early communication and warning between the host and the device and the rational use of resources.

[0065] It should be noted that when the task execution order needs to be adjusted, the target task will continue to be executed after the lowest priority task in the current main processing task sequence has been completed, or after the last task in the current main processing task sequence has been completed. If the target task is not the last task in the main processing task sequence, the lowest priority task in the current main processing task sequence will be retrieved again, and the waiting time of the lowest priority task will be recalculated.

[0066] Step S1212: Determine the resource release method for the current task based on the target task and release the resources.

[0067] The resource release methods in this embodiment include a first resource release method and a second resource release method. If the priority of the task type corresponding to the target task is the highest priority among all task types, that is, the priority of the target task is HP3 (including system crash, system restart, system emergency event, system low battery), the resource release method for such emergency tasks is the second resource release method. The second resource release method temporarily stores all unexecuted tasks in the current main processing task sequence and releases the resources directly. During the release, the resources can also be released directly according to the task priority and the priority of the required task processing operation from low to high.

[0068] It should be noted that for system emergencies or low battery events, previously stored and unprocessed tasks can continue to be processed on the device after such tasks are completed.

[0069] Otherwise, if the priority of the task type corresponding to the target task is not the highest priority among all task types, that is, if the priority of the target task is HP2, HP0, or HP1, the corresponding resource release method is the first resource release method. In the first resource release method, the mapping relationship between each task and the task processing operations it needs to perform is obtained, and the priority corresponding to each task processing operation is obtained. Specifically, the task processing operations involved in the host task with priority HP0 have priorities of DP0 and DP3; the task processing operations involved in the host task with priority HP1 have priorities of DP0, DP1, and DP2; the task processing operations involved in the host task with priority HP2 have priorities of DP0 and DP2; and the task processing operations involved in the host task with priority HP3 have priorities of DP2 and DP3. Through this mapping relationship, different task types are quickly identified and internal storage resources of storage particles are planned in advance, thereby realizing the coordinated allocation of task processing operations (resources) between the host and device sides and optimizing the overall task execution process.

[0070] Then, based on the current task, the target task, and the mapping relationship, the shared task processing operations between the current task and the target task are determined, and resources are released in ascending order of priority according to the shared task processing operations.

[0071] For example, if the priority of the task currently being processed by the device (i.e., the current task) is HP0, and the task processing operations involved involve one or more of DP0 and DP3, while the priority of the target task is HP3, and the task processing operations involved involve one or more of DP2 and DP3, for the resources that both the current task and the target task need to use, such as the task processing operations that both need to use data DMA and NAND programming, when the current task is executed, they are executed in order from low to high priority according to the shared task processing operations, thereby releasing resources.

[0072] In this embodiment, the eMMC task management hardware logic architecture is as follows: Figure 6As shown, this demonstrates how the entire device allocates resources rationally based on different task types and priorities after receiving a host task, thereby improving overall performance. The PWR provides power, the RISC-V is the central processing unit, ROM stores the boot program, RAM runs the device firmware, the eMMC Interface receives Vendor CMD custom commands from the host, the Host Task categorizes and marks host task types and priorities, NAND Flash is the physical storage unit, Task Management primarily schedules and configures internal resource algorithms based on the Host Task's task type and priority, prepares corresponding buffer space, updates the LBA / PBA mapping table in a timely manner, and refreshes the data in the buffer into the NAND Flash, the FTL HardwareModule mainly manages the firmware's internal logic algorithms, the Mapping Table stores the LBA / PBA mapping table, the ReadBuffer stores read data, and the Write Buffer stores write data.

[0073] This embodiment is based on different application scenarios for host tasks and the task processing operations involved in each host task (configuring corresponding priorities); and the task sequence to be executed by the host in a future unit time is pre-stored and sent to the device in parallel. The device makes reasonable allocation of internal resources based on the task sequence it is currently processing (i.e., the main processing task sequence) and the task sequence pre-stored by the host (i.e., the pre-processing task sequence) it receives.

[0074] When executing the main processing task sequence on the device side, the task execution order is adjusted according to the waiting time of the lowest priority task in the current main processing task sequence. This ensures that high-priority tasks are executed first, while avoiding excessive waiting for low-priority tasks. During the execution of low-priority tasks, resources are prepared in advance for high-priority tasks that will be executed in the future. When the main processing task sequence is about to be completed, resources are further prepared in advance according to the highest priority task in the preprocessing task sequence. By deeply analyzing the behavior of the host and the pre-configured conditions on the storage particle device side, the device side can prepare data receiving and sending operations in advance, thereby improving the performance efficiency between the eMMC storage particle device side (device side) and the host side. This changes the current passive receiving mode of eMMC to bidirectional communication between the host side and the device side, solving the problem of long response time due to insufficient processing capacity of the current passive receiving mode of eMMC, and poor response to sudden, large-scale system operations and complex application scenarios. It enables early communication and warning between the host side and the device side, and realizes reasonable resource sharing, ensuring that various types of tasks consume less resources and are executed and processed in a timely manner.

[0075] Furthermore, this embodiment optimizes the internal logic of both the host and eMMC storage chips (device side) through a combination of hardware and software. It offers high flexibility, is compatible with various complex application scenarios, improves the coverage testing of the processing capabilities of both the host and device sides, comprehensively captures potential risks and defects in the processing flow of the host and firmware, and enhances the stability and compatibility of the host and firmware programs. This comprehensively improves the ability of eMMC firmware to cope with complex logic scenarios, addresses the issue of reasonable and unified resource allocation between the host and device sides, and ultimately improves the overall performance of the storage chips.

[0076] Some embodiments of the present invention also disclose a computer-readable storage medium storing a computer program that can be executed by a processor to implement the methods described in any of the embodiments herein.

[0077] Those skilled in the art will understand that all or part of the functions of the various methods in the above embodiments can be implemented by hardware or by computer programs. When all or part of the functions in the above embodiments are implemented by computer programs, the program can be stored in a computer-readable storage medium, which may include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to achieve the above functions. For example, the program can be stored in the memory of a device, and when the program in the memory is executed by the processor, all or part of the above functions can be achieved. In addition, when all or part of the functions in the above embodiments are implemented by computer programs, the program can also be stored in a server, another computer, disk, optical disk, flash drive, or external hard drive, etc., and can be downloaded or copied to the memory of a local device, or the system of the local device can be updated. When the program in the memory is executed by the processor, all or part of the functions in the above embodiments can be achieved.

[0078] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A method for accelerating a memory chip, applied to a device, the device including a cache area, the cache area being used to receive and cache tasks from a host connected in communication with the device via a preprocessed task sequence, characterized in that... The method for accelerating the memory chip includes: Obtain the main processing task sequence of the device and the priority of the tasks included in the main processing task sequence, wherein the main processing task sequence represents the task sequence being processed by the device. The device acquires the preprocessing task sequence cached on the device and the priorities of the tasks included in the preprocessing task sequence, wherein the preprocessing task sequence represents the sequence of tasks that the device will process in the future. The pre-send task status on the host side and the task priority processing status on the device side are obtained. The pre-send task status on the host side indicates whether the host side currently has a pre-processed task to send to the buffer area on the device side. The task priority processing status on the device side indicates whether the task currently being processed by the device side is the lowest priority task in the main processing task sequence. The tasks in the main processing task sequence on the device are processed according to their priority. During the processing, the resource release method for the current task is determined and resources are released based on whether the pre-sent task status on the host and the task priority processing status on the device meet the preset rules.

2. The memory chip speed-up method as described in claim 1, characterized in that, The step of determining the resource release method for the current task and releasing resources based on whether the pre-sent task status on the host side and the task priority processing status on the device side meet preset rules includes: When the pre-sending task status on the host side is that there is a task to be sent to the buffer area on the device side and the task priority processing status on the device side is that the task currently being processed by the device side is not the task corresponding to the lowest priority in the main processing task sequence, it is considered that the preset rule is not met. The priority of each task in the main processing task sequence is processed in descending order, and multiple preset checkpoints are used during the processing to determine whether to adjust the execution order of the tasks in the main processing task sequence. When the pre-sending task status on the host side is that there is no task to send pre-processing to the cache area on the device side, or when the task priority processing status on the device side is that the task currently being processed by the device side is the task corresponding to the lowest priority in the main processing task sequence, it is considered that the preset rule is met, the target task that needs the current task to prepare resources is obtained, the resource release method of the current task is determined according to the target task, and the resources are released.

3. The memory chip speed-up method as described in claim 2, characterized in that, The step of determining whether to adjust the execution order of tasks in the main processing task sequence by setting multiple checkpoints includes: The total execution time is obtained based on the theoretical execution time of all tasks contained in the initial main processing task sequence, and the time nodes corresponding to a preset number of checkpoints are determined based on the total execution time. Obtain the waiting time of the lowest priority task in the current main processing task sequence; For any checkpoint: obtain the actual execution time of the highest priority task within the time range between the checkpoint and the previous checkpoint; determine the execution status of the highest priority task within the time range corresponding to the checkpoint based on the actual execution time and the preset proportion of the time range corresponding to the checkpoint; determine whether to adjust the task execution order based on the execution status corresponding to the checkpoint and the waiting time.

4. The memory chip speed-up method as described in claim 3, characterized in that, The step of determining the execution status of the highest priority task within the time range corresponding to the checkpoint based on the actual execution time and the preset proportion of the time range corresponding to the checkpoint includes: If the actual execution time is less than or equal to the duration corresponding to the preset proportion of the time range corresponding to the checkpoint, the highest priority task within the time range corresponding to the checkpoint has been completed, and the execution status is a completed status. If the highest priority task within the time range corresponding to the checkpoint is not completed within the preset percentage of the time range, the execution status is incomplete.

5. The memory chip speed-up method as described in claim 4, characterized in that, The step of determining whether to adjust the task execution order based on the execution status corresponding to the checkpoint and the waiting time includes: If the execution status is incomplete and the waiting time does not exceed the maximum waiting time, there is no need to adjust the task execution order, and the highest priority task within the time range corresponding to the checkpoint continues to be executed. If the execution status is complete and the waiting time has not exceeded the maximum waiting time, there is no need to adjust the task execution order, and the highest priority task that has not been executed in the current main processing task sequence continues to be executed. If the waiting time exceeds the maximum waiting time, the task execution order needs to be adjusted, and the task with the lowest priority in the current main processing task sequence should be executed.

6. The memory chip speed-up method as described in claim 5, characterized in that, The process of obtaining the target task that requires resource preparation by the current task includes: When it is necessary to adjust the task execution order, the highest priority task within the time range corresponding to the checkpoint or the highest priority unexecuted task in the current main processing task sequence is taken as the target task, based on the execution status. Alternatively, when the device is currently executing the last task in the main processing task sequence and the preprocessing task sequence is not an empty set, the task corresponding to the highest priority in the preprocessing task sequence is obtained and that task is taken as the target task.

7. The memory chip speed-up method as described in claim 6, characterized in that, When it is necessary to adjust the task execution order, the highest priority task within the time range corresponding to the checkpoint or the highest priority unexecuted task in the current main processing task sequence is taken as the target task, based on the execution status. This includes: If the execution status is incomplete, then the task with the highest priority within the time range corresponding to the checkpoint is taken as the target task. If the execution status is complete, then the highest priority task that has not yet been executed in the current main processing task sequence will be taken as the target task.

8. The memory chip speed-up method as described in claim 6, characterized in that, When the task execution order needs to be adjusted, the target task will continue to be executed after the lowest priority task in the current main processing task sequence has been completed, or after the last task in the current main processing task sequence has been completed. If the target task is not the last task in the main processing task sequence, the lowest priority task in the current main processing task sequence will be retrieved again, and the waiting time of the lowest priority task will be recalculated.

9. The memory chip speed-up method as described in claim 7, characterized in that, The step of determining the resource release method for the current task based on the target task and releasing the resources includes: The resource release method includes a first resource release method and a second resource release method; wherein, if the priority of the task type corresponding to the target task is the highest priority among all task types, the resource release method is the second resource release method, which temporarily stores all unexecuted tasks in the current main processing task sequence and directly releases the resources; Otherwise, the resource release method is the first resource release method, which obtains the mapping relationship between each task and the task processing operations it needs to perform, and obtains the priority corresponding to each task processing operation; determines the shared task processing operations between the current task and the target task according to the current task, the target task and the mapping relationship, and executes them in order from low to high priority according to the shared task processing operations to release resources.

10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program that can be executed by a processor to implement the method as described in any one of claims 1-9.

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