Error detection method and system for single-instruction multi-thread processor, electronic equipment and medium
By counting the number of active and inactive threads in a single-instruction multithreaded processor, and performing thread reorganization and redundant computation, the problems of high hardware redundancy cost and low resource utilization are solved, thereby improving computational reliability and efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- YUANQIXIN (SHANDONG) SEMICONDUCTOR TECHNOLOGY CO LTD
- Filing Date
- 2025-11-28
- Publication Date
- 2026-04-21
AI Technical Summary
Single-instruction multithreaded processors suffer from high hardware redundancy costs and low resource utilization in highly parallel computing, especially in SIMT architectures where inactive thread resources are idle, leading to limited computational reliability and efficiency.
By counting the number of active and inactive threads, a thread reorganization operation is triggered to form a new thread bundle. Inactive threads are used for redundant calculations, and the original and redundant calculation results are compared to detect errors, thereby reducing hardware costs and improving resource utilization.
This approach improves the resource utilization and computational reliability of a single-instruction multithreaded processor without increasing hardware costs, while reducing error detection costs.
Smart Images
Figure CN121901020A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer technology, and in particular to an error detection method, system, electronic device, and medium for a single-instruction multithreaded processor. Background Technology
[0002] Single Instruction Multiple Threads (SIMT) processors, especially general-purpose graphics processing units (GPUs) as their mainstream implementation, have been widely used in high-performance computing, artificial intelligence, and other fields due to their massively parallel processing capabilities. In these applications where computational accuracy and stability are extremely critical, the reliability of the computational results is paramount. However, to support high parallelism, SIMT processors integrate a massive number of hardware threads. The tiny probability of error in each thread accumulates at the chip level to an exponentially high error risk, posing a serious threat to system reliability.
[0003] In existing technologies, error detection mechanisms such as hardware redundancy or temporal redundancy are commonly used to improve computational reliability. However, these methods generally have some inherent drawbacks. For example, hardware redundancy incurs significant hardware overhead and power consumption costs, while temporal redundancy causes severe performance degradation. Furthermore, in the execution model of the SIMT architecture, due to branching and other reasons, a large number of inactive threads often exist within a single warp, leaving their corresponding valuable computing resources idle and resulting in low resource utilization. Summary of the Invention
[0004] This invention provides an error detection method, system, electronic device, and medium for a single-instruction multi-threaded processor, to address the shortcomings of existing error detection methods for single-instruction multi-threaded processors, such as high cost and low resource utilization.
[0005] This invention provides an error detection method for a single-instruction multithreaded processor, comprising: Count the number of active and inactive threads in the current thread bundle of a Single Instruction Multithreaded (SIMT) processor; The number of active threads is compared with the number of inactive threads. When the number of active threads is greater than the number of inactive threads, a thread reorganization operation is triggered to update the current thread bundle and obtain a new thread bundle. The number of new active threads in the new thread bundle is less than or equal to the number of new inactive threads. Based on the new inactive threads in the new thread bundle, redundant calculations are performed on the computational tasks of the new active threads in the new thread bundle to obtain the first redundant calculation result. The first original calculation result of the new active thread in the new thread bundle is compared with the first redundant calculation result to obtain the first comparison result, and error detection is performed based on the first comparison result.
[0006] In some embodiments, updating the current thread bundle to obtain a new thread bundle includes: One or more target thread bundles are selected from the thread pool of the SIMT processor; the sum of the number of active threads and the number of inactive threads in the target thread bundle is equal to the sum of the number of active threads and the number of inactive threads in the current thread bundle. The threads in the current thread bundle are swapped with the threads in one or more target thread bundles, and threads with the same program counter (PC) value are reorganized to concentrate active threads and / or concentrate inactive threads. Based on the reorganization result, the current thread bundle is updated to obtain a new thread bundle.
[0007] In some embodiments, error detection is performed based on the first comparison result, including: If the first original calculation result is inconsistent with the first redundant calculation result, it is determined that there is a calculation error in the new active thread in the new thread bundle, an error alarm message is generated, and an alarm is issued. If the first original calculation result is consistent with the first redundant calculation result, the calculation of the new active thread in the new thread bundle is determined to be correct.
[0008] In some embodiments, the error detection based on the first comparison result includes: If the first original calculation result is inconsistent with the first redundant calculation result, the faulty thread is identified from the new thread bundle, and the calculation task of the faulty thread is migrated.
[0009] In some embodiments, after comparing the number of active threads with the number of inactive threads, the method further includes: If the number of active threads is determined to be less than or equal to the number of inactive threads, redundant calculations are performed on the computational tasks of the active threads in the current thread bundle based on the inactive threads in the current thread bundle to obtain a second redundant calculation result. The second original calculation result of the active thread in the current thread bundle is compared with the second redundant calculation result to obtain a second comparison result, and error detection is performed based on the second comparison result.
[0010] In some embodiments, the step of performing redundant computation on the computational tasks of the new active threads in the new thread bundle based on the new inactive threads in the new thread bundle includes: Get the error detection command input by the user; In response to the error detection command, a preset error detection mechanism is activated, and the idle execution unit corresponding to the new inactive thread in the new thread bundle performs redundant execution of the computational tasks of the new active thread in the new thread bundle.
[0011] This invention also provides an error detection system for a single-instruction multithreaded processor, comprising: The statistics unit is used to count the number of active and inactive threads in the current thread bundle of a Single Instruction Multithreaded (SIMT) processor. The reorganization unit is used to compare the number of active threads with the number of inactive threads. When the number of active threads is greater than the number of inactive threads, a thread reorganization operation is triggered to update the current thread bundle and obtain a new thread bundle. The number of new active threads in the new thread bundle is less than or equal to the number of new inactive threads. The first redundant calculation unit is used to perform redundant calculations on the calculation tasks of the new active threads in the new thread bundle based on the new inactive threads in the new thread bundle, and obtain the first redundant calculation result. The first error detection unit is used to compare the first original calculation result of the new active thread in the new thread bundle with the first redundant calculation result to obtain a first comparison result, and to perform error detection based on the first comparison result.
[0012] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the error detection method of any of the single-instruction multi-threaded processors described above.
[0013] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the error detection method of a single-instruction multi-threaded processor as described above.
[0014] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the error detection method of any of the single-instruction multi-threaded processors described above.
[0015] The present invention provides an error detection method, system, electronic device, and medium for a single-instruction multithreaded processor (SIMT). This method involves: statistically analyzing the number of active and inactive threads in the current thread bundle of the SIMT processor; comparing the number of active threads with the number of inactive threads; and triggering a thread reorganization operation when the number of active threads exceeds the number of inactive threads. This updates the current thread bundle to obtain a new thread bundle, ensuring that there are enough inactive threads available in the new thread bundle. Based on the new inactive threads in the new thread bundle, redundant calculations are performed on the computational tasks of the new active threads in the new thread bundle to obtain a first redundant calculation result. Finally, the first original calculation result of the new active threads in the new thread bundle is compared with the first redundant calculation result, and error detection is performed based on the first comparison result. This reduces error detection costs and significantly improves the overall resource utilization of the processor. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0017] Figure 1 This is a flowchart illustrating the error detection method for a single-instruction multithreaded processor provided in an embodiment of the present invention.
[0018] Figure 2 This is a schematic diagram of the process for updating the current thread bundle provided in an embodiment of the present invention.
[0019] Figure 3 This is a schematic diagram of the thread reorganization process provided in an embodiment of the present invention.
[0020] Figure 4 This is an architecture diagram of the error detection system for a single-instruction multi-threaded processor provided in an embodiment of the present invention.
[0021] Figure 5 This is a schematic diagram of the error detection system for a single-instruction multi-threaded processor provided in an embodiment of the present invention.
[0022] Figure 6 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. Detailed Implementation
[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0024] The terms "first," "second," etc., used in this invention are used to distinguish similar objects, not to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first" and "second" are generally of the same class, not limited in number; for example, the first object can be one or more. Furthermore, in this invention, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0025] Figure 1 This is a flowchart illustrating the error detection method for a single-instruction multithreaded processor provided in an embodiment of the present invention. Figure 1 As shown, an error detection method for a single-instruction multithreaded processor is provided, including the following steps: steps 110, 120, 130, and 140. This method flow is merely one possible implementation of the present invention.
[0026] Step 110: Count the number of active and inactive threads in the current thread bundle of the Single Instruction Multithreaded (SIMT) processor.
[0027] The Single Instruction Multithreaded (SIMT) processor features a parallel computing architecture. Its core characteristic is using a single instruction to control multiple independent threads, which perform the same operation on different data. General-purpose graphics processing units (GPUs) are its most typical implementation. In the SIMT architecture, a thread bundle is not only the basic unit of thread scheduling but also the underlying unit for implementing lockstep parallel execution. A thread bundle typically contains a fixed number of threads, such as 32. All threads within the same bundle are grouped together at the hardware level to execute the same instruction sequence in a lockstep manner.
[0028] It should be noted that within a thread bundle, due to conditional branches in the program, different threads may choose to execute different code paths. In any given execution cycle, the thread currently executing the instruction is called the active thread; while the thread that is temporarily blocked and not executing the instruction because the branch condition is not met is called the inactive thread. The execution unit corresponding to an inactive thread is idle during that cycle.
[0029] Optionally, a monitoring logic is built into the thread bundle scheduler of the SIMT processor. This logic counts the number of active and inactive threads within the current thread bundle in real time during each instruction cycle or critical execution phase. This counting can be efficiently accomplished by reading the execution mask of the current thread bundle. The execution mask is a bit vector, with each bit corresponding to the state of a thread, whether it is active or inactive.
[0030] Step 120: Compare the number of active threads with the number of inactive threads. When the number of active threads is greater than the number of inactive threads, trigger a thread reorganization operation to update the current thread bundle and obtain a new thread bundle. The number of new active threads in the new thread bundle is less than or equal to the number of new inactive threads.
[0031] It's important to note that when the number of active threads exceeds the number of inactive threads, it means that the idle resources available for redundant computation are insufficient to cover all working threads, making one-to-one error detection impossible. In this case, the system triggers a thread reorganization operation, pausing the execution of the current thread bundle through the thread scheduler and merging and re-dividing it with other thread bundles. The number of new active threads in the new thread bundle is less than or equal to the number of new inactive threads, thus ensuring that for each new active thread, there is at least one new inactive thread that can be paired with it for one-to-one redundant computation.
[0032] Step 130: Based on the new inactive threads in the new thread bundle, perform redundant calculations on the computation tasks of the new active threads in the new thread bundle to obtain the first redundant calculation result.
[0033] It should be noted that when a new thread bundle executes a computation task, the scheduler pairs each new active thread with a new inactive thread to obtain a thread pair. Instructions are then dispatched to both threads in the thread pair simultaneously, allowing redundant computations and original computations to be executed in parallel.
[0034] Step 140: Compare the first original calculation result of the new active thread in the new thread bundle with the first redundant calculation result to obtain the first comparison result, and perform error detection based on the first comparison result.
[0035] It should be noted that if the first original calculation result differs from the first redundant calculation result, it indicates that at least one thread's execution unit experienced a transient or permanent failure during the calculation process. The system will determine that an error has been detected and immediately trigger the corresponding error handling mechanism, such as setting an error flag, reporting the exception, pausing the system, or executing a recovery procedure.
[0036] Understandably, by reusing the inactive threads and their execution units inherent in the SIMT architecture and generated by branching, error detection can be performed without adding an extra set of physical execution units, thus reducing hardware costs and power consumption.
[0037] In this embodiment of the invention, the number of active and inactive threads in the current thread bundle of a Single Instruction Multithreaded (SIMT) processor is statistically analyzed. The number of active threads is compared with the number of inactive threads. When the number of active threads exceeds the number of inactive threads, a thread reorganization operation is triggered to update the current thread bundle, resulting in a new thread bundle. This ensures that there are enough inactive threads available in the new thread bundle. Based on the new inactive threads in the new thread bundle, redundant computation is performed on the computational tasks of the new active threads in the new thread bundle to obtain a first redundant computation result. The first original computation result of the new active threads in the new thread bundle is compared with the first redundant computation result. Error detection is performed based on the first comparison result, reducing error detection costs and significantly improving the overall resource utilization of the processor. Figure 2 This is a schematic diagram illustrating the process of updating the current thread bundle according to an embodiment of the present invention. Figure 2 As shown, in some embodiments, step 120 updates the current thread bundle to obtain a new thread bundle, including: Step 121: Select one or more target thread bundles from the thread pool of the SIMT processor; the sum of the number of active threads and the number of inactive threads in the target thread bundle is equal to the sum of the number of active threads and the number of inactive threads in the current thread bundle.
[0038] In this context, a thread pool refers to a collection of all thread bundles that are to be executed or are currently being executed, managed by a hardware scheduler. The scheduler can select appropriate thread bundles from the thread pool for operation.
[0039] Step 122: Swap the threads in the current thread bundle with threads in one or more target thread bundles, reorganize threads with the same program counter (PC) value to concentrate active threads and / or concentrate inactive threads.
[0040] The program counter (PC) is a register used to store the memory address of the next instruction the processor will execute. In the SIMT architecture, all threads within a thread bundle share the same PC. However, due to branching, even with the same PC, only threads that meet the execution conditions will actually execute the instruction. Threads with the same PC value are those about to execute the same instruction. The PC value directly relates to the thread's execution path and active state. Using this as a standard for grouping and swapping threads is logically clear, easy to implement in hardware, and ensures that swapped threads can seamlessly continue execution, avoiding complex context synchronization problems.
[0041] Optionally, the number of inactive threads in the target thread bundle is much greater than the number of active threads.
[0042] Alternatively, active threads can be grouped into one or a few thread bundles, while inactive threads can be grouped into other thread bundles. For example, some active threads can be taken from the current thread bundle and swapped with inactive threads in the target thread bundle.
[0043] Step 123: Based on the reorganization result, update the current thread bundle to obtain the new thread bundle.
[0044] In this embodiment of the invention, by swapping threads in the current thread bundle with threads in one or more target thread bundles, threads with the same program counter (PC) value are reorganized, which significantly improves error detection coverage and further optimizes global resource utilization.
[0045] Figure 3 This is a schematic diagram of the thread reorganization process provided in an embodiment of the present invention. Figure 3 As shown, after the Warp active blocked thread statistics unit counts the number of active threads and inactive threads executing the same PC, it first compares the number of active threads with the number of inactive threads. When the number of active threads is greater than the number of inactive threads, a reassembly operation is performed. The Warp reassembler selects threads with the same PC value for reassembly. After that, it needs to ensure that the number of active threads in the reassembled Warp is less than or equal to the number of inactive threads. When the number of active threads is less than or equal to the number of inactive threads, it is determined that no reassembly is needed, and subsequent operations such as instruction fetching and decoding are performed directly.
[0046] In some embodiments, error detection is performed based on the first comparison result, including: If the first original calculation result is inconsistent with the first redundant calculation result, it is determined that the new active thread in the new thread bundle has a calculation error, an error alarm message is generated, and an alarm is issued. If the first original calculation result is consistent with the first redundant calculation result, the calculation of the new active thread in the new thread bundle is determined to be correct.
[0047] The error alarm information includes at least the following: the thread bundle ID where the error occurred, the thread ID, the address of the instruction executed when the error occurred, and the timestamp.
[0048] Optionally, error alarm information can be passed to upper-level software or specific hardware management modules.
[0049] In some embodiments, error detection is performed based on the first comparison result, including: If the first original calculation result is inconsistent with the first redundant calculation result, the faulty thread is identified from the new thread bundle, and the calculation task of the faulty thread is migrated.
[0050] In this embodiment of the invention, by identifying the faulty thread from the new thread bundle and migrating the computational tasks of the faulty thread, the reliability of the system is improved and the smooth execution of the computational tasks is ensured.
[0051] In some embodiments, after comparing the number of active threads with the number of inactive threads, the method further includes: If the number of active threads is less than or equal to the number of inactive threads, redundant calculations are performed on the computational tasks of the active threads in the current thread bundle based on the inactive threads in the current thread bundle to obtain a second redundant calculation result. The second original calculation result of the active thread in the current thread bundle is compared with the second redundant calculation result to obtain the second comparison result, and error detection is performed based on the second comparison result.
[0052] In this embodiment of the invention, when the number of active threads is determined to be less than or equal to the number of inactive threads, redundant calculations are performed on the calculation tasks of the active threads in the current thread bundle based directly on the inactive threads in the current thread bundle to obtain a second redundant calculation result; the second original calculation result of the active threads in the current thread bundle is compared with the second redundant calculation result to obtain a second comparison result; and error detection is performed based on the second comparison result, which is highly flexible and improves error detection efficiency.
[0053] In some embodiments, redundant computation is performed on the computational tasks of the new active threads in the new thread bundle based on the new inactive threads in the new thread bundle, including: Get the error detection command input by the user; In response to the error detection command, the preset error detection mechanism is activated, and the idle execution unit corresponding to the new inactive thread in the new thread bundle performs redundant execution of the computation tasks of the new active thread in the new thread bundle.
[0054] The pre-defined error detection mechanism includes at least the following: performing redundant calculations, result comparison, and error detection. This pre-defined error detection mechanism is a capability embedded in the hardware. An idle execution unit refers to hardware resources such as arithmetic logic units and floating-point units that are associated with a new inactive thread and have no computational tasks in the current cycle.
[0055] Specifically, when programmers write code, or when compilers analyze code, they identify critical code segments where the reliability of the calculation results is extremely important. Specific error-checking instructions are then inserted before these critical calculation instructions.
[0056] It should be noted that the subsequent redundant calculations, result comparisons, and error detection processes will only be executed if the error detection mechanism is activated. If the error detection mechanism is not activated, the subsequent redundant calculations, result comparisons, and error detection processes will not be executed, which provides high flexibility.
[0057] In this embodiment of the invention, by obtaining the error detection command input by the user, and in response to the error detection command, a preset error detection mechanism is activated. The idle execution unit corresponding to the new inactive thread in the new thread bundle performs redundant execution on the computational tasks of the new active thread in the new thread bundle. This provides high flexibility, improves the user experience, and avoids unnecessary error detection overhead.
[0058] The following describes the error detection system for a single-instruction multi-threaded processor provided in the embodiments of the present invention. The error detection system for a single-instruction multi-threaded processor described below can be referred to in correspondence with the error detection method for a single-instruction multi-threaded processor described above.
[0059] Figure 4 This is an architecture diagram of an error detection system for a single-instruction multi-threaded processor provided in an embodiment of the present invention. Figure 4 As shown, the system includes a Warp active blocked thread statistics unit and multiple execution units. The Warp active blocked thread statistics unit dynamically counts the branch divergence of threads executing the same instruction, compares the number of active and inactive threads, and determines whether a reorganization operation should be performed. The Warp reorganizer, upon receiving a reorganization request, reorganizes threads executing the same PC value, ensuring that the number of active threads is less than or equal to the number of inactive threads. With the error detection mechanism enabled, if the number of idle execution units is greater than or equal to the number of active execution units, the idle execution units are used for repeated calculation, and the results are compared. When the error detection mechanism is not enabled, repeated calculation is not performed to save power.
[0060] Figure 5 This is a schematic diagram of the structure of the error detection system for a single-instruction multithreaded processor provided in an embodiment of the present invention, as shown below. Figure 5 As shown, the error detection system 500 of the single-instruction multithreaded processor includes: The statistics unit 510 is used to count the number of active threads and inactive threads in the current thread bundle of the single instruction multithreaded SIMT processor. The reorganization unit 520 is used to compare the number of active threads with the number of inactive threads. When the number of active threads is greater than the number of inactive threads, a thread reorganization operation is triggered to update the current thread bundle and obtain a new thread bundle. The number of new active threads in the new thread bundle is less than or equal to the number of new inactive threads. The first redundant calculation unit 530 is used to perform redundant calculations on the calculation tasks of the new active threads in the new thread bundle based on the new inactive threads in the new thread bundle, and obtain the first redundant calculation result. The first error detection unit 540 is used to compare the first original calculation result of the new active thread in the new thread bundle with the first redundant calculation result to obtain the first comparison result, and to perform error detection based on the first comparison result.
[0061] Optionally, the current thread bundle is updated to obtain a new thread bundle, including: Select one or more target thread bundles from the thread pool of the SIMT processor; the sum of the number of active threads and the number of inactive threads in the target thread bundle is equal to the sum of the number of active threads and the number of inactive threads in the current thread bundle. Swap threads in the current thread bundle with threads in one or more target thread bundles, reorganize threads with the same program counter (PC) value, and concentrate active threads and / or concentrate inactive threads. Based on the reorganization result, the current thread bundle is updated to obtain a new thread bundle.
[0062] Optionally, error detection is performed based on the first comparison result, including: If the first original calculation result is inconsistent with the first redundant calculation result, it is determined that the new active thread in the new thread bundle has a calculation error, an error alarm message is generated, and an alarm is issued. If the first original calculation result is consistent with the first redundant calculation result, the calculation of the new active thread in the new thread bundle is determined to be correct.
[0063] Optionally, error detection is performed based on the first comparison result, including: If the first original calculation result is inconsistent with the first redundant calculation result, the faulty thread is identified from the new thread bundle, and the calculation task of the faulty thread is migrated.
[0064] Optionally, the error detection system for a single-instruction multithreaded processor may also include: The second redundant calculation unit is used to perform redundant calculations on the calculation tasks of the active threads in the current thread bundle based on the inactive threads in the current thread bundle when the number of active threads is determined to be less than or equal to the number of inactive threads, and to obtain the second redundant calculation result. The second error detection unit is used to compare the second original calculation result of the active thread in the current thread bundle with the second redundant calculation result to obtain the second comparison result, and to perform error detection based on the second comparison result.
[0065] Optionally, based on the new inactive threads in the new thread bundle, redundant computation is performed on the computation tasks of the new active threads in the new thread bundle, including: Get the error detection command input by the user; In response to the error detection command, the preset error detection mechanism is activated, and the idle execution unit corresponding to the new inactive thread in the new thread bundle performs redundant execution of the computation tasks of the new active thread in the new thread bundle.
[0066] It should be noted that the error detection system for a single-instruction multi-threaded processor provided in this embodiment of the invention can implement all the method steps implemented in the above-described error detection method embodiment for a single-instruction multi-threaded processor, and can achieve the same technical effect. Therefore, the parts and beneficial effects that are the same as those in the method embodiment will not be described in detail here.
[0067] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention, such as... Figure 6 As shown, the electronic device may include: a processor 610, a communications interface 620, a memory 630, and a communications bus 640, wherein the processor 610, the communications interface 620, and the memory 630 communicate with each other through the communications bus 640. The processor 610 can call logical instructions in the memory 630 to execute an error detection method for a single-instruction multi-threaded processor. This method includes: counting the number of active and inactive threads in the current thread bundle of the single-instruction multi-threaded processor; comparing the number of active threads with the number of inactive threads; when the number of active threads is greater than the number of inactive threads, triggering a thread reorganization operation to update the current thread bundle and obtain a new thread bundle; the number of new active threads in the new thread bundle is less than or equal to the number of new inactive threads; performing redundant calculations on the computational tasks of the new active threads in the new thread bundle based on the new inactive threads in the new thread bundle to obtain a first redundant calculation result; comparing the first original calculation result of the new active threads in the new thread bundle with the first redundant calculation result to obtain a first comparison result; and performing error detection based on the first comparison result.
[0068] Furthermore, the logical instructions in the aforementioned memory 630 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0069] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the error detection method for a single-instruction multithreaded processor provided by the above methods. The method includes: counting the number of active threads and inactive threads in the current thread bundle of the single-instruction multithreaded processor; comparing the number of active threads with the number of inactive threads, and when the number of active threads is greater than the number of inactive threads, triggering a thread reorganization operation to update the current thread bundle and obtain a new thread bundle; the number of new active threads in the new thread bundle is less than or equal to the number of new inactive threads; performing redundant calculations on the computational tasks of the new active threads in the new thread bundle based on the new inactive threads in the new thread bundle to obtain a first redundant calculation result; comparing the first original calculation result of the new active threads in the new thread bundle with the first redundant calculation result to obtain a first comparison result, and performing error detection based on the first comparison result.
[0070] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements an error detection method for a single-instruction multithreaded processor (SIMT) provided by the above methods. The method includes: counting the number of active threads and inactive threads in the current thread bundle of the SIMT processor; comparing the number of active threads with the number of inactive threads, and when the number of active threads is greater than the number of inactive threads, triggering a thread reorganization operation to update the current thread bundle and obtain a new thread bundle; the number of new active threads in the new thread bundle is less than or equal to the number of new inactive threads; performing redundant calculations on the computational tasks of the new active threads in the new thread bundle based on the new inactive threads in the new thread bundle to obtain a first redundant calculation result; comparing the first original calculation result of the new active threads in the new thread bundle with the first redundant calculation result to obtain a first comparison result, and performing error detection based on the first comparison result.
[0071] The system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.
[0072] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.
[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for error detection in a single-instruction multithreaded processor, characterized in that, include: Count the number of active and inactive threads in the current thread bundle of a Single Instruction Multithreaded (SIMT) processor; The number of active threads is compared with the number of inactive threads. When the number of active threads is greater than the number of inactive threads, a thread reorganization operation is triggered to update the current thread bundle and obtain a new thread bundle. The number of new active threads in the new thread bundle is less than or equal to the number of new inactive threads. Based on the new inactive threads in the new thread bundle, redundant calculations are performed on the computational tasks of the new active threads in the new thread bundle to obtain the first redundant calculation result. The first original calculation result of the new active thread in the new thread bundle is compared with the first redundant calculation result to obtain the first comparison result, and error detection is performed based on the first comparison result.
2. The error detection method for a single-instruction multi-threaded processor according to claim 1, characterized in that, The step of updating the current thread bundle to obtain a new thread bundle includes: One or more target thread bundles are selected from the thread pool of the SIMT processor; the sum of the number of active threads and the number of inactive threads in the target thread bundle is equal to the sum of the number of active threads and the number of inactive threads in the current thread bundle. Exchange threads in the current thread bundle with threads in one or more target thread bundles, reorganize threads with the same program counter (PC) value, and concentrate active threads and / or concentrate inactive threads. Based on the reorganization result, the current thread bundle is updated to obtain a new thread bundle.
3. The error detection method for a single-instruction multithreaded processor according to claim 1, characterized in that, The error detection based on the first comparison result includes: If the first original calculation result is inconsistent with the first redundant calculation result, it is determined that there is a calculation error in the new active thread in the new thread bundle, an error alarm message is generated, and an alarm is issued. If the first original calculation result is consistent with the first redundant calculation result, the calculation of the new active thread in the new thread bundle is determined to be correct.
4. The error detection method for a single-instruction multithreaded processor according to claim 1, characterized in that, The error detection based on the first comparison result includes: If the first original calculation result is inconsistent with the first redundant calculation result, the faulty thread is identified from the new thread bundle, and the calculation task of the faulty thread is migrated.
5. The error detection method for a single-instruction multithreaded processor according to claim 1, characterized in that, After comparing the number of active threads with the number of inactive threads, the method further includes: If the number of active threads is determined to be less than or equal to the number of inactive threads, redundant calculations are performed on the computational tasks of the active threads in the current thread bundle based on the inactive threads in the current thread bundle to obtain a second redundant calculation result. The second original calculation result of the active thread in the current thread bundle is compared with the second redundant calculation result to obtain a second comparison result, and error detection is performed based on the second comparison result.
6. The error detection method for a single-instruction multithreaded processor according to claim 1, characterized in that, The redundant computation of the computation tasks of the new active threads in the new thread bundle based on the new inactive threads in the new thread bundle includes: Get the error detection command input by the user; In response to the error detection command, a preset error detection mechanism is activated, and the idle execution unit corresponding to the new inactive thread in the new thread bundle performs redundant execution of the computational tasks of the new active thread in the new thread bundle.
7. An error detection system for a single-instruction multi-threaded processor, characterized in that, include: The statistics unit is used to count the number of active and inactive threads in the current thread bundle of a Single Instruction Multithreaded (SIMT) processor. The reorganization unit is used to compare the number of active threads with the number of inactive threads. When the number of active threads is greater than the number of inactive threads, a thread reorganization operation is triggered to update the current thread bundle and obtain a new thread bundle. The number of new active threads in the new thread bundle is less than or equal to the number of new inactive threads. The first redundant calculation unit is used to perform redundant calculations on the calculation tasks of the new active threads in the new thread bundle based on the new inactive threads in the new thread bundle, and obtain the first redundant calculation result. The first error detection unit is used to compare the first original calculation result of the new active thread in the new thread bundle with the first redundant calculation result to obtain a first comparison result, and to perform error detection based on the first comparison result.
8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the error detection method of the single-instruction multithreaded processor as described in any one of claims 1 to 6.
9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the error detection method of the single-instruction multi-threaded processor as described in any one of claims 1 to 6.
10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the error detection method of the single-instruction multi-threaded processor as described in any one of claims 1 to 6.