Data comparison method in chip power-on process and related equipment
By using a tag value comparison method with inverse codes during chip power-up, the problem of calibration value reading errors during chip power-up is solved, ensuring the accuracy and integrity of calibration values and improving the chip's startup success rate and operational stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GIANTEC SEMICON LTD INC
- Filing Date
- 2025-12-31
- Publication Date
- 2026-04-21
AI Technical Summary
During power-up, voltage instability causes errors in the calibration values read from non-volatile memory, affecting chip performance.
Tag values that are inverses of each other are stored in the chip's non-volatile memory and compared upon power-up. Only after ensuring that the original code and the inverse code of the calibration value are inverses of each other are written to the register. Potential data reading errors are identified and corrected through a two-level comparison process.
It improves the chip's startup success rate and operational stability in complex power environments, ensures the accuracy and integrity of calibration values, and avoids chip initialization failure or entering unexpected states.
Smart Images
Figure CN121901023A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip technology, and in particular to a data comparison method and related equipment during the chip power-on process. Background Technology
[0002] Before leaving the factory, the chip's internal control circuitry needs to be calibrated, and the calibration values are stored in the chip's non-volatile memory (NVR). During power-on initialization, the chip reads the calibration values from the NVR and loads them into the corresponding control registers. However, voltage instability may occur during the power-on phase, leading to errors in the calibration values read from the NVR, and consequently, the chip's final performance failing to meet expectations.
[0003] The statements herein provide only background information in relation to this invention and do not necessarily constitute prior art. Summary of the Invention
[0004] The purpose of this invention is to provide a data comparison method and related equipment during the chip power-on process to ensure the accuracy of calibration value reading, increase the reliability of control registers, and thus improve chip performance.
[0005] To achieve the above objectives, a first aspect of the present invention provides a data comparison method during chip power-up, wherein a first address of the chip's NVR and an adjacent second address store a first tag value and a second tag value that are inverses of each other, comprising: S10, reading the first tag value and the second tag value from the first address and the second address respectively, and comparing them with a preset value to check whether the first tag value and the second tag value are correct; S20, if both the first tag value and the second tag value are correct, sequentially reading calibration value data stored after the second address; the calibration value data includes a plurality of calibration value pairs composed of the original code and the inverse code of calibration values located at adjacent addresses; S30, sequentially comparing whether the original code and the inverse code of the calibration value in each calibration value pair are inverses of each other, and if they are inverses of each other, writing the original code of the calibration value into the corresponding register, until all calibration value pairs have been read and compared.
[0006] In one embodiment, step S10 specifically includes: S11, reading the first Tag value from the first address n and storing it in a register; S12, comparing the first Tag value with a preset value to see if it is correct; if correct, proceeding to step S13; otherwise, re-executing step S11; S13, reading the second Tag value from the second address n+1 and storing it in a register; S14, comparing the second Tag value with a preset value to see if it is correct; if correct, proceeding to step S20; otherwise, re-executing steps S11 to S14.
[0007] In one embodiment, step S20 specifically includes: S21, reading the original code of the calibration value in the m-th calibration value pair from the third address n+m+2 and storing it in the register; S22, reading the inverse code of the calibration value in the m-th calibration value pair from the fourth address n+m+3 and storing it in the register; where m=0, 1, 2, 3... and m is an integer.
[0008] In one embodiment, step S30 specifically includes: S31, comparing whether the original code of the calibration value and the inverse code of the calibration value in the m-th calibration value pair are inverse codes of each other; if they are inverse codes of each other, the original code of the calibration value is written into the corresponding register, and steps S21 to S31 are repeated until all the calibration value data is read and compared; S32, comparing whether the address of the calibration value is equal to the number of calibration value pairs in the calibration value data and whether the comparison of each calibration value is completed, and determining whether the power-on initialization is finished; if the number of calibration value pairs is equal and the comparison of each calibration value pair is correct, the power-on initialization is finished; if the number of calibration value pairs is not equal or the comparison of any calibration value pair is incorrect, steps S21 to S32 are repeated until all the calibration value data is read and compared.
[0009] In one embodiment, if in step S30, the original code of the calibration value and the inverse code of the calibration value in the m-th calibration value pair are not inverse codes of each other, then return to step S10 and repeat steps S10 to S30 until all the calibration value data have been read and compared.
[0010] In one embodiment, before executing step S10, the method further includes: S00, determining whether the reset signal is equal to 1; if the reset signal is equal to 1, then executing steps S10 to S30; if the reset signal is not equal to 1, then waiting for the reset signal to become 1, waiting for a preset delay time, and then executing steps S10 to S30.
[0011] In one embodiment, step S20 further includes: S23, after the original code of the calibration value and the inverse code of the calibration value in the m-th calibration value pair are read, the register generates a high-level signal with a duration of at least 1 CLK as an enable signal to start the calibration value data comparison.
[0012] A second aspect of the present invention provides an electronic device comprising: a processor and a memory, the processor being coupled to the memory; the memory being used to store a program; and the processor being used to execute the program in the memory, causing the electronic device to perform the data comparison method as described above.
[0013] A third aspect of the present invention provides a computer-readable storage medium storing a program that, when run on a computer, causes the computer to perform the data comparison method as described above.
[0014] A fourth aspect of the present invention provides a computer program product, characterized in that the computer program product includes a program that, when the program is run on a computer, causes the computer to execute the data comparison method described above.
[0015] Compared with the prior art, the data comparison method and related equipment provided by the present invention during the chip power-on process have at least the following beneficial effects: By storing the original code and inverse code of the Tag value at a specific address in the NVR, and comparing the original code and inverse code of the Tag value with the preset value before loading the calibration value, the integrity and accuracy of reading the configuration data containing the calibration value are guaranteed. This reduces the probability of chip initialization failure, functional abnormality or entering an unexpected state due to loading a corrupted calibration value, and improves the chip's startup success rate and operational stability in complex power environments.
[0016] Secondly, by setting a step to ensure that the calibration values are strictly inverses of each other, random bit errors introduced by power-on disturbances are effectively filtered out, ensuring that the calibration value finally written to the chip control register is consistent with the original value written to the non-volatile memory after the chip is tested. This eliminates the calibration value deviation caused by the randomness of the power-on process, enabling the chip to work under the expected parameters after each power-on, and ensuring that the final performance of the chip reaches the design expectation. Attached Figure Description
[0017] Figure 1 This is a flowchart of the data comparison method during the chip power-on process of the present invention; Figure 2 A flowchart illustrating one embodiment of the data comparison method during chip power-on process of the present invention; Figure 3 This is a timing diagram of an embodiment of the data comparison method during chip power-up of the present invention; Figure 4 This is a schematic diagram of an electronic device for the data comparison method during the chip power-on process of the present invention. Detailed Implementation
[0018] The data comparison method and related equipment during the chip power-on process proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, only for the purpose of conveniently and clearly illustrating the embodiments of this invention. Please refer to the accompanying drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives achieved by this invention, should still fall within the scope of the technical content disclosed in this invention.
[0019] After chip testing is complete, some calibration values are stored in a specific area of non-volatile memory (NVR), and a designated address in the NVR stores the loadable tag data. When the chip is powered on, it takes some time for the chip voltage to rise from GND (0 V) to VDD (operating voltage). During this power-up process, external conditions may cause the voltage supply to the chip to be unstable. In this case, the calibration values obtained from the NVR may be incorrect. Loading the obtained calibration values into the control register at this time will cause the chip's final performance to fall short of expectations.
[0020] Based on the above-mentioned defects, such as Figure 1 As shown, this embodiment of the invention provides a data comparison method during chip power-up. The first address and the adjacent second address of the chip's NVR store a first tag value and a second tag value that are inverses of each other. The data comparison method includes: S10, reading the first tag value and the second tag value from the first address and the second address respectively, and comparing them with a preset value to check whether the first tag value and the second tag value are correct; S20, if the first tag value and the second tag value are both correct, then sequentially reading the calibration value data stored after the second address; the calibration value data includes several calibration value pairs composed of the original code and the inverse code of the calibration value located at adjacent addresses; S30, sequentially comparing whether the original code and the inverse code of the calibration value in each calibration value pair are inverses of each other. If they are inverses of each other, then writing the original code of the calibration value into the corresponding register, until all calibration value pairs have been read and compared.
[0021] This invention stores the original code and inverse code of the Tag value at a specific address in the NVR. The calibration value is only loaded after the original code and inverse code of the Tag value are correctly compared with preset values. This ensures the integrity and accuracy of reading configuration data containing calibration values, thereby reducing the probability of chip initialization failure, functional abnormalities, or entering unexpected states due to loading corrupted calibration values. This improves the chip's startup success rate and operational stability in complex power environments. Secondly, by setting a step where the calibration value pairs are strictly inverse codes, random bit errors introduced by power-on disturbances are effectively filtered out. This ensures that the calibration value finally written to the chip control register is consistent with the original value written to non-volatile memory after chip testing. This eliminates calibration value deviations caused by the randomness of the power-on process, allowing the chip to operate under the designed parameters after each power-on. Its performance indicators (such as accuracy, speed, and power consumption) are stably reproduced, achieving the expected level during testing and verification.
[0022] In some embodiments, the tag value data and calibration value data used for verification are stored in the NVR as follows: n in the address column adrr is the first address of the first tag value (Tag) (i.e., the starting address for reading data), n+1 is the second address of the second tag value (Tag Inv), and the NVR stores m calibration value pairs, where the third address of the original code (Cal datam) of the mth calibration value is n+m+2, and the fourth address of the inverse code (Cal datam Inv) of the mth calibration value is n+m+3, where m takes the value 0, 1, 2, ..., and m is an integer.
[0023] Please see Figure 2 , Figure 2The flowchart illustrates an embodiment of the data comparison method during chip power-up of the present invention. Step S10 specifically includes: S11, reading a first Tag value (Tag) from a first address n and storing it in a register; S12, comparing the first Tag value (Tag) against a preset value to determine if it is correct. If correct, proceed to step S13; otherwise, repeat step S11; S13, reading a second Tag value (i.e., the inverse code TagInv of the first Tag value) from a second address n+1 and storing it in a register; S14, comparing the second Tag value (TagInv) against a preset value to determine if it is correct. If correct, proceed to step S20; otherwise, repeat steps S11 to S14. It should be noted that in this embodiment, there is only one unique first tag value and a second tag value that is the inverse of the first tag. The first tag value and the second tag value serve only as indicators of voltage stability, i.e., as indicators of whether the chip can correctly read data, rather than indicating the address where the data is stored. When the first tag value and the second tag value match the preset value, the voltage is considered stable, and the calibration value data in the NVR can be read correctly. Furthermore, the preset value can be manually set according to requirements. This preset value can be a set of preset value data that contains both 0 and 1 after being converted to binary, generally with 0 and 1 alternating, such as 0x55 and 0xaa. This invention does not limit this.
[0024] In this embodiment, a two-level comparison process is constructed by first reading and independently comparing the first tag value with the preset value, and then reading and comparing its inverse code (i.e., the second tag value) after confirming its correctness. This process can identify data read failures or storage unit damage at a single address at an early stage, avoiding direct reading and comparison of potentially erroneous complete tag pairs. Simultaneously, a re-execution loop mechanism is set up for read failures or comparison errors, improving the fault tolerance capability of finally obtaining the correct tag value under transient interference conditions. This provides a reliable starting point for data area validity judgment for subsequent batch comparisons of calibration values, ensuring the integrity and accuracy of reading configuration data containing correction values.
[0025] Please continue reading. Figure 2 After the data comparison between the first Tag value (Tag) and the second Tag value (Tag_inv) is correct and completed, step S20 is executed, that is, each calibration value pair in the calibration value data is compared. Step S20 specifically includes: S21, reading the original code of the calibration value in the m-th calibration value pair from the third address n+m+2 and storing it in the register; S22, reading the inverse code of the calibration value in the m-th calibration value pair from the fourth address n+m+3 and storing it in the register; where m=0, 1, 2, 3... and m is an integer.
[0026] Furthermore, such as Figure 2 As shown, based on the original code and the inverse code of the calibration value in the m-th calibration value pair, step S30 is executed. Step S30 specifically includes: S31, comparing whether the original code and the inverse code of the calibration value in the m-th calibration value pair are inverse codes of each other. If they are inverse codes, the original code of the calibration value is written into the corresponding register, and steps S20 to S21 are repeated until all the calibration value data has been read and compared; if the original code and the inverse code of the calibration value in the m-th calibration value pair are not inverse codes of each other, the process returns to step... S10, Repeat steps S10 to S30 until all calibration value data has been read and compared; S32, Compare whether the address of the calibration value is equal to the number of calibration value pairs in the calibration value data and whether the comparison of each calibration value is completed, and determine whether the power-on initialization is finished; If the number of calibration value pairs is equal and the comparison of each calibration value pair is correct, then the power-on initialization is finished; If the number of calibration value pairs is not equal or the comparison of any calibration value pair is incorrect, repeat steps S21 to S32 until all calibration value data has been read and compared. The method for comparing whether the original code and the inverse code of the calibration value are inverse codes is as follows: if all bits of the read original code and the inverse code of the calibration value are 1 after addition, then the comparison is considered correct, such as binary data 01010101 and 10101010.
[0027] This embodiment ensures that each calibration value undergoes integrity verification before being loaded into the working register by performing pairwise comparisons between the original code and the inverse code of the calibration value. This prevents a single erroneous calibration value from affecting chip performance. Simultaneously, by comparing the number of processed addresses with the number of calibration value pairs in the calibration data, a deterministic closed-loop verification mechanism is established. This reliably detects whether the data reading process has been interrupted unexpectedly, resulting in the omission of some calibration values. This ensures that the entire calibration dataset is loaded completely and correctly, making the chip's initialization state predictable and verifiable.
[0028] In some embodiments, step S20 further includes: S23, after the original code of the calibration value and the inverse code of the calibration value in the m-th calibration value pair are read, the register generates a high-level signal with a duration of at least 1 CLK as an enable signal to start the calibration value data comparison.
[0029] In some embodiments, such as Figure 2As shown, before executing step S10, the process includes: S00, determining whether the reset signal is equal to 1; if the reset signal is equal to 1, then executing steps S10 to S30; if the reset signal is not equal to 1, then waiting for the reset signal to become 1, waiting for a preset delay time, and then executing steps S10 to S30. This is because during chip power-on, the internal power supply and clock are not yet stable, and the memory cells are in a random state. Keeping the reset signal valid can force all timing logic to be initialized to a deterministic state, avoiding functional malfunctions or illegal operations caused by random logic levels. The preset time can be set according to actual needs to ensure that the reset signal is 1, thereby avoiding incorrect comparisons in subsequent data reading and comparison processes due to an unstable voltage caused by a short preset time.
[0030] In one specific embodiment, such as Figure 3 As shown, Figure 3 The timing diagram of the power-on process in this specific embodiment is shown. A data comparison method is implemented through dedicated timing control signals, specifically including: when the data DOUT read from the NVR is trim_data and trim_data_inv, steps S12 and S14 are executed on trim_data and trim_data_inv respectively. After a correct comparison with a preset value, a high-level signal for one clock cycle (1 CLK) is generated as an enable signal to start the calibration value data comparison. This embodiment uses a register Reg_keep to temporarily store the steps. When the address is n+2, the original code of the calibration value stored at this address is data_0. To implement the calibration value data comparison process, the inverse code of the calibration value, data_0_inv, stored at address n+3, is read. The original code data_0 and the inverse code data_0_inv are compared. If data_0 and data_0_inv are inverse codes, the next pair of calibration value pairs is read, until all calibration value pairs have passed the comparison, completing the chip power-on initialization process.
[0031] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. The electronic device 100 can specifically be a laptop, tablet, or mobile phone, etc., and the present invention does not limit it to this. Specifically, the electronic device 300 includes: a processor 101 and a memory 102 (wherein the number of processors 101 in the electronic device 100 can be one or more). Figure 4 (Taking a processor as an example), in some embodiments of the present invention, the processor 101 and the memory 102 may be connected via a bus or other means.
[0032] Memory 102 may include read-only memory and random access memory, and provides instructions and data to processor 101. A portion of memory 102 may also include non-volatile memory (NVR). Memory 102 stores processor and operation instructions, executable modules or data structures, or subsets thereof, or extended sets thereof, wherein the operation instructions may include various operation instructions for implementing various operations.
[0033] Processor 101 controls the operation of electronic devices. In specific applications, the various components of electronic devices are coupled together through a bus system, which may include not only data buses but also power buses, control buses, and status signal buses. However, for clarity, all buses in the diagram are referred to as a bus system.
[0034] The data comparison method during chip power-on process disclosed in the above embodiments of the present invention can be applied to the processor 101, or implemented by the processor 101.
[0035] Processor 101 can be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of processor 101 or by instructions in software form. Processor 101 can be a general-purpose processor, a digital signal processor (DSP), a microprocessor, or a microcontroller, and may further include an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. Processor 101 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this invention can be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory 102. Processor 101 reads information from memory 102 and, in conjunction with its hardware, completes the steps of the above method. In this embodiment of the invention, processor 101 is used to execute... Figure 1 and Figure 2 The data comparison method executed by the electronic device in the corresponding embodiment during the chip power-on process.
[0036] This invention also provides a computer-readable storage medium storing a program for performing signal processing, which, when run on a computer, causes the computer to perform the aforementioned actions. Figure 1 and Figure 2 The method steps described in the illustrated embodiments, or causing a computer to perform as described above. Figure 1 and Figure 2 The steps performed by the electronic device in the method described in the illustrated embodiment.
[0037] The electronic device provided in this embodiment of the invention can also be a chip, which includes a processing unit and a communication unit. The processing unit may be, for example, a processor, and the communication unit may be, for example, an input / output interface, pins, or circuitry. The processing unit can execute computer execution instructions stored in a storage unit to cause the chip to perform the aforementioned operations. Figure 1 and Figure 2 The illustrated embodiment describes a data comparison method during chip power-up. Optionally, the storage unit is a storage unit within the chip, such as a register or cache. Alternatively, the storage unit can be a storage unit located outside the chip within the wireless access device, such as a read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, such as random access memory (RAM).
[0038] The processor mentioned above can be a general-purpose central processing unit, a microprocessor, an ASIC, or one or more integrated circuits used to control the execution of a program in the first aspect of the method.
[0039] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the accompanying drawings of the device embodiments provided by this invention, the connection relationship between modules indicates that they have a communication connection, which can be implemented as one or more communication buses or signal lines.
[0040] Through the above description of the embodiments, those skilled in the art can clearly understand that the present invention can be implemented by means of software plus necessary general-purpose hardware, and of course, it can also be implemented by special hardware including application-specific integrated circuits, special CPUs, special memory, special components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for the present invention, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments of the present invention.
[0041] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.
[0042] The computer program product includes one or more computer program instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present invention are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).
[0043] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0044] It should be noted that, in this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only the expressly listed elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.
[0045] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.
Claims
1. A data comparison method during chip power-on, characterized in that, The chip's NVR's first address and adjacent second address store a first tag value and a second tag value that are inverses of each other, including: S10. Read the first Tag value and the second Tag value from the first address and the second address respectively, and compare them with a preset value to check whether the first Tag value and the second Tag value are correct. S20. If both the first Tag value and the second Tag value are correct, then read the calibration value data stored after the second address in sequence; the calibration value data includes several calibration value pairs composed of the original code and the inverse code of the calibration values located at adjacent addresses; S30. In each calibration value pair, compare the original code and the inverse code of the calibration value to see if they are inverse codes of each other. If they are inverse codes, write the original code of the calibration value into the corresponding register until all calibration value pairs have been read and compared.
2. The data comparison method as described in claim 1, characterized in that, Step S10 specifically includes: S11. Read the first Tag value from the first address n and store it in the register; S12. Compare the first Tag value with the preset value to see if it is correct. If it is correct, proceed to step S13; otherwise, repeat step S11. S13. Read the second Tag value from the second address n+1 and store it in the register; S14. Compare the second Tag value with the preset value to see if it is correct. If it is correct, proceed to step S20; otherwise, repeat steps S11 to S14.
3. The data comparison method as described in claim 2, characterized in that, Step S20 specifically includes: S21. Read the original code of the calibration value in the m-th calibration value pair from the third address n+m+2 and store it in the register; S22. Read the inverse code of the calibration value in the m-th calibration value pair from the fourth address n+m+3 and store it in the register; where m=0,1,2,3... and m is an integer.
4. The data comparison method as described in claim 3, characterized in that, Step S30 specifically includes: S31. Compare whether the original code of the calibration value and the inverse code of the calibration value in the m-th calibration value pair are inverse codes of each other. If they are inverse codes of each other, write the original code of the calibration value into the corresponding register, and repeat steps S21 to S31 until all the calibration value data have been read and compared. S32. Compare the address of the calibration value with the number of calibration value pairs in the calibration value data to see if they are equal and whether the comparison of each calibration value is completed. Determine whether the power-on initialization is over. If the number of calibration value pairs is equal and the comparison of each calibration value pair is correct, then the power-on initialization is over. If the number of calibration value pairs is not equal or the comparison of any calibration value pair is incorrect, repeat steps S21 to S32 until all the calibration value data is read and compared.
5. The data comparison method as described in claim 4, characterized in that, If, in step S30, the original code of the calibration value and the inverse code of the calibration value in the m-th calibration value pair are not inverse codes of each other, then return to step S10 and repeat steps S10 to S30 until all the calibration value data have been read and compared.
6. The data comparison method as described in claim 1, characterized in that, Before executing step S10, the procedure also includes: S00, determining whether the reset signal is equal to 1; if the reset signal is equal to 1, then executing steps S10 to S30; if the reset signal is not equal to 1, then waiting for the reset signal to become 1, waiting for a preset delay time, and then executing steps S10 to S30.
7. The data comparison method as described in claim 3, characterized in that, Step S20 further includes: S23, after the original code of the calibration value and the inverse code of the calibration value in the m-th calibration value pair are read, the register generates a high-level signal with a duration of at least 1 CLK as an enable signal to start the calibration value data comparison.
8. An electronic device, characterized in that, include: A processor and a memory, wherein the processor is coupled to the memory; The memory is used to store programs; The processor is configured to execute a program in the memory, causing the electronic device to perform the data comparison method as described in any one of claims 1 to 7.
9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a program that, when run on a computer, causes the computer to perform the data comparison method as described in any one of claims 1 to 7.
10. A computer program product, characterized in that, The computer program product includes a program that, when run on a computer, causes the computer to perform the data comparison method as described in any one of claims 1 to 7.