System-on-chip (SOC) chip distributed debugging architecture and method thereof
By introducing a distributed debugging architecture into the SOC chip, integrating the debugging chain logic unit, and utilizing APB and JTAG protocol conversion, the problems of SOC chip debugging resource consumption and timing convergence difficulties are solved, achieving resource optimization, timing improvement, and debugging efficiency enhancement, with good compatibility and scalability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- JINDIE SPACETIME (BEIJING) TECHNOLOGY CO LTD
- Filing Date
- 2025-12-31
- Publication Date
- 2026-04-21
AI Technical Summary
Existing SOC chip debugging architectures suffer from problems such as resource consumption, timing convergence difficulties, and low debugging efficiency, especially in large-scale chips.
A distributed debugging architecture is adopted, which integrates debugging chain logic units, including register stamping modules, signal splitting modules and debugging port modules, into each module to be debugged. By using APB protocol and JTAG protocol conversion, a continuous distributed debugging network is formed.
It optimizes resource utilization, improves timing convergence, enhances debugging efficiency, strengthens scalability, improves fault location and repair speed, maintains the rationality and global synchronization of the address space, and has good compatibility.
Smart Images
Figure CN121901044A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit chip technology, and particularly relates to a distributed debugging architecture and method for a system-on-a-chip (SOC) chip. Background Technology
[0002] With the rapid development of integrated circuit technology, the number of functional modules and CPU cores integrated on large-scale SOC chips has increased dramatically, which places higher demands on chip debugging. Traditional debugging architectures are mainly divided into the following two categories: 1. Centralized debugging architecture: All components and CPU cores that need to be debugged are connected to the top-level debugging controller through a unified debugging interface. When there are many components, this architecture will occupy a lot of top-level routing resources, making timing difficult to converge, which in turn affects the operating frequency of other modules on the chip. 2. JTAG Daisy Chain Structure: Multiple debugging components are connected in series into a long chain through the JTAG protocol. Although this simplifies wiring, the increased length of the entire chain will significantly reduce debugging efficiency. Moreover, if any debugging component in the chain fails, the entire debugging path will fail, making it difficult to locate the fault. Summary of the Invention
[0003] The purpose of this invention is to solve the above-mentioned technical problems existing in the prior art, and to provide a distributed debugging architecture and method for a system-on-a-chip (SOC) chip, which solves the problems of resource consumption, timing convergence difficulties, and low debugging efficiency during chip debugging.
[0004] To solve the above-mentioned technical problems, the present invention adopts the following technical solution: A distributed debugging architecture for a system-on-a-chip (SoC) is characterized by comprising: Debug chain logic unit, which is integrated inside each module to be debugged in the SOC chip; The debug chain logic unit includes: Register timing module: The register timing module is used to perform register timing processing on the input debugging signals; The signal splitting module is used to split the debug signal processed by the register stamping module into a first debug signal and a second debug signal according to preset address information or flag information. The first debug signal is used for internal debugging of the current module to be debugged, and the second debug signal is used as a debug output, so that the debug output of the current module to be debugged is connected to the debug path entrance of the next module to be debugged, so as to form a continuous distributed debug network.
[0005] Furthermore, the register timing module uses an APB synchronizer to interrupt the transmission path by registering one APB signal.
[0006] Furthermore, the signal splitting module adopts an APB 1 to 2 bridge, which routes the input APB transaction to the internal APB interface corresponding to the first debugging signal or to the output APB interface corresponding to the second debugging signal based on the address decoding.
[0007] Furthermore, it also includes a debug port module, which is used to convert between the external debug interface protocol and the internal debug bus protocol.
[0008] Furthermore, the debug port module adopts a TAP controller, with the external debug interface protocol being the JTAG protocol and the internal debug bus protocol being the APB protocol.
[0009] Furthermore, the debug chain logic unit is connected to the module to be debugged via the APB bus.
[0010] A debugging method for a distributed debugging architecture of a system-on-a-chip (SoC) chip, characterized by the following steps: S1. An external debugger generates debugging instructions and inputs them into the SOC chip; S2. Debugging commands are passed level by level in the distributed debugging network. When a debugging chain logic unit inside a module to be debugged receives a debugging command: S2-1. The input debugging signal is processed by register timing module; S2-2. The debugging signal processed by the register stamping module is divided into a first debugging signal and a second debugging signal through the signal splitting module. The current module to be debugged performs internal debugging operations according to the first debugging signal, and outputs the second debugging signal to the next module to be debugged. S3. Repeat step S2 until the debugging command reaches the target debugging module and completes the debugging operation; S4. After the module being debugged completes the debugging operation, the debugging data results are returned to the external debugger step by step through the distributed debugging network along the path opposite to the path of the debugging command.
[0011] Furthermore, in step S1, the external debugger is connected to the SOC chip via the JTAG interface; in step S2, the SOC chip first converts the JTAG protocol into the APB protocol through the debug port module, and then connects the debug commands to the distributed debug network through the APB bus; in step S4, the debug port module converts the debug data results returned by the APB bus into the JTAG protocol, and transmits them to the external debugger through the TDO signal.
[0012] The present invention, by adopting the above-described technical solution, has the following beneficial effects: 1. Resource optimization: Since each module independently processes and forwards debug signals, the distributed debug architecture can better adapt to the back-end layout and routing, significantly reduce the use of top-level routing resources, provide more space for other critical signals, and optimize the overall chip layout.
[0013] 2. Timing Improvement: Through distributed processing, the length of each debugging path is shortened, timing convergence is easier, and the stability and frequency of the debugging signal are improved to meet the debugging requirements of high-speed chips.
[0014] 3. Improved debugging efficiency: It avoids debugging delays caused by long daisy chains, and single-point failures do not affect the debugging of other modules, thus improving the speed of fault location and repair.
[0015] 4. High scalability: When adding a new module to be debugged, simply integrate the debug chain logic at the corresponding location and connect it to the existing network. The architecture is easy to expand and maintain.
[0016] 5. Rationality of address space allocation: Rationally plan the address mapping of each module being debugged to ensure no conflicts and easy access by the software.
[0017] 6. Global Synchronization: The debugging chain logic units in the entire distributed debugging network are planned to be globally synchronized.
[0018] 7. Good compatibility: The distributed debugging architecture does not change the address space mapping of the modules, but only distributes the centralized memory mapping to the tightly coupled debugging chain logic units of each debugging module, thus making it compatible with traditional debugging architectures. Attached Figure Description
[0019] The present invention will be further described below with reference to the accompanying drawings: Figure 1 This is a schematic diagram of the debug chain logic unit in this invention; Figure 2 This is a schematic diagram showing the connection between the debug chain logic unit and the module to be debugged via the APB bus in this invention; Figure 3 This is a logic diagram of the signal splitting module in this invention; Figure 4 This is a logic diagram of the signal splitting module in this invention; Figure 5 This is a logic diagram of the signal splitting module in this invention; Figure 6 This is a schematic diagram showing the distribution of the AP module to be debugged on the SOC chip. Figure 7 A schematic diagram of a debugging network for a module to be debugged that does not integrate a debugging chain logic unit; Figure 8 This is a schematic diagram of the distributed debugging network in this invention; Figure 9 This is a schematic diagram of the distributed debugging network in this invention; Figure 10 This is a flowchart of the debugging process of the present invention. Detailed Implementation
[0020] A distributed debugging architecture for a system-on-a-chip (SoC) includes a debug chain logic unit and a debug port module. The debug port module is used to convert between an external debug interface protocol and an internal debug bus protocol. The debug port module uses a TAP controller, with the external debug interface protocol being the JTAG protocol and the internal debug bus protocol being the APB protocol.
[0021] The debug chain logic unit is integrated inside each module to be debugged in the SOC chip. The debug chain logic unit is used to receive, process and forward debug signals.
[0022] Debugging essentially involves obtaining the internal state information of a module to locate problems. This state information is implemented through registers within the module being debugged. The software reads the register information through register access ports, and the register access ports of the module being debugged use the APB protocol.
[0023] The debug chain logic unit and the module to be debugged are connected via the APB bus and are packaged at the same level, such as... Figure 2 As shown, the backend can use the outer layer A_Wrapper to perform hardening implementation.
[0024] like Figure 1 As shown, the debug chain logic unit includes a register timing module and a signal splitting module. The register timing module is used to perform register timing processing on the input debug signals to stabilize the signals and reduce timing conflicts. The register timing module uses an APB synchronizer, which interrupts the transmission path by registering one APB signal, facilitating backend implementation.
[0025] The signal splitting module is used to split the debug signal processed by the register stamping module into a first debug signal and a second debug signal according to preset address information or flag information. The first debug signal is used for internal debugging of the current module to be debugged, and the second debug signal is used as a debug output and connected to the debug path entry of the next module to be debugged in the chain through the APB protocol to maintain the consistency of the protocol.
[0026] The signal splitter module uses an APB 1 to 2 bridge, which routes the input APB transaction to the internal APB interface corresponding to the first debug signal or to the output APB interface corresponding to the second debug signal based on the address decoding. Figures 3 to 5 As shown.
[0027] When integrating with a SoC, memory mapping information is required. Assuming address space A is the address of the module being debugged, when the address bus PADDR falls within this address region, the APB transaction will be forwarded to the corresponding module being debugged; when the address bus PADDR falls in other address spaces, it will be routed to another APB interface.
[0028] The debugging paths of adjacent modules to be debugged are connected to form a continuous distributed debugging network.
[0029] like Figure 8 and Figure 9 As shown, the debugging logic unit and the module being debugged are integrated into the A_Wrapper (A_W) level, which allows for flexible adjustment of the topology. The resulting distributed network architecture can better adapt to the backend layout and cabling, reducing the occupation of top-level cabling resources.
[0030] The APB protocol sends debug commands via the address bus PADDR, the read / write control signal PWRITE, and the write data bus PWDATA, and returns debug data results via the read data bus PRDATA. Essentially, it reads a target address register via APB and then returns the register value via the read data bus PRDATA.
[0031] A debugging method for a distributed debugging architecture of a system-on-a-chip (SoC) includes the following steps: S1. An external debugger connects to the SOC chip via the JTAG interface and inputs the generated debugging commands to the SOC chip.
[0032] S2 and the SOC chip first convert the JTAG protocol to the APB protocol through the debug port module, and then connect the debug command to the distributed debug network through the APB bus. The debug command is passed level by level in the distributed debug network. When a debug chain logic unit inside a module to be debugged receives the debug command: S2-1. The input debug signal is processed by register timing module. This stabilizes the debug signal, reduces timing conflicts, and improves the reliability of debug signal transmission.
[0033] S2-2. The debugging signal processed by the register stamping module is divided into a first debugging signal and a second debugging signal by the signal splitting module. The current module to be debugged performs internal debugging operations based on the first debugging signal and outputs the second debugging signal to the next module to be debugged.
[0034] S3. Repeat step S2 until the debugging command reaches the target debugging module and completes the debugging operation, such as... Figure 10 As shown.
[0035] S4. After the module being debugged completes the debugging operation, the debugging data results are returned to the debugging port module through the distributed debugging network along the path opposite to the path of the debugging command transmission. The debugging port module converts the debugging data results returned by the APB bus into the JTAG protocol and transmits them to the external debugger through the TDO signal.
[0036] The above are merely specific embodiments of the present invention, but the technical features of the present invention are not limited thereto. Any simple changes, equivalent substitutions, or modifications made based on the present invention to solve essentially the same technical problems and achieve essentially the same technical effects are all covered within the protection scope of the present invention.
Claims
1. A distributed debugging architecture for a system-on-a-chip (SoC), characterized in that, include: A debug chain logic unit, which is integrated inside each module to be debugged in the SOC chip; The debug chain logic unit includes: a register timing module, which is used to perform register timing processing on the input debug signal; The signal splitting module is used to split the debugging signal processed by the register stamping module into a first debugging signal and a second debugging signal according to preset address information or flag information. The first debugging signal is used for internal debugging of the current module to be debugged, and the second debugging signal is used as a debugging output, so that the debugging output of the current module to be debugged is connected to the debugging path entrance of the next module to be debugged, so as to form a continuous distributed debugging network.
2. The distributed debugging architecture for a system-on-a-chip (SoC) chip according to claim 1, characterized in that: The register timing module uses an APB synchronizer to interrupt the transmission path by registering one APB signal.
3. The distributed debugging architecture for a system-on-a-chip (SoC) according to claim 1, characterized in that: The signal splitting module uses an APB 1 to 2 bridge to route the input APB transaction to the internal APB interface corresponding to the first debugging signal or to the output APB interface corresponding to the second debugging signal, based on the address decoding.
4. The distributed debugging architecture for a system-on-a-chip (SoC) according to claim 1, characterized in that: It also includes a debug port module, which is used to convert between the external debug interface protocol and the internal debug bus protocol.
5. The distributed debugging architecture for a system-on-a-chip (SoC) according to claim 4, characterized in that: The debug port module uses a TAP controller, the external debug interface protocol is the JTAG protocol, and the internal debug bus protocol is the APB protocol.
6. The distributed debugging architecture for a system-on-a-chip (SoC) according to claim 1, characterized in that: The debug chain logic unit is connected to the module to be debugged via an APB bus.
7. A debugging method for a distributed debugging architecture of a system-on-a-chip (SoC), characterized in that... The process includes the following steps: S1. An external debugger generates debug commands and inputs them into the SOC chip; S2. The debug commands are passed step by step in the distributed debug network. When a debug chain logic unit inside a module to be debugged receives a debug command: S2-1. The input debug signal is processed by a register stamping module; S2-2. The debug signal processed by the register stamping module is divided into a first debug signal and a second debug signal by a signal splitting module. The current module to be debugged performs internal debugging operations based on the first debug signal and outputs the second debug signal to the next module to be debugged. S3. Repeat step S2 until the debugging command reaches the target debugging module and completes the debugging operation; S4. After the module being debugged completes the debugging operation, the debugging data results are returned to the external debugger step by step through the distributed debugging network along the path opposite to the path of the debugging command.
8. The debugging method for a distributed debugging architecture of a system-on-a-chip (SoC) according to claim 7, characterized in that: In step S1, the external debugger is connected to the SOC chip via the JTAG interface; in step S2, the SOC chip first converts the JTAG protocol into the APB protocol through the debug port module, and then connects the debug commands to the distributed debug network through the APB bus; in step S4, the debug port module converts the debug data results returned by the APB bus into the JTAG protocol and transmits them to the external debugger through the TDO signal.