SPI communication method, device and system in embedded system, medium and product

Abstract

The embodiment of the invention discloses an SPI (Serial Peripheral Interface) communication method, device and system in an embedded system, a medium and a product, and the method comprises the following steps: after the embedded system is powered on and started, carrying out initialization configuration on a general timer module GTM through a main core in an MCU (Microprogrammed Control Unit), and establishing a mapping relation between a target input / output channel in the GTM and a target GPIO (General Purpose Input / Output) pin in the MCU; wherein a standard SPI communication connection is established between the target GPIO pin and the target slave device; copying the executable SPI drive code into a static random access memory distributed by an MCS (Modulation and Coding Scheme) sub-module of the GTM; and triggering the MCS sub-module to execute the SPI drive code, so that the GTM replaces the main core in the MCU to perform SPI communication with the target slave device. According to the technical scheme provided by the invention, the computing power of the main CPU of the microcontroller can be saved under the condition of ensuring efficient communication between the MCU and the SPI peripheral.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to an SPI communication method, apparatus, system, medium and product in an embedded system. Background Technology

[0002] In the field of embedded systems, the Serial Peripheral Interface (SPI) has become one of the mainstream communication methods for data exchange between microcontroller units (MUCs) and external slave devices such as sensors, memory, and communication modules due to its advantages such as simple protocol, full-duplex operation, and high speed. With the rapid development of applications such as the Internet of Things, automotive electronics, and industrial control, the number of SPI devices that embedded systems need to connect to is increasing daily, and the requirements for communication speed and real-time performance are constantly improving.

[0003] In existing technologies, SPI communication is mainly carried out through the main CPU (also referred to as cpu0) of the MCU in the embedded system. In high-speed SPI communication scenarios, the main CPU bears a huge burden due to the need to continuously process the underlying protocol. The computing power of the main CPU is heavily occupied, which leads to a decline in the overall system performance and affects the real-time response and processing capabilities of other critical tasks. Summary of the Invention

[0004] This invention provides an SPI communication method, device, system, medium, and product in an embedded system. Through the technical solution of the embodiments of this invention, the main CPU computing power of the microcontroller can be saved while ensuring efficient communication between the MCU and the SPI peripheral.

[0005] In a first aspect, embodiments of the present invention provide an SPI communication method in an embedded system, characterized by comprising:

[0006] After the embedded system is powered on, the main core in the MCU initializes and configures the GTM (Generic Timer Module) to establish the mapping relationship between the target input / output channels in the GTM and the target GPIO (General-Purpose Input / Output) pins in the MCU.

[0007] In this process, a standard SPI communication connection is established between the target GPIO pin and the target slave device.

[0008] Copy the executable SPI driver code to the static random access memory allocated to the MCS (Multi-Channel Sequencer) submodule of the GTM;

[0009] The MCS submodule is triggered to execute the SPI driver code, so that the GTM can replace the master core in the MCU to communicate with the target slave device via SPI.

[0010] Secondly, embodiments of the present invention provide an SPI communication device in an embedded system, comprising:

[0011] The mapping module is used to initialize and configure the GTM through the main core in the MCU after the embedded system is powered on and started, and to establish the mapping relationship between the target input / output channels in the GTM and the target GPIO pins in the MCU.

[0012] In this process, a standard SPI communication connection is established between the target GPIO pin and the target slave device.

[0013] The allocation module is used to copy the executable SPI driver code to the static random access memory allocated by the MCS submodule of the GTM.

[0014] The execution module is used to trigger the MCS submodule to execute the SPI driver code so that the GTM can replace the master core in the MCU to communicate with the target slave device via SPI.

[0015] Thirdly, embodiments of the present invention provide an embedded system, the embedded system including: a microcontroller MCU and multiple slave devices that establish a standard SPI communication connection with the MCU;

[0016] The MCU is used to implement the SPI communication method in the embedded system according to any one of the embodiments of the present invention.

[0017] Fourthly, embodiments of the present invention provide a computer-readable storage medium, characterized in that the computer-readable storage medium stores computer instructions, which are used to cause a processor to execute and implement the SPI communication method in the embedded system described in any one of the embodiments of the present invention.

[0018] Fifthly, embodiments of the present invention provide a computer program product, the computer program product including a computer program, which, when executed by a processor, implements the SPI communication method in an embedded system as described in any one of the embodiments of the present invention.

[0019] This invention provides an SPI communication method, apparatus, system, medium, and product in an embedded system. The method includes: after the embedded system powers on, initializing and configuring the Gaussian Transmission Module (GTM) through the main core in the MCU, establishing a mapping relationship between the target input / output channels in the GTM and the target GPIO pins in the MCU; wherein a standard SPI communication connection is established between the target GPIO pins and the target slave device; copying executable SPI driver code to the static random access memory allocated to the MCS submodule of the GTM; and triggering the MCS submodule to execute the SPI driver code, so that the GTM replaces the main core in the MCU to perform SPI communication with the target slave device. Specifically, by initializing and configuring the GTM, SPI communication with the target slave device can be achieved through the MCS submodule. Therefore, the method of this invention can save the main CPU computing power of the microcontroller while ensuring efficient communication between the MCU and the SPI peripheral. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart of an SPI communication method in an embedded system provided in Embodiment 1 of the present invention;

[0022] Figure 2 This is a flowchart of the SPI communication method in an embedded system provided in Embodiment 2 of the present invention;

[0023] Figure 3 This is a schematic diagram of the structure of an SPI communication device in an embedded system according to Embodiment 3 of the present invention;

[0024] Figure 4 This is a schematic diagram of the structure of an electronic device provided in Embodiment 4 of the present invention. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0027] It should be noted that the collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in the technical solution disclosed herein all comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0028] Example 1

[0029] Figure 1 This is a flowchart of an SPI communication method in an embedded system provided in Embodiment 1 of the present invention. The method is specifically applicable to the case of SPI peripheral communication through the MCS submodule of the MCU. The method can be executed by an SPI communication device in an embedded system, which can be composed of software and / or hardware and configured in the MCU of the embedded system.

[0030] like Figure 1 As shown, the method includes:

[0031] Step 110: After the embedded system is powered on, the GTM is initialized and configured by the main core in the MCU, and the mapping relationship between the target input / output channels in the GTM and the target GPIO pins in the MCU is established; among them, a standard SPI communication connection is established between the target GPIO pins and the target slave device.

[0032] The embedded system includes an MCU and multiple slave devices that establish a standard SPI communication connection with the MCU. The MCU is the core chip of the embedded system, which integrates a processor core (main core), memory, and various input / output interfaces and dedicated function modules, such as GTM.

[0033] A slave device can be understood as a hardware component in an embedded system that connects to an MCU via the SPI communication protocol and is controlled by the MCU to perform a specific function. For example, the slave device can be various sensors, actuators, flash memory, and display driver chips.

[0034] Generally, embedded systems often have a large number of slave devices configured using the SPI communication protocol. If these slave devices all communicate and process data through the MCU's master core, it will significantly impact the MCU's computing power. Therefore, we consider using the GTM (Genius Controller) within the MCU to replace the MCU's master core, enabling SPI communication processing for one, several, or even all slave devices in the embedded operating system. Correspondingly, the slave devices selected from all slave devices and controlled by the GTM for SPI communication are the target slave devices.

[0035] In this embodiment, the number of target slave devices controlled by the GTM for data communication can be preset based on the number of input / output channels remaining after the GTM completes its existing functions in the embedded system. This embodiment does not limit this number. Generally, when the GTM performs SPI communication control on a target slave device, it needs to use one input channel and three output channels. Subsequently, for each new target slave device controlled, a new output channel (for the corresponding chip select signal) needs to be added.

[0036] The main core is the central processing unit core in the MCU. In the prior art, the main core generally bears the computational load of SPI communication. Therefore, it is necessary to use the method of the embodiment of the present invention to delegate part or all of the SPI communication work to the MCS sub-module in order to reduce the computational load of the main core.

[0037] The GTM is used for parsing the SPI communication protocol and processing actual data. The GTM includes at least one MCS submodule, which is used to execute SPI driver code and complete communication tasks.

[0038] The initial configuration of GTM refers to the process by which the main core sets the parameters of the GTM module through software after the system is powered on. This includes configuring its input / output channels, clock source, and operating mode, so that it is ready to replace the main core in performing SPI communication tasks.

[0039] GPIO pins are physical pins in an MCU that can be programmably controlled to function as digital inputs or digital outputs. In various embodiments of this invention, specific GPIO pins are used as signal lines for chip select, clock, master output, slave input, master input, and slave output required for SPI communication.

[0040] Specifically, after the system powers on, the main core initializes the GTM, mapping its four internal dedicated hardware channels to designated external GPIO pins. These GPIO pins are then connected to the slave device's SPI interface via hardware. This method establishes the hardware link for SPI communication.

[0041] Step 120: Copy the executable SPI driver code to the static random access memory allocated by the MCS submodule of the GTM.

[0042] Specifically, the SPI driver code is executable machine code that implements the SPI communication timing and logic. It defines how to control the chip select, clock, and voltage levels, etc. The SPI driver code is executed by the MCS submodule to complete the SPI communication operation. It should be noted that SPI communication requires some memory space. Therefore, the size of the Static Random-Access Memory (SRAM) needs to be preset according to the SPI communication requirements for the storage and execution of the SPI driver code.

[0043] Optionally, before copying the executable SPI driver code to the static random access memory allocated to the MCS submodule of the GTM, the process may further include: initializing the configuration of the static random access memory for the MCS submodule in the GTM through the master core, and clearing the existing data in the static random access memory.

[0044] Step 130: Trigger the MCS submodule to execute the SPI driver code so that the GTM can replace the master core in the MCU to communicate with the target slave device via SPI.

[0045] Specifically, by controlling the MCS submodule to execute the SPI driver code, the target slave device and the master device can perform SPI communication.

[0046] Optionally, the number of target slave devices is one or more, and the target slave devices are selected from the embedded system and have an SPI communication rate greater than a preset rate threshold.

[0047] Specifically, since this method supports SPI communication between the master device and multiple slave devices, and the higher the communication rate, the greater the consumption of computing resources, slave devices with SPI communication rates exceeding a preset threshold can be identified as target slave devices, and this method can be used to implement SPI communication between them and the master device, thereby allocating system resources more rationally and improving overall operating efficiency.

[0048] This invention provides an SPI communication method for an embedded system. The method includes: after the embedded system powers on, initializing and configuring the Gaussian Transmission Module (GTM) through the main core of the MCU, establishing a mapping relationship between the target input / output channels in the GTM and the target GPIO pins in the MCU; wherein a standard SPI communication connection is established between the target GPIO pins and the target slave device; copying executable SPI driver code to the static random access memory allocated by the MCS submodule of the GTM; and triggering the MCS submodule to execute the SPI driver code, so that the GTM replaces the main core of the MCU to perform SPI communication with the target slave device. Specifically, by initializing and configuring the GTM, SPI communication with the target slave device can be achieved through the MCS submodule. Therefore, the method of this invention can save the main CPU computing power of the microcontroller while ensuring efficient communication between the MCU and the SPI peripheral.

[0049] In an optional implementation of this embodiment, initializing and configuring the general-purpose timer module (GTM) via the main core in the MCU may include:

[0050] The main core initializes and configures the TIM channel in the GTM (Timer Input Module) so that the TIM channel can obtain data sent by the target device from the matched target GPIO pin;

[0051] The main core initializes and configures the first ATOM (Advanced Routing Unit-connected Timer Output Module) channel in the GTM ATOM, so that the first ATOM channel sends a chip select signal to the target slave device through the matched target GPIO pin;

[0052] The second ATOM channel in the ATOM of the GTM is initialized and configured by the main core so that the second ATOM channel sends a clock signal to the target slave device through the matched target GPIO pin;

[0053] The third ATOM channel in the ATOM of the GTM is initialized and configured by the main core so that the third ATOM channel can send data to the target slave device through the matched target GPIO pin.

[0054] Specifically, when the target slave device sends data to the MCU via the SPI bus, the TIM channel in the GTM automatically captures the data bit level from the bound target GPIO pin in real time and temporarily stores it inside the GTM. The first ATOM channel is used to precisely control the corresponding GPIO pin to output a high level (not selecting the slave device) or a low level (selecting the slave device), thereby initiating or ending an SPI communication transaction. The second ATOM channel can automatically and periodically toggle the corresponding GPIO level according to the baud rate set in the program, generating the precise clock pulse required for communication to synchronize the transmission and reception of each bit of data. The third ATOM channel outputs each bit of the data to be sent to the corresponding target GPIO pin sequentially according to the clock.

[0055] Furthermore, the essence of the above configuration is to map the four physical signal lines required by the SPI protocol to four dedicated hardware channels within the GTM: the chip select signal (CS) is controlled by the first ATOM channel; the serial clock (SCLK) is generated by the second ATOM channel; the master output / slave input (MasterOut, SlaveIn) is driven by the third ATOM channel; and the master input / slave output (MISO, MasterIn, SlaveOut) is captured by the TIM channel. At this point, the GTM possesses all the hardware interfaces and capabilities required to independently complete SPI communication.

[0056] Example 2

[0057] Figure 2 This is a flowchart of an SPI communication method in an embedded system provided in Embodiment 2 of the present invention. Based on the above embodiment, this method further defines the implementation of each step of the SPI communication method in the embedded system.

[0058] like Figure 2 As shown, the method may specifically include:

[0059] Step 201: After the embedded system is powered on, the GTM is initialized and configured by the main core in the MCU, and the mapping relationship between the target input / output channels in the GTM and the target GPIO pins in the MCU is established.

[0060] Step 202: Copy the executable SPI driver code to the static random access memory allocated by the MCS submodule of GTM.

[0061] Step 203: Trigger the MCS submodule to execute the SPI driver code.

[0062] Step 204: When it is necessary to send a frame of target data to the target slave device, the MCS submodule outputs bit 0 to the matched target GPIO through the first ATOM channel to send a low-level chip select signal to the target slave device.

[0063] Specifically, according to the SPI protocol, when the chip select signal (CS) is low (bit 0), it indicates that the master device has selected the slave device as the target slave device, and communication officially begins. Therefore, the MCS submodule outputs a digital 0 (low level) through the first ATOM channel to establish the communication relationship between the master device and the target slave device.

[0064] Step 205: The MCS submodule outputs bit 0 to the matched target GPIO through the second ATOM channel to send a low-level clock signal to the target slave device.

[0065] Step 206: Based on the set baud rate clock used for SPI communication, the MCS submodule delays and waits for the low-level time corresponding to the clock.

[0066] Specifically, the MCS submodule first outputs 0 through the second ATOM channel. Then, it calculates the delay duration (low-level time) based on the set SPI baud rate clock to ensure that the duration of each low level of the clock signal fully complies with the SPI protocol requirements, thereby ensuring data transmission efficiency.

[0067] Step 207: Following the order from high bit to low bit, the MCS submodule obtains a target bit from a frame of target data and outputs the target bit to the matching target GPIO through the third ATOM channel.

[0068] Specifically, the MCS submodule extracts the highest bit (target bit) to be sent from a frame of data to be sent in sequence, and outputs the value (0 or 1) of the bit to the target GPIO through the third ATOM channel.

[0069] Step 208: The MCS submodule outputs bit 1 to the matched target GPIO through the second ATOM channel to send a high-level clock signal to the target slave device.

[0070] Step 209: Based on the set baud rate clock used for SPI communication, the MCS submodule delays and waits for the high-level time corresponding to the clock.

[0071] Specifically, the MCS submodule first outputs 1 through the second ATOM channel. Then, it calculates the delay duration (high-level time) based on the set SPI baud rate clock to ensure that the duration of each high level of the clock signal fully complies with the SPI protocol requirements, thereby ensuring data transmission efficiency.

[0072] Step 210: After the MCS submodule outputs a high-level clock signal, it simultaneously reads the data sent by the target slave device through the TIM channel.

[0073] Specifically, after the clock goes high, the MCS submodule simultaneously reads the level state of the connected GPIO through the TIM channel. SPI is full-duplex communication; while the MCS submodule, acting as the master device, sends one bit of data, the target slave device is also sending back one bit of data. At this time, the master MCS submodule uses the stable period of the high clock level to sample and read the data bits sent by the target slave device. This step achieves synchronous data reception.

[0074] Step 211: Determine whether to send all bits in a frame of target data to the target slave device in sequence, and simultaneously receive all corresponding data from the target slave device: if yes, proceed to step 212; otherwise, return to step 205.

[0075] Specifically, the MCS submodule will repeat "prepare bits -> toggle clock -> sample bits" to process each bit in turn until all bits of a whole frame of data (e.g., 8 cycles corresponding to 8 bits of data) have been sent, and synchronously receive all bits returned by the target from the device.

[0076] Step 212: After completing the transmission of a frame of target data, the MCS submodule outputs bit 1 to the matched target GPIO through the first ATOM channel to send a high-level chip select signal to the target slave device, indicating that the transmission and reception of a frame of target data in SPI communication has been completed.

[0077] Specifically, after all bits of a data frame have been transmitted, the MCS submodule outputs a digital 1 (high level) through the first ATOM channel (CS line) to indicate that the master device has ended the current communication process with the target slave device.

[0078] Specifically, after completing the initial configuration of the hardware channel, the MCS submodule automatically controls the GTM module to transmit and receive one frame of SPI data with the target slave device by executing the SPI driver code. The process is as follows: First, the MCS submodule outputs bit 0 to the matched target GPIO through the first ATOM channel to send a low-level chip select signal to start communication. Then, the MCS submodule sets the output of the second ATOM channel to bit 0, causing the clock signal to enter a low-level state, and performs a low-level delay according to the set baud rate clock. Next, the MCS submodule obtains a target bit from the data frame to be transmitted in descending order of high bit and outputs it through the third ATOM channel. Afterwards, the MCS submodule flips the output of the second ATOM channel to bit 1 to generate a rising edge of the clock and performs a high-level delay; after the clock goes high, the MCS submodule simultaneously reads the data bits returned by the slave device through the TIM channel. The above process of outputting the clock, preparing data, flipping the clock, delaying, and reading data will be executed cyclically until all bits of a frame of target data have been sent sequentially and all data from the slave device has been received synchronously. Finally, the MCS submodule outputs bit 1 through the first ATOM channel to set the chip select signal high, marking the end of this frame data transmission. Optionally, based on the actual communication requirements with the target slave device, the transmission and reception process of the target frame data can be executed cyclically to complete the required SPI communication data transmission and reception.

[0079] This invention maps SPI pins to the ATOM and TIM channels of the GTM and executes driver code via the MCS submodule, replacing the main core's direct control of GPIO pins. The method in this embodiment allows for flexible expansion of the virtual SPI interface, saving the microcontroller's main CPU computing power while ensuring efficient communication between the MCU and SPI peripherals.

[0080] Example 3

[0081] Figure 3 This is a schematic diagram of the structure of an SPI communication device in an embedded system according to Embodiment 3 of the present invention. Figure 3 As shown, the device includes:

[0082] The mapping module 310 is used to initialize and configure the GTM through the main core in the MCU after the embedded system is powered on and started, and to establish the mapping relationship between the target input / output channels in the GTM and the target GPIO pins in the MCU.

[0083] In this process, a standard SPI communication connection is established between the target GPIO pin and the target slave device.

[0084] Allocation module 320 is used to copy executable SPI driver code to the static random access memory allocated by the MCS submodule of GTM;

[0085] The execution module 330 is used to trigger the MCS submodule to execute the SPI driver code so that the GTM can replace the master core in the MCU to communicate with the target slave device via SPI.

[0086] This invention provides an SPI communication device for an embedded system. After the embedded system powers on, the device initializes and configures the Gateway Transmission Module (GTM) via the MCU's master core, establishing a mapping between the target input / output channels in the GTM and the target GPIO pins in the MCU. A standard SPI communication connection is established between the target GPIO pins and the target slave device. Executable SPI driver code is copied to the static random access memory allocated to the GTM's MCS submodule. The MCS submodule is then triggered to execute the SPI driver code, enabling the GTM to replace the MCU's master core in performing SPI communication with the target slave device. Specifically, by initializing and configuring the GTM, SPI communication with the target slave device can be achieved through the MCS submodule. Therefore, this invention's device can save the microcontroller's main CPU computing power while ensuring efficient communication between the MCU and the SPI peripheral.

[0087] Optionally, the mapping module 310 includes:

[0088] The first mapping unit is used to initialize and configure the TIM channel in the TIM of GTM through the main core, so that the TIM channel can obtain the data sent by the target device from the matched target GPIO pin;

[0089] The second mapping unit is used to initialize and configure the first ATOM channel in the ATOM of GTM through the main core, so that the first ATOM channel sends a chip select signal to the target slave device through the matched target GPIO pin;

[0090] The third mapping unit is used to initialize and configure the second ATOM channel in the ATOM of GTM through the main core, so that the second ATOM channel sends a clock signal to the target slave device through the matched target GPIO pin;

[0091] The fourth mapping unit is used to initialize and configure the third ATOM channel in the ATOM of the GTM through the main core, so that the third ATOM channel can send data to the target slave device through the matched target GPIO pin.

[0092] Optionally, the allocation module 320 is further configured to: initialize and configure static random access memory for the MCS submodule in GTM through the main core, and clear the existing data in the static random access memory.

[0093] Optionally, execution module 330 includes:

[0094] The chip select unit is used to send a low-level chip select signal to the target slave device when a frame of target data needs to be sent to the target slave device. The MCS submodule outputs bit 0 to the matched target GPIO through the first ATOM channel.

[0095] The low-level transmission unit is used by the MCS submodule to output bit 0 to the matched target GPIO through the second ATOM channel in order to send a low-level clock signal to the target slave device.

[0096] The low-level delay clock unit is used to delay the low-level time corresponding to the clock according to the set baud rate clock used in SPI communication.

[0097] The data transmission unit is used to obtain a target bit from a frame of target data in order from the most significant bit to the least significant bit, and output the target bit to the matching target GPIO through the third ATOM channel.

[0098] The high-level transmission unit is used by the MCS submodule to output bit 1 to the matched target GPIO through the second ATOM channel in order to send a high-level clock signal to the target slave device.

[0099] The high-level delay clock unit waits for the corresponding high-level time of the clock according to the set baud rate clock used in SPI communication;

[0100] The data reading unit is used to read the data sent by the target slave device through the TIM channel when the MCS submodule outputs a high-level clock signal;

[0101] The loop unit is used to return to the operation of the execution MCS submodule outputting bit 0 to the matched target GPIO through the second ATOM channel to send a low-level clock signal to the target slave device, until all bits in a frame of target data are sent to the target slave device in sequence, and at the same time all corresponding data are received from the target slave device.

[0102] The termination unit is used to output bit 1 to the matched target GPIO through the first ATOM channel after the complete transmission of a frame of target data is completed, so as to send a high-level chip select signal to the target slave device, indicating that the transmission and reception of a frame of target data in SPI communication has been completed.

[0103] Optionally, the execution module 330 is also used to cyclically execute the transmission and reception process of the target data frame according to the actual communication needs with the target slave device, so as to complete the transmission and reception of the required SPI communication data.

[0104] Optionally, the number of target slave devices is one or more, and the target slave devices are selected from the embedded system and have an SPI communication rate greater than a preset rate threshold.

[0105] The SPI communication device in the embedded system provided in the embodiments of the present invention can execute the SPI communication method in the embedded system provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of executing the method.

[0106] Example 4

[0107] Figure 4 A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0108] like Figure 4 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0109] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0110] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, digital signal processors (DSPs), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as SPI communication methods in embedded systems.

[0111] That is, after the embedded system is powered on and started, the main core in the MCU initializes and configures the GTM, and establishes the mapping relationship between the target input / output channels in the GTM and the target GPIO pins in the MCU.

[0112] In this process, a standard SPI communication connection is established between the target GPIO pin and the target slave device.

[0113] Copy the executable SPI driver code to the static random access memory allocated by the MCS submodule of the GTM;

[0114] The MCS submodule is triggered to execute the SPI driver code, so that the GTM can replace the master core in the MCU to communicate with the target slave device via SPI.

[0115] In some embodiments, the SPI communication method in the embedded system may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or mounted on the electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the SPI communication method in the embedded system described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to execute the SPI communication method in the embedded system by any other suitable means (e.g., by means of firmware).

[0116] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include: implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0117] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0118] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0119] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0120] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0121] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0122] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and no limitation is imposed herein.

[0123] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A serial peripheral interface (SPI) communication method in an embedded system, characterized in that, include: After the embedded system is powered on, the main core in the MCU initializes and configures the general-purpose timer module (GTM) to establish the mapping relationship between the target input / output channels in the GTM and the target general-purpose input / output (GPIO) pins in the MCU. In this process, a standard SPI communication connection is established between the target GPIO pin and the target slave device. Copy the executable SPI driver code to the static random access memory allocated to the GTM multichannel sequencer MCS submodule; The MCS submodule is triggered to execute the SPI driver code, so that the GTM can replace the master core in the MCU to communicate with the target slave device via SPI.

2. The method according to claim 1, characterized in that, The general-purpose timer module (GTM) is initialized and configured via the main core of the MCU, including: The TIM channel in the timing input module TIM in GTM is initialized and configured by the main core so that the TIM channel can obtain the data sent by the target device from the matched target GPIO pin; The first ATOM channel in the timer output module ATOM connected to the advanced routing unit in the GTM is initialized and configured by the main core so that the first ATOM channel sends a chip select signal to the target slave device through the matched target GPIO pin; The second ATOM channel in the ATOM of the GTM is initialized and configured by the main core so that the second ATOM channel sends a clock signal to the target slave device through the matched target GPIO pin; The third ATOM channel in the ATOM of the GTM is initialized and configured by the main core so that the third ATOM channel can send data to the target slave device through the matched target GPIO pin.

3. The method according to claim 1, characterized in that, Before copying the executable SPI driver code to the static random access memory allocated to the GTM's MCS submodule, the following is also included: The main core initializes and configures the static random access memory (SRAM) for the MCS submodule in GTM, and clears the existing data in the SRAM.

4. The method according to claim 1, characterized in that, Trigger the MCS submodule to execute the SPI driver code, so that the GTM can replace the master core in the MCU to communicate with the target slave device via SPI, including: When it is necessary to send a frame of target data to the target slave device, the MCS submodule outputs bit 0 to the matched target GPIO through the first ATOM channel to send a low-level chip select signal to the target slave device. The MCS submodule outputs bit 0 to the matched target GPIO through the second ATOM channel to send a low-level clock signal to the target slave device. Based on the set baud rate clock used in SPI communication, the MCS submodule delays and waits for the low-level time corresponding to the clock. Following the order from high bit to low bit, the MCS submodule obtains a target bit from a frame of target data and outputs the target bit to the matching target GPIO through the third ATOM channel. The MCS submodule outputs bit 1 to the matched target GPIO through the second ATOM channel to send a high-level clock signal to the target slave device; Based on the set baud rate clock used in SPI communication, the MCS submodule delays and waits for the high-level time corresponding to the clock. When the MCS submodule outputs a high-level clock signal, it simultaneously reads the data sent by the target device through the TIM channel; The MCS submodule returns to the operation of sending a low-level clock signal to the target slave device by outputting bit 0 to the matched target GPIO through the second ATOM channel, until all bits in a frame of target data are sent to the target slave device in sequence, and at the same time, all corresponding data is received from the target slave device. After completing the transmission of a frame of target data, the MCS submodule outputs bit 1 to the matched target GPIO through the first ATOM channel to send a high-level chip select signal to the target slave device, indicating that the transmission and reception of a frame of target data in SPI communication has been completed.

5. The method according to claim 4, characterized in that, The method further includes: Based on the actual communication requirements with the target slave device, the process of sending and receiving one frame of target data is executed cyclically to complete the required SPI communication data transmission and reception.

6. The method according to any one of claims 1-5, characterized in that, The number of target slave devices is one or more, and the target slave devices are selected from the embedded system and have an SPI communication rate greater than a preset rate threshold.

7. A serial peripheral interface (SPI) communication device for an embedded system, characterized in that, include: The mapping module is used to initialize and configure the general-purpose timer module GTM through the main core in the MCU after the embedded system is powered on and started, and to establish the mapping relationship between the target input / output channels in GTM and the target general-purpose input / output GPIO pins in the MCU. In this process, a standard SPI communication connection is established between the target GPIO pin and the target slave device. The allocation module is used to copy the executable SPI driver code to the static random access memory allocated by the GTM multichannel sequencer MCS submodule; The execution module is used to trigger the MCS submodule to execute the SPI driver code so that the GTM can replace the master core in the MCU to communicate with the target slave device via SPI.

8. An embedded system, characterized in that, The embedded system includes: a microcontroller (MCU) and multiple slave devices that establish a standard SPI communication connection with the MCU; The MCU is used to implement the SPI communication method of the embedded system as described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by a processor, implement the Serial Peripheral Interface (SPI) communication method in the embedded system according to any one of claims 1-6.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the SPI communication method for embedded systems according to any one of claims 1-6.

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