Data transmission method and device of network on chip, routing node and storage medium

Abstract

The embodiment of the application discloses a data transmission method and device of a network on chip, a routing node and a storage medium, wherein the method comprises the following steps: in the case that a data packet sent by an upstream routing node is received from a target input direction, confirming a target output direction of the data packet; writing the data packet into a target steering register corresponding to the target input direction and the target output direction, or sending a retransmission signal for the data packet to the upstream routing node; sending the data packet to a downstream routing node of the target output direction through the target steering register, and temporarily storing the data packet in the target steering register or a target backup register corresponding to the target output direction before confirming that the downstream routing node receives the data packet; in the case that a retransmission signal sent by the downstream routing node for the data packet is received, sending the data packet from the target backup register or the target steering register to the downstream routing node.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of on-chip network technology, and in particular to a data transmission method, apparatus, routing node, and storage medium for on-chip networks. Background Technology

[0002] With the rapid development of multi-core processors and Network-on-Chip (NoC) technology, efficient data communication has become crucial for improving system performance. NoC uses routers to temporarily store and transmit data packets, and the flow control methods of these routers directly impact communication efficiency, latency, and resource utilization.

[0003] In existing technologies, credit-based flow control is commonly used as the mainstream flow control method for on-chip networks. Credit-based flow control manages buffer resources through a credit mechanism, but still requires downstream configuration of a large buffer to ensure uninterrupted packet flow during routing. However, this scheme requires upstream routing nodes to send buffered data packets to downstream routing nodes only when there is space in the downstream routing node's buffer. If the downstream routing node does not have space for a long time, it will cause head-of-line blocking problems for upstream routing nodes. That is, when a data packet cannot proceed due to resource occupation, it will block subsequent data packets that could have been transmitted, causing congestion for upstream routing nodes to be unable to accept new data packets, which seriously affects network communication performance. Summary of the Invention

[0004] In view of this, embodiments of this application provide at least one data transmission method, apparatus, routing node, and storage medium for a network-on-a-chip.

[0005] The technical solution of this application embodiment is implemented as follows:

[0006] On one hand, embodiments of this application provide a data transmission method for an on-chip network, applied to a routing node in the on-chip network. The routing node has multiple redirection registers for different output directions in each input direction, and a backup register in each output direction. The method includes:

[0007] Upon receiving a data packet sent by an upstream routing node from the target input direction, the target output direction of the data packet is confirmed.

[0008] Based on the storage state of the target steering register corresponding to the target input direction and the target output direction, the data packet is written into the target steering register, or a retransmission signal for the data packet is sent to the upstream routing node;

[0009] The data packet is sent to the downstream routing node in the target output direction through the target steering register, and the data packet is temporarily stored in the target steering register or the target backup register corresponding to the target output direction before the downstream routing node is confirmed to have received the data packet.

[0010] Upon receiving a retransmission signal from the downstream routing node for the data packet, the data packet is sent from the target backup register or the target redirection register to the downstream routing node.

[0011] On the other hand, embodiments of this application provide another data transmission method for on-chip networks, applied to routing nodes in an on-chip network. The routing node has multiple redirection registers for different output directions in each input direction, and a backup register in each output direction. The method includes:

[0012] The processing module is used to determine the target output direction of the data packet when it receives a data packet sent by an upstream routing node from the target input direction;

[0013] The transmission module is configured to: write the data packet into the target redirection register or send a retransmission signal for the data packet to the upstream routing node according to the storage state of the target redirection register corresponding to the target input direction and the target output direction; send the data packet to the downstream routing node in the target output direction through the target redirection register, and temporarily store the data packet in the target redirection register or the target backup register corresponding to the target output direction before confirming that the downstream routing node has received the data packet; and, upon receiving a retransmission signal for the data packet from the downstream routing node, send the data packet from the target backup register or the target redirection register to the downstream routing node.

[0014] In another aspect, embodiments of this application provide a routing node, the routing node comprising: a processor, a plurality of redirection registers for different output directions in each input direction, and a backup register in each output direction, wherein the processor executes the program to implement some or all of the steps in the above-described on-chip network data transmission method.

[0015] In another aspect, embodiments of this application provide a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements some or all of the steps in the above-described data transmission method for a network-on-a-chip.

[0016] In another aspect, embodiments of this application provide a computer program including computer-readable code. When the computer-readable code is run in a routing node, the processor in the routing node executes some or all of the steps in the above-described data transmission method for implementing a network-on-a-chip.

[0017] In another aspect, embodiments of this application provide a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described data transmission method for a network-on-a-chip.

[0018] This application embodiment sets corresponding redirection registers and backup registers for each output direction of the current routing node to transmit and back up received data packets. This allows the current routing node to back up data packets locally before they are successfully sent to downstream routing nodes, so that they can be resent to downstream routing nodes. This avoids the problem of data interruption caused by downstream data nodes being unable to receive data. For data packets that the current routing node cannot successfully receive, a retransmission signal can be sent to the upstream routing node to make the upstream routing node resend the data packets. This retransmission mechanism does not require setting up a buffer queue in the current routing node. Therefore, while avoiding the head blocking problem, it ensures uninterrupted data communication between routing nodes.

[0019] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of this application. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application.

[0021] Figure 1 A schematic diagram illustrating the implementation flow of a data transmission method for an on-chip network provided in an embodiment of this application;

[0022] Figure 2 A schematic diagram illustrating the composition structure of a routing node provided in an embodiment of this application;

[0023] Figure 3 A schematic diagram of data transmission method for an on-chip network provided in an embodiment of this application;

[0024] Figure 4 A system transmission diagram illustrating a data transmission method for an on-chip network provided in this application embodiment;

[0025] Figure 5A schematic diagram illustrating the composition of a data transmission device for an on-chip network provided in an embodiment of this application;

[0026] Figure 6 This is a schematic diagram of the hardware entity of a routing node provided in an embodiment of this application. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0029] The terms “first / second / third” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first / second / third” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used herein is for descriptive purposes only and is not intended to be limiting of this application.

[0031] This application provides a data transmission method for a network-on-a-chip (NIC). The method is applied to a routing node in the NIC. The routing node has multiple redirection registers for different output directions in each input direction, and a backup register in each output direction. Figure 1 This is a schematic diagram illustrating the implementation flow of a data transmission method for an on-chip network provided in an embodiment of this application, as shown below. Figure 1 As shown, the method includes:

[0032] Step 101: If a data packet sent by an upstream routing node is received from the target input direction, confirm the target output direction of the data packet.

[0033] In this application embodiment, network-on-chip (NoC) is a novel communication method for System-on-Chip (SoC). As a key component of multi-core technology, it achieves concurrent communication through distributed routing nodes and time-division multiplexing links, replacing the traditional bus architecture to solve scalability and performance bottlenecks. The slicing component is a hardware device located within the SoC and positioned between routing nodes, possessing at least data processing, data transmission, and data storage functions.

[0034] A data packet is a data unit transmitted in an on-chip network, containing routing information and payload content. An upstream routing node is the node preceding the current routing node and is responsible for sending data packets. The destination input direction is the physical direction in which the data packet enters the current routing node, such as west or north. The destination output direction is the physical direction in which the data packet leaves the current routing node, determined by the routing algorithm. For example, based on an XY routing algorithm, the packet might change from west to east.

[0035] Reference Figure 2 The execution subject of this application embodiment is Figure 2 In the context of routing node 2, if the sender of the data packet is routing node 1, then routing node 1 is the upstream routing node; if the receiver of the data packet is routing node 3, then routing node 3 is the downstream routing node; and if the receiver of the data packet is routing node 4, then routing node 4 is the downstream routing node. In other words, upstream and downstream routing nodes do not refer to any specific fixed routing node, but rather to the direction of data transmission. An upstream routing node means the routing node that sends the data packet to the slicing component, while a downstream routing node means the routing node that needs the slicing component to send the packet.

[0036] When a current routing node receives a data packet from an upstream routing node in the destination input direction, it first parses the routing information in the packet. The routing node calculates the next transmission direction of the data packet, i.e., the destination output direction, based on a predefined routing algorithm, such as XY routing. This process involves extracting the routing field from the packet header and performing calculations through logic circuits or processing units to ensure the packet can be correctly forwarded to the next-hop node. After the calculation is complete, the current routing node associates the destination output direction with the data packet and stores it for use in subsequent processing steps.

[0037] Step 102: Based on the storage state of the target steering register corresponding to the target input direction and the target output direction, write the data packet into the target steering register, or send a retransmission signal for the data packet to the upstream routing node.

[0038] In this embodiment, the target redirection register is a logical storage unit in the input buffer of the routing node corresponding to a specific input and output direction, used to temporarily store data packets. The retransmission signal sent by the current routing node to the upstream routing node is an indication signal used to instruct the upstream routing node to retransmit the data packet at the next time node.

[0039] After receiving a data packet, the current routing node will check the current state of the destination redirection register. If the current state of the destination redirection register does not allow for writing data packets (e.g., the destination redirection register is not currently empty, meaning it stores data packets that need to be sent), the routing node cannot buffer the data packet at the current time. In this case, to ensure uninterrupted network communication with the upstream routing node, the current routing node can send a retransmission signal to the upstream routing node, instructing the upstream routing node to retransmit the data packet at the next time point. If the current state of the destination redirection register allows for writing data packets, then the data packet can be written to the destination redirection register.

[0040] Step 103: Send the data packet to the downstream routing node in the target output direction through the target redirection register, and temporarily store the data packet in the target redirection register or the target backup register corresponding to the target output direction before confirming that the downstream routing node has received the data packet.

[0041] In this embodiment, the target backup register is a storage unit in the routing node associated with a specific output direction, used to temporarily store copies of sent data packets in case retransmission is needed. The downstream routing node is the node following the current routing node and is responsible for receiving data packets.

[0042] The current routing node sends data packets to downstream routing nodes in the target output direction via the target redirection register. The sending process includes reading the packet from the redirection register, transmitting it through the output interface, and simultaneously, the current routing node temporarily stores the data packet in the target backup register or keeps it in the original redirection register. This mechanism is implemented through parallel hardware operations to ensure that a backup of the packet is available during transmission, preventing data loss due to downstream issues and supporting non-blocking communication.

[0043] Step 104: Upon receiving a retransmission signal from the downstream routing node for the data packet, send the data packet from the target backup register or the target redirection register to the downstream routing node.

[0044] In this embodiment, when the current routing node receives a retransmission signal from a downstream routing node, it retrieves the data packet from the target backup register or the target redirection register and retransmits it to the downstream node through the output interface. This process involves the coordination of signal detection, register access, and transmission logic to ensure that the packet can be retransmitted quickly without relying on the upstream routing node.

[0045] This application embodiment sets corresponding redirection registers and backup registers for each output direction of the current routing node to transmit and back up received data packets. This allows the current routing node to back up data packets locally before they are successfully sent to downstream routing nodes, so that they can be resent to downstream routing nodes. This avoids the problem of data interruption caused by downstream data nodes being unable to receive data. For data packets that the current routing node cannot successfully receive, a retransmission signal can be sent to the upstream routing node to make the upstream routing node resend the data packets. This retransmission mechanism does not require setting up a buffer queue in the current routing node. Therefore, while avoiding the head blocking problem, it ensures uninterrupted data communication between routing nodes.

[0046] In some embodiments, step 102 includes:

[0047] Step 1021: If the target steering registers corresponding to the target input direction and the target output direction meet the write conditions, the data packet is written into the target steering register.

[0048] In this embodiment of the application, the write condition is a logical rule defined by the routing node, used to determine whether the target redirection register can receive new packets, such as checking whether the redirection register is empty or meets a specific arbitration state.

[0049] The current routing node checks whether the destination redirection register meets the write conditions. This includes verifying whether the redirection register is free or meets other preset conditions, such as the arbitrator status. If the conditions are met, the current routing node writes the data packet from the input interface to the destination redirection register, and may update relevant pointers or status information. The write process is implemented through hardware logic to ensure that the packet is correctly stored in the buffer, preparing it for subsequent transmission. If the conditions are not met, the current routing node skips the write and triggers a subsequent retransmission mechanism.

[0050] Step 1022: If the target redirection register does not meet the write conditions, send a retransmission signal for the data packet to the upstream routing node.

[0051] In this embodiment, the retransmission signal sent by the current routing node to the upstream routing node is used to instruct the upstream routing node to retransmit the data packet, which is usually triggered when the target redirection register cannot receive the packet.

[0052] When the current routing node encounters a situation where the destination redirection register does not meet the write conditions, it generates a retransmission signal and sends it to the upstream routing node via the communication interface. The current routing node checks the status of the redirection register, such as whether it is occupied by other packets or if arbitration has failed, and then triggers the signal generation logic. The retransmission signal ensures that the upstream node can retransmit data packets in a timely manner, preventing data loss or network interruption.

[0053] In some embodiments, step 1021 includes:

[0054] Step 10211: If the target redirection register is empty, write the data packet into the target redirection register.

[0055] In this embodiment, the current routing node first checks if the destination redirection register is empty. If the destination redirection register is empty, the current routing node directly writes the data packet to the destination redirection register. The write operation includes storing the packet data in the destination redirection register and updating relevant pointers to maintain the linked list structure. The routing node ensures that the routing information of the data packet is correctly extracted and stored during the write process so that the next hop can be calculated subsequently. The current routing node allows the data packet to enter the buffer as soon as possible, avoiding delays caused by register occupancy, thereby supporting efficient data stream transmission.

[0056] Step 10212: If the target redirection register is not empty and the retransmission signal corresponding to the target redirection register is empty, the data packet is written into the target redirection register at the next time node.

[0057] In this embodiment, when the target redirection register is not empty, the current routing node further checks whether the corresponding retransmission signal is empty. If the retransmission signal is empty, the current routing node schedules the data packet to be written to the target redirection register at the next time node. The current routing node ensures that the write operation is performed in the next cycle through a timing control mechanism, while simultaneously updating the arbitrator pointer to reflect the new transmission state. This process avoids transmission interruptions caused by register occupancy. Through a delayed write strategy, it ensures that packets are processed immediately when the register becomes available, thereby maintaining the continuity of the data flow.

[0058] Step 10213: If the target direction register is not empty and the arbitrator corresponding to the target output direction receives only one output request, the data packet is written into the target direction register at the next time node.

[0059] In this embodiment, the arbitrator is a logical functional block of the routing node, responsible for selecting one from multiple data channel transmission requests to obtain an output channel authorization. An output request is a transmission request sent by a data packet to the arbitrator to compete for output resources. Receiving only one output request indicates that only one packet is requesting transmission in that output direction during the current period, simplifying the arbitration decision-making process.

[0060] When the destination redirection register is not empty, the current routing node checks whether the arbitrator corresponding to the destination output direction has received only one output request. If the condition is met, the current routing node schedules the data packet to be written to the destination redirection register at the next time node. The current routing node evaluates the contention state of the output request through the arbitrator logic, ensuring that packet writing is prioritized in a low-contention environment. This leverages parallel processing capabilities, avoids header blocking caused by multiple packet contention, and improves data transmission efficiency by optimizing resource allocation.

[0061] This application's embodiments ensure efficient data packet writing under various conditions by dynamically checking the target redirection register status and retransmission signal, combined with arbitrator logic. This eliminates head blocking, improves the communication efficiency of the on-chip network, and supports parallel data transmission under arbitrary topologies.

[0062] In some embodiments, step 1022 includes:

[0063] Step 10221: If the target redirection register is not empty and the retransmission signal corresponding to the target redirection register is not empty, send the retransmission signal of the data packet to the upstream routing node.

[0064] In this embodiment, the current routing node first checks if the target redirection register is empty. If the target redirection register is not empty, it further checks if the retransmission signal corresponding to the target redirection register is not empty, meaning there is a retransmission signal sent to the target redirection register by the downstream routing node at the previous time node. When both conditions are met, the current routing node generates a retransmission signal for the data packet and sends the signal to the upstream routing node. This process ensures that if the target redirection register is occupied and the retransmission signal is valid, the upstream routing node can retransmit the data packet in a timely manner, avoiding data loss or transmission interruption.

[0065] Step 10222: If the target routing register is not empty and there are at least two output requests from the arbitrator corresponding to the target output direction, send a retransmission signal for the data packet to the upstream routing node.

[0066] In this embodiment, the current routing node first checks if the target redirection register is empty. If the target redirection register is not empty, it further checks if there are at least two output requests in the arbitrator corresponding to the target output direction. When both conditions are met, the routing node generates a retransmission signal for the data packet and sends this signal to the upstream routing node. This is because the target redirection register can only send one data packet at a time. If there are two or more output requests in the arbitrator, it cannot be guaranteed that the target redirection register can send the data packet at the next time. This situation will cause the data packet to not be written to the target redirection register in time, leading to data congestion and data loss due to the data packet not being stored in time. This process ensures that the upstream routing node can retransmit the data packet when the target redirection register is occupied and there are multiple contention requests in the output direction, preventing transmission congestion and data loss.

[0067] This application embodiment achieves efficient data packet transmission control by dynamically monitoring the target redirection register and arbitrator status through downstream routing nodes and sending retransmission signals to upstream routing nodes. The current routing node can avoid head-blocking, ensuring uninterrupted data flow transmission in the on-chip network. Simultaneously, the retransmission mechanism improves communication reliability and parallel processing capabilities, making it suitable for various topologies and significantly enhancing the overall performance and efficiency of the on-chip network.

[0068] In some embodiments, step 103 includes:

[0069] Step 1031: Send an output request to the target arbitrator corresponding to the target output direction through the target steering register. The arbitrator is used to assign arbitration priority to the forwarding register corresponding to the target output direction for different input directions.

[0070] In this embodiment, the current routing node first generates an output request signal through a target redirection register. This output request signal contains the packet's routing information and redirection direction identifier. The target redirection register sends the output request to the target arbitrator, which receives request requests from multiple input directions (such as west and north). The target arbitrator evaluates the priority of each request based on its internal pointer state or preset arbitration rules (such as a polling mechanism) and assigns arbitration priority to eligible redirection registers. During the allocation process, the target arbitrator updates its pointer to point to the next candidate register, ensuring fairness and avoiding starvation. If the target redirection register obtains arbitration priority, the current routing node prepares to enter the packet transmission phase; otherwise, the target redirection register remains in a waiting state until it re-requests in a subsequent cycle. The entire process is completed within a single clock cycle, ensuring that the current routing node can efficiently handle parallel data streams and reduce transmission latency.

[0071] Step 1032: If the arbitrator assigns arbitration priority to the data packet, the data packet is sent to the downstream routing node through the target redirection register.

[0072] In this embodiment, after the target arbitrator assigns arbitration priority to the data packet, the current routing node immediately initiates the transmission process through the target redirection register. The target redirection register copies the data packet to a backup register for backup, and simultaneously transmits the packet to the downstream routing node through the output channel. During transmission, the current routing node monitors the feedback from the downstream routing node: if the downstream node successfully receives the packet, it will not return a retransmission signal; if the downstream node cannot receive the packet due to a full buffer or other reasons, it will send a retransmission signal in the next clock cycle. After receiving the retransmission signal, the current routing node retransmits the packet from the backup register to ensure uninterrupted transmission. After transmission is completed, if no retransmission signal is received, the current routing node discards the original packet in the redirection register and updates the arbitrator pointer; if a retransmission signal is received, the current routing node maintains its current state and repeats the transmission operation. This mechanism ensures the continuous flow of data packets in the on-chip network, avoiding header blocking and interruption problems.

[0073] This application's embodiments utilize a target redirection register to request output and an arbitrator to allocate priority, combined with a backup and retransmission mechanism in the backup register, to ensure efficient and continuous transmission of data packets in the on-chip network. This design eliminates head-blocking, allows for parallel processing of packets in multiple directions, and improves network throughput and communication efficiency.

[0074] In some embodiments, step 103 includes:

[0075] Step 1033: If the data packet is stored in the target redirection register and the target backup register is empty, transfer the data packet from the target redirection register to the target backup register.

[0076] In this embodiment, the current routing node first checks whether a data packet exists in the target redirection register and confirms whether the target backup register is empty. If the target backup register is empty, the current routing node copies the data packet from the target redirection register to the target backup register. The current routing node reads the contents of the target redirection register and writes the data to the target backup register, while updating relevant status flags to indicate that the backup operation is complete. The current routing node ensures the atomicity of data transmission, avoiding data corruption or conflicts during the transfer process.

[0077] Step 1034: If the data packet is stored in the target redirection register and the target backup register is not empty, the data packet is temporarily stored in the target redirection register.

[0078] In this embodiment, the current routing node first checks whether a data packet exists in the target redirection register and confirms whether the target backup register is not empty. If the target backup register is not empty, the routing node retains the data packet in the target redirection register without performing any transfer operation. The current routing node updates its internal state to indicate that the data packet in the target redirection register is in a waiting state and may trigger an arbitration mechanism to re-evaluate the output priority. This process ensures that data packets are not lost due to backup register occupancy while maintaining the stability of the transmission queue.

[0079] The embodiments of this application realize efficient data packet management and transmission control, ensuring timely backup of packets when the backup register is available, reducing the risk of transmission interruption, and maintaining packets in the redirection register when the backup register is occupied, thus avoiding data conflicts.

[0080] In some embodiments, step 104 includes: if no retransmission signal for the data packet is received from the downstream routing node at the next time node, confirming that the downstream routing node has received the data packet, and discarding the data packet in the target backup register or target redirection register.

[0081] In this embodiment, discarding is the process by which a routing node performs a clearing operation on data packets in a storage unit, releasing buffer resources for use by new packets.

[0082] During operation, the current routing node continuously monitors the communication interface from downstream routing nodes. When a retransmission signal for a specific data packet is detected, the routing node first parses the signal to identify the corresponding data packet identifier. Subsequently, the current routing node accesses the destination redirection register or the destination backup register to retrieve the stored original data packet. The current routing node re-encapsulates the data packet into a transmission frame through the output channel controller and activates the physical layer driver circuitry to send it to the downstream routing node. Throughout this process, the current routing node maintains its arbitrator state to ensure that subsequent packet scheduling is not affected, while the data in the backup register is retained until successful transmission confirmation.

[0083] The current routing node continuously monitors the response status of downstream routing nodes through a timer module and signal detection circuit. When no retransmission signal for a specific data packet is detected within a preset clock cycle, the current routing node determines that the packet has been successfully received downstream. The current routing node then triggers the storage management unit to execute a data clearing instruction on the target backup register or target redirection register. The clearing operation includes resetting the pointer state of the storage unit and releasing the occupied buffer capacity. Simultaneously, the current routing node updates the arbitrator pointer to the next pending packet position and sends a register availability notification to the resource allocation module, ensuring that subsequent packets can immediately use the storage resource.

[0084] This application implements a high-performance non-blocking data transmission mechanism. It eliminates the head-blocking problem in traditional flow control through a backup and retransmission mechanism, ensuring that data packets can still attempt transmission even when encountering downstream congestion. Furthermore, an intelligent drop-off strategy avoids wasting buffer resources and improves storage utilization efficiency. The combination of these two mechanisms enables routing nodes to maintain a constant throughput under various network load conditions. Simultaneously, by reducing latency and eliminating data interruptions, it significantly improves the parallel communication performance of on-chip networks in multi-core architectures.

[0085] In some embodiments, the method further includes:

[0086] Step 201: Count the number of retransmissions of the target backup register using a counter register.

[0087] In this embodiment, the counter register is a hardware register used to store and update values. In this step, it is specifically used to record the number of times the data packet in the target backup register has been retransmitted. The target backup register is a storage unit in the current routing node used to temporarily store copies of data packets. Its function is to retain the packet for retransmission if the downstream routing node fails to receive the data packet successfully. The retransmission count refers to the cumulative number of times the data packet stored in the target backup register has been retransmitted to the downstream routing node.

[0088] The current routing node uses a counter register to count the number of retransmissions of data packets in the target backup register. The counter register automatically increments its stored value each time a data packet in the target backup register is retransmitted. The current routing node continuously monitors the retransmission process to ensure the counter register accurately records the number of retransmissions, providing a data basis for subsequent determination of whether the livelock prevention mechanism has been triggered.

[0089] Step 202: If the number of retransmissions to the target backup register exceeds the threshold, a flag signal is sent to the downstream routing node. The flag signal is used to instruct the downstream routing node to refuse to receive other data packets before successfully receiving the data packet in the target backup register.

[0090] In this embodiment, the retransmission threshold is a preset numerical limit used to determine whether the number of retransmissions is too high, thereby triggering the livelock prevention mechanism. The marking signal is a control signal generated by the current routing node, used to notify downstream routing nodes to suspend receiving other data packets under specific conditions. The downstream routing node is the next processor in the data packet transmission path, responsible for receiving and forwarding data packets. A data packet is the basic information unit of transmission, containing routing information and a payload.

[0091] If a downstream routing node lacks available space to receive a data packet from its backup register for an extended period, it will repeatedly send retransmission signals to the backup register. The backup register will then repeatedly retransmit the data packet to the downstream routing node. This may cause the retransmission count recorded by the counter register to exceed a preset threshold. If the retransmission count exceeds the predicted number, the current routing node will automatically generate a marker signal and send it to the downstream routing node. Upon receiving this marker signal, the downstream routing node's output register will consider itself marked. After discarding previously written data packets, if it receives a transmission request for a data packet other than the one from the backup register, it will not write to it. Instead, the downstream routing node will send a retransmission signal to the current routing node. This process continues until the data packet from the current routing node's backup register is written into the downstream routing node's output register, at which point the downstream routing node's output register will be unlocked. In other words, upon receiving the marker signal, the downstream routing node adjusts its receiving logic, prioritizing the processing of retransmitted packets from the target backup register to ensure that the packet is not preempted by other packets. The current routing node uses this mechanism to prevent livelock and ensure successful data packet transmission.

[0092] This application embodiment automatically detects and handles retransmission exceeding limits for packets in the target backup register, ensuring that downstream routing nodes prioritize receiving critical packets and avoiding transmission stalls caused by resource contention. This improves the reliability and efficiency of data transmission in the on-chip network, while reducing hardware resource consumption and optimizing the overall performance of the current routing nodes.

[0093] In some embodiments, the method further includes:

[0094] Step 301: Add a number to the sent data packet.

[0095] In this embodiment of the application, the number is a unique sequence identifier assigned by the routing node to each data packet, used to distinguish different packets and support sequential tracking.

[0096] When a data packet enters the sending queue, the routing node automatically generates and appends an incrementing or unique number to the packet header. For example, if two data packets exist, they can be numbered 0 and 1 respectively. This number is implemented based on a hardware counter or sequence generator, ensuring that each packet has a unique identifier. The routing node stores the number in association with the packet metadata (such as routing direction and priority) and maintains the number during transmission to support identification and processing by downstream nodes.

[0097] Step 302: If all the data packets to be sent have been sent, the cached data packets are sent to the downstream routing nodes in a round-robin fashion according to the number order, wherein the number is used by the downstream routing nodes to perform deduplication on the data packets to be sent.

[0098] In this embodiment, polling refers to routing nodes cyclically checking and sending data packets in the buffer queue in a fixed order. Downstream routing nodes are adjacent routing nodes or processors that receive packets. Deduplication involves downstream nodes identifying and discarding duplicate packets based on their packet numbers to maintain data consistency.

[0099] The current routing node continuously monitors the sending queue status. When it detects that all new data packets have been sent, it automatically switches to buffered packet sending mode. The routing node reads packets sequentially from the buffer (such as an output register or backup register) in ascending order of their numbers and authorizes transmission to downstream routing nodes through an arbitrator. Upon receiving a packet, the downstream routing node parses its number and compares it with its local record: if the number already exists, the packet is discarded; if it is a new number, it is stored and processed. This process is implemented using a hardware comparator and a status register to ensure uninterrupted transmission and data integrity. It's worth noting that the numbering process for data packets is continuous, while the polling retransmission mechanism is only triggered when the current routing node has no data packets to send, i.e., during periods of low traffic. If new data packets continuously need to be sent, previously sent data packets will not be retransmitted.

[0100] For example, if the current routing node has successfully sent two data packets, numbered 0 and 1 respectively, then during the round-robin transmission, the data packets received by the downstream routing node will be numbered 0, 1, 0, 1... If there is only one data packet numbered 1, then the data packets received by the downstream routing node will be numbered 1, 1, 1, 1...

[0101] The embodiments of this application ensure message order and traceability through a numbering mechanism. Polling and deduplication eliminate head blocking and duplicate transmission problems, thereby improving the parallel communication efficiency of the on-chip network, reducing latency, and adapting to various topologies with minimal hardware resources.

[0102] In some embodiments, refer to Figure 2 An example is given of westward (W) and northward (N) buffers transmitting packets to southward (S). The dashed boxes on the left represent the input buffers for westward packets in the routing nodes, and the dashed boxes on the right represent the input buffers for northward packets in the on-chip network routing nodes. Only these two directions are used as examples; other directions include east (E), south (S), and device (P). The westward input buffer has four redirection registers (WE / WN / WS / WP), while the northward buffer only has two (NS / NP). This is because the XY routing algorithm transmits data in the X direction first, then in the Y direction. Packets can redirect from west / east to south / north in the X direction, but cannot redirect from south / north to west / east in the Y direction.

[0103] When a data packet enters the westbound input buffer of a routing node, the routing calculation has already been completed at the upstream routing node. That is, when the routing node enters the buffer, it already knows which direction it needs to be transmitted to. At the same time, the routing information in the data packet is extracted and the next-hop routing is calculated. The calculation result is stored in the same routing register as the data packet.

[0104] The west-to-south redirection register W-S11 arbitrates with the data packets in the redirection register N-S14 (including data packets in the ES redirection register, etc.). The data packet that wins the arbitration priority will be output in the south (S) direction. At the same time, the pointer in the arbitrator 12 will jump. While outputting, the data packet will be written to the backup register 13 for backup. If the downstream routing node cannot receive the data packet, it will return a retransmission signal in the next cycle. If the retransmission signal is received from the downstream routing node, the current routing node will resend the data packet in the backup register downstream.

[0105] In this way, the required packets can be continuously sent to the downstream routing nodes without any interruption. Once the registers of the downstream routing nodes become available, the data packets can be written immediately. At the same time, since there are multiple direction registers in the input buffer, the routing node can achieve completely headless and blocking parallel data stream transmission.

[0106] In some embodiments, refer to Figure 3 Messages from multiple transfer registers will be output downstream after passing through the arbitrator. In this case, the following three situations exist:

[0107] In cycle 0, if there is no packet in the backup register, the arbiter pointer needs to be updated to move packet A from the transfer register to the backup register and transmit it downstream. In cycle 1, if packet A (Txlfitv_A) is in the backup register, packet B (Txlfitv_B), which has obtained output priority, is transmitted downstream without updating the arbiter pointer. Packet B in the transfer register is not discarded. Simultaneously, if the downstream router sends back a retransmission signal (Retrans_A) for packet A, in cycle 2, the packet in the backup register will be retransmitted. A retransmission signal for packet B may also be received in cycle 2. If a retransmission signal for packet B is not received in cycle 2, it means that packet B has been received downstream. In the next cycle, packet B in the transfer register will be discarded, and the arbiter pointer will be updated to point to another transfer register. If a retransmission signal for packet B is received in cycle 2, packet B will continue to be sent in the next cycle. Packet B will not be discarded from the transfer register, and the arbiter pointer will not be updated.

[0108] The second case is similar to message B of cycle1 in the first case;

[0109] The third scenario is similar to message A in cycle2 in the first scenario.

[0110] From the downstream receiving end's perspective, there are several scenarios in which messages can be received:

[0111] If the redirection register in the input buffer corresponding to the data packet is empty, then the redirection register can receive the data packet.

[0112] The redirection register in the input buffer corresponding to the data packet is not empty, but the output direction it arbitrates only has one request (i.e., no other directions have sent packets to this output direction) and the backup register of this output direction is empty;

[0113] The redirection register in the input buffer corresponding to the data packet is not empty, but the retransmission signal corresponding to the data packet is empty, meaning that the packet can be discarded from the redirection register in the next clock cycle.

[0114] Except for the three cases mentioned above where a retransmission signal will not be sent upstream, in all other cases the routing node will send a retransmission signal upstream.

[0115] Reference Figure 4In the on-chip network of the whole chip, the data transmission method of the on-chip network provided in this application is adopted. The packet can pass through a route in each cycle without head-blocking. In cycle 2, at router (3,1), since the WE redirection register to which the packet is to be sent is occupied, router (3,1) sends a retransmission signal for the packet to router (2,1) in cycle 3. At the same time, in cycle 3, router (2,1) retransmits the packet to the downstream router. At this time, the redirection register in router (3,1) is free and can receive the packet. Since router (2,1) received the retransmission signal for the packet in cycle 3, router (2,1) will retransmit the packet in cycle 4. At this time, the downstream router observes that the packet encoding is 1 in two consecutive times, so it will directly discard the packet and will not send a retransmission signal to the upstream.

[0116] Based on the foregoing embodiments, this application provides a data transmission device for an on-chip network. The device includes various units and modules included in each unit, which can be implemented by a processor in a routing node; of course, it can also be implemented by specific logic circuits. In the implementation process, the processor can be a central processing unit (CPU), a microprocessor unit (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA), etc.

[0117] Figure 5 This application provides a schematic diagram of the composition structure of a data transmission device for an on-chip network, applied to a routing node in an on-chip network. The routing node has multiple redirection registers for different output directions in each input direction, and a backup register in each output direction, such as... Figure 5 As shown, the data transmission device 40 of the on-chip network includes:

[0118] Processing module 401 is used to confirm the target output direction of the data packet when a data packet sent by an upstream routing node is received from the target input direction;

[0119] The transmission module 402 is configured to: write the data packet into the target redirection register or send a retransmission signal for the data packet to the upstream routing node according to the storage state of the target redirection register corresponding to the target input direction and the target output direction; send the data packet to the downstream routing node in the target output direction through the target redirection register, and temporarily store the data packet in the target redirection register or the target backup register corresponding to the target output direction before confirming that the downstream routing node has received the data packet; and send the data packet from the target backup register or the target redirection register to the downstream routing node upon receiving a retransmission signal for the data packet from the downstream routing node.

[0120] In some embodiments, the transmission module 402 is further configured to: write the data packet into the target redirection register if the target redirection register meets the write conditions; and send a retransmission signal for the data packet to the upstream routing node if the target redirection register does not meet the write conditions.

[0121] In some embodiments, the transmission module 402 is further configured to: write the data packet into the target redirection register when the target redirection register is empty; write the data packet into the target redirection register at the next time node when the target redirection register is not empty and the retransmission signal corresponding to the target redirection register is empty; and write the data packet into the target redirection register at the next time node when the target redirection register is not empty and the arbitrator corresponding to the target output direction receives only one output request.

[0122] In some embodiments, the transmission module 402 is further configured to: send a retransmission signal of the data packet to the upstream routing node when the target redirection register is not empty and the retransmission signal corresponding to the target redirection register is not empty; and send a retransmission signal of the data packet to the upstream routing node when the target redirection register is not empty and the arbitrator corresponding to the target output direction has at least two output requests.

[0123] In some embodiments, the transmission module 402 is further configured to: transfer the data packet from the target redirection register to the target backup register when the data packet is stored in the target redirection register and the target backup register is empty; and temporarily store the data packet in the target redirection register when the data packet is stored in the target redirection register and the target backup register is not empty.

[0124] In some embodiments, the transmission module 402 is further configured to: if no retransmission signal is received from the downstream routing node for the data packet at the next time node, confirm that the downstream routing node has received the data packet, and discard the data packet in the target backup register or the target redirection register.

[0125] In some embodiments, the processing module 401 is further configured to: count the number of retransmissions of the target backup register using a counter register; and, if the number of retransmissions of the target backup register exceeds a threshold, send a flag signal to the downstream routing node, wherein the flag signal is used to instruct the downstream routing node to refuse to receive other data packets before successfully receiving the data packet in the target backup register.

[0126] In some embodiments, the processing module 401 is further configured to: add a number to the data packets to be sent; and, when all data packets to be sent have been sent, send the cached data packets to the downstream routing nodes in a round-robin fashion according to the number order, wherein the number is used by the downstream routing nodes to perform deduplication processing on the data packets to be sent.

[0127] This application embodiment sets corresponding redirection registers and backup registers for each output direction of the current routing node to transmit and back up received data packets. This allows the current routing node to back up data packets locally before they are successfully sent to downstream routing nodes, so that they can be resent to downstream routing nodes. This avoids the problem of data interruption caused by downstream data nodes being unable to receive data. For data packets that the current routing node cannot successfully receive, a retransmission signal can be sent to the upstream routing node to make the upstream routing node resend the data packets. This retransmission mechanism does not require setting up a buffer queue in the current routing node. Therefore, while avoiding the head blocking problem, it ensures uninterrupted data communication between routing nodes.

[0128] The descriptions of the apparatus embodiments above are similar to those of the method embodiments above, and have similar beneficial effects. In some embodiments, the functions or modules included in the apparatus provided in this application can be used to perform the methods described in the method embodiments above. For technical details not disclosed in the apparatus embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0129] It should be noted that, in the embodiments of this application, if the above-described on-chip network data transmission method is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of this application, or the part that contributes to the related technology, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a routing node (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this application are not limited to any specific hardware, software, or firmware, or any combination of hardware, software, and firmware.

[0130] This application provides a routing node, including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor executes the program, it implements some or all of the steps in the above method.

[0131] This application provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements some or all of the steps in the above-described method. The computer-readable storage medium can be transient or non-transient.

[0132] This application provides a computer program including computer-readable code, wherein when the computer-readable code is executed in a routing node, a processor in the routing node performs some or all of the steps in the above method.

[0133] This application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described method. This computer program product can be implemented specifically through hardware, software, or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium; in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0134] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between them, while their similarities or commonalities can be referred to interchangeably. The descriptions of the above embodiments of the device, storage medium, computer program, and computer program product are similar to the descriptions of the above method embodiments and have similar beneficial effects. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0135] It should be noted that, Figure 6 This is a schematic diagram of a hardware entity of a routing node in an embodiment of this application, such as... Figure 6 As shown, the hardware entity of the routing node 700 includes: one or more processors 701, a communication interface 702, and a memory 703, wherein:

[0136] Processor 701 typically controls the overall operation of routing node 700.

[0137] Communication interface 702 enables routing nodes to communicate with other terminals or servers over a network.

[0138] The memory 703 is configured to store instructions and applications executable by the processor 701, and can also cache data to be processed or already processed (e.g., image data, audio data, voice communication data, and video communication data) in the processor 701 and various modules in the routing node 700. It can be implemented using flash memory or random access memory (RAM). Data transfer between the processor 701, communication interface 702, and memory 703 can be performed via bus 704. Only one processor is shown in the figure; each routing node 700 includes one or more cores.

[0139] It should be noted that the routing node may include multiple processors 701, and each processor 701 can interact with each other through aggregation communication methods such as all-to-all, all-gather, or all-reduce. The processors 701 can be central processing units (CPUs), graphics processing units (GPUs), embedded neural network processing units (NPUs), tensor processing units (TPUs), data processing units (DPUs), accelerated processing units (APUs), floating-point processing units (FPUs), or application-specific integrated circuits (ASICs). The processors can also be single-core or multi-core processors. The processor can be a combination of a CPU and hardware chips. The hardware chips can be ASICs, PLDs, or combinations thereof. The PLDs can be complex programmable logic devices (CPLDs), FPGAs, generic array logic (GALs), or any combination thereof. The processor can also be implemented using logic devices with built-in processing logic, such as FPGAs or digital signal processors (DSPs).

[0140] The communication interface 702 can be a wired interface or a wireless interface, used to communicate with other modules or devices. The wired interface can be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface can be a cellular network interface or a wireless LAN interface, etc.

[0141] Memory 703 can be non-volatile memory, such as read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Memory 703 can also be volatile memory, which can be random access memory (RAM) used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synclink dynamic random access memory (SLDRAM), and direct rambus RAM (DRRAM), direct rambus DRAM (DRDRAM), and rambus DRAM.

[0142] The 704 bus can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus can be divided into address bus, data bus, control bus, etc.

[0143] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0144] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0145] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0146] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0147] In addition, each functional unit in the various embodiments of this application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0148] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0149] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a routing node (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0150] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A data transmission method for an on-chip network, characterized in that, A routing node applied in an on-chip network, wherein the routing node has multiple redirection registers for different output directions in each input direction, and a backup register in each output direction, the method comprising: Upon receiving a data packet sent by an upstream routing node from the target input direction, the target output direction of the data packet is confirmed. If the target redirection register meets the write conditions, the data packet is written to the target redirection register, including: If the target redirection register is empty, the data packet is written into the target redirection register; If the target redirection register is not empty and the retransmission signal corresponding to the target redirection register is empty, the data packet is written into the target redirection register at the next time node. If the target direction register is not empty and the arbitrator corresponding to the target output direction receives only one output request, the data packet will be written into the target direction register at the next time node. If the target redirection register does not meet the write conditions, a retransmission signal for the data packet will be sent to the upstream routing node; The data packet is sent to the downstream routing node in the target output direction through the target steering register, and the data packet is temporarily stored in the target steering register or the target backup register corresponding to the target output direction before the downstream routing node is confirmed to have received the data packet. Upon receiving a retransmission signal from the downstream routing node for the data packet, the data packet is sent from the target backup register or the target redirection register to the downstream routing node.

2. The method according to claim 1, characterized in that, The step of sending a retransmission signal for the data packet to the upstream routing node when the target redirection register does not meet the write conditions includes: If the target redirection register is not empty and the retransmission signal corresponding to the target redirection register is not empty, send the retransmission signal of the data packet to the upstream routing node; If the target routing register is not empty and there are at least two output requests from the arbitrator corresponding to the target output direction, a retransmission signal for the data packet is sent to the upstream routing node.

3. The method according to any one of claims 1-2, characterized in that, The step of temporarily storing the data packet in the target redirection register or the target backup register corresponding to the target output direction includes: If the data packet is stored in the target redirection register and the target backup register is empty, the data packet is transferred from the target redirection register to the target backup register. If the data packet is stored in the target redirection register and the target backup register is not empty, the data packet is temporarily stored in the target redirection register.

4. The method according to any one of claims 1-2, characterized in that, The confirmation that the downstream routing node has received the data packet includes: If no retransmission signal for the data packet is received from the downstream routing node at the next time node, the downstream routing node is confirmed to have received the data packet, and the data packet in the target backup register or target redirection register is discarded.

5. The method according to any one of claims 1-2, characterized in that, The method further includes: The number of retransmissions to the target backup register is counted using a counter register; If the number of retransmissions to the target backup register exceeds a threshold, a flag signal is sent to the downstream routing node. The flag signal is used to instruct the downstream routing node to refuse to receive other data packets until it successfully receives a data packet from the target backup register.

6. The method according to any one of claims 1-2, characterized in that, The method further includes: Add a number to the sent data packets; Once all the data packets to be sent have been sent, the cached data packets are sent to the downstream routing nodes in a round-robin fashion according to their numerical order. The numerical order is used by the downstream routing nodes to perform deduplication on the data packets to be sent.

7. A data transmission device for an on-chip network, characterized in that, A routing node applied in an on-chip network, wherein the routing node has multiple redirection registers for different output directions in each input direction, and a backup register in each output direction, the device comprising: The processing module is used to determine the target output direction of the data packet when it receives a data packet sent by an upstream routing node from the target input direction; A transmission module is configured to write a data packet into a target redirection register when the target redirection register meets the write conditions, including: writing the data packet into the target redirection register when the target redirection register is empty; writing the data packet into the target redirection register at the next time node when the target redirection register is not empty and the retransmission signal corresponding to the target redirection register is empty; writing the data packet into the target redirection register at the next time node when the target redirection register is not empty and the arbitrator corresponding to the target output direction receives only one output request; sending a retransmission signal for the data packet to the upstream routing node when the target redirection register does not meet the write conditions; sending the data packet to the downstream routing node in the target output direction through the target redirection register, and temporarily storing the data packet in the target redirection register or the target backup register corresponding to the target output direction before confirming that the downstream routing node has received the data packet; and sending the data packet from the target backup register or the target redirection register to the downstream routing node when receiving a retransmission signal for the data packet from the downstream routing node.

8. A routing node, characterized in that, The routing node includes: a processor, a plurality of redirection registers for different output directions in each input direction, and a backup register in each output direction, wherein the processor executes the steps of the data transmission method of the on-chip network according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the steps of the data transmission method of the on-chip network according to any one of claims 1 to 6.

Images