System and method for generating images using dithered motion vectors

Abstract

The invention relates to a system and method for generating an image using a dithered motion vector, and specifically discloses a system and method for improving the quality of a rendered image. Time accumulation of motion vectors using dithering may be performed in the intermediate channel.

Description

[0001] This application is a divisional application of the application filed on August 27, 2021, with application number 202110997742.6 and invention title "System and method for generating images using jittered motion vectors". Technical Field

[0002] At least one embodiment relates to image generation. For example, at least one embodiment relates to image generation using jittered motion vectors. Background Technology

[0003] Current displays often produce a jagged effect, typically perceived by users as jagged edges in images. This is due to the limited size of display pixels, making it inherently unable to reproduce truly curved or non-linear surfaces. Anti-aliasing techniques have been developed to attempt to compensate for this limitation, thereby generating more realistic-looking images on modern displays. One such technique, for example, is temporal anti-aliasing, which samples subpixel values ​​from one or more previous frames to determine the subpixel values ​​for the current frame, attempting to effectively improve the resolution of the current image. This and other techniques can interpolate between selected subpixel values ​​from previous frames based on motion vectors, introducing time-varying elements designed to effectively smooth sharp boundaries in the image. Ongoing efforts exist to improve these and other techniques involving the temporal accumulation of image values. Summary of the Invention

[0004] This application provides the following: 1) A processor, comprising: One or more circuits for applying jitter to one or more motion vectors during image rendering.

[0005] 2) The processor as described in 1), wherein the motion vector is the motion vector of one or more intermediate image rendering channels.

[0006] 3) The processor as described in 2), wherein the intermediate image rendering channel includes one or more of a shadow channel, an occlusion channel, a reflection channel, or a specular reflection channel.

[0007] 4) The processor as described in 1) further includes: One or more memories for storing jitter values ​​to be applied to the motion vector.

[0008] 5) The processor as described in 4), wherein the one or more circuits are further configured to retrieve the jitter value from the buffer and apply the jitter value to the one or more motion vectors during the rendering.

[0009] 6) The processor as described in 1), wherein the one or more processors are further configured to determine at least one image value of the current image frame by interpolation of image values ​​from one or more previous image frames, wherein the interpolation is performed based on the one or more motion vectors to which the jitter value is applied.

[0010] 7) The processor as described in 6), wherein the interpolation is Catmull-Rom interpolation.

[0011] 8) A machine-readable medium having a set of instructions stored thereon, said instructions, when executed by one or more processors, causing said one or more processors to at least: Dithering is applied to one or more motion vectors during image rendering.

[0012] 9) A machine-readable medium as described in 8), wherein the motion vector is a motion vector of one or more intermediate image rendering channels.

[0013] 10) A machine-readable medium as described in 9), wherein the intermediate image rendering channel includes one or more of a shadow channel, an occlusion channel, a reflection channel, or a specular reflection channel.

[0014] 11) A machine-readable medium as described in 8), wherein the instructions, if executed by one or more processors, further cause the one or more processors to: Store the jitter values ​​to be applied to the motion vector.

[0015] 12) A machine-readable medium as described in 11), wherein the instructions, if executed by one or more processors, further cause said one or more processors to: Retrieve the jitter value from the buffer; and The jitter value is applied to the one or more motion vectors during the rendering process.

[0016] 13) A machine-readable medium as described in 8), wherein the instructions, if executed by one or more processors, further cause said one or more processors to: At least one image value of the current image frame is determined by interpolation of image values ​​from one or more previous image frames, and the interpolation is performed based on the one or more motion vectors to which the jitter value is applied.

[0017] 14) A machine-readable medium as described in 13), wherein the interpolation is Catmull-Rom interpolation.

[0018] 15) A display system, comprising: One or more processors are used to generate the image for display on a display device, at least in part by applying dithering to one or more motion vectors during the rendering of the image.

[0019] 16) The system as described in 15), wherein the motion vector is the motion vector of one or more intermediate image rendering channels.

[0020] 17) The system as described in 16), wherein the intermediate image rendering channel includes one or more of a shadow channel, an occlusion channel, a reflection channel, or a specular reflection channel.

[0021] 18) The system as described in 15) further includes: One or more memories for storing jitter values ​​to be applied to the motion vector.

[0022] 19) The system as described in 18), wherein the one or more processors are further configured to retrieve the jitter value from the buffer and apply the jitter value to the one or more motion vectors during the rendering.

[0023] 20) The system as described in 15), wherein the one or more processors further determine at least one image value of the current image frame by interpolation of image values ​​from one or more previous image frames, and perform the interpolation based on the one or more motion vectors to which the jitter value is applied.

[0024] 21) The system as described in 20), wherein the interpolation is Catmull-Rom interpolation. Attached Figure Description

[0025] The above and other objects and advantages of this disclosure will become apparent from the following detailed description taken in conjunction with the accompanying drawings, wherein like reference numerals always refer to like parts, wherein: Figure 1 The determination of the motion vector of jitter according to at least one embodiment is conceptually illustrated; Figure 2 This is a generalized embodiment of an illustrative processing system constructed for use according to at least one embodiment; Figure 3A The inference and / or training logic according to at least one embodiment is illustrated; Figure 3B The inference and / or training logic according to at least one embodiment is illustrated; Figure 4 The training and deployment of a neural network according to at least one embodiment are illustrated; Figure 5 An example data center system according to at least one embodiment is shown; Figure 6A An example of an autonomous vehicle according to at least one embodiment is shown; Figure 6B The illustration shows an embodiment according to at least one of the embodiments. Figure 6A Examples of camera positions and field of view for autonomous vehicles; Figure 6C This is an illustration based on at least one embodiment. Figure 6A A block diagram of an example system architecture for an autonomous vehicle; Figure 6D The illustration, according to at least one embodiment, is for one or more cloud-based servers and Figure 6A A diagram of a system for communication between autonomous vehicles; Figure 7 This is a block diagram illustrating a computer system according to at least one embodiment; Figure 8 This is a block diagram illustrating a computer system according to at least one embodiment; Figure 9 A computer system according to at least one embodiment is shown; Figure 10 A computer system according to at least one embodiment is shown; Figure 11A A computer system according to at least one embodiment is shown; Figure 11B A computer system according to at least one embodiment is shown; Figure 11C A computer system according to at least one embodiment is shown; Figure 11D A computer system according to at least one embodiment is shown; Figure 11E and Figure 11F A shared programming model according to at least one embodiment is shown; Figure 12 An exemplary integrated circuit and a related graphics processor according to at least one embodiment are shown.

[0026] Figures 13A-13B An exemplary integrated circuit and an associated graphics processor according to at least one embodiment are shown.

[0027] Figure 14A and Figure 14B Additional exemplary graphics processor logic according to at least one embodiment is shown; Figure 15 A computer system according to at least one embodiment is shown; Figure 16A A parallel processor according to at least one embodiment is shown; Figure 16B A partitioning unit according to at least one embodiment is shown; Figure 16C A processing cluster according to at least one embodiment is shown; Figure 16D A graphics multiprocessor according to at least one embodiment is shown; Figure 17 A multi-graphics processing unit (GPU) system according to at least one embodiment is illustrated; Figure 18 A graphics processor according to at least one embodiment is shown; Figure 19 It is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment; Figure 20 A deep learning application processor according to at least one embodiment is shown; Figure 21 A block diagram of an example neuromorphic processor is shown according to at least one embodiment; Figure 22 At least a portion of a graphics processor according to one or more embodiments is shown; Figure 23 At least a portion of a graphics processor according to one or more embodiments is shown; Figure 24 At least a portion of a graphics processor according to one or more embodiments is shown; Figure 25 A block diagram of a graphics processing engine of a graphics processor is shown according to at least one embodiment; Figure 26 This is a block diagram illustrating at least a portion of a graphics processor core according to at least one embodiment; Figures 27A-27B The diagram illustrates thread execution logic according to at least one embodiment, which includes an array of processing elements of a graphics processor core.

[0028] Figure 28 A parallel processing unit (“PPU”) according to at least one embodiment is shown. Figure 29 A general-purpose processing cluster (“GPC”) according to at least one embodiment is illustrated. Figure 30 A memory partitioning unit of a parallel processing unit (“PPU”) according to at least one embodiment is shown; Figure 31 A streaming multiprocessor according to at least one embodiment is illustrated; Figure 32 This is an example data flow diagram of an advanced computing pipeline according to at least one embodiment; Figure 33 This is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline, according to at least one embodiment; Figure 34 Example illustrations of an advanced computing pipeline for processing imaging data according to at least one embodiment; Figure 35A Includes example data flow diagrams of virtual instruments supporting ultrasound equipment according to at least one embodiment; Figure 35B Includes example data flow diagrams of virtual instruments supporting CT scanners according to at least one embodiment; Figure 36A A data flow diagram illustrating the process for training a machine learning model according to at least one embodiment is shown; and Figure 36B This is an example illustration of a client-server architecture that utilizes a pre-trained annotation model to enhance an annotation tool according to at least one embodiment; Figure 37 This is a flowchart illustrating processing steps for generating image values ​​according to at least one embodiment; Figure 38A and Figure 38B The illustration illustrates the drawbacks of generating images using jitter-free motion vectors; Figure 39A and Figure 39B The illustrations illustrate the drawbacks of images generated using jitter-free motion vectors and Catmull-ROM filtering; and Figure 40A and Figure 40B The illustrations illustrate the advantages of generating images using jittered motion vectors (with Catmull-ROM filtering applied) determined according to at least one embodiment. Detailed Implementation

[0029] In at least one embodiment, the system and method involve image generation using a time-accumulation process that employs a dithered motion vector for any portion of the image (e.g., an intermediate channel image portion). As an example, the image values ​​of intermediate channels (e.g., shadow channels) can be determined based on the dithered motion vector. In at least one embodiment, the dithered values ​​used in those shadow channels are those used in combination with other channels (e.g., default channels). To compensate for blurring that may be introduced by using motion vectors in image rendering channels (e.g., intermediate image rendering channels), filters can be applied, such as self-sharpening cubic interpolation filters, an example being a Catmull-ROM filter.

[0030] Figure 1The determination of a jittered motion vector according to at least one embodiment is conceptually illustrated. In at least one embodiment, the motion vector may be employed in the temporal accumulation of previous image values ​​to determine the image value of the current frame. In at least one embodiment, such an accumulation method may be employed in any image channel, such as a default image channel (e.g., a process for determining the image value of an object in an image), and / or in intermediate image channels (e.g., a process for modifying or generating additional visual effects, modifying the appearance of an object generated in the default image channel). In at least one embodiment, the jitter values ​​of the motion vectors applied to each image rendering channel may be substantially the same as those employed in any aspect of other image rendering channels. In at least one embodiment, "jitter" refers to a vector that offsets the magnitude and / or direction of those motion vectors when added to them. In at least one embodiment, the jitter vector may be generated in any manner, such as by randomly generating direction and magnitude values. In at least one embodiment, jitter may be added to the motion vector during intermediate channels such as shadow channels, occlusion channels, reflection channels, specular reflection channels, etc.

[0031] exist Figure 1 In this embodiment, a motion vector 100 describes the motion of object 10 from one frame (n-1) to the next frame (n) and has a jitter value applied to slightly modify its amplitude and / or orientation. In at least one embodiment, a jitter-free motion vector 90 can measure the distance a point on object 10 moves from frame (n-1) to frame n. Specifically, point 20 is the center of a pixel, shown as one of the square grids covering object 10. In at least one embodiment, the jitter-free motion vector 90 can thus extend from point 20 to the same point 30 in frame n-1 of object 10, representing the distance and orientation of point 30's travel from frame (n-1) to frame n. In at least one embodiment, jitter can be applied to each point 20, 30 in each frame n-1, n. That is, a jitter value or vector can be applied to each frame to slightly shift the motion vector and generate a certain amount of blur to compensate for jagged edges in the appearance of object 10 when represented by a discrete set of pixels. Specifically, dithering value 70 can be applied to object 10 in frame (n-1), and dithering value 60 can be applied to object 10 in frame n. In at least one embodiment, any image rendering channel can use the dithered motion vector 100 to determine the image value of any image portion, such as any portion of object 10. In at least one embodiment, the same dithering values ​​60 and 70 used in any selected intermediate channel can be dithering values ​​used in any aspect of another or more image rendering channels.

[0032] In at least one embodiment, the image value of each pixel can be determined in part by mapping the pixel center to a corresponding point in the previous frame and determining the color value of that mapped point by interpolation with neighboring pixels. That is, the pixel value of the current image frame can be determined at least in part as an estimate of the neighboring pixel values ​​of the previous image frame. For example, the color value of the pixel having center point 20 can be calculated by determining the position of the corresponding point 30, receiving the current jitter vector 60, retrieving the previous jitter vector 70 from memory (such as a buffer), and calculating the jitter motion vector 100 as a vector sum of vectors drawn between points 20 and 30 (and vectors 60 and 70).

[0033] In at least one embodiment, the position of point 30 or point 40 can then be determined from motion vector 90 or 100, depending on the situation. In at least one embodiment, the color value of the point can then be estimated from the color values ​​of neighboring pixel centers 110, 120, 130, 140. The estimation can be performed in any manner. In at least one embodiment, the color values ​​of points 30 and 40 can be estimated by bilinear interpolation of the color values ​​of points 110, 120, 130, 140. However, any other method for estimating the color values ​​of points 30 and 40 from the color values ​​of neighboring points 110, 120, 130, 140 is also considered. In at least one embodiment, and as further described below, interpolation can be performed by a process such as the Catmull-Rom interpolation method.

[0034] In at least one embodiment, the color value of point 20 or a pixel in frame n is determined at least partially from the estimated color value of point 30 / 40. That is, the color value of the pixel in frame n is determined using the estimated colors of those corresponding points in the previous frame n-1. In at least one embodiment, other values ​​may also contribute to the color value of the pixel in frame n. In at least one embodiment, color samples may optionally be acquired at a new jitter point 150 (different from the jitter values ​​60, 70 applied to the motion vector). That is, the image may be sampled at the new jitter point 150 such that the final color value at point 20 also includes information about the current image it represents. In at least one embodiment, one or more samples of object 10 may be acquired in the nth frame (acquired at one or more jitter points 150), and the color values ​​of these samples may be combined with the interpolated color values ​​of point 30 / 40, as determined above. The combination or mixing of these sample and interpolated values ​​may be performed in any manner, such as simple averaging, any weighted average using any one or more fixed or adaptive mixing weights, or similar methods. In this way, the color value of a specific pixel in the current image frame n can be determined by interpolation of neighboring color values ​​from the previous image frame n-1 and a combination of one or more samples acquired at the jitter point in the current image frame n. In at least one embodiment, this sampling using the new jitter point 150 is optional and can be used or not used as needed.

[0035] Figure 2 This is a generalized embodiment of an illustrative electronic computing device constructed for use according to at least one embodiment. In at least one embodiment, the computing device 200 can be any device capable of performing the operations of the embodiments. For example, the computing device 200 can perform any of the above-described processes to generate motion vectors and determine pixel color values ​​accordingly.

[0036] As a non-limiting example, computing device 200 can be any electronic computing device, such as a system-on-a-chip (SoC), an embedded processor, or a microprocessor, and any associated device or hardware. In at least one embodiment, computing device 200 can send and receive data via input / output (hereinafter “I / O”) paths 202 and 214, which can communicate electronically with any other device, for example, via an electronic communication medium (e.g., via the public Internet). In at least one embodiment, I / O path 202 can provide data and other inputs to control circuitry 204, which includes processing circuitry 206 and storage device 208. In at least one embodiment, control circuitry 204 can be used to send and receive commands, requests, and other suitable data using I / O path 202. In at least one embodiment, I / O path 202 can connect control circuitry 204 (and particularly processing circuitry 206) to one or more communication paths. In at least one embodiment, I / O functionality can be provided by one or more of these communication paths, but… Figure 2 The path is shown as a single path to avoid making the graph overly complex. User input interface 310 can be any suitable user interface, such as a remote control, mouse, trackball, keypad, keyboard, touchscreen, touchpad, stylus input, joystick, voice recognition interface, or other user input interface. Display 212 can be provided as a standalone device or integrated with other components of computing device 200. For example, display 212 can be a touchscreen or touch-sensitive display. In this case, user input interface 210 can be integrated with or combined with display 212. Display 212 can be a monitor, television, liquid crystal display (LCD) for mobile devices, amorphous silicon display, low-temperature polycrystalline silicon display, electronic ink display, electrophoretic display, active matrix display, electrowetting display, electrofluid display, cathode ray tube display, light-emitting diode display, electroluminescent display, plasma display panel, high-performance addressable display, thin-film transistor display, organic light-emitting diode display, surface conduction electron emission display (SED), laser television, carbon nanotube, quantum dot display, interferometric modulator display, or any other suitable device for displaying visual images, or one or more of these.

[0037] Control circuitry 204 may be based on any suitable processing circuitry, such as processing circuitry 206. As referred to herein, processing circuitry can be understood to mean circuitry based on one or more microprocessors, microcontrollers, digital signal processors, programmable logic devices, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), etc., and may include multi-core processors (e.g., dual-core, quad-core, hexa-core, or any suitable number of cores). In at least one embodiment, the processing circuitry may be distributed across multiple individual processors or processing units, such as multiple processing units (e.g., multiple NVIDIA® Tegra™ or Volta™ processors, Intel® Core™ processors, etc.) or multiple different processors (e.g., Intel® Nervana™ processors and NVIDIA® Volta™ processors, etc.). Processing circuitry of any type and structure can be employed. For example, processing circuitry 206 may include a multi-core processor, a multi-core processor configured for parallel execution of operations in a graphics or computing pipeline, a neuromorphic processor, any other parallel processor or graphics processor, etc. In at least one embodiment, the processing circuitry 206 may include, but is not limited to, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor that implements instruction set combinations, or any other processor device, such as a digital signal processor or a graphics processor.

[0038] In at least one embodiment, control circuitry 204 executes instructions for security authentication, which may be embedded instructions or part of an application running on an operating system. In at least one embodiment, computing device 100 may execute a version of the Windows operating system available from Microsoft Corporation, Redmond, Washington, although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0039] In at least one embodiment, the memory may be an electronic storage device provided as part of the storage device 208 of the control circuitry 204. As referred to herein, "electronic storage device" or "storage device" may be understood to mean any device for storing electronic data, computer software, or firmware, such as random access memory, read-only memory, hard disk drive, solid-state device, quantum storage device, or any other suitable fixed or removable storage device, and / or any combination thereof. In at least one embodiment, the storage device 208 may be used to store code modules as described below. In at least one embodiment, non-volatile memory may also be used (e.g., to start boot routines and other instructions). In at least one embodiment, cloud-based storage may be used to supplement or replace the storage device 208.

[0040] In at least one embodiment, the storage device 208 may also store instructions or code for the anti-aliasing processing described above to perform the operations of at least one embodiment. In operation, the processing circuit 206 may retrieve and execute the instructions stored in the storage device 208 to perform the processes described herein.

[0041] In at least one embodiment, storage device 208 may be a memory storing multiple program or instruction modules for execution by processing circuitry 206. For example, storage device 208 may store rendering engine 216, anti-aliasing module 218, and storage device 220, which may include buffers and other data structures and storage devices for performing anti-aliasing processing according to at least one embodiment. In at least one embodiment, rendering engine 216 may be a set of instructions for rendering image frames or generating color values ​​for pixels of image frames. In at least one embodiment, rendering engine 216 may retrieve dithering values ​​cached in storage device 220 and generate motion vectors as described herein, passing the determined motion vectors to anti-aliasing module 218. In at least one embodiment, anti-aliasing module 218 may be a set of instructions for performing the aforementioned time accumulation process, including color value interpolation and image sampling or resampling, correction, and accumulation or blending of sampled values ​​to generate pixel color values. In at least one embodiment, storage device 220 may be any storage device for storing pixel color values ​​of previous image frames and storing dithering values ​​for determining motion vectors according to at least one embodiment. In at least one embodiment, storage device 220 may include one or more buffers that store these image frames and associated jitter values ​​for retrieval by rendering engine 216 and anti-aliasing module 218. In at least one embodiment, storage device 220 may be a local storage device (e.g., a partition or other portion of storage device 208) or remote storage implemented in a remote device (such as a remote database) or a remote computing device (such as a security server).

[0042] In at least one embodiment, computing device 200 may be a standalone computing device, such as a desktop or laptop computer, a server computer, etc. However, embodiments are not limited to this configuration, and other implementations of computing device 200 are contemplated. For example, computing device 200 may be a remote computing device that is wired or wirelessly connected to another electronic computing device via an electronic communication network (such as the public Internet). In such later embodiments, a user may remotely instruct computing device 200 to implement the processes described herein to select a version of a program to be executed on device 200.

[0043] In at least one embodiment, the computing device 200 can be any electronic computing device capable of performing pixel color value determination and anti-aliasing processing. For example, the computing device 200 can be an embedded processor, microcontroller, locally or remotely located desktop computer, tablet computer, or server that communicates electronically with camera 90 and actuator 70, etc. In at least one embodiment, the computing device 200 can have any configuration or architecture that allows it to select and execute program versions according to any embodiment, such as any configuration or architecture described below.

[0044] Reasoning and training logic Figure 3A Inference and / or training logic 315 is illustrated for performing inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 3A and / or Figure 3B Provide details about reasoning and / or training logic 315.

[0045] In at least one embodiment, inference and / or training logic 315 may include, but is not limited to, code and / or data storage 301 for storing forward and / or output weights and / or input / output data, and / or other parameters configuring neurons or layers of a neural network trained for and / or used for inference in one or more embodiments. In at least one embodiment, training logic 315 may include or be coupled to code and / or data storage 301 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic, including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 301 stores weight parameters and / or input / output data of each layer of a neural network trained or used in one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using one or more embodiments. In at least one embodiment, any portion of the code and / or data storage 301 may be included within other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0046] In at least one embodiment, any portion of the code and / or data storage 301 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 301 may be a cache memory, dynamic random-addressable memory (“DRAM”), static random-addressable memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether the code and / or data storage 301 is internal or external to the processor, for example, or composed of DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip or off-chip storage space, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0047] In at least one embodiment, the inference and / or training logic 315 may include, but is not limited to, code and / or data storage 305 for storing backpropagation and / or output weights and / or input / output data neural networks corresponding to neurons or layers of a neural network trained and / or used for inference in one or more embodiments. In at least one embodiment, during training and / or inference using one or more embodiments, the code and / or data storage 305 stores weight parameters and / or input / output data for each layer of a neural network trained or used in one or more embodiments during backpropagation of input / output data and / or weight parameters. In at least one embodiment, the training logic 315 may include or be coupled to code and / or data storage 305 for storing graph code or other software to control timing and / or sequence, wherein weight and / or other parameter information is loaded to configure logic including integer and / or floating-point units (collectively, arithmetic logic units (ALUs)).

[0048] In at least one embodiment, code (such as graph code) causes the architecture of the neural network corresponding to that code to load weights or other parameter information into the processor ALU. In at least one embodiment, any portion of the code and / or data storage 305 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of the code and / or data storage 305 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, the code and / or data storage 305 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice between the code and / or data storage 305 being internal or external to the processor, for example, whether it consists of DRAM, SRAM, flash memory, or some other type of storage, depends on whether the available storage is on-chip or off-chip, the latency requirements of the training and / or inference functions being performed, the data batch size used in the inference and / or training of the neural network, or some combination of these factors.

[0049] In at least one embodiment, code and / or data storage 301 and code and / or data storage 305 may be separate storage structures. In at least one embodiment, code and / or data storage 301 and code and / or data storage 305 may be the same storage structure. In at least one embodiment, code and / or data storage 301 and code and / or data storage 305 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 301 and code and / or data storage 305 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0050] In at least one embodiment, the inference and / or training logic 315 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 310 (including integer and / or floating-point units) for performing logical and / or mathematical operations at least in part based on or instructed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from layers or neurons within a neural network) stored in activation storage 320, which are functions of input / output and / or weight parameter data stored in code and / or data storage 301 and / or code and / or data storage 305. In at least one embodiment, activation is activated in response to execution instructions or other code, and linear algebraic and / or matrix-based mathematical generation performed by ALU 310 is stored in activation storage 320, wherein weight values ​​stored in code and / or data storage 305 and / or code and / or data storage 301 are used as operands with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, and any or all of these can be stored in code and / or data storage 305 or code and / or data storage 301 or other on-chip or off-chip storage.

[0051] In at least one embodiment, one or more processors or other hardware logic devices or circuits include one or more ALUs 310, while in another embodiment, one or more ALUs 310 may be located outside the processor or other hardware logic device or the circuitry using them (e.g., a coprocessor). In at least one embodiment, one or more ALUs 310 may be included within an execution unit of a processor, or otherwise included in a group of ALUs accessible by the execution unit of the processor, which may be within the same processor or distributed among different processors of different types (e.g., a central processing unit, a graphics processing unit, a fixed-function unit, etc.). In at least one embodiment, code and / or data storage 301, code and / or data storage 305, and activation storage 320 may share a processor or other hardware logic device or circuitry, while in another embodiment, they may be located in different processors or other hardware logic devices or circuitry, or in some combination of the same and different processors or other hardware logic devices or circuitry. In at least one embodiment, any portion of activation storage 320 may be included together with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Furthermore, inference and / or training code may be stored together with other code accessible to the processor or other hardware logic or circuitry, and may be retrieved and / or processed using the processor’s fetch, decode, schedule, execute, exit, and / or other logic circuitry.

[0052] In at least one embodiment, the active memory 320 may be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, the active memory 320 may be wholly or partially located inside or outside one or more processors or other logic circuits. In at least one embodiment, the choice of whether the active memory 320 is internal to or external to the processor may depend on the available on-chip or off-chip storage, the latency requirements for training and / or inference functions, the batch size of data used in inference and / or training the neural network, or some combination of these factors. For example, it may include DRAM, SRAM, flash memory, or other memory types.

[0053] In at least one embodiment, Figure 3A The inference and / or training logic 315 shown can be used in conjunction with an application-specific integrated circuit (“ASIC”), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment, Figure 3A The inference and / or training logic 315 shown can be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as field programmable gate array (“FPGA”).

[0054] Figure 3B Inference and / or training logic 315 according to at least one embodiment is illustrated. In at least one embodiment, the inference and / or training logic 315 may include, but is not limited to, hardware logic, wherein computational resources are dedicated or otherwise uniquely used in conjunction with weight values ​​or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 3B The inference and / or training logic 315 shown can be used in conjunction with an application-specific integrated circuit (ASIC), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment, Figure 3BThe inference and / or training logic 315 shown can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (e.g., field-programmable gate array (FPGA)). In at least one embodiment, the inference and / or training logic 315 includes, but is not limited to, code and / or data storage 301 and code and / or data storage 305, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 3B In at least one embodiment shown, each of code and / or data storage 301 and code and / or data storage 305 is associated with dedicated computing resources (e.g., computing hardware 302 and computing hardware 306). In at least one embodiment, each of computing hardware 302 and computing hardware 306 includes one or more ALUs that perform mathematical functions (e.g., linear algebraic functions) on information stored in code and / or data storage 301 and code and / or data storage 305, respectively, and the results of the function execution are stored in activation memory 320.

[0055] In at least one embodiment, each of the code and / or data storage 301 and 305 and the corresponding computing hardware 302 and 306 corresponds to a different layer of the neural network, such that activation obtained from one “store / computation pair 301 / 302” of the code and / or data storage 301 and computing hardware 302 provides input as input to the next “store / computation pair 305 / 306” of the code and / or data storage 305 and computing hardware 306, in order to reflect the conceptual organization of the neural network. In at least one embodiment, each store / computation pair 301 / 302 and 305 / 306 may correspond to more than one neural network layer. In at least one embodiment, additional store / computation pairs (not shown) may be included in the inference and / or training logic 315 after or in parallel with the store / computation pairs 301 / 302 and 305 / 306.

[0056] Neural network training and deployment Figure 4Training and deployment of a deep neural network according to at least one embodiment are illustrated. In at least one embodiment, an untrained neural network 406 is trained using a training dataset 402. In at least one embodiment, the training framework 404 is the PyTorch framework, while in other embodiments, the training framework 404 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 404 trains the untrained neural network 406 and enables it to be trained using the processing resources described herein to generate a trained neural network 408. In at least one embodiment, the weights may be randomly selected or pre-trained using a deep belief network. In at least one embodiment, training may be performed in a supervised, partially supervised, or unsupervised manner.

[0057] In at least one embodiment, supervised learning is used to train an untrained neural network 406, wherein the training dataset 402 includes inputs paired with desired outputs for input, or wherein the training dataset 402 includes inputs with known outputs and the neural network 406 is manually graded output. In at least one embodiment, the untrained neural network 406 is trained in a supervised manner, and inputs from the training dataset 402 are processed, and the resulting output is compared with a set of expected or desired outputs. In at least one embodiment, errors are then propagated back through the untrained neural network 406. In at least one embodiment, a training framework 404 adjusts the weights controlling the untrained neural network 406. In at least one embodiment, the training framework 404 includes tools for monitoring the degree to which the untrained neural network 406 converges to a model (e.g., a trained neural network 408) adapted to generate the correct answer (e.g., result 414) based on input data (e.g., a new dataset 412). In at least one embodiment, the training framework 404 repeatedly trains the untrained neural network 406 while adjusting the weights to improve the output of the untrained neural network 406 using a loss function and tuning algorithms (e.g., stochastic gradient descent). In at least one embodiment, the training framework 404 trains an untrained neural network 406 until the untrained neural network 406 reaches the desired accuracy. In at least one embodiment, the trained neural network 408 can then be deployed to perform any number of machine learning operations.

[0058] In at least one embodiment, unsupervised learning is used to train an untrained neural network 406, wherein the untrained neural network 406 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 402 will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 406 can learn groupings within the training dataset 402 and can determine how each input relates to the untrained dataset 402. In at least one embodiment, unsupervised training can be used to generate a self-organizing graph in a trained neural network 408, which is capable of performing operations useful for reducing the dimensionality of the new dataset 412. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows the identification of data points in the new dataset 412 that deviate from the normal patterns of the new dataset 412.

[0059] In at least one embodiment, semi-supervised learning can be used, a technique in which a mixture of labeled and unlabeled data is included in the training dataset 402. In at least one embodiment, the training framework 404 can be used to perform incremental learning, for example, through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 408 to adapt to a new dataset 412 without forgetting the knowledge injected into the trained neural network 408 during initial training.

[0060] Data Center Figure 5 An example data center 500 that can be used with at least one embodiment is shown. In at least one embodiment, the data center 500 includes a data center infrastructure layer 510, a framework layer 520, a software layer 530, and an application layer 540.

[0061] In at least one embodiment, such as Figure 5As shown, the data center infrastructure layer 510 may include a resource coordinator 512, grouped computing resources 514, and node computing resources (“nodes CR”) 516(1)-516(N), where “N” represents a positive integer (which may be an integer “N” different from the integers used in other diagrams). In at least one embodiment, nodes CR 516(1)-516(N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field-programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 518(1)-518(N) (e.g., dynamic read-only memory, solid-state drives, or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more of nodes CR 516(1)-516(N) may be servers having one or more of the aforementioned computing resources.

[0062] In at least one embodiment, the grouped computing resource 514 may include individual groups (not shown) of node CRs housed within one or more racks, or a plurality of racks (also not shown) housed within data centers in various geographic locations. In at least one embodiment, the individual groups of node CRs within the grouped computing resource 514 may include computing, networking, memory, or storage resources that can be configured or allocated to support groups of one or more workloads. In at least one embodiment, several node CRs, including CPUs or processors, may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, the one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination.

[0063] In at least one embodiment, resource coordinator 512 may configure or otherwise control one or more nodes CR516(1)-516(N) and / or grouped computing resources 514. In at least one embodiment, resource coordinator 512 may include a Software Design Infrastructure (“SDI”) management entity for data center 500. In at least one embodiment, resource coordinator 512 may include hardware, software, or some combination thereof.

[0064] In at least one embodiment, such as Figure 5As shown, framework layer 520 includes job scheduler 522, configuration manager 524, resource manager 526, and distributed file system 528. In at least one embodiment, framework layer 520 may include a framework of software 532 supporting software layer 530 and / or one or more applications 542 supporting application layer 540. In at least one embodiment, software 532 or application 542 may respectively include web-based service software or applications, such as services or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 520 may be, but is not limited to, a free and open-source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark") which can leverage distributed file system 528 for large-scale data processing (e.g., "big data"). In at least one embodiment, job scheduler 532 may include Spark drivers to facilitate the scheduling of workloads supported by the various layers of data center 500. In at least one embodiment, configuration manager 524 may be able to configure different layers, such as software layer 530 and framework layer 520 including Spark and distributed file system 528 for supporting large-scale data processing. In at least one embodiment, resource manager 526 is capable of managing cluster or group computing resources mapped to or allocated to support distributed file system 528 and job scheduler 522. In at least one embodiment, cluster or group computing resources may include group computing resources 514 on data center infrastructure layer 510. In at least one embodiment, resource manager 526 may coordinate with resource coordinator 512 to manage these mapped or allocated computing resources.

[0065] In at least one embodiment, the software 532 included in the software layer 530 may include software used by at least a portion of nodes CR 516(1)-516(N), grouped computing resources 514, and / or the distributed file system 528 of the framework layer 520. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0066] In at least one embodiment, one or more applications 542 included in application layer 540 may include one or more types of applications used by at least a portion of nodes CR 516(1)-516(N), grouped computing resources 514, and / or the distributed file system 528 of framework layer 520. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0067] In at least one embodiment, any of the configuration manager 524, resource manager 526, and resource coordinator 512 can perform any number and type of self-modification actions based on any amount and type of data acquired in any technically feasible manner. In at least one embodiment, self-modification actions can mitigate potentially poor configuration decisions by data center operators of data center 500 and can prevent underutilization and / or poor performance of the data center.

[0068] In at least one embodiment, data center 500 may include tools, services, software, or other resources to train one or more machine learning models or to use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model can be trained by calculating weight parameters based on a neural network architecture using the software and computing resources described above with respect to data center 500. In at least one embodiment, information can be inferred or predicted using trained machine learning models corresponding to one or more neural networks using the resources described above with respect to data center 500 by using weight parameters calculated through one or more training techniques described herein.

[0069] In at least one embodiment, the data center may use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to utilize the aforementioned resources to perform training and / or inference. Furthermore, one or more of the aforementioned software and / or hardware resources may be configured as a service to allow a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0070] Inference and / or training logic 315 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 3A and / or Figure 3BDetails are provided regarding the inference and / or training logic 315. In at least one embodiment, the inference and / or training logic 315 can be in the system. Figure 5 It is used in the context of reasoning or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0071] Autonomous vehicles Figure 6A An example of an autonomous vehicle 600 according to at least one embodiment is shown. In at least one embodiment, the autonomous vehicle 600 (which may alternatively be referred to herein as "vehicle 600") may be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle capable of accommodating one or more passengers. In at least one embodiment, vehicle 600 may be a semi-tractor-trailer for hauling goods. In at least one embodiment, vehicle 600 may be an aircraft, robotic vehicle, or other type of vehicle.

[0072] Autonomous vehicles can be described according to the levels of automation defined by the National Highway Traffic Safety Administration (“NHTSA”) and the Society of Automotive Engineers (“SAE”) of the U.S. Department of Transportation in their “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., standard number J3016-201806, published June 15, 2018; standard number J3016-201609, published September 30, 2016; and previous and future versions of this standard). In at least one embodiment, vehicle 600 may be able to function according to one or more of the levels of autonomous driving from Level 1 to Level 5. For example, in at least one embodiment, vehicle 600 may be able to perform conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5).

[0073] In at least one embodiment, vehicle 600 may include, but is not limited to, components such as chassis, body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other vehicle components. In at least one embodiment, vehicle 600 may include, but is not limited to, propulsion system 650, such as an internal combustion engine, a hybrid powertrain, an all-electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 650 may be connected to the drivetrain of vehicle 600, which may include, but is not limited to, a transmission, to enable propulsion of vehicle 600. In at least one embodiment, propulsion system 650 may be controlled in response to receiving a signal from throttle / accelerator 652.

[0074] In at least one embodiment, when the propulsion system 650 is operating (e.g., when the vehicle 600 is traveling), the steering system 654 (which may include, but is not limited to, a steering wheel) is used to steer the vehicle 600 (e.g., along a desired path or route). In at least one embodiment, the steering system 654 may receive signals from the steering actuator 656. In at least one embodiment, the steering wheel may be optional for fully automated (Level 7) functionality. In at least one embodiment, the brake sensor system 646 may be used to operate the vehicle brakes in response to signals received from the brake actuator 648 and / or brake sensors.

[0075] In at least one embodiment, controller 636 may include, but is not limited to, one or more system-on-chips (“SoCs”). Figure 6A A controller 636 (not shown) and / or a graphics processing unit (“GPU”) provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 600. For example, in at least one embodiment, controller 636 may send signals to operate vehicle braking via brake actuator 648, to operate steering system 654 via one or more steering actuators 656, and to operate propulsion system 650 via one or more throttles / accelerators 652. In at least one embodiment, one or more controllers 636 may include one or more onboard (e.g., integrated) computing devices that process sensor signals and output operating commands (e.g., signals representing commands) to enable autonomous driving and / or assist a driver in driving vehicle 600. In at least one embodiment, one or more controllers 636 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the functions described above, and two or more controllers may handle a single function and / or any combination thereof.

[0076] In at least one embodiment, one or more controllers 636 provide signals for controlling one or more components and / or systems of vehicle 600 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data can be received from sensors, including but not limited to one or more Global Navigation Satellite System (“GNSS”) sensors 658 (e.g., one or more Global Positioning System sensors), one or more RADAR sensors 660, one or more ultrasonic sensors 662, one or more LIDAR sensors 664, one or more inertial measurement unit (IMU) sensors 666 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 696, one or more stereo cameras 668, one or more wide-angle cameras 670 (e.g., fisheye cameras), one or more infrared cameras 672, one or more surround cameras 674 (e.g., 360-degree cameras), and remote cameras (…). Figure 6A (not shown in the image), medium-range camera ( Figure 6A (Not shown in the diagram) One or more speed sensors 644 (e.g., for measuring the speed of vehicle 600), one or more vibration sensors 642, one or more steering sensors 640, one or more brake sensors (e.g., as part of brake sensor system 646) and / or other sensor types are received.

[0077] In at least one embodiment, one or more controllers 636 may receive input (e.g., represented by input data) from the dashboard 632 of the vehicle 600 and provide output (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 634, a voice signaler, a speaker, and / or other components of the vehicle 600. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high-definition map). Figure 6A The HMI display 634 may display information such as (not shown in the image), location data (e.g., the location of vehicle 600, for example, on a map), direction, the location of other vehicles (e.g., occupancy raster), information about objects, and the state of objects sensed by one or more controllers 636. For example, in at least one embodiment, the HMI display 634 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving operations that have been, are being, or will be made (e.g., changing lanes now, exiting exit 36B within two miles, etc.).

[0078] In at least one embodiment, vehicle 600 further includes a network interface 624 that can communicate via one or more networks using one or more wireless antennas 626 and / or one or more modems. For example, in at least one embodiment, network interface 624 may be able to communicate via Long Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multicarrier (“CDMA2000”) networks, etc. In at least one embodiment, one or more wireless antennas 626 may also enable communication between objects in the environment (e.g., vehicles, mobile devices) using one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (hereinafter referred to as “LPWAN”) (e.g., LoRaWAN, SigFox, etc. protocols).

[0079] Inference and / or training logic 315 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 3A and / or Figure 3B Details are provided regarding the inference and / or training logic 315. In at least one embodiment, the inference and / or training logic 315 can be in the system. Figure 6A The operation is used to infer or predict based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0080] Figure 6B The illustration shows an embodiment according to at least one of the embodiments. Figure 6A Examples of camera positions and fields of view for an autonomous vehicle 600. In at least one embodiment, the camera and its respective field of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different positions on the vehicle 600.

[0081] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera suitable for use with components and / or systems of vehicle 600. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level (“ASIL”) B and / or other ASILs. In at least one embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc. In at least one embodiment, the camera may be able to use a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red-to-clear (“RCCC”) color filter array, a red-to-clear-blue (“RCCB”) color filter array, a red-blue-green (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensor (“RGGB”) color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, a transparent pixel camera, such as a camera with RCCC, RCCB, and / or RBGC color filter arrays, may be used to improve photosensitivity.

[0082] In at least one embodiment, one or more cameras may be used to perform advanced driver assistance system (“ADAS”) functions (e.g., as part of a redundancy or fail-safe design). For example, in at least one embodiment, a multi-function mono camera may be installed to provide functions including lane departure warning, traffic sign assist, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).

[0083] In at least one embodiment, one or more cameras may be mounted in a mounting assembly, such as a custom-designed (three-dimensional (“3D” printed) assembly, to cut out stray light and reflections within the vehicle 600 (e.g., reflections from the dashboard in the windshield mirror), which may interfere with the camera’s image data capture capabilities. Regarding the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly may be 3D printed custom-made such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras may be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras may also be integrated within four pillars at each corner of the cabin.

[0084] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view including a portion of the environment in front of the vehicle 600 can be used for surround view and, with the assistance of one or more controllers 636 and / or control SoCs, to help identify forward paths and obstacles, thereby providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, the forward-facing camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions (e.g., traffic sign recognition).

[0085] In at least one embodiment, various cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS (“Complementary Metal-Oxide-Semiconductor” color imager. In at least one embodiment, a wide-angle camera 670 can be used to sense objects entering from the periphery (e.g., pedestrians, people crossing the street, or bicycles). Although in Figure 6B Only one wide-angle camera 670 is shown; however, in other embodiments, the vehicle 600 may have any number (including zero) of wide-angle cameras. In at least one embodiment, any number of remote cameras 698 (e.g., a pair of remote stereo cameras) can be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, the remote camera 698 can also be used for object detection and classification, as well as basic object tracking.

[0086] In at least one embodiment, any number of stereo cameras 668 may also be included in the forward configuration. In at least one embodiment, one or more stereo cameras 668 may include an integrated control unit comprising a scalable processing unit that may provide programmable logic (“FPGA”) and a multi-core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of the vehicle 600, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 668 may include, but are not limited to, a compact stereo vision sensor, which may include, but is not limited to, two camera lenses (one on the left and one on the right) and an image processing chip that can measure the distance from the vehicle 600 to a target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 668 may also be used in addition to those described herein.

[0087] In at least one embodiment, a camera (e.g., a side-view camera) having a field of view including a portion of the environment on the side of the vehicle 600 can be used for surround viewing, thereby providing information for creating and updating the occupied grid, and generating a side collision warning. For example, in at least one embodiment, a surround camera 674 (e.g., as...) Figure 6B The four surround cameras shown can be positioned on vehicle 600. In at least one embodiment, one or more surround cameras 674 can include, but are not limited to, any number and combination of wide-angle cameras, one or more fisheye lenses, one or more 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye lens cameras can be located at the front, rear, and sides of vehicle 600. In at least one embodiment, vehicle 600 can use three surround cameras 674 (e.g., left, right, and rear) and can utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera.

[0088] In at least one embodiment, a camera (e.g., a rear-view camera) having a field of view including a portion of the environment behind the vehicle 600 can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy raster. In at least one embodiment, a wide variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 698 and / or one or more mid-range cameras 676, one or more stereo cameras 668, one or more infrared cameras 672, etc.), as described herein.

[0089] Inference and / or training logic 315 is used to perform inference and / or training operations associated with one or more embodiments. Figure 3A and / or Figure 3B This document provides details regarding inference and / or training logic 315. In at least one embodiment, inference and / or training logic 315 may be... Figure 6B Used in systems for reasoning or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0090] Figure 6C The illustration shows an embodiment according to at least one of the embodiments. Figure 6A A block diagram of an example system architecture for an autonomous vehicle 600. In at least one embodiment, Figure 6CEach of one or more components, one or more features, and one or more systems of vehicle 600 is shown as connected via bus 602. In at least one embodiment, bus 602 may include, but is not limited to, a CAN data interface (which may alternatively be referred to herein as “CAN bus”). In at least one embodiment, CAN may be a network within vehicle 600 used to help control various features and functions of vehicle 600, such as brake actuation, acceleration, braking, steering, windshield wipers, etc. In one embodiment, bus 602 may be configured to have dozens or even hundreds of nodes, each node having its own unique identifier (e.g., CAN ID). In at least one embodiment, bus 602 can be read to find steering wheel angle, ground speed, engine rotation speed (“RPM”), button position, and / or other vehicle status indicators. In at least one embodiment, bus 602 may be an ASIL B compliant CAN bus.

[0091] In at least one embodiment, FlexRay and / or Ethernet protocols may be used in addition to or from CAN. In at least one embodiment, there may be any number of molded buses 602, which may include, but are not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for a collision avoidance function, and a second bus may be used for actuation control. In at least one embodiment, each of the buses 602 may communicate with any component of the vehicle 600, and two or more buses 602 may communicate with corresponding components. In at least one embodiment, each of any number of System-on-Chip (“SoC”) 604 (e.g., SoC 604(A) and SoC 604(B)), each of one or more controllers 636, and / or each computer within the vehicle may access the same input data (e.g., input from sensors of the vehicle 600) and may be connected to a common bus, such as a CAN bus.

[0092] In at least one embodiment, vehicle 600 may include one or more controllers 636, such as those described herein. Figure 6A As described above. In at least one embodiment, controller 636 can be used for a variety of functions. In at least one embodiment, controller 636 can be coupled to any of various other components and systems of vehicle 600, and can be used to control vehicle 600, artificial intelligence of vehicle 600, infotainment and / or other functions of vehicle 600.

[0093] In at least one embodiment, vehicle 600 may include any number of SoCs 604. In at least one embodiment, each of the SoCs 604 may include, but is not limited to, a central processing unit (“one or more CPUs”) 606, a graphics processing unit (“one or more GPUs”) 608, one or more processors 610, one or more caches 612, one or more accelerators 614, one or more data storage 616, and / or other components and features not shown. In at least one embodiment, one or more SoCs 604 may be used to control vehicle 600 on various platforms and systems. For example, in at least one embodiment, one or more SoCs 604 may be combined with a high-definition (“HD”) map 622 in a system (e.g., the system of vehicle 600), the HD map 622 being accessible from one or more servers via a network interface 624. Figure 6C (Not shown in the image) Get map refresh and / or update.

[0094] In at least one embodiment, one or more CPUs 606 may include CPU clusters or CPU complexes (which may alternatively be referred to herein as “CCPLEX”). In at least one embodiment, one or more CPUs 606 may include multiple cores and / or a secondary (“L2”) cache. For example, in at least one embodiment, one or more CPUs 606 may include eight cores in an intercoupled multiprocessor configuration. In at least one embodiment, one or more CPUs 606 may include four dual-core clusters, each with a dedicated L2 cache (e.g., 2MB L2 cache). In at least one embodiment, one or more CPUs 606 (e.g., CCPLEX) may be configured to support simultaneous cluster operation, such that any combination of clusters of one or more CPUs 606 can be active at any given time.

[0095] In at least one embodiment, one or more CPUs 606 may implement power management functions, including but not limited to one or more of the following features: automatic clock gating of individual hardware modules to conserve dynamic power when idle; clock gating of each core when the core is not actively executing instructions due to executing Wait for Interrupt (“WFI”) / Event Wait (“WFE”) instructions; independent power supply for each core; independent clock gating for each core cluster when all cores are clock-gated or power-gated; and / or independent power gating for each core cluster when all cores are power-gated. In at least one embodiment, one or more CPUs 606 may further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power state for cores, clusters, and CCPLEX inputs. In at least one embodiment, the processing core may support a simplified power state input sequence in software, wherein the work is offloaded to the microcode.

[0096] In at least one embodiment, one or more GPUs 608 may include integrated GPUs (or “iGPUs” herein). In at least one embodiment, one or more GPUs 608 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 608 may use an enhanced tensor instruction set. In one embodiment, one or more GPUs 608 may include one or more streaming microprocessors, wherein each streaming microprocessor may include a Level 1 (“L1”) cache (e.g., an L1 cache with at least 116 KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with 712 KB of storage capacity). In at least one embodiment, one or more GPUs 608 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 608 may use a computation application programming interface (API). In at least one embodiment, one or more GPUs 608 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA’s CUDA model).

[0097] In at least one embodiment, one or more GPU 608s may be power-optimized for optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPU 608s may be fabricated on FinFET (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores divided into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores may be divided into four processing blocks. In at least one embodiment, each processing block may be allocated 18 FP32 cores, 10 FP64 cores, 18 INT32 cores, two mixed-precision NVIDIA Tensor cores for deep learning matrix arithmetic, a level-zero (“L0”) instruction cache, a thread bundle scheduler, a dispatch unit, and / or an 84 KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths to provide efficient execution of workloads that mix computation and addressing operations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0098] In at least one embodiment, one or more GPUs 608 may include high-bandwidth memory (“HBM”) and / or an 18 GB HBM2 memory subsystem to provide a peak storage bandwidth of approximately 1100 GB / s in some examples. In at least one embodiment, in addition to or instead of HBM memory, synchronous graphics random access memory (“SGRAM”), such as graphics double data rate type five synchronous random access memory (“GDDR5”), may be used.

[0099] In at least one embodiment, one or more GPUs 608 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support can be used to allow one or more GPUs 608 to directly access the page tables of one or more CPUs 606. In at least one embodiment, when a memory management unit (“MMU”) of one or more GPUs 608 experiences a miss, an address translation request can be sent to one or more CPUs 606. In response, in at least one embodiment, two CPUs of one or more CPUs 606 can look up the virtual-physical mapping of the address in their page tables and transfer the translation back to one or more GPUs 608. In at least one embodiment, unified memory technology can allow a single unified virtual address space to be used for the memory of both one or more CPUs 606 and one or more GPUs 608, thereby simplifying the programming of one or more GPUs 608 and the porting of applications to one or more GPUs 608.

[0100] In at least one embodiment, one or more GPUs 608 may include any number of access counters that can track the frequency of memory accesses by one or more GPUs 608 to other processors. In at least one embodiment, one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the pages most frequently, thereby improving the efficiency of shared memory ranges between processors.

[0101] In at least one embodiment, one or more SoCs 604 may include any number of caches 612, including those described herein. For example, in at least one embodiment, one or more caches 612 may include a Level 3 (“L3”) cache available for one or more CPUs 606 and one or more GPUs 608 (e.g., connected to CPUs 606 and GPUs 608). In at least one embodiment, one or more caches 612 may include a write-back cache that can, for example, track the state of a line using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, although a smaller cache size may be used, according to embodiments, the L3 cache may include 6 MB of memory or more.

[0102] In at least one embodiment, one or more SoCs 604 may include one or more accelerators 614 (e.g., hardware accelerators, software accelerators, or combinations thereof). In at least one embodiment, one or more SoCs 604 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 6MB of SRAM) enables the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 608 and offload some tasks from one or more GPUs 608 (e.g., freeing up more cycles from one or more GPUs 608 to perform other tasks). In at least one embodiment, one or more accelerators 614 may be used for a target workload (e.g., perceptual, convolutional neural network (“CNN”), recurrent neural network (“RNN”), etc.) that is sufficiently stable to withstand acceleration testing. In at least one embodiment, the CNN may include region-based or region convolutional neural networks (“RCNN”) and fast RCNN (e.g., for object detection) or other types of CNNs.

[0103] In at least one embodiment, one or more accelerators 614 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more Tensor Processing Units (“TPUs”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized for performing image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, one or more DLAs may be further optimized for specific sets of neural network types and floating-point operations and inference. In at least one embodiment, one or more DLAs are designed to provide higher performance per millimeter than typical general-purpose GPUs and typically significantly outperform CPUs. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions supporting, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can execute neural networks, particularly CNNs, quickly and efficiently on processed or unprocessed data for any of the various functions, including, but not limited to: CNNs for object recognition and detection using data from camera sensors; CNNs for distance estimation using data from camera sensors; CNNs for emergency vehicle detection, recognition, and identification using data from microphones; CNNs for face recognition and vehicle owner recognition using data from camera sensors; and / or CNNs for safety and / or safety-related events.

[0104] In at least one embodiment, the DLA can perform any function of one or more GPUs 608, and by using an inference accelerator, for example, the designer can target one or more DLAs or one or more GPUs 608 for any function. For example, in at least one embodiment, the designer can concentrate the CNN processing and floating-point operations on one or more DLAs, leaving other functions to one or more GPUs 608 and / or one or more accelerators 614.

[0105] In at least one embodiment, one or more accelerators 614 may include programmable vision accelerators (“PVAs”), which may alternatively be referred to herein as computer vision accelerators. In at least one embodiment, one or more PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 638, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, one or more PVAs may strike a balance between performance and flexibility. For example, in at least one embodiment, each of one or more PVAs may include, for example, but not limited to, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0106] In at least one embodiment, the RISC core can interact with an image sensor (e.g., the image sensor of any camera described herein), an image signal processor, etc. In at least one embodiment, each RISC core may include any number of memories. In at least one embodiment, the RISC core may use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core may execute a real-time operating system (“RTOS”). In at least one embodiment, the RISC core may be implemented using one or more integrated circuit devices, application-specific integrated circuits (“ASICs”), and / or storage devices. For example, in at least one embodiment, the RISC core may include an instruction cache and / or tightly coupled RAM.

[0107] In at least one embodiment, DMA enables components of the PVA to access system memory independently of one or more CPUs 606. In at least one embodiment, DMA can support any number of features for providing optimization to the PVA, including but not limited to, support for multidimensional addressing and / or circular addressing. In at least one embodiment, DMA can support up to six or more addressing dimensions, which may include, but are not limited to, block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0108] In at least one embodiment, the vector processor may be a programmable processor designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may serve as the main processing engine of the PVA and may include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core may include a digital signal processor, such as a Single Instruction Multiple Data (“SIMD”) or Very Long Instruction Word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can improve throughput and speed.

[0109] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute general-purpose computer vision algorithms, except on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on a single image, or even execute different algorithms on a sequence of images or portions of images. In at least one embodiment, among others, any number of PVAs may be included in the hardware-accelerated cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error-correcting code (“ECC”) memory to enhance overall system security.

[0110] In at least one embodiment, one or more accelerators 614 may include an on-chip computer vision network and static random access memory (“SRAM”) for providing high-bandwidth, low-latency SRAM to one or more accelerators 614. In at least one embodiment, the on-chip memory may include at least 6 MB of SRAM, comprising, for example, but not limited to, eight field-configurable memory blocks accessible to both the PVA and DLA. In at least one embodiment, each pair of memory blocks may include an Advanced Peripheral Bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and DLA may access the memory via a backbone providing high-speed access to the memory for both the PVA and DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and DLA to the memory (e.g., using an APB).

[0111] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / addresses / data, as well as bursty communication for continuous data transmission. In at least one embodiment, although other standards and protocols may be used, the interface may conform to the International Organization for Standardization (“ISO”) 28262 or the International Electrotechnical Commission (“IEC”) 81508 standard.

[0112] In at least one embodiment, one or more SoCs 604 may include a real-time eye-tracking hardware accelerator. In at least one embodiment, the real-time eye-tracking hardware accelerator may be used to quickly and efficiently determine the location and extent of an object (e.g., within a world model) to generate real-time visualization simulations for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for SONAR system simulation, for general wave propagation simulation, for comparison with LIDAR data for localization and / or other functions, and / or for other purposes.

[0113] In at least one embodiment, one or more accelerators 614 have broad applications for autonomous driving. In at least one embodiment, PVA can be used in critical processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of PVA with low power consumption and low latency are well-matched to algorithmic domains requiring predictable processing. In other words, PVA performs well in semi-intensive or intensive conventional computations, even on small datasets that may require predictable runtimes with low latency and low power consumption. In at least one embodiment, such as in vehicle 600, PVA may be designed to run classical computer vision algorithms, as they are efficient in object detection and integer mathematical operations.

[0114] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use dynamic estimation / stereo matching (e.g., structure recovery from motion, pedestrian recognition, lane detection, etc.) during operation. In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0115] In at least one embodiment, the PVA can be used to perform intensive optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using a 6D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0116] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, but not limited to, neural networks whose output is used for a confidence score for each object detection. In at least one embodiment, the confidence score can be represented or interpreted as a probability, or as providing a relative “weight” for each detection relative to other detections. In at least one embodiment, the confidence score measurement enables the system to make further decisions about which detections should be considered true positives rather than false positives. In at least one embodiment, the system can set a threshold for the confidence score and only consider detections exceeding the threshold as true positives. In embodiments using an Automatic Emergency Braking (“AEB”) system, false positives would cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence score value. In at least one embodiment, the neural network may take at least a subset of parameters as its input, such as bounding box size, obtained ground plane estimate (e.g., from another subsystem), and outputs of one or more IMU sensors 666 related to the vehicle 600 orientation, distance, and 3D position estimate of the object obtained from the neural network and / or other sensors (e.g., one or more LiDAR sensors 664 or one or more RADAR sensors 660).

[0117] In at least one embodiment, one or more SoCs 604 may include one or more data storage devices 616 (e.g., memory). In at least one embodiment, one or more data storage devices 616 may be on-chip memory of one or more SoCs 604, which may store neural networks to be executed on one or more GPUs 608 and / or DLAs. In at least one embodiment, one or more data storage devices 616 may have a sufficiently large capacity to store multiple instances of the neural network for redundancy and security. In at least one embodiment, one or more data storage devices 616 may include L2 or L3 caches.

[0118] In at least one embodiment, one or more SoCs 604 may include any number of processors 610 (e.g., embedded processors). In at least one embodiment, one or more processors 610 may include a startup and power management processor, which may be a dedicated processor and subsystem to handle startup power and management functions, as well as associated security implementations. In at least one embodiment, the startup and power management processor may be part of a startup sequence of one or more SoCs 604s and may provide runtime power management services. In at least one embodiment, the startup power and management processor may provide clock and voltage programming, assist system low-power state transitions, thermal and temperature sensor management of one or more SoCs 604s, and / or power state management of one or more SoCs 604s. In at least one embodiment, each temperature sensor may be implemented with its output frequency proportional to temperature, and one or more SoCs 604s may use the ring oscillator to detect the temperature of one or more CPUs 606s, one or more GPUs 608s, and / or one or more accelerators 614s. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the startup and power management processor may enter a temperature fault routine and place one or more SoCs 604s into a lower power state and / or place the vehicle 600 into a driver’s safe stopping pattern (e.g., bring the vehicle 600 to a safe stop).

[0119] In at least one embodiment, one or more processors 610 may further include a set of embedded processors that can serve as an audio processing engine. The audio processing engine may be an audio subsystem capable of providing full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core with a digital signal processor featuring dedicated RAM.

[0120] In at least one embodiment, one or more processors 610 may further include an always-on processor engine that can provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the processor on the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, peripheral support devices (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0121] In at least one embodiment, one or more processors 610 may further include a secure clustering engine, which includes, but is not limited to, a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the secure clustering engine may include, but is not limited to, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and / or routing logic. In secure mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 610 may further include a real-time camera engine, which may include, but is not limited to, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 610 may further include a high dynamic range signal processor, which may include, but is not limited to, an image signal processor, which is a hardware engine as part of the camera processing pipeline.

[0122] In at least one embodiment, one or more processors 610 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions required by the video playback application to produce the final image for the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 670, one or more surround cameras 674, and / or one or more cabin monitoring camera sensors. In at least one embodiment, preferably, the cabin monitoring camera sensors are monitored by a neural network running on another instance of the SoC 604, the neural network being configured to recognize cabin events and respond accordingly. In at least one embodiment, the cabin system may perform, but is not limited to, lip reading to activate cellular service and make phone calls, instruct emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web browsing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, and are otherwise disabled.

[0123] In at least one embodiment, the video image synthesizer may include enhanced temporal denoising for simultaneous spatial and temporal denoising. For example, in at least one embodiment, when motion occurs in the video, denoising appropriately weights spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, when the image or a portion of the image does not contain motion, temporal denoising performed by the video image synthesizer may use information from previous images to reduce noise in the current image.

[0124] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic correction on the input stereo lens frames. In at least one embodiment, when using an operating system desktop, the video image compositor can also be used for user interface compositing and does not require one or more GPUs 608 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 608 are powered and actively performing 3D rendering, the video image compositor can be used to offload one or more GPUs 608 to improve performance and responsiveness.

[0125] In at least one embodiment, one or more SoCs of SoC 604 may further include a Mobile Industrial Processor Interface (“MIPI”) camera serial interface, a high-speed interface, and / or a video input block that can be used for receiving video and input from a camera and associated pixel input functions. In at least one embodiment, one or more SoCs of SoC 604 may further include an input / output controller that can be software controlled and can be used to receive I / O signals not assigned to a specific role.

[0126] In at least one embodiment, one or more SoCs of SoC 604 may further include extensive peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders (“codecs”), power management and / or other devices. In at least one embodiment, one or more SoCs of SoC 604 may be used to process data from (e.g., connected via gigabit multimedia serial links and Ethernet channels) cameras, sensors (e.g., one or more LiDAR sensors 664, one or more RADAR sensors 660, etc., which may be connected via Ethernet channels), data from bus 602 (e.g., vehicle 600 speed, steering wheel position, etc.), data from one or more GNSS sensors 658 (e.g., connected via Ethernet bus or CAN bus), etc. In at least one embodiment, one or more SoCs of SoC 604 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and may be used to free one or more CPUs of SoC 606 from routine data management tasks.

[0127] In at least one embodiment, one or more SoCs 604 can be an end-to-end platform with a flexible architecture spanning automation levels 3-5, providing a comprehensive functional safety architecture that leverages and effectively utilizes computer vision and ADAS technologies to achieve diversity and redundancy. This provides a platform offering a flexible and reliable driving software stack as well as deep learning tools. In at least one embodiment, one or more SoCs 604 can be faster, more reliable, and even more energy and space efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 614, when combined with one or more CPUs 606, one or more GPUs 608, and one or more data storage devices 616, can provide a fast and efficient platform for Level 3-5 autonomous vehicles.

[0128] In at least one embodiment, the computer vision algorithm can be executed on a CPU, which can be configured using a high-level programming language (e.g., C) to execute multiple processing algorithms on a variety of visual data. However, in at least one embodiment, the CPU typically cannot meet the performance requirements of many computer vision applications, such as performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real time, which are used in automotive ADAS applications and practical Level 3-5 autonomous vehicles.

[0129] The embodiments described herein allow multiple neural networks to be executed simultaneously and / or sequentially, and allow the results to be combined to achieve Level 3-5 autonomous driving capabilities. For example, in at least one embodiment, a CNN executed on a DLA or discrete GPU (e.g., one or more GPUs 620) may include text and word recognition, thereby allowing a supercomputer to read and understand traffic signs, including signs for which the neural network has not yet been specifically trained. In at least one embodiment, the DLA may also include a neural network capable of recognizing, interpreting, and providing semantic understanding of symbols, and passing this semantic understanding to a path planning module running on a CPU Complex.

[0130] In at least one embodiment, for drives of levels 3, 4, or 5, multiple neural networks can run simultaneously. For example, in at least one embodiment, a warning sign consisting of a light bulb accompanied by the warning sign “Caution: flashing lights indicate icy conditions” can be interpreted independently or jointly by multiple neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text “flashing lights indicate icy conditions” can be interpreted by a second deployed neural network, which informs the vehicle’s path planning software (preferably executed on a CPU Complex) that icing conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network across multiple frames, informing the vehicle’s path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within a DLA and / or on one or more GPUs 608.

[0131] In at least one embodiment, the CNN for facial recognition and vehicle owner identification can use data from camera sensors to identify the presence of an authorized driver and / or the owner of vehicle 600. In at least one embodiment, a normally open sensor processor engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in security mode, can be used to disable the vehicle when the owner leaves it. In this way, one or more SoCs 604 provide protection against theft and / or carjacking.

[0132] In at least one embodiment, the CNN for emergency vehicle detection and identification can use data from microphone 696 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 604 use the CNN to classify environmental and urban sounds, as well as visual data. In at least one embodiment, the CNN running on DLA is trained to identify the relative approach speed of emergency vehicles (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles in the area where the vehicle is operating, as identified by one or more GNSS sensors 658. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while in North America, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used, with the assistance of one or more ultrasonic sensors 662, to execute emergency vehicle safety routines, slow the vehicle, pull the vehicle to the side of the road, stop, and / or leave the vehicle idle until the emergency vehicle passes.

[0133] In at least one embodiment, vehicle 600 may include one or more CPUs 618 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to one or more SoCs 604 via high-speed interconnects (e.g., PCIe). In at least one embodiment, one or more CPUs 618 may include x86 processors. For example, one or more CPUs 618 may be used to perform any of the various functions, such as arbitrating the results of potential inconsistencies between ADAS sensors and one or more SoCs 604, and / or monitoring the status and health of one or more monitoring controllers 636 and / or on-chip information systems (“information SoCs”) 630.

[0134] In at least one embodiment, vehicle 600 may include one or more GPUs 620 (e.g., one or more discrete GPUs or one or more dGPUs) coupled to one or more SoCs 604 via high-speed interconnects (e.g., NVIDIA's NVLINK channels). In at least one embodiment, one or more GPUs 620 may provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on inputs from sensors of vehicle 600 (e.g., sensor data).

[0135] In at least one embodiment, vehicle 600 may further include a network interface 624, which may include, but is not limited to, one or more wireless antennas 626 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 624 may be used to enable wireless connectivity with other vehicles and / or computing devices (e.g., passenger client devices) via Internet cloud services (e.g., using servers and / or other network devices). In at least one embodiment, for communication with other vehicles, a direct link and / or an indirect link (e.g., via a network and the Internet) may be established between vehicle 600 and another vehicle. In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide a direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 600 with information about vehicles near vehicle 600 (e.g., vehicles in front, to the side, and / or behind vehicle 600). In at least one embodiment, the foregoing functionality may be part of a cooperative adaptive cruise control function of vehicle 600.

[0136] In at least one embodiment, network interface 624 may include a System-on-Chip (SoC) that provides modulation and demodulation functions and enables one or more controllers 636 to communicate over a wireless network. In at least one embodiment, network interface 624 may include a radio frequency (RF) front-end for up-conversion from baseband to radio frequency (RF) and down-conversion from RF to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed using known processes and / or using a superheterodyne process. In at least one embodiment, the RF front-end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functions for communication over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0137] In at least one embodiment, vehicle 600 may further include one or more data storage units 628, which may include, but are not limited to, off-chip (e.g., one or more SoC 604) storage. In at least one embodiment, one or more data storage units 628 may include, but are not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disk and / or other components and / or devices capable of storing at least one bit of data.

[0138] In at least one embodiment, vehicle 600 may further include one or more GNSS sensors 658 (e.g., GPS and / or auxiliary GPS sensors) to assist in map creation, perception, occupancy raster generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 658 may be used, including, for example, but not limited to, GPS sensors connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

[0139] In at least one embodiment, vehicle 600 may further include one or more RADAR sensors 660. In at least one embodiment, one or more RADAR sensors 660 may be used by vehicle 600 for remote vehicle detection, even in dark and / or inclement weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, one or more RADAR sensors 660 may use a CAN bus and / or bus 602 (e.g., to transmit data generated by one or more RADAR sensors 660) for control and access to object tracking data, and in some examples may access an Ethernet channel to access raw data. In at least one embodiment, a wide variety of RADAR sensor types may be used. For example, but not limited to, one or more of the RADAR sensors 660 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more RADAR sensors 660 are pulse Doppler RADAR sensors.

[0140] In at least one embodiment, one or more RADAR sensors 660 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functions. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a 270m range). In at least one embodiment, one or more RADAR sensors 660 can help distinguish between stationary and moving objects and can be used by the ADAS system 638 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more sensors 660 included in the long-range RADAR system may include, but are not limited to, a monostatic multimode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, having six antennas, with the four central antennas creating a focused beammap designed to record the surrounding environment of the vehicle 600 at a high speed while minimizing traffic interference from adjacent lanes. In at least one embodiment, the other two antennas can expand the field of view, thereby enabling rapid detection of vehicles 600 entering or leaving the lane.

[0141] In at least one embodiment, as an example, a mid-range RADAR system may include, for example, a range of up to 180m (front) or 100m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 660 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that continuously monitor the rearward direction of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system may be used in ADAS system 638 for blind spot detection and / or lane change assistance.

[0142] In at least one embodiment, vehicle 600 may further include one or more ultrasonic sensors 662. In at least one embodiment, one or more ultrasonic sensors 662, which may be positioned at the front, rear, and / or sides of vehicle 600, may be used for parking assistance and / or creating and updating occupancy detectors. In at least one embodiment, a wide variety of ultrasonic sensors 662 may be used, and different ultrasonic sensors 662 may be used for different detection ranges (e.g., 2.5m, 4m). In at least one embodiment, the ultrasonic sensors 662 may operate at ASIL B functional safety level.

[0143] In at least one embodiment, vehicle 600 may include one or more LiDAR sensors 664. In at least one embodiment, the one or more LiDAR sensors 664 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the one or more LiDAR sensors 664 may operate at functional safety level ASIL B. In at least one embodiment, vehicle 600 may include multiple (e.g., two, four, six, etc.) LiDAR sensors 664 that can use Ethernet channels (e.g., providing data to a Gigabit Ethernet switch).

[0144] In at least one embodiment, one or more LiDAR sensors 664 may be able to provide a list of objects and their distances for a 360-degree field of view. In at least one embodiment, one or more commercially available LiDAR sensors 664 may, for example, have an advertising range of approximately 120m, an accuracy of 2cm-3cm, and support a 120Mbps Ethernet connection. In at least one embodiment, one or more non-protruding LiDAR sensors may be used. In such an embodiment, one or more LiDAR sensors 664 may include small devices that can be embedded in the front, rear, side, and / or corner locations of a vehicle 600. In at least one embodiment, one or more LiDAR sensors 664, in such an embodiment, can provide a horizontal field of view of up to 140 degrees and a vertical field of view of 35 degrees, even for objects with low reflectivity, and have a range of 220m. In at least one embodiment, one or more forward-facing LiDAR sensors 664 may be configured for a horizontal field of view between 65 and 155 degrees.

[0145] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200m around the vehicle 600. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and reflected light on each pixel, which in turn corresponds to the range from the vehicle 600 to the object. In at least one embodiment, flash LIDAR can allow the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one on each side of the vehicle 600. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use a 5-nanosecond Class I (eye-safe) laser pulse per frame and can capture reflected laser light as a 3D ranging point cloud and co-registered intensity data.

[0146] In at least one embodiment, vehicle 600 may further include one or more IMU sensors 666. In at least one embodiment, one or more IMU sensors 666 may be located at the center of the rear axle of vehicle 600. In at least one embodiment, one or more IMU sensors 666 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, a magnetic compass, multiple magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, one or more IMU sensors 666 may include, but are not limited to, accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, one or more IMU sensors 666 may include, but are not limited to, accelerometers, gyroscopes, and magnetometers.

[0147] In at least one embodiment, one or more IMU sensors 666 may be implemented as a miniature, high-performance GPS-assisted inertial navigation system (“GPS / INS”) combining a microelectromechanical system (“MEMS”) inertial sensor, a high-sensitivity GPS receiver, and an advanced Kalman filtering algorithm to provide position, velocity, and attitude estimations; in at least one embodiment, one or more IMU sensors 666 may enable vehicle 600 to estimate heading without input from a magnetic sensor obtained by directly observing and correlating velocity changes from GPS to one or more IMU sensors 666. In at least one embodiment, one or more IMU sensors 666 and one or more GNSS sensors 658 may be combined in a single integrated unit.

[0148] In at least one embodiment, vehicle 600 may include one or more microphones 696 placed inside and / or around vehicle 600. In at least one embodiment, in addition, one or more microphones 696 may be used for emergency vehicle detection and identification.

[0149] In at least one embodiment, vehicle 600 may further include any number of camera types, including one or more stereo cameras 668, one or more wide-angle cameras 670, one or more infrared cameras 672, one or more surround cameras 674, one or more long-range cameras 698, one or more mid-range cameras 676, and / or other camera types. In at least one embodiment, the cameras can be used to capture image data around the entire perimeter of vehicle 600. In at least one embodiment, the type of camera used depends on vehicle 600. In at least one embodiment, any combination of camera types can be used to provide the necessary coverage around vehicle 600. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, vehicle 600 may include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. In at least one embodiment, the cameras may be, by way of example but not limited to, supporting Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet communication. In at least one embodiment, previously referenced herein... Figure 6A and Figure 6B Each camera can be described in more detail.

[0150] In at least one embodiment, vehicle 600 may further include one or more vibration sensors 642. In at least one embodiment, one or more vibration sensors 642 may measure vibrations of components of vehicle 600 (e.g., axles). For example, in at least one embodiment, changes in vibration may indicate changes in road surface. In at least one embodiment, when two or more vibration sensors 642 are used, differences between vibrations may be used to determine road surface friction or slippage (e.g., when there is a vibration difference between a power drive axle and a free-rotating axle).

[0151] In at least one embodiment, vehicle 600 may include ADAS system 638. In at least one embodiment, ADAS system 638 may include, but is not limited to, SoC. In at least one embodiment, ADAS system 638 may include, but is not limited to, any number of autonomous / adaptive / automatic cruise control (“ACC”) systems, cooperative adaptive cruise control (“CACC”) systems, forward collision warning (“FCW”) systems, automatic emergency braking (“AEB”) systems, lane departure warning (“LDW”) systems, lane keeping assist (“LKA”) systems, blind spot warning (“BSW”) systems, rear cross traffic warning (“RCTW”) systems, collision warning (“CW”) systems, lane centering (“LC”) systems, and / or other systems, features, and / or functions, and combinations thereof.

[0152] In at least one embodiment, the ACC system may use one or more RADAR sensors 660, one or more LIDAR sensors 664, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle adjacent to vehicle 600 and automatically adjusts the speed of vehicle 600 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance holding and suggests that vehicle 600 change lanes if necessary. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0153] In at least one embodiment, the CACC system uses information from other vehicles, which may be received from other vehicles via network interface 624 and / or one or more wireless antennas 626 via a wireless link or indirectly via a network connection (e.g., via the Internet). In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. Typically, V2V communication provides information about the vehicle immediately preceding it (e.g., a vehicle immediately in front of vehicle 600 and in the same lane as it), while I2V communication provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about vehicles preceding vehicle 600, the CACC system can be more reliable and has the potential to improve traffic flow smoothness and reduce road congestion.

[0154] In at least one embodiment, the FCW system is designed to warn the driver of a hazard so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 660, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to components providing driver feedback, such as a display, speaker, and / or vibration. In at least one embodiment, the FCW system can provide warnings, for example, in the form of audible, visual warnings, vibrations, and / or rapid braking pulses.

[0155] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply brakes if the driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, the AEB system may use one or more forward-facing cameras and / or one or more RADAR sensors 660 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid a collision, and if the driver does not take corrective action, the AEB system may automatically apply brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system may include techniques such as dynamic braking to support and / or brakes for impending collisions.

[0156] In at least one embodiment, when vehicle 600 crosses lane markings, the LDW system provides visual, auditory, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver. In at least one embodiment, the LDW system is inactive when the driver indicates intentional lane departure, such as by activating turn signals. In at least one embodiment, the LDW system may use a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration components. In at least one embodiment, the LKA system is a variant of the LDW system. In at least one embodiment, if vehicle 600 begins to leave the lane, the LKA system provides steering input or braking to correct vehicle 600.

[0157] In at least one embodiment, the BSW system detects and warns the driver of a vehicle in the blind spot. In at least one embodiment, the BSW system can provide visual, auditory, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses the turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 660 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, electrically coupled to driver feedback, such as a display, speaker, and / or vibration assembly.

[0158] In at least one embodiment, the RCTW system can provide visual, auditory, and / or tactile notifications when an object is detected outside the range of the rear camera while the vehicle 600 is reversing. In at least one embodiment, the RCTW system includes an AEB system to ensure the vehicle brakes to avoid a collision. In at least one embodiment, the RCTW system may use one or more rear-facing RADAR sensors 660 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as displays, speakers, and / or vibration components.

[0159] In at least one embodiment, conventional ADAS systems may be prone to generating false alarms, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems warn the driver and allow the driver to determine whether a safe situation truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, vehicle 600 itself decides whether to follow the result of the main computer or the auxiliary computer (e.g., the first or second controller of controller 636). For example, in at least one embodiment, ADAS system 638 may be a backup and / or auxiliary computer for providing perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor may run redundant software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, output from ADAS system 638 may be provided to a monitoring MCU. In at least one embodiment, if output from the main computer and output from the auxiliary computer conflict, the monitoring MCU decides how to reconcile the conflict to ensure safe operation.

[0160] In at least one embodiment, the master computer may be configured to provide a confidence score to the supervisory MCU to indicate the master computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU may follow the master computer's instructions regardless of whether the auxiliary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the master computer and the auxiliary computer indicate different results (e.g., conflict), the supervisory MCU may arbitrate between the computers to determine the appropriate result.

[0161] In at least one embodiment, the supervisory MCU may be configured to run a neural network trained and configured to determine, at least in part, the conditions under which the auxiliary computer provides a false alarm based on outputs from a host computer and an auxiliary computer. In at least one embodiment, the neural network in the supervisory MCU may learn when the outputs of the auxiliary computer can be trusted and when they cannot. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, the neural network in the supervisory MCU may learn when the FCW system identifies a metallic object that is not actually dangerous, such as a drain grating or manhole cover that would trigger an alarm. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU may learn to override the LDW when a cyclist or pedestrian is present and lane departure is actually the safest operation. In at least one embodiment, the supervisory MCU may include at least one of a DLA or GPU suitable for running a neural network with associated memory. In at least one embodiment, the supervisory MCU may include and / or be included as a component of one or more SoC 604s.

[0162] In at least one embodiment, the ADAS system 638 may include an auxiliary computer that performs ADAS functions using conventional computer vision rules. In at least one embodiment, the auxiliary computer may use classic computer vision rules (if-then), and the presence of a neural network in the supervisory MCU can improve reliability, security, and performance. For example, in at least one embodiment, diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if a software vulnerability or bug exists in the software running on the host computer, and different software code running on the auxiliary computer provides consistent overall results, the supervisory MCU can more confidently assume that the overall result is correct and that the vulnerability in the software or hardware on the host computer will not lead to a significant error.

[0163] In at least one embodiment, the output of the ADAS system 638 can be input to the perception module and / or the dynamic driving task module of the host computer. For example, in at least one embodiment, if the ADAS system 638 indicates a forward collision warning due to an object directly ahead, the perception block can use this information when identifying the object. In at least one embodiment, as described herein, the assistance computer can have its own neural network trained to reduce the risk of false alarms.

[0164] In at least one embodiment, vehicle 600 may further include an infotainment SoC 630 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system SoC 630 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 630 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming media, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.) and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total coverage distance, brake fuel level, fuel level, door opening / closing, air filter information, etc.) to vehicle 600. For example, the infotainment SoC 630 may include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, automobile, in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, head-up display (“HUD”), HMI display 634, telematics device, control panel (e.g., for controlling and / or interacting with various components, features and / or systems) and / or other components. In at least one embodiment, the infotainment SoC 630 may further be used to provide information (e.g., visual and / or auditory) to a user of vehicle 600, such as information from ADAS system 638, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.) and / or other information.

[0165] In at least one embodiment, the infotainment SoC 630 may include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 630 may communicate with other devices, systems, and / or components of the vehicle 600 via bus 602. In at least one embodiment, the infotainment SoC 630 may be coupled to a monitoring MCU, enabling the GPU of the infotainment system to perform some autonomous driving functions in the event of a failure of the main controller 636 (e.g., the main computer and / or backup computer of the vehicle 600). In at least one embodiment, the infotainment SoC 630 may cause the vehicle 600 to enter a driver-to-safe-stop mode, as described herein.

[0166] In at least one embodiment, vehicle 600 may further include instrument panel 632 (e.g., digital instrument panel, electronic instrument panel, digital instrument control panel, etc.). In at least one embodiment, instrument panel 632 may include, but is not limited to, controllers and / or supercomputers (e.g., discrete controllers or supercomputers). In at least one embodiment, instrument panel 632 may include, but is not limited to, any number and combination of a set of instruments, such as speedometer, fuel level, oil pressure, tachometer, odometer, turn indicator, shift position indicator, one or more seatbelt warning lights, one or more parking brake warning lights, one or more engine malfunction lights, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between infotainment SoC 630 and instrument panel 632. In at least one embodiment, instrument panel 632 may be included as part of infotainment SoC 630, or vice versa.

[0167] Inference and / or training logic 315 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 3A and / or Figure 3B Details are provided regarding the inference and / or training logic 315. In at least one embodiment, the inference and / or training logic 315 can be in the system. Figure 6C The operation is used to infer or predict based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0168] Figure 6D It is based on at least one embodiment in a cloud-based server and Figure 6AA diagram of a system 676 for communication between autonomous vehicles 600. In at least one embodiment, system 676 may include, but is not limited to, one or more servers 678, one or more networks 690, and any number and type of vehicles, including vehicle 600. In at least one embodiment, one or more servers 678 may include, but is not limited to, multiple GPUs 684(A)-684(H) (collectively referred to herein as GPU 684), PCIe switches 682(A)-682(D) (collectively referred to herein as PCIe switch 682), and / or CPUs 680(A)-680(B) (collectively referred to herein as CPU 680). GPU 684, CPU 680, and PCIe switch 682 may be interconnected with high-speed interconnects, such as, but not limited to, NVLink interface 688 developed by NVIDIA and / or PCIe connection 686. In at least one embodiment, GPU 684 is connected via NVLink and / or NVSwitchSoC, and GPU 684 and PCIe switch 682 are connected via PCIe interconnect. Although eight GPUs 684, two CPUs 680, and four PCIe switches 682 are shown, this is not intended to be limiting. In at least one embodiment, each of one or more servers 678 may include, but is not limited to, any combination of any number of GPUs 684, CPUs 680, and / or PCIe switches 682. For example, in at least one embodiment, one or more servers 678 may each include eight, sixteen, thirty-two, and / or more GPUs 684.

[0169] In at least one embodiment, one or more servers 678 may receive image data representing images from vehicles via one or more networks 690, the images showing unexpected or changed road conditions, such as recently started roadworks. In at least one embodiment, one or more servers 678 may transmit updated neural network 692 and / or map information 694, including but not limited to information about traffic and road conditions, to vehicles via one or more networks 690. In at least one embodiment, updates to map information 694 may include, but are not limited to, updates to HD map 622, such as information about construction sites, potholes, sidewalks, floods, and / or other obstacles. In at least one embodiment, neural network 692 and / or map information 694 may be generated from new training and / or experience represented by data received from any number of vehicles in the environment, and / or at least based on training performed in a data center (e.g., using one or more servers 678 and / or other servers).

[0170] In at least one embodiment, one or more servers 678 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. In at least one embodiment, the training data may be generated by the vehicle, and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of training data is labeled and / or preprocessed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 690), and / or the machine learning model may be used by one or more servers 678 to remotely monitor the vehicle.

[0171] In at least one embodiment, one or more servers 678 may receive data from the vehicle and apply the data to state-of-the-art real-time neural networks for real-time intelligent inference. In at least one embodiment, one or more servers 678 may include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 684, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 678 may include a deep learning infrastructure in a data center using CPU power.

[0172] In at least one embodiment, the deep learning infrastructure of one or more servers 678 may be capable of fast, real-time inference and can be used to assess and verify the health of the processor, software, and / or associated hardware in vehicle 600. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 600, such as image sequences and / or objects located by vehicle 600 in the image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them with objects identified by vehicle 600, and if the results do not match and the deep learning infrastructure determines that the AI ​​in vehicle 600 is malfunctioning, one or more servers 678 may signal to vehicle 600 to instruct the fail-safe computer of vehicle 600 to take control, notify passengers, and complete a safe stopping operation.

[0173] In at least one embodiment, one or more servers 678 may include one or more GPUs 684 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 devices). In at least one embodiment, the combination of GPU-driven servers and inference acceleration enables real-time response. In at least one embodiment, for example, where performance is less critical, servers driven by CPUs, FPGAs, and other processors may be used for inference. In at least one embodiment, hardware architecture 315 is used to execute one or more embodiments. This document incorporates... Figure 3A and / or Figure 3B Provide details about the hardware architecture 315.

[0174] Computer System Figure 7 This is a block diagram illustrating an exemplary computer system according to at least one embodiment. The exemplary computer system may be a system with interconnected devices and components, a system-on-a-chip (SoC), or some combination thereof formed with a processor, which may include an execution unit to execute instructions. In at least one embodiment, according to this disclosure, such as the embodiments described herein, computer system 700 may include, but is not limited to, components such as processor 702, whose execution unit includes logic to execute algorithms for process data. In at least one embodiment, computer system 700 may include a processor, such as the PENTIUM® processor family, Xeon™, Itanium®, XScale™ and / or StrongARM™, Intel® Core™ or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs, engineering workstations, set-top boxes, etc.) with other microprocessors may also be used. In at least one embodiment, the computer system 700 may execute a version of the Windows operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0175] The embodiments can be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor (“DSP”), a system-on-a-chip (SoC), a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0176] In at least one embodiment, the computer system 700 may include, but is not limited to, a processor 702, which may include, but is not limited to, one or more execution units 708, to perform machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, the computer system 700 is a single-processor desktop or server system, but in another embodiment, the computer system 700 may be a multiprocessor system. In at least one embodiment, the processor 702 may include, but is not limited to, a Complex Instruction Set Computer (“CISC”) microprocessor, a Reduced Instruction Set Computing (“RISC”) microprocessor, a Very Long Instruction Word (“VLIW”) microprocessor, a processor implementing instruction set combination, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 702 may be coupled to a processor bus 710, which can transmit data signals between the processor 702 and other components in the computer system 700.

[0177] In at least one embodiment, processor 702 may include, but is not limited to, a Level 1 (“L1”) internal cache memory (“cache”) 704. In at least one embodiment, processor 702 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 702. Depending on specific implementation and requirements, other embodiments may also include a combination of internal and external caches. In at least one embodiment, register file 706 may store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0178] In at least one embodiment, an execution unit 708, including but not limited to logic for performing integer and floating-point operations, is also located within the processor 702. In at least one embodiment, the processor 702 may further include a microcode (“ucode”) read-only memory (“ROM”) for storing microcode for certain macro instructions. In at least one embodiment, the execution unit 708 may include logic for processing a packaged instruction set 709. In at least one embodiment, by including the packaged instruction set 709 in the instruction set of a general-purpose processor, along with the associated circuitry for executing the instructions, the packaged data in the processor 702 can be used to perform operations used by numerous multimedia applications. In at least one embodiment, many multimedia applications can be executed more quickly and efficiently by using the full width of the processor’s data bus to perform operations on the packaged data, which may eliminate the need to transfer smaller data units on the processor’s data bus to perform one or more operations on one data element at a time.

[0179] In at least one embodiment, the execution unit 708 may also be used in a microcontroller, embedded processor, graphics device, DSP, and other types of logic circuitry. In at least one embodiment, the computer system 700 may include, but is not limited to, memory 720. In at least one embodiment, memory 720 may be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or another storage device. In at least one embodiment, memory 720 may store instructions 719 and / or data 721 represented by data signals that can be executed by processor 702.

[0180] In at least one embodiment, the system logic chip may be coupled to the processor bus 710 and the memory 720. In at least one embodiment, the system logic chip may include, but is not limited to, a memory controller hub (“MCH”) 716, and the processor 702 may communicate with the MCH 716 via the processor bus 710. In at least one embodiment, the MCH 716 may provide a high-bandwidth memory path 718 to the memory 720 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 716 may initiate data signals between the processor 702, the memory 720, and other components in the computer system 700, and bridge data signals between the processor bus 710, the memory 720, and the system I / O interface 722. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 716 may be coupled to the memory 720 via the high-bandwidth memory path 718, and the graphics / video card 712 may be coupled to the MCH 716 via an Accelerated Graphics Port (“AGP”) interconnect 714.

[0181] In at least one embodiment, the computer system 700 may use the system I / O interface 722 as a proprietary hub interface bus to couple the MCH 716 to the I / O controller hub (“ICH”) 730. In at least one embodiment, the ICH 730 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 720, chipset, and processor 702. Examples may include, but are not limited to, an audio controller 729, a firmware hub (“Flash BIOS”) 728, a wireless transceiver 726, a data storage 724, a conventional I / O controller 723 including a user input and keyboard interface 725, a serial expansion port 727 (e.g., a Universal Serial Bus (USB) port), and a network controller 734. In at least one embodiment, the data storage 724 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0182] In at least one embodiment, Figure 7 A system including interconnected hardware devices or "chips" is shown, while in other embodiments, Figure 7 The SoC can be shown. In at least one embodiment, Figure 7The devices shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of the computer system 700 are interconnected using a Compute Fast Link (CXL) interconnect.

[0183] Inference and / or training logic 315 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 3A and / or Figure 3B Details are provided regarding the inference and / or training logic 315. In at least one embodiment, the inference and / or training logic 315 may be... Figure 7 Used in systems for reasoning or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0184] Figure 8 This is a block diagram illustrating an electronic device 800 for utilizing a processor 810 according to at least one embodiment. In at least one embodiment, the electronic device 800 may be, for example, but not limited to, a laptop computer, tower server, rack server, blade server, laptop computer, desktop computer, tablet computer, mobile device, telephone, embedded computer, or any other suitable electronic device.

[0185] In at least one embodiment, the electronic device 800 may, but is not limited to, a processor 810 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 810 uses a bus or interface coupling, such as an I2C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advanced Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 8 The system shown includes interconnected hardware devices or "chips," while in other embodiments, Figure 8 An exemplary SoC can be shown. In at least one embodiment, Figure 8 The device shown can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 8 One or more components are interconnected using Computational Fast Link (CXL) interconnects.

[0186] In at least one embodiment, Figure 8This may include a display 824, a touchscreen 825, a touchpad 830, a near-field communication unit (“NFC”) 845, a sensor hub 840, a thermal sensor 846, a fast chipset (“EC”) 835, a trusted platform module (“TPM”) 838, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 822, a DSP 860, a drive 820 (e.g., a solid-state drive (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 850, a Bluetooth unit 852, a wireless wide area network unit (“WWAN”) 856, a global positioning system (GPS) unit 855, a camera (“USB 3.0 camera”) 854 (e.g., a USB 3.0 camera), and / or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 815 implemented in, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0187] In at least one embodiment, other components may be communicatively coupled to processor 810 via the components described herein. In at least one embodiment, accelerometer 841, ambient light sensor (“ALS”) 842, compass 843, and gyroscope 844 may be communicatively coupled to sensor hub 840. In at least one embodiment, thermal sensor 839, fan 837, keyboard 836, and touchpad 830 may be communicatively coupled to EC 835. In at least one embodiment, speaker 863, earphone 864, and microphone (“mic”) 865 may be communicatively coupled to audio unit (“audio codec and Class D amplifier”) 862, which in turn may be communicatively coupled to DSP 860. In at least one embodiment, audio unit 862 may include, for example, but not limited to, audio encoder / decoder (“codec”) and Class D amplifier. In at least one embodiment, SIM card (“SIM”) 857 may be communicatively coupled to WWAN unit 856. In at least one embodiment, components such as WLAN unit 850, Bluetooth unit 852, and WWAN unit 856 may be implemented as next-generation form factors (NGFF).

[0188] Inference and / or training logic 315 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 3A and / or Figure 3B Details are provided regarding the inference and / or training logic 315. In at least one embodiment, the inference and / or training logic 315 can be in the system. Figure 8 It is used in the context of reasoning or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0189] Figure 9 A computer system 900 according to at least one embodiment is shown. In at least one embodiment, the computer system 900 is configured to implement various processes and methods described throughout this disclosure.

[0190] In at least one embodiment, the computer system 900 includes, but is not limited to, at least one central processing unit (“CPU”) 902 connected to a communication bus 910 implemented using any suitable protocol, such as PCI (“Peripheral Device Interconnect”), Peripheral Component Interconnect Express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 900 includes, but is not limited to, main memory 904 and control logic (e.g., implemented in hardware, software, or a combination thereof), and data may be stored in main memory 904 in the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“Network Interface”) 922 provides an interface to other computing devices and networks for receiving data using the computer system 900 and transferring data to other systems.

[0191] In at least one embodiment, the computer system 900 includes, but is not limited to, an input device 908, a parallel processing system 912, and a display device 906, which may be implemented using conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light-emitting diode (“LED”) display, plasma display, or other suitable display technologies. In at least one embodiment, user input is received from the input device 908 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the modules described herein may reside on a single semiconductor platform to form the processing system.

[0192] Inference and / or training logic 315 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 3A and / or Figure 3B Details are provided regarding the inference and / or training logic 315. In at least one embodiment, the inference and / or training logic 315 can be in the system. Figure 9 It is used in the context of reasoning or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0193] Figure 10A computer system 1000 according to at least one embodiment is illustrated. In at least one embodiment, the computer system 1000 includes, but is not limited to, a computer 1010 and a USB flash drive 1020. In at least one embodiment, the computer 1010 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, the computer 1010 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0194] In at least one embodiment, the USB flash drive 1020 includes, but is not limited to, a processing unit 1030, a USB interface 1040, and USB interface logic 1050. In at least one embodiment, the processing unit 1030 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1030 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1030 includes an application-specific integrated circuit (“ASIC”) optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1030 is a tensor processing unit (“TPC”) optimized to perform machine learning inference operations. In at least one embodiment, the processing unit 1030 is a vision processing unit (“VPU”) optimized to perform machine vision and machine learning inference operations.

[0195] In at least one embodiment, the USB interface 1040 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, the USB interface 1040 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, the USB interface 1040 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1050 may include any amount and type of logic enabling the processing unit 1030 to connect to a device (e.g., computer 1010) via the USB connector 1040.

[0196] Inference and / or training logic 315 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 3A and / or Figure 3B Details are provided regarding the inference and / or training logic 315. In at least one embodiment, the inference and / or training logic 315 can be in the system. Figure 10 It is used in the context of reasoning or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0197] Figure 11AAn exemplary architecture is shown in which multiple GPUs 1110(1)-1110(N) are communicatively coupled to multiple multi-core processors 1105(1)-1105(M) via high-speed links 1140(1)-1140(N) (e.g., bus / point-to-point interconnect, etc.). In at least one embodiment, the high-speed links 1140(1)-1140(N) support communication throughput of 6GB / s, 32GB / s, 100GB / s, or higher. In at least one embodiment, various interconnect protocols may be used, including but not limited to PCIe 6.0 or 7.0 and NVLink 2.0. In the various figures, “N” and “M” represent positive integers, the values ​​of which may vary from figure to figure.

[0198] Furthermore, in at least one embodiment, two or more GPUs 1110 are interconnected via high-speed links 1129(1)-1129(2), which can be implemented using a protocol / link similar to or different from that used for high-speed links 1140(1)-1140(N). Similarly, two or more multi-core processors 1105 can be connected via high-speed link 1128, which can be a symmetric multiprocessor (SMP) bus operating at speeds of 20GB / s, 30GB / s, 120GB / s, or higher. Alternatively, similar protocols / links (e.g., via a common interconnect structure) can be used. Figure 11A This shows all communication between the various system components.

[0199] In at least one embodiment, each multi-core processor 1105 is communicatively coupled to processor memory 1101(1)-1101(M) via memory interconnects 1126(1)-1126(M), and each GPU 1110(1)-1110(N) is communicatively coupled to GPU memory 1120(1)-1120(N) via GPU memory interconnects 1150(1)-1150(N). In at least one embodiment, memory interconnects 1126 and 1150 may utilize similar or different memory access technologies. By way of example and not limitation, processor memory 1101(1)-1101(M) and GPU memory 1120 may be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memory, such as 3D XPoint or Nano-RAM. In at least one embodiment, some portions of the processor memory 1101 may be volatile memory, while other portions may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0200] As described herein, although the various multi-core processors 1105 and GPUs 1110 can be physically coupled to specific memories 1101 and 1120 respectively, and / or can implement a unified memory architecture, in which the virtual system address space (also known as the “effective address” space) is distributed among the various physical memories. For example, processor memories 1101(1)-1101(M) can each contain 64 GB of system memory address space, and GPU memories 1120(1)-1120(N) can each contain 32 GB of system memory address space, resulting in a total addressable memory size of 276 GB when M = 2 and N = 4. N and M may also be other values.

[0201] Figure 11B Additional details are shown regarding the interconnection between a multi-core processor 1107 and a graphics acceleration module 1146 according to an exemplary embodiment. In at least one embodiment, the graphics acceleration module 1146 may include one or more GPU chips integrated on a line card coupled to the processor 1107 via a high-speed link 1140 (e.g., PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1146 may optionally be integrated on a package or chip having the processor 1107.

[0202] In at least one embodiment, processor 1107 includes a plurality of cores 1160A-1160D, each core having a translation back cover buffer (“TLB”) 1161A-1161D and one or more caches 1162A-1162D. In at least one embodiment, cores 1160A-1160D may include various other components (not shown) for executing instructions and processing data. In at least one embodiment, caches 1162A-1162D may include level 1 (L1) and level 2 (L2) caches. Furthermore, one or more shared caches 1156 may be included in caches 1162A-1162D and shared by the respective groups of cores 1160A-1160D. For example, one embodiment of processor 1107 includes 24 cores, each core having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1107 and the graphics acceleration module 1146 are connected to the system memory 1114, which may include... Figure 11A The processor memory 1101(1)-1101(M) in the memory.

[0203] In at least one embodiment, consistency of data and instructions stored in the various caches 1162A-1162D, 1156 and system memory 1114 is maintained via inter-core communication through the consistency bus 1164. In at least one embodiment, for example, each cache may have associated cache consistency logic / circuit to communicate via the consistency bus 1164 in response to the detection of a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented via the consistency bus 1164 to snoop on cache accesses.

[0204] In at least one embodiment, proxy circuitry 1125 communicatively couples graphics acceleration module 1146 to coherence bus 1164, thereby allowing graphics acceleration module 1146 to participate in cache coherence protocols as a peer of cores 1160A-1160D. Specifically, in at least one embodiment, interface 1135 provides connectivity to proxy circuitry 1125 via high-speed link 1140, and interface 1137 connects graphics acceleration module 1146 to high-speed link 1140.

[0205] In at least one embodiment, the accelerator integrated circuit 1136 provides cache management, memory access, context management, and interrupt management services for a plurality of graphics processing engines 1131(1)-1131(N) of the graphics acceleration module. In at least one embodiment, each of the graphics processing engines 1131(1)-1131(N) may include a separate graphics processing unit (GPU). In at least one embodiment, the graphics processing engines 1131(1)-1131(N) may optionally include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, the graphics acceleration module 1146 may be a GPU having a plurality of graphics processing engines 1131(1)-1131(N), or the graphics processing engines 1131(1)-1131(N) may be individual GPUs integrated on a general-purpose package, line card, or chip.

[0206] In at least one embodiment, the accelerator integrated circuit 1136 includes a memory management unit (MMU) 1139 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1114. In at least one embodiment, the MMU 1139 may also include a translation back buffer (“TLB”) (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, a cache 1138 may store commands and data for efficient access by graphics processing engines 1131(1)-1131(N). In at least one embodiment, a fetch unit 1144 may be used to keep data stored in cache 1138 and graphics memory 1133(1)-1133(M) consistent with core caches 1162A-1162D, 1156 and system memory 1114. As previously mentioned, this task can be accomplished via proxy circuitry 1125 representing cache 1138 and graphics memory 1133(1)-1133(M) (e.g., sending updates related to the modification / access of cache lines on processor caches 1162A-1162D, 1156 to cache 1138 and receiving updates from cache 1138).

[0207] In at least one embodiment, a set of registers 1145 stores context data of threads executed by graphics processing engines 1131(1)-1131(N), and context management circuitry 1148 manages the thread context. For example, context management circuitry 1148 may perform save and restore operations to save and restore the context of individual threads during context switching (e.g., saving the first thread and storing the second thread so that the second thread can be executed by the graphics processing engine). For example, during context switching, context management circuitry 1148 may store the current register value in a designated area of ​​memory (e.g., identified by a context pointer). The register value can then be restored when returning to the context. In at least one embodiment, interrupt management circuitry 1147 receives and processes interrupts received from system devices.

[0208] In at least one embodiment, MMU 1139 translates virtual / effective addresses from graphics processing engine 1131 into real / physical addresses in system memory 1114. In at least one embodiment, accelerator integrated circuit 1136 supports multiple (e.g., 6, 10, 18) graphics accelerator modules 1146 and / or other accelerator devices. In at least one embodiment, graphics accelerator module 1146 may be dedicated to a single application executing on processor 1107, or may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented, wherein resources of graphics processing engines 1131(1)-1131(N) are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” based on processing requirements and priorities associated with VMs and / or applications, which are allocated to different VMs and / or applications.

[0209] In at least one embodiment, the accelerator integrated circuit 1136 acts as a bridge to the system of the graphics acceleration module 1146 and provides address translation and system memory caching services. Additionally, in at least one embodiment, the accelerator integrated circuit 1136 can provide virtualization facilities for the host processor to manage the virtualization, interrupt, and memory management of the graphics processing engines 1131(1)-1131(N).

[0210] In at least one embodiment, since the hardware resources of the graphics processing engines 1131(1)-1131(N) are explicitly mapped to the real address space seen by the host processor 1107, any host processor can directly address these resources using valid address values. In at least one embodiment, a function of the accelerator integrated circuit 1136 is to physically separate the graphics processing engines 1131(1)-1131(N) so that they appear as independent units to the system.

[0211] In at least one embodiment, one or more graphics memories 1133(1)-1133(M) are coupled to each graphics processing engine 1131(1)-1131(N), and N = M. In at least one embodiment, the graphics memories 1133(1)-1133(M) store instructions and data processed by each graphics processing engine 1131(1)-1131(N). In at least one embodiment, the graphics memories 1133(1)-1133(M) may be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory, such as 3DXPoint or Nano-RAM.

[0212] In at least one embodiment, to reduce data traffic on the high-speed link 1140, a biasing technique can be used to ensure that the data stored in the graphics memory 1133(1)-1133(M) is the data most frequently used by the graphics processing engine 1131(1)-1131(N), and preferably not used (or at least infrequently used) by the cores 1160A-1160D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep the data needed by the cores (and preferably not the graphics processing engine 1131(1)-1131(N)) in the caches 1162A-1162D, 1156 and system memory 1114.

[0213] Figure 11C Another exemplary embodiment is shown, wherein the accelerator integrated circuit 1136 is integrated within the processor 1107. In this embodiment, the graphics processing engines 1131(1)-1131(N) communicate directly with the accelerator integrated circuit 1136 via a high-speed link 1140 through interfaces 1137 and 1135 (which may also be any form of bus or interface protocol). In at least one embodiment, the accelerator integrated circuit 1136 can perform operations related to... Figure 11B The described operation is similar. However, due to its close proximity to the coherence bus 1164 and caches 1162A-1162D, 1156, it may have higher throughput. In at least one embodiment, the accelerator integrated circuit supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which may include a programming model controlled by the accelerator integrated circuit 1136 and a programming model controlled by the graphics acceleration module 1146.

[0214] In at least one embodiment, graphics processing engines 1131(1)-1131(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel requests from other applications to graphics processing engines 1131(1)-1131(N), thereby providing virtualization within a VM / partition.

[0215] In at least one embodiment, graphics processing engines 1131(1)-1131(N) can be shared by multiple VM / application partitions. In at least one embodiment, the shared model can use a hypervisor to virtualize graphics processing engines 1131(1)-1131(N) to allow each operating system to access them. In at least one embodiment, for a single-partition system without a hypervisor, the operating system owns graphics processing engines 1131(1)-1131(N). In at least one embodiment, the operating system can virtualize graphics processing engines 1131(1)-1131(N) to provide access to each process or application.

[0216] In at least one embodiment, the graphics acceleration module 1146 or the individual graphics processing engine 1131(1)-1131(N) uses a process handle to select a process element. In at least one embodiment, the process element is stored in system memory 1114 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 1131(1)-1131(N) (i.e., invoking system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element in the process element linked list.

[0217] Figure 11D An exemplary accelerator integration slice 1190 is illustrated. In at least one embodiment, a "slice" includes a designated portion of the processing resources of an accelerator integrated circuit 1136. In at least one embodiment, the application is an effective address space 1182 in system memory 1114, which stores process element 1183. In at least one embodiment, process element 1183 is stored in response to a GPU call 1181 from an application 1180 executing on processor 1107. In at least one embodiment, process element 1183 contains the process state of the corresponding application 1180. In one embodiment, a job descriptor (WD) 1184 contained in process element 1183 may be a single job requested by the application, or it may contain a pointer to a job queue. In at least one embodiment, WD 1184 is a pointer to a job request queue in the effective address space 1182 of the application.

[0218] In at least one embodiment, the graphics acceleration module 1146 and / or the various graphics processing engines 1131(1)-1131(N) may be shared by all processes or a subset of processes in the system. In at least one embodiment, infrastructure may be included for setting process states and sending WD 1184 to the graphics acceleration module 1146 to begin operations in a virtualized environment.

[0219] In at least one embodiment, the dedicated process programming model is implementation-specific. In at least one embodiment, in this model, a single process owns either the graphics acceleration module 1146 or an individual graphics processing engine 1131. In at least one embodiment, when the graphics acceleration module 1146 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when the graphics acceleration module 1146 is assigned, the operating system initializes the accelerator integrated circuit 1136 for the owned process.

[0220] In at least one embodiment, during operation, the WD acquisition unit 1191 in the accelerator integration slice 1190 acquires the next WD 1184, which includes instructions for work to be performed by one or more graphics processing engines of the graphics acceleration module 1146. In at least one embodiment, data from the WD 1184 may be stored in register 1145 and used by the MMU 1139, interrupt management circuitry 1147, and / or context management circuitry 1148, as shown. For example, one embodiment of the MMU 1139 includes segment / page roaming circuitry for accessing segment / page tables 1186 within the OS virtual address space 1185. In at least one embodiment, the interrupt management circuitry 1147 may process an interrupt event 1192 received from the graphics acceleration module 1146. In at least one embodiment, when performing graphics operations, a valid address 1193 generated by graphics processing engines 1131(1)-1131(N) is translated into a real address by the MMU 1139.

[0221] In at least one embodiment, register 1145 is copied for each graphics processing engine 1131(1)-1131(N) and / or graphics acceleration module 1146, and said register 1145 may be initialized by a hypervisor or operating system. In at least one embodiment, each of these copied registers may be included in accelerator integration slice 1190. Exemplary registers that may be initialized by a hypervisor are shown in Table 1. Table 2 shows exemplary registers that can be initialized by the operating system. In at least one embodiment, each WD 1184 is specific to a particular graphics acceleration module 1146 and / or graphics processing engine 1131(1)-1131(N). In at least one embodiment, it contains all the information required for the graphics processing engine 1131(1)-1131(N) to complete its work, or it may be a pointer to a memory location where the application has set up a command queue for the work to be completed.

[0222] Figure 11E Additional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1198, in which a list of process elements 1199 is stored. In at least one embodiment, the hypervisor real address space 1198 can be accessed via a hypervisor 1196, which virtualizes the graphics acceleration module engine for the operating system 1195.

[0223] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1146. In at least one embodiment, there are two programming models in which the graphics acceleration module 1146 is shared by multiple processes and partitions, namely, time-slice sharing and graphics-oriented sharing.

[0224] In at least one embodiment, in this model, the hypervisor 1196 owns the graphics acceleration module 1146 and makes its functionality available to all operating systems 1195. In at least one embodiment, for the graphics acceleration module 1146 to support virtualization through the hypervisor 1196, the graphics acceleration module 1146 may comply with certain requirements, such as (1) the job requests of the application must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1146 must provide a context saving and recovery mechanism, (2) the graphics acceleration module 1146 guarantees that the job requests of the application are completed within a specified amount of time, including any conversion errors, or the graphics acceleration module 1146 provides the ability to preempt job processing, and (3) when operating in a directed shared programming model, fairness between the processes of the graphics acceleration module 1146 must be ensured.

[0225] In at least one embodiment, application 1180 needs to make system calls to operating system 1195 using the graphics acceleration module type, working descriptor (WD), permission mask register (AMR) value, and context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is specifically formatted for graphics acceleration module 1146 and can take the form of graphics acceleration module 1146 commands, valid address pointers to user-defined structures, valid address pointers to command queues, or any other data structure describing the work to be performed by graphics acceleration module 1146.

[0226] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of the application that sets the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1136 (not shown) and the graphics acceleration module 1146 does not support the User Rights Mask Overwrite Register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. In at least one embodiment, the hypervisor 1196 may selectively apply the current Rights Mask Overwrite Register (AMOR) value before placing the AMR into the process element 1183. In at least one embodiment, CSRP is one of the registers 1145 that contains the effective address of a region in the effective address space 1182 of the application for the graphics acceleration module 1146 to save and restore the context state. In at least one embodiment, this pointer is optional if it is not necessary to save state between jobs or when a job is preempted. In at least one embodiment, the context save / restore region may be fixed system memory.

[0227] Upon receiving a system call, the operating system 1195 can verify that the application 1180 has been registered and granted permission to use the graphics acceleration module 1146. Then, in at least one embodiment, the operating system 1195 uses the information shown in Table 3 to invoke the hypervisor 1196. In at least one embodiment, upon receiving a hypervisor call, hypervisor 1196 verifies that operating system 1195 has been registered and granted permission to use graphics acceleration module 1146. Then, in at least one embodiment, hypervisor 1196 adds process element 1183 to a linked list of process elements of the corresponding graphics acceleration module 1146 type. In at least one embodiment, the process element may include the information shown in Table 4. In at least one embodiment, the hypervisor initializes registers 1145 of multiple accelerator integration slices 1190.

[0228] like Figure 11FAs shown, in at least one embodiment, a unified memory is used, which is addressable via a common virtual memory address space for accessing physical processor memories 1101(1)-1101(N) and GPU memories 1120(1)-1120(N). In this implementation, operations performed on GPUs 1110(1)-1110(N) utilize the same virtual / effective memory address space to access processor memories 1101(1)-1101(M) and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1101(1), a second portion to second processor memory 1101(N), a third portion to GPU memory 1120(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memory 1101 and GPU memory 1120, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0229] In at least one embodiment, the bias / coherence management circuitry 1194A-1194E within one or more MMUs 1139A-1139E ensures cache coherence between one or more host processors (e.g., 1105) and the cache of GPU 1110, and implements biasing techniques to indicate the physical memory in which certain types of data should be stored. In at least one embodiment, although in Figure 11F Several instances of bias / coherence management circuitry 1194A-1194E are shown, but bias / coherence circuitry can be implemented within the MMU of one or more host processors 1105 and / or within the accelerator integrated circuit 1136.

[0230] One embodiment allows GPU memory 1120 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU memory 1120 as system memory without the heavy overhead of cache coherence provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows the host processor 1105 to software-set operands and access computation results without the overhead of conventional I / O DMA data copying. In at least one embodiment, such conventional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, all of which are less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU memory 1120 without cache coherence overhead may be critical to the execution time of offloaded computations. In at least one embodiment, for example, in cases with high streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 1110. In at least one embodiment, the efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0231] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table can be used, which may be a page-granular structure (e.g., controlled at the memory page level) comprising one or two bits of memory pages attached to each GPU. In at least one embodiment, with or without a bias cache (e.g., for caching frequently / recently used entries in the bias table) in GPU 1110, the bias table can be implemented across one or more stolen memory ranges of GPU memory 1120. Alternatively, in at least one embodiment, the entire bias table can be maintained within the GPU.

[0232] In at least one embodiment, prior to actual access to GPU memory, an access to the bias table entry associated with each access to GPU-attached memory 1120 is performed, resulting in the following operations: In at least one embodiment, a local request from GPU 1110 to locate its page in the GPU bias is directly forwarded to the corresponding GPU memory 1120. In at least one embodiment, a local request from the GPU to locate its page in the host bias is forwarded to processor 1105 (e.g., via the high-speed link described herein). In at least one embodiment, a request from processor 1105 to locate the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, a request to a GPU bias page can be forwarded to GPU 1110. In at least one embodiment, if the GPU is not currently using the page, the GPU may subsequently migrate the page to the host processor bias. In at least one embodiment, the page bias state can be changed through software-based mechanisms, hardware-assisted software mechanisms, or, in limited cases, purely hardware-based mechanisms.

[0233] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL), which subsequently invokes the GPU's device driver. The device driver then sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and, in some migration, performs a cache refresh operation on the host. In at least one embodiment, the cache refresh operation is used for migration from the host processor 1105 bias to the GPU bias, but not for the reverse migration.

[0234] In one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that the host processor 1105 cannot cache. In at least one embodiment, to access these pages, the processor 1105 may request access from the GPU 1110, which may or may not immediately grant access. Therefore, in at least one embodiment, to reduce communication between the processor 1105 and the GPU 1110, it is beneficial to ensure that the GPU bias pages are pages needed by the GPU, not those needed by the host processor 1105, and vice versa.

[0235] One or more hardware structures 135 are used to execute one or more embodiments. This can be combined with... Figure 3A and / or Figure 3B Provide details about one or more hardware structures 135.

[0236] Figure 12Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be manufactured using one or more IP cores. In addition to the illustrations, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0237] Figure 12 This is a block diagram illustrating an exemplary system on a chip integrated circuit 1200 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, the integrated circuit 1200 includes one or more application processors 1205 (e.g., CPUs), at least one graphics processor 1210, and may additionally include an image processor 1215 and / or a video processor 1220, any of which may be a modular IP core. In at least one embodiment, the integrated circuit 1200 includes peripheral or bus logic including a USB controller 1225, a UART controller 1230, an SPI / SDIO controller 1235, and an I22S / I22C controller 1240. In at least one embodiment, the integrated circuit 1200 may include a display device 1245 coupled to one or more of a High Definition Multimedia Interface (HDMI) controller 1250 and a Mobile Industrial Processor Interface (MIPI) display interface 1255. In at least one embodiment, storage may be provided by a flash memory subsystem 1260, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1265 for accessing an SDRAM or SRAM memory device. In at least one embodiment, some integrated circuits also include an embedded security engine 1270.

[0238] Inference and / or training logic 315 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 3A and / or Figure 3B Details regarding inference and / or training logic 315 are provided. In at least one embodiment, inference and / or training logic 315 may be used in integrated circuit 1200 to infer or predict operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.

[0239] Figures 13A-13B Exemplary integrated circuits and associated graphics processors according to various embodiments described herein are illustrated, which may be fabricated using one or more IP cores. In addition to those shown, at least one embodiment may include other logic and circuitry, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0240] Figures 13A-13B This is a block diagram illustrating an exemplary graphics processor used within a SoC according to embodiments described herein. Figure 13A An exemplary graphics processor 1310 of a system-on-a-chip according to at least one embodiment is shown, which can be manufactured using one or more IP cores. Figure 13B Further exemplary graphics processor 1340 of a system-on-a-chip according to at least one embodiment is shown, which can be manufactured using one or more IP cores. In at least one embodiment, Figure 13A The graphics processor 1310 is a low-power graphics processor core. In at least one embodiment, Figure 13B The graphics processor 1340 is a higher-performance graphics processor core. In at least one embodiment, each graphics processor 1310, 1340 may be... Figure 12 A variant of the 1210 graphics processor.

[0241] In at least one embodiment, the graphics processor 1310 includes a vertex processor 1305 and one or more fragment processors 1315A-1315N (e.g., 1315A, 1315B, 1315C, 1315D to 1315N-1 and 1315N). In at least one embodiment, the graphics processor 1310 may execute different shader programs via separate logic, such that the vertex processor 1305 is optimized to perform operations for the vertex shader program, while one or more fragment processors 1315A-1315N perform fragment (e.g., pixel) shading operations for fragments or pixels or shader programs. In at least one embodiment, the vertex processor 1305 performs the vertex processing stage of the 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, one or more fragment processors 1315A-1315N use the primitive and vertex data generated by the vertex processor 1305 to generate framebuffers for display on a display device. In at least one embodiment, one or more fragment processors 1315A-1315N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to those of pixel shader programs provided in the Direct 3D API.

[0242] In at least one embodiment, the graphics processor 1310 additionally includes one or more memory management units (MMUs) 1320A-1320B, one or more caches 1325A-1325B, and one or more circuit interconnects 1330A-1330B. In at least one embodiment, one or more MMUs 1320A-1320B provide virtual-to-physical address mappings for the graphics processor 1310, including for vertex processors 1305 and / or fragment processors 1315A-1315N, which can reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1325A-1325B. In at least one embodiment, one or more MMUs 1320A-1320B can be synchronized with other MMUs within the system, including with... Figure 12 One or more application processors 1205, graphics processors 1215, and / or video processors 1220 are associated with one or more MMUs, enabling each processor 1205-1220 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1330A-1330B enable the graphics processor 1310 to connect to other IP cores within the SoC via the SoC's internal bus or via a direct connection.

[0243] In at least one embodiment, the graphics processor 1340 includes one or more shader cores 1355A-1355N (e.g., 1355A, 1355B, 1355C, 1355D, 1355E, 1355F to 1355N-1 and 1355N), such as Figure 13B As shown, it provides a unified shader core architecture, where a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1340 includes an inter-core task manager 1345, which acts as a thread dispatcher to assign execution threads to one or more shader cores 1355A-1355N and a tile unit 1358 to accelerate tile-based rendering operations, where scene rendering operations are subdivided in image space, for example, to utilize local spatial consistency within the scene or optimize the use of internal caches.

[0244] Inference and / or training logic 315 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 3A and / or Figure 3BDetails regarding the inference and / or training logic 315 are provided. In at least one embodiment, the inference and / or training logic 315 may be integrated into an integrated circuit. Figure 13A and / or Figure 13B The above is used for inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions or architectures, or neural network use cases described herein.

[0245] Figures 14A-14B Additional exemplary graphics processor logic according to embodiments described herein is illustrated. In at least one embodiment, Figure 14A It shows that it can be included in Figure 12 The graphics core 1400 within the graphics processor 1210, and in at least one embodiment, may be as follows: Figure 13B The unified shader cores shown are 1355A-1355N. Figure 14B A highly parallel general-purpose graphics processing unit (“GPGPU”) 1430 suitable for deployment on a multi-chip module is shown in at least one embodiment.

[0246] In at least one embodiment, the graphics core 1400 includes a shared instruction cache 1402, texture units 1418, and cache / shared memory 1420, which are common to the execution resources within the graphics core 1400. In at least one embodiment, the graphics core 1400 may include multiple slices 1401A-1401N or partitions of each core, and the graphics processor may include multiple instances of the graphics core 1400. In at least one embodiment, slices 1401A-1401N may include supporting logic, including local instruction caches 1404A-1404N, thread schedulers 1406A-1406N, thread dispatchers 1408A-1408N, and a set of registers 1410A-1410N. In at least one embodiment, slices 1401A-1401N may include a set of additional functional units (AFU 1412A-1412N), floating-point units (FPU 1414A-1414N), integer arithmetic logic units (ALU 1416A-1416N), address calculation units (ACU 1413A-1413N), double-precision floating-point units (DPFPU 1415A-1415N), and matrix processing units (MPU 1417A-1417N).

[0247] In at least one embodiment, the FPU 1414A-1414N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPU 1415A-1415N performs double-precision (64-bit) floating-point operations. In at least one embodiment, the ALU 1416A-1416N can perform variable-precision integer operations with 10-bit, 18-bit, and 34-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPU 1417A-1417N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 10-bit integer operations. In at least one embodiment, the MPU 1417-1417N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated generalized matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFU 1412A-1412N can perform additional logical operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0248] Inference and / or training logic 315 is used to perform inference and / or training operations associated with one or more embodiments. This is combined with... Figure 3A and / or Figure 3B Details are provided regarding inference and / or training logic 315. In at least one embodiment, inference and / or training logic 315 may be used in graphics core 1400 for inferring or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0249] Figure 14BA general-purpose processing unit (GPGPU) 1430 is illustrated in at least one embodiment, which can be configured to enable highly parallel computational operations to be performed by a set of graphics processing units. In at least one embodiment, the GPGPU 1430 can be directly linked to other instances of the GPGPU 1430 to create a multi-GPU cluster to improve the training speed for deep neural networks. In at least one embodiment, the GPGPU 1430 includes a host interface 1432 for connection to a host processor. In at least one embodiment, the host interface 1432 is a PCI Express interface. In at least one embodiment, the host interface 1432 may be a vendor-specific communication interface or communication structure. In at least one embodiment, the GPGPU 1430 receives commands from the host processor and uses a global scheduler 1434 to allocate execution threads associated with those commands to a set of compute clusters 1436A-1436H. In at least one embodiment, compute clusters 1436A-1436H share a cache memory 1438. In at least one embodiment, cache memory 1438 can be used as a higher-level cache within the cache memory of computing clusters 1436A-1436H.

[0250] In at least one embodiment, the GPGPU 1430 includes memories 1444A-1444B, which are coupled to the computing cluster 1436A-1436H via a set of memory controllers 1442A-1442B. In at least one embodiment, memories 1444A-1444B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0251] In at least one embodiment, each of the computing clusters 1436A-1436H includes a set of graphics cores, for example... Figure 14A The graphics core 1400 may include various types of integer and floating-point logic units that can perform computational operations across a range of precisions, including precisions suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each computing cluster 1436A-1436H may be configured to perform 16-bit or 32-bit floating-point operations, while different subsets of the floating-point units may be configured to perform 64-bit floating-point operations.

[0252] In at least one embodiment, multiple instances of GPGPU 1430 can be configured as a computing cluster. In at least one embodiment, the communication used for synchronization and data exchange by computing clusters 1436A-1436H varies between embodiments. In at least one embodiment, multiple instances of GPGPU 1430 communicate via host interface 1432. In at least one embodiment, GPGPU 1430 includes an I / O hub 1439 that couples GPGPU 1430 to GPU link 1440, enabling direct connection to other instances of GPGPU 1430. In at least one embodiment, GPU link 1440 is coupled to a dedicated GPU-to-GPU bridge, which enables communication and synchronization between multiple instances of GPGPU 1430. In at least one embodiment, GPU link 1440 is coupled to a high-speed interconnect for sending and receiving data to and from other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1430 reside in a separate data processing system and communicate via network devices accessible through host interface 1432. In at least one embodiment, GPU link 1440 may be configured to enable connection to a host processor other than or as a replacement for host interface 1432.

[0253] In at least one embodiment, the GPGPU 1430 can be configured to train a neural network. In at least one embodiment, the GPGPU 1430 can be used within an inference platform. In at least one embodiment, where the GPGPU 1430 is used for inference, the GPGPU 1430 may include fewer compute clusters 1436A-1436H compared to when the GPGPU 1430 is used to train a neural network. In at least one embodiment, the memory technology associated with the memories 1444A-1444B can differ between inference and training configurations, wherein a higher bandwidth memory technology is dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1430 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 10-bit integer dot product instructions, which can be used during the inference operation of the deployed neural network.

[0254] Inference and / or training logic 315 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 3A and / or Figure 3BDetails regarding inference and / or training logic 315 are provided. In at least one embodiment, inference and / or training logic 315 may be used in the GPGPU 1430 for inferring or predicting operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architecture, or neural network use cases described herein.

[0255] Figure 15 A block diagram of a computer system 1500 according to at least one embodiment is shown. In at least one embodiment, the computer system 1500 includes a processing subsystem 1501 having one or more processors 1502 and a system memory 1504 communicating via an interconnect path that may include a memory hub 1505. In at least one embodiment, the memory hub 1505 may be a separate component within a chipset assembly or may be integrated within one or more processors 1502. In at least one embodiment, the memory hub 1505 is coupled to an I / O subsystem 1511 via a communication link 1506. In one embodiment, the I / O subsystem 1511 includes an I / O hub 1507 that enables the computer system 1500 to receive input from one or more input devices 1508. In at least one embodiment, the I / O hub 1507 enables a display controller to provide output to one or more display devices 1510A, the display controller being included in one or more processors 1502. In at least one embodiment, one or more display devices 1510A coupled to the I / O hub 1507 may include local, internal, or embedded display devices.

[0256] In at least one embodiment, the processing subsystem 1501 includes one or more parallel processors 1512 coupled to the memory hub 1505 via a bus or other communication link 1513. In at least one embodiment, the communication link 1513 may use any of many standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or may be a vendor-specific communication interface or communication architecture. In at least one embodiment, one or more parallel processors 1512 form a compute-intensive parallel or vector processing system, which may include a large number of processing cores and / or processing clusters, such as a multi-core integrated (MIC) processor. In at least one embodiment, one or more parallel processors 1512 form a graphics processing subsystem that can output pixels to one or more display devices 1510A coupled via an I / O hub 1507. In at least one embodiment, the parallel processors 1512 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display devices 1510B.

[0257] In at least one embodiment, system storage unit 1514 may be connected to I / O hub 1507 to provide a storage mechanism for computer system 1500. In at least one embodiment, I / O switch 1516 may be used to provide an interface mechanism to enable connectivity between I / O hub 1507 and other components, such as network adapter 1518 and / or wireless network adapter 1519 that may be integrated into the platform, and various other devices that may be added via one or more additional devices 1520. In at least one embodiment, network adapter 1518 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter 1519 may include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more wireless devices.

[0258] In at least one embodiment, the computer system 1500 may include other components not explicitly shown, such as USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to the I / O hub 1507. In at least one embodiment, the interconnection may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol. Figure 15 The communication paths of the various components, such as NV-Link high-speed interconnect or interconnect protocols.

[0259] In at least one embodiment, one or more parallel processors 1512 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constituting a graphics processing unit (GPU). In at least one embodiment, the parallel processor 1512 includes circuitry optimized for general-purpose processing. In at least one embodiment, components of the computer system 1500 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, the parallel processor 1512, memory hub 1505, processor 1502, and I / O hub 1507 may be integrated into a system-on-a-chip (SoC) integrated circuit. In at least one embodiment, components of the computer system 1500 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computer system 1500 may be integrated into a multi-chip module (MCM) that can interconnect with other MCMs to a modular computer system.

[0260] Inference and / or training logic 315 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 3A and / or Figure 3B Details are provided regarding the inference and / or training logic 315. In at least one embodiment, the inference and / or training logic 315 may be... Figure 15 The system 1500 is used for reasoning or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0261] processor Figure 16A A parallel processor 1600 according to at least one embodiment is illustrated. In at least one embodiment, various components of the parallel processor 1600 may be implemented using one or more integrated circuit devices, such as programmable processors, application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 1600 is according to an exemplary embodiment. Figure 15 The variant of the 1512, which includes one or more parallel processors, is shown.

[0262] In at least one embodiment, the parallel processor 1600 includes a parallel processing unit 1602. In at least one embodiment, the parallel processing unit 1602 includes an I / O unit 1604 that enables communication with other devices, including other instances of the parallel processing unit 1602. In at least one embodiment, the I / O unit 1604 can be directly connected to other devices. In at least one embodiment, the I / O unit 1604 is connected to other devices using a hub or switch interface (e.g., a memory hub 2105). In at least one embodiment, the connection between the memory hub 1605 and the I / O unit 1604 forms a communication link 1613. In at least one embodiment, the I / O unit 1604 is connected to a host interface 1606 and a memory crossbar switch 1616, wherein the host interface 1606 receives commands for performing processing operations, and the memory crossbar switch 1616 receives commands for performing memory operations.

[0263] In at least one embodiment, when host interface 1606 receives a command buffer via I / O unit 1604, host interface 1606 can direct work operations to execute those commands to front end 1608. In at least one embodiment, front end 1608 is coupled to scheduler 1610, which is configured to assign commands or other work items to processing cluster array 1612. In at least one embodiment, scheduler 1610 ensures that processing cluster array 1612 is correctly configured and in an active state before assigning tasks to processing cluster array 1612. In at least one embodiment, scheduler 1610 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 1610 can be configured to perform complex scheduling and work assignment operations at both coarse and fine granular levels, thereby enabling fast preemption and context switching of threads executing on processing array 1612. In at least one embodiment, host software can demonstrate workloads for scheduling on processing array 1612 via one of multiple graphics processing paths. In at least one embodiment, the workload can then be automatically distributed on the processing array 1612 by the scheduler 1610 logic within the microcontroller, which includes the scheduler 1610.

[0264] In at least one embodiment, the processing cluster array 1612 may include up to "N" processing clusters (e.g., clusters 1614A, 1614B to 1614N), where "N" represents a positive integer (which may be an integer different from the integer "N" used in other diagrams). In at least one embodiment, each cluster 1614A-1614N of the processing cluster array 1612 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 1610 may use various scheduling and / or work allocation algorithms to allocate work to the clusters 1614A-1614N of the processing cluster array 1612, which may vary depending on the workload generated by each type of program or computation. In at least one embodiment, scheduling may be handled dynamically by the scheduler 1610, or may be partially assisted by compiler logic during the compilation of program logic configured to be executed by the processing cluster array 1612. In at least one embodiment, the different clusters 1614A-1614N of the processing cluster array 1612 may be assigned to process different types of programs or to perform different types of computations.

[0265] In at least one embodiment, the processing cluster array 1612 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 1612 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 1612 may include logic for performing processing tasks, including filtering video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0266] In at least one embodiment, the processing cluster array 1612 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 1612 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 1612 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 1602 may transfer data from system memory via I / O unit 1604 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1622) and then written back to system memory.

[0267] In at least one embodiment, when the parallel processing unit 1602 is used to perform graphics processing, the scheduler 1610 may be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations among the multiple clusters 1614A-1614N of the processing cluster array 1612. In at least one embodiment, portions of the processing cluster array 1612 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 1614A-1614N may be stored in a buffer to allow intermediate data to be transferred between the clusters 1614A-1614N for further processing.

[0268] In at least one embodiment, the processing cluster array 1612 may receive processing tasks to be executed via a scheduler 1610, which receives commands defining the processing tasks from a front end 1608. In at least one embodiment, the processing task may include an index of data to be processed, such as surface (patch) data, raw data, vertex data, and / or pixel data, as well as state parameters and commands defining how the data is processed (e.g., what program to execute). In at least one embodiment, the scheduler 1610 may be configured to acquire an index corresponding to a task, or may receive an index from the front end 1608. In at least one embodiment, the front end 1608 may be configured to ensure that the processing cluster array 1612 is configured to be active before initiating the workload specified by an incoming command buffer (e.g., a batch buffer, push buffer, etc.).

[0269] In at least one embodiment, each of one or more instances of the parallel processing unit 1602 may be coupled to the parallel processor memory 1622. In at least one embodiment, the parallel processor memory 1622 may be accessed via a memory crossbar switch 1616, which may receive memory requests from the processing cluster array 1612 and the I / O unit 1604. In at least one embodiment, the memory crossbar switch 1616 may be accessed via a memory interface 1618. In at least one embodiment, the memory interface 1618 may include a plurality of partition units (e.g., partition units 1620A, 1620B to 1620N), each of which may be coupled to a portion (e.g., a memory cell) of the parallel processor memory 1622. In at least one embodiment, the plurality of partition units 1620A-1620N are configured to be equal to the number of memory units, such that the first partition unit 1620A has a corresponding first memory unit 1624A, the second partition unit 1620B has a corresponding memory unit 1624B, and the Nth partition unit 1620N has a corresponding Nth memory unit 1624N. In at least one embodiment, the number of partition units 1620A-1620N may not be equal to the number of memory units.

[0270] In at least one embodiment, memory cells 1624A-1624N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory cells 1624A-1624N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, rendering targets such as frame buffers or texture maps may be stored across memory cells 1624A-1624N, allowing partitioning cells 1620A-1620N to write portions of each rendering target in parallel, to efficiently utilize the available bandwidth of the parallel processor memory 1622. In at least one embodiment, local instances of the parallel processor memory 1622 may be excluded to facilitate a unified memory design that combines system memory with local cache memory.

[0271] In at least one embodiment, any of the clusters 1614A-1614N of the processing cluster array 1612 can process data to be written to any memory cell 1624A-1624N within the parallel processor memory 1622. In at least one embodiment, the memory crossbar switch 1616 can be configured to transfer the output of each cluster 1614A-1614N to any partition cell 1620A-1620N or another cluster 1614A-1614N, and the clusters 1614A-1614N can perform further processing operations on the output. In at least one embodiment, each cluster 1614A-1614N can communicate with the memory interface 1618 via the memory crossbar switch 1616 to read from or write to various external storage devices. In at least one embodiment, the memory crossbar switch 1616 has a connection to a memory interface 1618 for communication with I / O unit 1604, and a connection to a local instance of parallel processor memory 1622, thereby enabling processing units within different processing clusters 1614A-1614N to communicate with system memory or other memory not local to parallel processing unit 1602. In at least one embodiment, the memory crossbar switch 1616 may use virtual channels to separate traffic flows between clusters 1614A-1614N and partition units 1620A-1620N.

[0272] In at least one embodiment, multiple instances of the parallel processing unit 1602 may be provided on a single insert card, or multiple insert cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 1602 may be configured to interoperate, even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 1602 may include higher-precision floating-point units relative to other instances. In at least one embodiment, a system combining one or more instances of the parallel processing unit 1602 or the parallel processor 1600 may be implemented in various configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0273] Figure 16B This is a block diagram of a partitioning unit 1620 according to at least one embodiment. In at least one embodiment, the partitioning unit 1620 is... Figure 16A This is an example of one of the partitioning units 1620A-1620N. In at least one embodiment, the partitioning unit 1620 includes an L2 cache 1621, a frame buffer interface 1625, and a ROP 1626 (raster operation unit). In at least one embodiment, the L2 cache 1621 is a read / write cache configured to perform load and store operations received from the memory crossbar switch 1616 and the ROP 1626. In at least one embodiment, the L2 cache 1621 outputs read misses and urgent write-back requests to the frame buffer interface 1625 for processing. In at least one embodiment, updates can also be sent to the frame buffer for processing via the frame buffer interface 1625. In at least one embodiment, the frame buffer interface 1625 communicates with memory cells in the parallel processor memory (such as...). Figure 16A It interacts with one of the memory cells 1624A-1624N (e.g., within the parallel processor memory 1622).

[0274] In at least one embodiment, ROP 1626 is a processing unit that performs raster operations such as stenciling, z-testing, blending, etc. In at least one embodiment, ROP 1626 then outputs processed graphics data stored in graphics memory. In at least one embodiment, ROP 1626 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic utilizing one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 1626 may vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed based on depth and color data on a per-tile basis.

[0275] In at least one embodiment, ROP 1626 is included within each processing cluster (e.g., Figure 16A Clusters 1614A-1614N are used instead of partition units 1620. In at least one embodiment, read and write requests for pixel data are made via memory crossbar switch 1616 instead of pixel fragment data transfer. In at least one embodiment, the processed graphics data can be displayed on a display device (such as...). Figure 15 Displayed by one or more display devices 1510, routed by processor 1502 for further processing, or by... Figure 16A One of the processing entities within the parallel processor 1600 is routed for further processing.

[0276] Figure 16C This is a block diagram of a processing cluster 1614 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is... Figure 16A An instance of one of the processing clusters 1614A-1614N. In at least one embodiment, the processing cluster 1614 can be configured to execute a number of threads in parallel, where a "thread" refers to an instance of a specific program executing on a particular set of input data. In at least one embodiment, a Single Instruction Multiple Data (SIMD) instruction issuing technique is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, a Single Instruction Multiple Threading (SIMT) technique is used to support the parallel execution of a large number of generally synchronous threads, which uses a common instruction unit configured to issue instructions to a set of processing engines within each processing cluster.

[0277] In at least one embodiment, the operation of the processing cluster 1614 can be controlled by a pipeline manager 1632 that assigns processing tasks to the SIMT parallel processors. In at least one embodiment, the pipeline manager 1632... Figure 16AThe scheduler 1610 receives instructions and manages the execution of these instructions via the graphics multiprocessor 1634 and / or texture unit 1636. In at least one embodiment, the graphics multiprocessor 1634 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, the processing cluster 1614 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, the processing cluster 1614 may include one or more instances of the graphics multiprocessor 1634. In at least one embodiment, the graphics multiprocessor 1634 can process data, and the data crossover switch 1640 can be used to distribute the processed data to one of a number of possible destinations, including other shader units. In at least one embodiment, the pipeline manager 1632 can facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data crossover switch 1640.

[0278] In at least one embodiment, each graphics multiprocessor 1634 within the processing cluster 1614 may include the same set of functional execution logic (e.g., arithmetic logic units, load-memory units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, wherein new instructions may be issued before previous instructions complete. In at least one embodiment, the functional execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shift operations, and computation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be used to perform different operations, and any combination of functional units may exist.

[0279] In at least one embodiment, instructions sent to the processing cluster 1614 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes a general program on different input data. In at least one embodiment, each thread within the thread group may be assigned to a different processing engine within the graphics multiprocessor 1634. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 1634. In at least one embodiment, when the number of threads included in the thread group is less than the number of processing engines, one or more processing engines may be idle during a loop that is processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 1634. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 1634, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 1634.

[0280] In at least one embodiment, the graphics multiprocessor 1634 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 1634 may forgo the internal cache and use a cache memory within the processing cluster 1614 (e.g., L1 cache 1648). In at least one embodiment, each graphics multiprocessor 1634 may also access partition units (e.g., Figure 16A The L2 cache is located within partition units 1620A-1620N, which are shared among all processing clusters 1614 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 1634 can also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory outside of the parallel processing unit 1602 can be used as global memory. In at least one embodiment, the processing cluster 1614 includes multiple instances of the graphics multiprocessor 1634, which can share common instructions and data that can be stored in the L1 cache 1648.

[0281] In at least one embodiment, each processing cluster 1614 may include a memory management unit (“MMU”) 1645 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 1645 may reside in Figure 16A The memory interface 1618 is located within the MMU 1645. In at least one embodiment, the MMU 1645 includes a set of page table entries (PTEs) for mapping virtual addresses to physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 1645 may include an address translation back buffer (TLB) or a cache that may reside within the graphics multiprocessor 1634, the L1 cache 1648, or the processing cluster 1614. In at least one embodiment, physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, cache line indices may be used to determine whether a request for a cache line is a hit or a miss.

[0282] In at least one embodiment, the processing cluster 1614 can be configured such that each graphics multiprocessor 1634 is coupled to a texture unit 1636 to perform texture mapping operations that determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read as needed from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 1634, and texture data is also retrieved from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 1634 outputs a processed task to a data crossbar switch 1640 to provide the processed task to another processing cluster 1614 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via a memory crossbar switch 1616. In at least one embodiment, a preROP 1642 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 1634 and direct the data to a ROP unit, which can be associated with a partitioning unit (e.g., [missing information]). Figure 16A The PreROP 1642 unit is located together with the partitioning units 1620A-1620N. In at least one embodiment, the PreROP 1642 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0283] Inference and / or training logic 315 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 3A and / or Figure 3B Details are provided regarding inference and / or training logic 315. In at least one embodiment, inference and / or training logic 315 may be used in a graphics processing cluster 1614 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0284] Figure 16D A graphics multiprocessor 1634 according to at least one embodiment is illustrated. In at least one embodiment, the graphics multiprocessor 1634 is coupled to a pipeline manager 1632 of a processing cluster 1614. In at least one embodiment, the graphics multiprocessor 1634 has an execution pipeline including, but not limited to, an instruction cache 1652, an instruction unit 1654, an address mapping unit 1656, a register file 1658, one or more general-purpose graphics processing unit (GPGPU) cores 1662, and one or more load / store units 1666. In at least one embodiment, the GPGPU cores 1662 and the load / store units 1666 are coupled to a cache memory 1672 and a shared memory 1670 via a memory and cache interconnect 1668.

[0285] In at least one embodiment, instruction cache 1652 receives a stream of instructions to be executed from pipeline manager 1632. In at least one embodiment, instructions are cached in instruction cache 1652 and dispatched to instruction unit 1654 for execution. In one embodiment, instruction unit 1654 may dispatch instructions as thread groups (e.g., thread bundles), assigning each thread of the thread group to a different execution unit within GPGPU core 1662. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit 1656 may be used to translate addresses in the unified address space into different memory addresses that can be accessed by load / store unit 1666.

[0286] In at least one embodiment, register file 1658 provides a set of registers for functional units of graphics multiprocessor 1634. In at least one embodiment, register file 1658 provides temporary storage for operands of data paths connected to functional units of graphics multiprocessor 1634 (e.g., GPGPU core 1662, load / store unit 1666). In at least one embodiment, register file 1658 is partitioned among each functional unit, such that a dedicated portion of register file 1658 is allocated to each functional unit. In at least one embodiment, register file 1658 is partitioned among different thread bundles being executed by graphics multiprocessor 1634.

[0287] In at least one embodiment, each of the GPGPU cores 1662 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 1634. In at least one embodiment, the GPGPU cores 1662 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 1662 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 954-2008 standard for floating-point algorithms or enable variable-precision floating-point algorithms. In at least one embodiment, the graphics multiprocessor 1634 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 1662 may also include fixed-function or special-function logic.

[0288] In at least one embodiment, the GPGPU core 1662 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 1662 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time or automatically generated when executing a program written and compiled for a Single Program Multiple Data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed using a single SIMD instruction. For example, in at least one embodiment, eight SIMD threads performing the same or similar operations can be executed in parallel using a single SIMD8 logic unit.

[0289] In at least one embodiment, the memory and cache interconnect 1668 is an interconnect network connecting each functional unit of the graphics multiprocessor 1634 to the register file 1658 and the shared memory 1670. In at least one embodiment, the memory and cache interconnect 1668 is a cross-switch interconnect that allows the load / store unit 1666 to perform load and store operations between the shared memory 1670 and the register file 1658. In at least one embodiment, the register file 1658 can operate at the same frequency as the GPGPU core 1662, resulting in very low latency for data transfer between the GPGPU core 1662 and the register file 1658. In at least one embodiment, the shared memory 1670 can be used to enable communication between threads executing on functional units within the graphics multiprocessor 1634. In at least one embodiment, the cache memory 1672 can be used, for example, as a data cache to cache texture data communicated between functional units and texture units 1636. In at least one embodiment, the shared memory 1670 can also be used as a program-managed cache. In at least one embodiment, in addition to the automatically cached data stored in cache memory 1672, the thread executing on GPGPU core 1662 can also programmatically store data in shared memory.

[0290] In at least one embodiment, a parallel processor or GPGPU, as described herein, is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., high-speed interconnects such as PCIe or NVLink). In at least one embodiment, the GPU may be integrated with the core on a package or chip and communicatively coupled to the core via an internal processor bus / interconnect (i.e., within the package or chip). In at least one embodiment, regardless of how the GPU is connected, the processor core may assign work to the GPU in the form of a sequence of commands / instructions contained in a job descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0291] Inference and / or training logic 315 is used to perform inference and / or training operations associated with one or more embodiments. The following is in conjunction with... Figure 3A and / or Figure 3B Details are provided regarding the inference and / or training logic 315. In at least one embodiment, the inference and / or training logic 315 may be used in the graphics multiprocessor 1634 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0292] Figure 17A multi-GPU computing system 1700 according to at least one embodiment is illustrated. In at least one embodiment, the multi-GPU computing system 1700 may include a processor 1702 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 1706A-D via a host interface switch 1704. In at least one embodiment, the host interface switch 1704 is a PCI Express switch device that couples the processor 1702 to a PCI Express bus, through which the processor 1702 can communicate with the GPGPUs 1706A-D. In at least one embodiment, the GPGPUs 1706A-D may be interconnected via a set of high-speed P2P GPU-to-GPU links 1716. In at least one embodiment, the GPU-to-GPU links 1716 are connected to each of the GPGPUs 1706A-D via dedicated GPU links. In at least one embodiment, the P2P GPU links 1716 enable direct communication between each GPGPU 1706A-D without communication via the host interface bus 1704 to which the processor 1702 is connected. In at least one embodiment, when GPU-to-GPU traffic is directed to the P2P GPU link 1716, the host interface bus 1704 remains available for system memory access or, for example, communication with other instances of the multi-GPU computing system 1700 via one or more network devices. While in at least one embodiment, the GPGPUs 1706A-D are connected to the processor 1702 via the host interface switch 1704, in at least one embodiment, the processor 1702 includes direct support for the P2P GPU link 1716 and can be directly connected to the GPGPUs 1706A-D.

[0293] Inference and / or training logic 315 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 3A and / or Figure 3B Details are provided regarding inference and / or training logic 315. In at least one embodiment, inference and / or training logic 315 may be used in a multi-GPU computing system 1700 for performing inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0294] Figure 18This is a block diagram of a graphics processor 1800 according to at least one embodiment. In at least one embodiment, the graphics processor 1800 includes a ring interconnect 1802, a pipeline front end 1804, a media engine 1837, and graphics cores 1880A-1880N. In at least one embodiment, the ring interconnect 1802 couples the graphics processor 1800 to other processing units, said processing units including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, the graphics processor 1800 is one of many processors integrated within a multi-core processing system.

[0295] In at least one embodiment, the graphics processor 1800 receives multiple batches of commands via a ring interconnect 1802. In at least one embodiment, the input commands are interpreted by a command streamer 1803 in a pipeline front-end 1804. In at least one embodiment, the graphics processor 1800 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 1880A-1880N. In at least one embodiment, for 3D geometry processing commands, the command streamer 1803 provides the commands to the geometry pipeline 1836. In at least one embodiment, for at least some media processing commands, the command streamer 1803 provides the commands to a video front-end 1834, which is coupled to a media engine 1837. In at least one embodiment, the media engine 1837 includes a video quality engine (VQE) 1830 for video and image post-processing, and a multi-format encoding / decoding (MFX) engine 1833 for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 1836 and the media engine 1837 each generate an execution thread for thread execution resources provided by at least one graphics core 1880.

[0296] In at least one embodiment, the graphics processor 1800 includes scalable thread execution resources featuring graphics cores 1880A-1880N (which may be modular and sometimes referred to as core slices), each graphics core having multiple sub-cores 1850A-1850N, 1860A-1860N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 1800 may have any number of graphics cores 1880A. In at least one embodiment, the graphics processor 1800 includes graphics cores 1880A having at least a first sub-core 1850A and a second sub-core 1860A. In at least one embodiment, the graphics processor 1800 is a low-power processor with a single sub-core (e.g., 1850A). In at least one embodiment, the graphics processor 1800 includes multiple graphics cores 1880A-1880N, each graphics core including a set of first sub-cores 1850A-1850N and a set of second sub-cores 1860A-1860N. In at least one embodiment, each of the first sub-cores 1850A-1850N includes at least a first set of execution units 1852A-1852N and media / texture samplers 1854A-1854N. In at least one embodiment, each of the second sub-cores 1860A-1860N includes at least a second set of execution units 1862A-1862N and samplers 1864A-1864N. In at least one embodiment, each of the sub-cores 1850A-1850N and 1860A-1860N shares a set of shared resources 1870A-1870N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0297] Inference and / or training logic 315 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 3A and / or Figure 3B Details are provided regarding inference and / or training logic 315. In at least one embodiment, inference and / or training logic 315 may be used in graphics processor 1800 to perform inference or prediction operations based at least in part on weight parameters computed using neural network training operations, neural network functions and / or architectures or neural network use cases described herein.

[0298] Figure 19This is a block diagram illustrating the microarchitecture of a processor 1900 according to at least one embodiment, which may include logic circuitry for executing instructions. In at least one embodiment, the processor 1900 may execute instructions, including x86 instructions, ARM instructions, and special-purpose instructions for application-specific integrated circuits (ASICs). In at least one embodiment, the processor 1900 may include registers for storing packaged data, such as the 84-bit wide MMX™ registers in an Intel microprocessor enabled by MMX technology in Santa Clara, California. In at least one embodiment, the MMX registers available in integer and floating-point forms may operate with packaged data elements accompanied by Single Instruction Multiple Data (“SIMD”) and Streaming SIMD Extensions (“SSE”) instructions. In at least one embodiment, a 148-bit wide XMM register associated with SSE2, SSE3, SSE4, AVX, or later (generally referred to as “SSEx”) technologies may hold such packaged data operands. In at least one embodiment, the processor 1900 may execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0299] In at least one embodiment, processor 1900 includes an ordered front end (“front end”) 1901 to fetch instructions to be executed and prepare instructions for later use in the processor pipeline. In at least one embodiment, front end 1901 may include several units. In at least one embodiment, instruction prefetcher 1926 fetches instructions from memory and provides the instructions to instruction decoder 1928, which in turn decodes or interprets the instructions. For example, in at least one embodiment, instruction decoder 1928 decodes the received instructions into one or more machine-executable so-called “micro-instructions” or “micro-operations” (also referred to as “micro-operations” or “micro-instructions”). In at least one embodiment, instruction decoder 1928 parses the instructions into opcodes and corresponding data and control fields, which can be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, trace cache 1930 may assemble the decoded micro-instructions into a program-ordered sequence or trace in micro-instruction queue 1934 for execution. In at least one embodiment, when trace cache 1930 encounters complex instructions, microcode ROM 1932 provides the micro-instructions required to complete the operation.

[0300] In at least one embodiment, some instructions may be converted into a single micro-operation, while others require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-instructions are required to complete an instruction, the instruction decoder 1928 may access the microcode ROM 1932 to execute the instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-instructions for processing at the instruction decoder 1928. In at least one embodiment, if multiple micro-instructions are required to complete the operation, the instructions may be stored in the microcode ROM 1932. In at least one embodiment, the trace cache 1930 references an entry point programmable logic array (“PLA”) to determine the correct micro-instruction pointer for reading a microcode sequence from the microcode ROM 1932 to complete one or more instructions, according to at least one embodiment. In at least one embodiment, after the microcode ROM 1932 has completed the micro-operation ordering of the instructions, the machine front end 1901 may resume fetching micro-operations from the trace cache 1930.

[0301] In at least one embodiment, the out-of-order execution engine (“out-of-order engine”) 1903 can prepare instructions for execution. In at least one embodiment, the out-of-order execution logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions descend the pipeline and are scheduled for execution. In at least one embodiment, the out-of-order execution engine 1903 includes, but is not limited to, an allocator / register renamer 1940, a memory microinstruction queue 1942, an integer / floating-point microinstruction queue 1944, a memory scheduler 1946, a fast scheduler 1902, a slow / general-purpose floating-point scheduler (“slow / general-purpose FP scheduler”) 1904, and a simple floating-point scheduler (“simple FP scheduler”) 1906. In at least one embodiment, the fast scheduler 1902, the slow / general-purpose floating-point scheduler 1904, and the simple floating-point scheduler 1906 are also collectively referred to as “microinstruction schedulers 1902, 1904, 1906”. In at least one embodiment, the allocator / register renamer 1940 allocates the machine buffers and resources required for the sequential execution of each microinstruction. In at least one embodiment, the allocator / register renamer 1940 renames logical registers to entries in a register file. In at least one embodiment, the allocator / register renamer 1940 also allocates entries for each microinstruction in one of two microinstruction queues, a memory microinstruction queue 1942 for memory operations and an integer / floating-point microinstruction queue 1944 for non-memory operations, preceding the memory scheduler 1946 and microinstruction schedulers 1902, 1904, and 1906. In at least one embodiment, the microinstruction schedulers 1902, 1904, and 1906 determine when they are ready to execute a microinstruction based on the readiness of their dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. The fast scheduler 1902 of at least one embodiment can schedule on each half of the master clock cycle, while the slow / general-purpose floating-point scheduler 1904 and the simple floating-point scheduler 1906 can schedule once per master processor clock cycle. In at least one embodiment, microinstruction schedulers 1902, 1904, and 1906 arbitrate the scheduling ports to schedule microinstructions for execution.

[0302] In at least one embodiment, execution block 1911 includes, but is not limited to, integer register file / tribute network 1908, floating-point register file / tribute network (“FP register file / tribute network”) 1910, address generation units (“AGU”) 1912 and 1914, fast arithmetic logic units (“fast ALU”) 1916 and 1918, slow arithmetic logic unit (“slow ALU”) 1920, floating-point ALU (“FP”) 1922, and floating-point move unit (“FP move”) 1924. In at least one embodiment, integer register file / tribute network 1908 and floating-point register file / bypass network 1910 are also referred to herein as “register files 1908, 1910”. In at least one embodiment, AGUs 1912 and 1914, fast ALUs 1916 and 1918, slow ALU 1920, floating-point ALU 1922, and floating-point movement unit 1924 are also referred to herein as "execution units 1912, 1914, 1916, 1918, 1920, 1922, and 1924". In at least one embodiment, execution block 1911 may include, but is not limited to, any number (including zeros) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0303] In at least one embodiment, register networks 1908 and 1910 may be arranged between microinstruction schedulers 1902, 1904, and 1906 and execution units 1912, 1914, 1916, 1918, 1920, 1922, and 1924. In at least one embodiment, integer register file / branch network 1908 performs integer operations. In at least one embodiment, floating-point register file / branch network 1910 performs floating-point operations. In at least one embodiment, each of register networks 1908 and 1910 may include, but is not limited to, a branch network that can bypass or forward recently completed results not yet written to a register file to a new dependent object. In at least one embodiment, register networks 1908 and 1910 can communicate data with each other. In at least one embodiment, integer register file / branch network 1908 may include, but is not limited to, two separate register files, one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, the floating-point register file / branch network 1910 may include, but is not limited to, entries that are 148 bits wide, since floating-point instructions typically have operands that are 84 to 148 bits wide.

[0304] In at least one embodiment, execution units 1912, 1914, 1916, 1918, 1920, 1922, and 1924 can execute instructions. In at least one embodiment, register networks 1908 and 1910 store integer and floating-point data operation values ​​that the microinstructions need to execute. In at least one embodiment, processor 1900 can be, but is not limited to, any number of execution units 1912, 1914, 1916, 1918, 1920, 1922, and 1924, and combinations thereof. In at least one embodiment, floating-point ALU 1922 and floating-point move unit 1924 can perform floating-point, MMX, SIMD, AVX, and SSE or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 1922 can be, but is not limited to, an 84-bit multiplication-84-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware can be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to the fast ALUs 1916 and 1918. In at least one embodiment, the fast ALUs 1916 and 1918 can perform fast operations with an effective delay of half a clock cycle. In at least one embodiment, most complex integer operations are routed to the slow ALU 1920, because the slow ALU 1920 can include, but is not limited to, integer execution hardware for long-latency type operations, such as multipliers, shifters, flag logic, and branching. In at least one embodiment, memory load / store operations can be performed by AGUs 1912 and 1914. In at least one embodiment, the fast ALU 1916, fast ALU 1918, and slow ALU 1920 can perform integer operations on 84-bit data operands. In at least one embodiment, the fast ALU 1916, fast ALU 1918, and slow ALU 1920 can be implemented to support various data bit sizes, including sixteen, thirty-two, 148, 276, etc. In at least one embodiment, the floating-point ALU 1922 and the floating-point moving unit 1924 can be implemented to support a range of operands with various bit widths, for example, they can be combined with SIMD and multimedia instructions to operate on 148-bit wide packaged data operands.

[0305] In at least one embodiment, microinstruction schedulers 1902, 1904, and 1906 schedule dependent operations before the parent load completes execution. In at least one embodiment, since microinstructions can be speculatively scheduled and executed within processor 1900, processor 1900 may also include logic for handling memory misses. In at least one embodiment, if a data load miss occurs in the data cache, there may be a dependent operation running in the pipeline that temporarily deprives the scheduler of the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and may allow independent operations to be completed. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0306] In at least one embodiment, "register" can refer to an onboard processor storage location that can be used as part of an instruction that identifies operands. In at least one embodiment, a register can be one that can be used externally to the processor (from a programmer's perspective). In at least one embodiment, a register may not be limited to a particular type of circuit. Rather, in at least one embodiment, a register can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented using a variety of different techniques via circuitry within the processor, such as dedicated physical registers, dynamically allocated physical registers renamed using register renaming, a combination of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, an integer register stores 34-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for encapsulating data.

[0307] Inference and / or training logic 315 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 3A and / or Figure 3B Details regarding inference and / or training logic 315 are provided. In at least one embodiment, some or all of the inference and / or training logic 315 may be incorporated into execution block 1911 and other memories or registers shown or not shown. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs shown in execution block 1911. Furthermore, weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown) that configure the ALUs of execution block 1911 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0308] Figure 20A deep learning application processor 2000 according to at least one embodiment is illustrated. In at least one embodiment, the deep learning application processor 2000 uses instructions, which, if executed by the deep learning application processor 2000, cause the deep learning application processor 2000 to perform some or all of the processes and techniques described herein. In at least one embodiment, the deep learning application processor 2000 is an application-specific integrated circuit (ASIC). In at least one embodiment, the application processor 2000 performs matrix multiplication operations or is "hardwired" into hardware as a result of executing one or more instructions or both. In at least one embodiment, the deep learning application processor 2000 includes, but is not limited to, processing clusters 2010(1)-2010(12), inter-chip links (“ICL”) 2020(1)-2020(12), inter-chip controllers (“ICC”) 2030(1)-2030(2), second-generation high-bandwidth memory (“HBM2”) 2040(1)-2040(4), memory controllers (“MemCtrlr”) 2042(1)-2042(4), high-bandwidth memory physical layers (“HBM PHY”) 2044(1)-2044(4), management controller central processing unit (“management controller CPU”) 2050, serial peripheral device interfaces, internal integrated circuits and general purpose input / output blocks (“SPI, I2C, GPIO”) 2060, peripheral component interconnect fast controller and direct memory access block (“PCIe controller and DMA”) 2070, and sixteen-channel peripheral component interconnect fast port (“PCI Express x”). 18”2080.

[0309] In at least one embodiment, the processing cluster 2010 can perform deep learning operations, including inference or prediction operations based on weight parameters computed using one or more training techniques, including those described herein. In at least one embodiment, each processing cluster 2010 can include, but is not limited to, any number and type of processors. In at least one embodiment, the deep learning application processor 2000 can include any number and type of processing cluster 2000. In at least one embodiment, the inter-chip link 2020 is bidirectional. In at least one embodiment, the inter-chip link 2020 and the inter-chip controller 2030 enable multiple deep learning application processors 2000 to exchange information, including activation information generated from executing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, the deep learning application processor 2000 can include any number (including zero) and type of ICL 2020 and ICC 2030.

[0310] In at least one embodiment, the HBM2 2040 provides a total of 34 GB of memory. In at least one embodiment, the HBM2 2040(i) is associated with both the memory controller 2042(i) and the HBM PHY 2044(i), where “i” is any integer. In at least one embodiment, any number of HBM2 2040s can provide any type and total amount of high-bandwidth memory and can be associated with any number (including zero) and type of memory controller 2042 and HBM PHY 2044. In at least one embodiment, any number and type of blocks can replace SPI, I2C, GPIO 3360, PCIe controller 2060 and DMA2070 and / or PCIe 2080 to implement any number and type of communication standards in any technically feasible manner.

[0311] Inference and / or training logic 315 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 3A and / or Figure 3B Details regarding the inference and / or training logic 315 are provided. In at least one embodiment, the deep learning application processor is used to train a machine learning model (e.g., a neural network) to predict or infer information provided to the deep learning application processor 2000. In at least one embodiment, the deep learning application processor 2000 is used to infer or predict information based on a trained machine learning model (e.g., a neural network) that has been trained by another processor or system or by the deep learning application processor 2000. In at least one embodiment, the processor 2000 may be used to perform one or more neural network use cases described herein.

[0312] Figure 21This is a block diagram of a neuromorphic processor 2100 according to at least one embodiment. In at least one embodiment, the neuromorphic processor 2100 may receive one or more inputs from a source external to the neuromorphic processor 2100. In at least one embodiment, these inputs may be transmitted to one or more neurons 2102 within the neuromorphic processor 2100. In at least one embodiment, the neurons 2102 and their components may be implemented using circuitry or logic including one or more arithmetic logic units (ALUs). In at least one embodiment, the neuromorphic processor 2100 may include, but is not limited to, thousands of instances of neurons 2102, but any suitable number of neurons 2102 may be used. In at least one embodiment, each instance of a neuron 2102 may include a neuron input 2104 and a neuron output 2106. In at least one embodiment, a neuron 2102 may generate an output that can be transmitted to the inputs of other instances of the neuron 2102. In at least one embodiment, the neuron input 2104 and the neuron output 2106 may be interconnected via synapses 2108.

[0313] In at least one embodiment, neuron 2102 and synapse 2108 may be interconnected, causing neuromorphic processor 2100 to operate to process or analyze information received by neuromorphic processor 2100. In at least one embodiment, neuron 2102 may send an output pulse (or “trigger” or “peak”) when the input received through neuron input 2104 exceeds a threshold. In at least one embodiment, neuron 2102 may sum or integrate the signal received at neuron input 2104. For example, in at least one embodiment, neuron 2102 may be implemented as a leaky integral-triggered neuron, wherein if the summation (referred to as “membrane potential”) exceeds a threshold, neuron 2102 may use a transfer function such as a sigmoid or threshold function to generate an output (or “trigger”). In at least one embodiment, a leaky integral-triggered neuron may sum the signal received at neuron input 2104 to a membrane potential and may apply an attenuation factor (or leak) to reduce the membrane potential. In at least one embodiment, a leaking integral-triggered neuron may trigger if multiple input signals are received at neuron input 2104 quickly enough to exceed a threshold (i.e., before the membrane potential decays too low to trigger). In at least one embodiment, neuron 2102 may be implemented using circuitry or logic that receives input, integrates the input to the membrane potential, and decays the membrane potential. In at least one embodiment, the input may be averaged, or any other suitable transfer function may be used. Furthermore, in at least one embodiment, neuron 2102 may include, but is not limited to, comparator circuitry or logic that generates an output spike at neuron output 2106 when the result of applying the transfer function to neuron input 2104 exceeds a threshold. In at least one embodiment, once neuron 2102 is triggered, it can ignore previously received input information by, for example, resetting the membrane potential to 0 or another suitable default value. In at least one embodiment, once the membrane potential is reset to 0, neuron 2102 may resume normal operation after a suitable period of time (or recovery period).

[0314] In at least one embodiment, neurons 2102 can be interconnected via synapses 2108. In at least one embodiment, synapses 2108 can be operated to transmit signals from the output of a first neuron 2102 to the input of a second neuron 2102. In at least one embodiment, neurons 2102 can transmit information on more than one instance of synapses 2108. In at least one embodiment, one or more instances of neuron outputs 2106 can be connected via instances of synapses 2108 to instances of neuron inputs 2104 within the same neuron 2102. In at least one embodiment, an instance of neuron 2102 that produces an output to be transmitted on the instance of synapse 2108 can be referred to as a "presynaptic neuron". In at least one embodiment, an instance of neuron 2102 that receives input transmitted via an instance of synapse 2108 can be referred to as a "postsynaptic neuron". In at least one embodiment, regarding various instances of synapse 2108, since an instance of neuron 2102 can receive input from one or more instances of synapse 2108 and can also transmit output through one or more instances of synapse 2108, a single instance of neuron 2102 can be both a "presynaptic neuron" and a "postsynaptic neuron".

[0315] In at least one embodiment, neurons 2102 may be organized into one or more layers. In at least one embodiment, each instance of neuron 2102 may have a neuron output 2106 that fans out to one or more neuron inputs 2104 via one or more synapses 2108. In at least one embodiment, the neuron output 2106 of neuron 2102 in the first layer 2110 may be connected to the neuron input 2104 of neuron 2102 in the second layer 2112. In at least one embodiment, layer 2110 may be referred to as a “feedforward layer.” In at least one embodiment, each instance of neuron 2102 in an instance of the first layer 2110 may fan out to each instance of neuron 2102 in the second layer 2112. In at least one embodiment, the first layer 2110 may be referred to as a “fully connected feedforward layer.” In at least one embodiment, each instance of neuron 2102 in an instance of the second layer 2112 fans out to fewer than all instances of neuron 2102 in the third layer 2114. In at least one embodiment, the second layer 2112 may be referred to as a “sparsely connected feedforward layer.” In at least one embodiment, neurons 2102 in the second layer 2112 may fan out to neurons 2102 in multiple other layers, including neurons 2102 fan out to the second layer 2112. In at least one embodiment, the second layer 2112 may be referred to as a “recurrent layer.” In at least one embodiment, the neuromorphic processor 2100 may be any suitable combination of recurrent layers and feedforward layers, including but not limited to sparsely connected feedforward layers and fully connected feedforward layers.

[0316] In at least one embodiment, the neuromorphic processor 2100 may include, but is not limited to, a reconfigurable interconnect architecture or dedicated hardwired interconnects to connect synapses 2108 to neurons 2102. In at least one embodiment, the neuromorphic processor 2100 may include, but is not limited to, circuitry or logic that allows synapses to be assigned to different neurons 2102 as needed, depending on the neural network topology and neuron fan-in / fan-out. For example, in at least one embodiment, synapses 2108 may be connected to neurons 2102 using interconnect structures such as on-chip networks or via dedicated connections. In at least one embodiment, synaptic interconnects and their components may be implemented using circuitry or logic.

[0317] Figure 22A processing system according to at least one embodiment is illustrated. In at least one embodiment, system 2200 includes one or more processors 2202 and one or more graphics processors 2208, and may be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 2202 or processor cores 2207. In at least one embodiment, system 2200 is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0318] In at least one embodiment, system 2200 may include or be integrated into a server-based gaming platform, including a game console, mobile game console, handheld game console, or online game console, which are game and media consoles. In at least one embodiment, system 2200 is a mobile phone, smartphone, tablet computing device, or mobile internet device. In at least one embodiment, processing system 2200 may also include components coupled to or integrated into a wearable device, such as a smartwatch wearable device, smart glasses device, augmented reality device, or virtual reality device. In at least one embodiment, processing system 2200 is a television or set-top box device having one or more processors 2202 and a graphical interface generated by one or more graphics processors 2208.

[0319] In at least one embodiment, each of the one or more processors 2202 includes one or more processor cores 2207 for processing instructions that, when executed, perform operations against the system and user software. In at least one embodiment, each of the one or more processor cores 2207 is configured to process a specific instruction sequence 2209. In at least one embodiment, the instruction sequence 2209 may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computation via Very Long Instruction Word (VLIW). In at least one embodiment, each processor core 2207 may process a different instruction sequence 2209, which may include instructions that facilitate the emulation of other instruction sequences. In at least one embodiment, the processor core 2207 may also include other processing devices, such as a digital signal processor (DSP).

[0320] In at least one embodiment, processor 2202 includes cache memory 2204. In at least one embodiment, processor 2202 may have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory is shared among various components of processor 2202. In at least one embodiment, processor 2202 also uses an external cache (e.g., a Level 3 (L3) cache or a last-level cache (LLC)) (not shown), which can be shared among processor cores 2207 using known cache coherence techniques. In at least one embodiment, processor 2202 further includes a register file 2206, which may include different types of registers for storing different types of data (e.g., integer registers, floating-point registers, status registers, and instruction pointer registers). In at least one embodiment, register file 2206 may include general-purpose registers or other registers.

[0321] In at least one embodiment, one or more processors 2202 are coupled to one or more interface buses 2210 to transmit communication signals, such as address, data, or control signals, between the processors 2202 and other components in the system 2200. In at least one embodiment, the interface bus 2210 may be a processor bus, such as a version of the Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 2210 is not limited to the DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), memory buses, or other types of interface buses. In at least one embodiment, the processor 2202 includes an integrated memory controller 2216 and a platform controller hub 2230. In at least one embodiment, the memory controller 2216 facilitates communication between memory devices and other components of the processing system 2200, while the platform controller hub (PCH) 2230 provides connectivity to input / output (I / O) devices via a local I / O bus.

[0322] In at least one embodiment, memory device 2220 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase-change memory device, or a device with suitable performance for use as processor memory. In at least one embodiment, memory device 2220 may be used as system memory of processing system 2200 to store data 2222 and instructions 2221 for use when one or more processors 2202 execute an application or process. In at least one embodiment, memory controller 2216 is also coupled to an optional external graphics processor 2212, which may communicate with one or more graphics processors 2208 of processor 2202 to perform graphics and media operations. In at least one embodiment, display device 2211 may be connected to processor 2202. In at least one embodiment, display device 2211 may include one or more internal display devices, such as in mobile electronic devices or laptop devices, or external display devices connected via a display interface (e.g., DisplayPort). In at least one embodiment, the display device 2211 may include a head-mounted display (HMD), such as a stereoscopic display device for virtual reality (VR) or augmented reality (AR) applications.

[0323] In at least one embodiment, the platform controller hub 2230 enables peripheral devices to connect to the storage device 2220 and the processor 2202 via a high-speed I / O bus. In at least one embodiment, the I / O peripheral devices include, but are not limited to, an audio controller 2246, a network controller 2234, a firmware interface 2228, a wireless transceiver 2226, a touch sensor 2225, and a data storage device 2224 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 2224 may be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 2225 may include a touchscreen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2226 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or LTE transceiver. In at least one embodiment, the firmware interface 2228 enables communication with the system firmware and may be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, network controller 2234 may enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to interface bus 2210. In at least one embodiment, audio controller 2246 is a multi-channel high-definition audio controller. In at least one embodiment, processing system 2200 includes an optional legacy I / O controller 2240 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to system 2200. In at least one embodiment, platform controller hub 2230 may also be connected to one or more Universal Serial Bus (USB) controllers 2242 that connect input devices, such as a keyboard and mouse combination 2243, a camera 2244, or other USB input devices.

[0324] In at least one embodiment, instances of the memory controller 2216 and platform controller hub 2230 may be integrated into a discrete external graphics processor, such as external graphics processor 2212. In at least one embodiment, the platform controller hub 2230 and / or the memory controller 2216 may be external to one or more processors 2202. For example, in at least one embodiment, system 2200 may include external memory controller 2216 and platform controller hub 2230, which may be configured as a memory controller hub and peripheral controller hub in a system chipset communicating with processor 2202.

[0325] Inference and / or training logic 315 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 3A and / or Figure 3BDetails regarding inference and / or training logic 315 are provided. In at least one embodiment, some or all of the inference and / or training logic 315 may be incorporated into the graphics processor 2200. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs embodied in a 3D pipeline. Furthermore, in at least one embodiment, the inference and / or training operations described herein may use, in addition to Figure 3A or Figure 3B The logic is performed using logic other than that shown. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALU of the graphics processor 2200 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0326] Figure 23 This is a block diagram of a processor 2300 having one or more processor cores 2302A-2302N, an integrated memory controller 2314, and an integrated graphics processor 2308 according to at least one embodiment. In at least one embodiment, the processor 2300 may include additional cores, up to and including additional cores 2302N indicated by dashed boxes. In at least one embodiment, each processor core 2302A-2302N includes one or more internal cache units 2304A-2304N. In at least one embodiment, each processor core may also access one or more shared cache units 2306.

[0327] In at least one embodiment, internal cache units 2304A-2304N and shared cache unit 2306 represent a cache memory hierarchy within processor 2300. In at least one embodiment, cache memory units 2304A-2304N may include at least one level of instruction and data cache within each processor core and one or more levels of cache in a shared intermediate cache, such as Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, wherein the highest level of cache preceding external memory is classified as LLC. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2306 and 2304A-2304N.

[0328] In at least one embodiment, the processor 2300 may further include a set of one or more bus controller units 2316 and a system agent core 2310. In at least one embodiment, the one or more bus controller units 2316 manage a set of peripheral buses, such as one or more PCI or PCIe buses. In at least one embodiment, the system agent core 2310 provides management functions for various processor components. In at least one embodiment, the system agent core 2310 includes one or more integrated memory controllers 2314 to manage access to various external memory devices (not shown).

[0329] In at least one embodiment, one or more processor cores 2302A-2302N include support for concurrent multithreading. In at least one embodiment, system agent core 2310 includes components for coordinating and operating cores 2302A-2302N during multithreaded processing. In at least one embodiment, system agent core 2310 may additionally include a power control unit (PCU) including logic and components for regulating one or more power states of processor cores 2302A-2302N and graphics processor 2308.

[0330] In at least one embodiment, processor 2300 further includes a graphics processor 2308 for performing graph processing operations. In at least one embodiment, graphics processor 2308 is coupled to a shared cache unit 2306 and a system proxy core 2310 including one or more integrated memory controllers 2314. In at least one embodiment, system proxy core 2310 further includes a display controller 2311 for driving graphics processor outputs to one or more coupled displays. In at least one embodiment, display controller 2311 may also be a separate module coupled to graphics processor 2308 via at least one interconnect, or it may be integrated within graphics processor 2308.

[0331] In at least one embodiment, the ring-based interconnect unit 2312 is used to couple internal components of the processor 2300. In at least one embodiment, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other technologies, may be used. In at least one embodiment, the graphics processor 2308 is coupled to the ring interconnect 2312 via I / O link 2313.

[0332] In at least one embodiment, I / O link 2313 represents at least one of a variety of I / O interconnects, including packaged I / O interconnects that facilitate communication between various processor components and high-performance embedded memory module 2318 (e.g., eDRAM module). In at least one embodiment, each of processor cores 2302A-2302N and graphics processor 2308 uses embedded memory module 2318 as a shared last-level cache.

[0333] In at least one embodiment, processor cores 2302A-2302N are homogeneous cores executing a common instruction set architecture. In at least one embodiment, processor cores 2302A-2302N are heterogeneous in terms of instruction set architecture (ISA), with one or more processor cores 2302A-2302N executing a common instruction set, while one or more other processor cores 2302A-2302N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, processor cores 2302A-2302N are heterogeneous in terms of microarchitecture, with one or more cores having relatively high power consumption coupled to one or more power cores having lower power consumption. In at least one embodiment, processor 2300 may be implemented on one or more chips or implemented as a SoC integrated circuit.

[0334] Inference and / or training logic 315 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 3A and / or Figure 3B Details regarding the inference and / or training logic 315 are provided. In at least one embodiment, some or all of the inference and / or training logic 315 may be incorporated into the graphics processor 2308. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs embodied in... Figure 23 The 3D pipeline, graphics core 2302, shared functional logic, or other logic are included. Furthermore, in at least one embodiment, the inference and / or training operations described herein can use, except... Figure 3A or Figure 3B The logic is performed using logic other than that shown. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALU of processor 2300 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0335] Figure 24This is a block diagram of a graphics processor 2400, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. In at least one embodiment, the graphics processor 2400 communicates with registers on the graphics processor 2400 and commands placed in memory via a memory-mapped I / O interface. In at least one embodiment, the graphics processor 2400 includes a memory interface 2414 for accessing memory. In at least one embodiment, the memory interface 2414 is an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0336] In at least one embodiment, the graphics processor 2400 further includes a display controller 2402 for driving display output data to the display device 2420. In at least one embodiment, the display controller 2402 includes a combination of hardware for one or more overlay planes of the display device 2420 and multi-layer video or user interface elements. In at least one embodiment, the display device 2420 may be an internal or external display device. In at least one embodiment, the display device 2420 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In at least one embodiment, the graphics processor 2400 includes a video codec engine 2406 for encoding, decoding, or transcoding media into, from, or between one or more media encoding formats, including but not limited to Moving Picture Experts Group (MPEG) formats (e.g., MPEG-2), Advanced Video Coding (AVC) formats (e.g., H.264 / MPEG-4 AVC, and SMPTE 621M / VC-1), and Joint Picture Experts Group (JPEG) formats (e.g., JPEG) and MotionJPEG (MJPEG).

[0337] In at least one embodiment, the graphics processor 2400 includes a block image transfer (BLIT) engine 2404 to perform two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfer. However, in at least one embodiment, one or more components of a graphics processing engine (GPE) 2410 are used to perform 2D graphics operations. In at least one embodiment, the GPE 2410 is a computational engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0338] In at least one embodiment, GPE 2410 includes a 3D pipeline 2412 for performing 3D operations, such as rendering 3D images and scenes using processing functions that manipulate 3D primitive shapes (e.g., rectangles, triangles, etc.). In at least one embodiment, 3D pipeline 2412 includes programmable and fixed function elements that perform various tasks and / or generate execution threads to 3D / media subsystem 2415. While 3D pipeline 2412 can be used to perform media operations, in at least one embodiment, GPE 2410 also includes a media pipeline 2416 for performing media operations such as video post-processing and image enhancement.

[0339] In at least one embodiment, the media pipeline 2416 includes fixed-function or programmable logic units for performing one or more specialized media operations, such as video decoding acceleration, video deinterlacing, and video encoding acceleration, replacing or representing the video codec engine 2406. In at least one embodiment, the media pipeline 2416 also includes a thread generation unit for generating threads to execute on the 3D / media subsystem 2415. In at least one embodiment, the generated threads perform computations of media operations on one or more graphics execution units included in the 3D / media subsystem 2415.

[0340] In at least one embodiment, the 3D / media subsystem 2415 includes logic for executing threads generated by the 3D pipeline 2412 and the media pipeline 2416. In at least one embodiment, the 3D pipeline 2412 and the media pipeline 2416 send thread execution requests to the 3D / media subsystem 2415, which includes thread dispatch logic for arbitrating various requests and dispatching them to available thread execution resources. In at least one embodiment, the execution resources include an array of graphics execution units for processing 3D and media threads. In at least one embodiment, the 3D / media subsystem 2415 includes one or more internal caches for thread instructions and data. In at least one embodiment, the subsystem 2415 also includes shared memory, which includes registers and addressable memory for sharing data between threads and storing output data.

[0341] Inference and / or training logic 315 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 3A and / or Figure 3B Details regarding inference and / or training logic 315 are provided. In at least one embodiment, some or all of the inference and / or training logic 315 may be incorporated into processor 2400. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs included in 3D pipeline 2412. Furthermore, in at least one embodiment, the inference and / or training operations described herein may use, except for... Figure 3A or Figure 3B The logic other than that shown is used to perform the task. In at least one embodiment, the weight parameters may be stored in on-chip or off-chip memory and / or registers (shown or not shown), which configure the ALU of the graphics processor 2400 to execute one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein.

[0342] Figure 25 This is a block diagram of a graphics processing engine 2510 of a graphics processor according to at least one embodiment. In at least one embodiment, the graphics processing engine (GPE) 2510 is... Figure 24 The version of GPE 2410 shown is illustrated. In at least one embodiment, the media pipeline 2516 is optional and may not be explicitly included in the GPE 2510. In at least one embodiment, a separate media and / or image processor is coupled to the GPE 2510.

[0343] In at least one embodiment, GPE 2510 is coupled to or includes command stream converter 2503, which provides command streams to 3D pipeline 2512 and / or media pipeline 2516. In at least one embodiment, command stream converter 2503 is coupled to memory, which may be system memory, or one or more of internal cache memory and shared cache memory. In at least one embodiment, command stream converter 2503 receives commands from memory and sends the commands to 3D pipeline 2512 and / or media pipeline 2516. In at least one embodiment, the commands are instructions, primitives, or micro-operations retrieved from a circular buffer that stores commands for 3D pipeline 2512 and media pipeline 2516. In at least one embodiment, the circular buffer may further include a batch command buffer storing multiple commands in batches. In at least one embodiment, commands for 3D pipeline 2512 may further include references to data stored in memory, such as, but not limited to, vertex and geometry data for 3D pipeline 2512 and / or image data and memory objects for media pipeline 2516. In at least one embodiment, the 3D pipeline 2512 and the media pipeline 2516 process commands and data by performing operations or by dispatching one or more execution threads to the graphics core array 2514. In at least one embodiment, the graphics core array 2514 includes one or more graphics core blocks (e.g., one or more graphics cores 2515A, one or more graphics cores 2515B), each block including one or more graphics cores. In at least one embodiment, each graphics core includes a set of graphics execution resources, which include general-purpose and graphics-specific execution logic for performing graphics and computation operations, and fixed-function texture processing and / or machine learning and artificial intelligence acceleration logic, including... Figure 3A and Figure 3B The reasoning and / or training logic in 315.

[0344] In at least one embodiment, the 3D pipeline 2512 includes fixed functions and programmable logic for processing one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 2514. In at least one embodiment, the graphics core array 2514 provides a unified execution resource block for processing shader programs. In at least one embodiment, the multipurpose execution logic (e.g., execution units) within the graphics cores 2515A-2515B of the graphics core array 2514 includes support for various 3D API shader languages ​​and can execute multiple concurrently running threads associated with multiple shaders.

[0345] In at least one embodiment, the graphics core array 2514 further includes execution logic for performing media functions, such as video and / or image processing. In at least one embodiment, in addition to graphics processing operations, the execution unit also includes general-purpose logic programmable to perform parallel general-purpose computing operations.

[0346] In at least one embodiment, output data can be output to memory in a unified return buffer (URB) 2518, the output data being generated by a thread executing on the graphics core array 2514. In at least one embodiment, the URB 2518 can store data from multiple threads. In at least one embodiment, the URB 2518 can be used to send data between different threads executing on the graphics core array 2514. In at least one embodiment, the URB 2518 can also be used for synchronization between threads on the graphics core array 2514 and fixed-function logic within shared-function logic 2520.

[0347] In at least one embodiment, the graphics core array 2514 is scalable, such that it includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of the GPE 2510. In at least one embodiment, the execution resources are dynamically scalable, such that they can be enabled or disabled as needed.

[0348] In at least one embodiment, the graphics core array 2514 is coupled to shared function logic 2520, which includes multiple resources shared among the graphics cores in the graphics core array 2514. In at least one embodiment, the shared functions performed by the shared function logic 2520 are embodied in hardware logic units that provide dedicated supplementary functions to the graphics core array 2514. In at least one embodiment, the shared function logic 2520 includes, but is not limited to, a sampler unit 2521, a math unit 2522, and inter-thread communication (ITC) logic 2523. In at least one embodiment, one or more caches 2525 are included in or coupled to the shared function logic 2520.

[0349] In at least one embodiment, shared functionality is used if the demand for dedicated functionality is insufficient to be contained within the graphics core array 2514. In at least one embodiment, a single instance of the dedicated functionality is used in shared functionality logic 2520 and shared among other execution resources within the graphics core array 2514. In at least one embodiment, a specific shared functionality may be included within shared functionality logic 2816 within the graphics core array 2514, said specific shared functionality being widely used within shared functionality logic 2520 of the graphics core array 2514. In at least one embodiment, shared functionality logic 2816 within the graphics core array 2514 may include some or all of the logic within shared functionality logic 2520. In at least one embodiment, all logic elements within shared functionality logic 2520 may be replicated within shared functionality logic 2526 of the graphics core array 2514. In at least one embodiment, shared functionality logic 2520 is excluded to support shared functionality logic 2526 within the graphics core array 2514.

[0350] Inference and / or training logic 315 is used to perform inference and / or training operations associated with one or more embodiments. This document combines... Figure 3A 3B and / or 3B provide details about the inference and / or training logic 315. In at least one embodiment, some or all of the inference and / or training logic 315 may be incorporated into the graphics processor 2510. For example, in at least one embodiment, the training and / or inference techniques described herein may use one or more ALUs embodied in the 3D pipeline 2512, graphics core 2515, shared function logic 2526, shared function logic 2520, or Figure 25 In other logic within the [process]. Furthermore, in at least one embodiment, the inference and / or training operations described herein can use [other methods besides...]. Figure 3A or Figure 3BThe logic is performed using logic other than that shown. In at least one embodiment, the weight parameters may be stored in on-chip or...

Claims

1. One or more processors, comprising: The circuit is used for: - Rendering the current frame of the graphics, wherein, for rendering the current frame of the graphics, the circuit performs at least the following operations: --One or more motion vectors are generated by mapping the center of the pixel in the current frame to the corresponding point in the previous frame; --Apply jitter to the one or more motion vectors; and --The color value of the pixel in the current frame is calculated by interpolating one or more color values ​​from the previous frame, wherein the positions of one or more color values ​​from the previous frame are determined at least in part based on the jittered one or more motion vectors.

2. The processors according to claim 1, wherein, The jitter is applied to the one or more motion vectors by adding a random value to at least one of the amplitude or direction values ​​of the one or more motion vectors.

3. The processors according to claim 1, wherein, Interpolation of the one or more color values ​​shall be performed using at least one of the following: bilinear interpolation, Catmull-Rom interpolation, maximum-order minimum support function, or Lanczos filtering.

4. The processors according to claim 1, wherein, The circuit is also used for: Apply a new jitter value to one or more motion vectors; as well as After the new jitter value is applied, the one or more motion vectors are resampled to calculate the color value of the pixel in the current frame.

5. The processors according to claim 1, wherein, The circuit reduces blur caused by jitter by applying a sharpening filter to the calculated color values, at least in part.

6. The processors according to claim 1, wherein, The jitter applied to the motion vector is performed during at least one of the shadow channel, occlusion channel, reflection channel, or specular reflection channel.

7. The processors according to claim 1, wherein, The circuit performs one or more time accumulation processes to determine the image value of the current frame based at least in part on the content from one or more previous frames.

8. A machine-readable medium having a set of instructions stored thereon, said instructions, if executed by one or more processors, causing said one or more processors to at least: One or more motion vectors are generated by mapping the center of the pixel in the current frame to the corresponding point in the previous frame. Apply jitter to one or more motion vectors; The color value of the pixel in the current frame is calculated by interpolating one or more color values ​​from the previous frame, wherein... The positions of one or more color values ​​in the previous frame are determined at least in part based on the one or more motion vectors of the jitter; and The rendering of the current frame of the output graphic is performed, the rendering being at least in part based on the color values.

9. The machine-readable medium according to claim 8, wherein, The jitter includes adding random amplitude and / or direction values ​​to the one or more motion vectors.

10. The machine-readable medium according to claim 8, wherein, Interpolation of the one or more color values ​​shall be performed using at least one of the following: bilinear interpolation, Catmull-Rom interpolation, maximum-order minimum support function, and / or Lanczos filtering.

11. The machine-readable medium according to claim 8, wherein, The one or more processors are used for: Apply a new jitter value to one or more motion vectors; as well as After the new jitter value is applied, the one or more motion vectors are resampled to calculate the color value of the pixel in the current frame.

12. The machine-readable medium according to claim 8, wherein, The one or more processors apply a sharpening filter to the calculated color values ​​to reduce blur caused by jitter.

13. The machine-readable medium according to claim 8, wherein, The jitter applied to the motion vector is performed during any of the shadow channel, occlusion channel, reflection channel, or specular reflection channel.

14. The machine-readable medium according to claim 8, wherein, The one or more processors utilize one or more time accumulation processes to determine the image value of the current frame based at least in part on the time content from one or more previous frames.

15. A system comprising: One or more processors that generate the current frame of the video by at least the following means: - One or more motion vectors are generated by mapping the center of the pixel in the current frame to the corresponding point in the previous frame; - Apply jitter to the one or more motion vectors; and - The color value of the pixel in the current frame is calculated by interpolating one or more color values ​​from the previous frame, wherein the positions of one or more color values ​​from the previous frame are determined at least in part based on the jittered one or more motion vectors.

16. The system according to claim 15, wherein, The jitter is applied to the one or more motion vectors by randomizing at least one of the amplitude or direction of the one or more motion vectors.

17. The system according to claim 15, wherein, The interpolation of the one or more color values ​​is performed in any of the following ways: linear, quadratic, cubic, or any other higher-order interpolation technique.

18. The system according to claim 15, wherein, The one or more processors are used for: Apply a new jitter value to one or more motion vectors; as well as After the new jitter value is applied, the one or more motion vectors are resampled to calculate the color value of the pixel in the current frame.

19. The system according to claim 15, wherein, The one or more processors apply a sharpening filter to the calculated color values.

20. The system according to claim 15, wherein, The jitter applied to the motion vector is performed during an intermediate channel, which includes any one of a shadow channel, an occlusion channel, a reflection channel, or a specular reflection channel.

21. The system according to claim 15, wherein, The one or more processors utilize one or more anti-aliasing techniques to determine the image value of the current frame based at least in part on the temporal content from one or more previous frames.

Images