Large depth-to-width ratio nano vacuum channel laser collaborative manufacturing process
By employing a combined laser and pulsed electroplating manufacturing process, along with precise nano-vacuum channel fabrication technology, the manufacturing compatibility and consistency issues of high aspect ratio nano-vacuum channel devices have been resolved, enabling efficient and precise production of nano-vacuum channel devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NINGBO INST OF MATERIALS TECH & ENG CHINESE ACAD OF SCI
- Filing Date
- 2025-12-02
- Publication Date
- 2026-04-21
AI Technical Summary
Existing processes present challenges in fabricating high aspect ratio nano-vacuum channel devices, particularly in terms of manufacturing compatibility, dimensional consistency, and critical structural control, especially in the quality control of metal films and the manufacturing precision of multilayer structures.
Employing a collaborative manufacturing process involving laser, deposition, and pulsed electroplating, the electrode pattern is defined using photoresist, and the fabrication of nano-vacuum channels is precisely controlled by combining inductively coupled plasma etching and femtosecond laser removal technology. This process includes metal electrode deposition, oxide sacrificial layer deposition, and laser glazing.
It enables the fabrication of high-precision, high-consistency nano-vacuum channels, improving the electrical performance and reliability of devices, and is suitable for mass production and high-performance integrated circuit manufacturing.
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Figure CN121905754A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of micro-nano electronic device manufacturing technology, and relates to a laser-assisted manufacturing process for a large aspect ratio nano-vacuum channel. Background Technology
[0002] In recent years, with the development of nanotechnology and microelectronics, nano-vacuum channel devices have attracted widespread attention in academia due to their unique electron transport characteristics. Electron transport is completed within a nanoscale channel in a vacuum or near-vacuum state. Electrons in a vacuum medium can achieve scatter-free ballistic transport with minimal signal distortion, and the electron velocity can approach the speed of light, thus enabling the devices to have ultrafast femtosecond-level response speeds and terahertz-level cutoff frequencies. Furthermore, due to the absence of the PN junction effect found in traditional semiconductor devices, these devices exhibit excellent stability and tolerance in harsh environments such as high temperatures or strong radiation. With the development of micro- and nanofabrication technologies, researchers have proposed using integrated circuit processes to fabricate vacuum electronic devices, aiming to combine the advantages of vacuum devices with those of solid-state devices.
[0003] In 2012, the concept of nanoscale vacuum channel transistors was first proposed, followed by designs such as vacuum channel field-effect transistors. These nanoscale vacuum devices, based on advanced micro- and nanofabrication technologies, share common revolutionary features: the electrode spacing has been reduced to near the mean free path of air molecules, the operating voltage is lower than the first ionization energy of air, and theoretically, electron ballistic transport can be achieved under atmospheric conditions without gas breakdown. These characteristics endow nanoscale vacuum channel devices with extremely fast response speeds and excellent anti-interference capabilities, making them an ideal choice for future radiation-resistant, high-frequency, and high-speed electronic systems. These superior characteristics have spurred in-depth research into the structure and fabrication processes of nanoscale vacuum channel devices.
[0004] Researchers have proposed various device structures (such as lateral, vertical, and ring gates) to optimize emission performance and have attempted to use a variety of materials, including silicon, metals, wide-bandgap semiconductors, and carbon nanomaterials, to improve device robustness and efficiency. However, each structural design has its own advantages and disadvantages in terms of manufacturing compatibility and critical dimension control. For example, the lateral coplanar structure has the highest compatibility with traditional CMOS processes, but it has extremely stringent requirements for technologies such as extreme ultraviolet lithography. Ring gate or tip emission structures have stronger electric field control capabilities, but their fabrication complexity and challenges in critical dimension consistency are significantly increased. In addition, high aspect ratio nanoscale vacuum channels are key structures for improving device electron transport efficiency and anti-interference capabilities, but existing processes still face many challenges in fabricating high aspect ratios, dimensional consistency, and device performance, especially in the quality control of metal films and the manufacturing precision of multilayer structures. Summary of the Invention
[0005] In view of the problems existing in the prior art, the purpose of this invention is to provide a laser-assisted manufacturing process for nano-vacuum channels with large aspect ratios. By using laser, deposition and pulse electroplating as assisted manufacturing processes, devices with nano-vacuum channels with large aspect ratios are prepared.
[0006] The present invention employs the following technical solutions to achieve its objective: A laser-assisted manufacturing process for high aspect ratio nano-vacuum channels includes the following steps: (1) A first metal reinforcement layer and a first metal seed layer are sequentially deposited on a dielectric substrate; (2) Define the first layer electrode pattern using photoresist process; (3) A first metal electrode is deposited in the first layer electrode pattern area using a pulse electroplating process and then annealed in a vacuum; (4) Laser glazing treatment is performed on the surface of the first metal electrode to improve the film quality; (5) Use inductively coupled plasma etching (ICP) to remove excess first metal reinforcement layer and first metal seed layer, leaving only the first metal electrode structure; (6) An oxide sacrificial layer is deposited on the device surface using deposition technology; (7) A second metal reinforcement layer and a second metal seed layer are sequentially deposited on the surface of the sacrificial layer; (8) Define the second layer electrode pattern using photoresist process; (9) A second metal electrode is deposited in the second electrode pattern area using a pulse electroplating process and then annealed in a vacuum; (10) Remove excess second metal reinforcement layer and second metal seed layer by inductively coupled plasma etching; (11) Use femtosecond laser to remove the overlapping area of the first and second layer electrodes, eliminate the defects caused by photolithography positioning error, and expose the structural gap of the nano-vacuum channel; (12) The oxide sacrificial layer is removed by wet etching process to release and form a nano-vacuum channel structure.
[0007] The following is a detailed explanation of step (1): Optionally, the dielectric substrate is a glass substrate or a silicon substrate.
[0008] The deposition method in step (1) is magnetron sputtering. The conditions for magnetron sputtering are not particularly limited, as long as the required metal reinforcement layer and metal seed layer can be deposited on the substrate surface, it falls within the protection scope of this invention.
[0009] Preferably, the first metal reinforcement layer is a metal layer formed from one or more of chromium, titanium, and tungsten. The thickness of the first metal reinforcement layer is 1~50 nm.
[0010] Preferably, the first metal seed layer is a metal layer formed from one or more of gold, copper, nickel, and platinum. The thickness of the first metal seed layer is 80~500 nm.
[0011] Depositing a metal reinforcement layer and a metal seed layer on the surface of a dielectric substrate enhances the adhesion between the electrode and the substrate, providing a reliable foundation for subsequent electroplating processes.
[0012] The following is a detailed description of step (2): Photoresist is coated on the surface of the metal seed layer. After baking, the first electrode pattern mask is aligned and covered on the photoresist layer. Ultraviolet exposure and development are performed to obtain the corresponding first electrode pattern.
[0013] Preferably, a double-layer photoresist process is used to define the first layer electrode pattern.
[0014] The double-layer photoresist includes ultraviolet photoresist and LOR (Light Oriented Resist) resist. Specifically, an LOR base resist is coated on the surface of the metal seed layer, baked, and then an ultraviolet photoresist is coated. After baking, the first electrode pattern mask is aligned and placed on the ultraviolet photoresist layer, and ultraviolet exposure and development are performed to obtain the corresponding first electrode pattern.
[0015] The following is a detailed explanation of step (3): The pulse electroplating process conditions include: immersing the substrate in an electroplating solution containing metal ions, electroplating in a constant current pulse mode, and an average current density of 0.1~10 mA / cm². 2 The frequency ranges from 1 to 100 kHz.
[0016] Optionally, the first metal electrode is made of an alloy formed from one or more of gold, copper, aluminum, tungsten, nickel, and platinum.
[0017] The electrolyte used in pulse electroplating is selected based on the specific metal electrode material.
[0018] Preferably, the thickness of the first metal electrode is 5 to 50 μm.
[0019] Preferably, the annealing temperature is 500–750 °C, and the annealing time is 10–100 min. Annealing is performed in a vacuum environment with a chamber pressure ≤1×10⁻⁶. -2 Pa.
[0020] Pulse electroplating technology is used to precisely control the amount of metal deposited during the electroplating process, deposit the first metal electrode, and eliminate stress during the annealing process to form a high-quality electrode layer.
[0021] The following is a detailed explanation of step (4): Laser glazing treatment: By applying a short-wavelength pulsed laser to the electrode surface, the electrode surface is rapidly melted and then rapidly cooled to form a dense and smooth glaze layer. This can significantly improve the uniformity of the metal surface, remove microparticles and surface stress concentration areas, and eliminate defects and inhomogeneities caused by the electroplating process.
[0022] The laser enamel treatment is preferably performed using a nanosecond laser with a wavelength of 300~365 nm.
[0023] The conditions for laser enamel treatment include: scanning speed of 50~500 mm / s, repetition rate of 50~200 kHz, and power density of 0.1~7.64*10⁻⁶. 6 W / m 2 The spot diameter is 30~100 μm and the pulse width is 50~1000 ns.
[0024] Steps (5) and (10) use inductively coupled plasma etching (ICP-E) to precisely remove excess metal layers (metal seed layer and metal reinforcement layer in non-electrode regions) while preserving the high-precision structure of the electrode regions. The conditions for ICP-E are not particularly limited; any conditions that can remove the metal seed layer and metal reinforcement layer are acceptable.
[0025] The following is a detailed description of step (6): Preferably, the oxide sacrificial layer is a silicon oxide layer.
[0026] Chemical vapor deposition (CVD) technology is used to deposit an oxide sacrificial layer on the device surface. The conditions of CVD technology are not particularly limited, as long as the conditions can be met to deposit the required oxide sacrificial layer on the device surface.
[0027] Preferably, the thickness of the oxide sacrificial layer is 2~200 nm. The thickness of the oxide sacrificial layer is the width of the subsequently formed nano-vacuum channel structure.
[0028] An oxide sacrificial layer is precisely grown using deposition technology, with adjustable thickness, allowing for adjustment of the width of the nano-vacuum channel structure as needed.
[0029] The following is a detailed explanation of step (7): The deposition method in step (7) is magnetron sputtering.
[0030] Preferably, the second metal reinforcement layer is a metal layer formed from one or more of chromium, titanium, and tungsten. The thickness of the second metal reinforcement layer is 1~50 nm.
[0031] A second metal reinforcement layer is sputtered onto the sacrificial layer to ensure the adhesion and conductivity of subsequent electroplating.
[0032] Preferably, the second metal seed layer is a metal layer formed from one or more of gold, copper, nickel, and platinum. The thickness of the second metal seed layer is 80~500 nm.
[0033] Step (8) is the same as step (2), except that the electrode pattern mask and the coverage position are different.
[0034] The process description for step (9) is the same as that for step (3). Preferably, the thickness of the second metal electrode is 5–50 μm. A second layer of electrode material is deposited using pulse electroplating technology to form a high-quality electrode structure, and then annealed to optimize the stress and performance of the electrode.
[0035] The following is a detailed explanation of step (11): Step (11) is performed using a femtosecond laser. The femtosecond laser has almost no heat-affected zone, which can achieve cold processing and avoid the consequences of melting in the ablation area.
[0036] Preferably, the femtosecond laser has a wavelength of 1030 nm, a pulse width of 5~300 fs, a scan repetition frequency >200 kHz, preferably 205~500 kHz, and a power density of 0.1~3*10 8 W / cm 2 The spot diameter is 3~10 μm.
[0037] Femtosecond lasers are used to remove the overlapping area between the first and second electrode layers to precisely control the nano-vacuum channel structure.
[0038] The following is a detailed explanation of step (12): The wet etching process uses a phosphoric acid solution or a BOE mixture as the etching solution.
[0039] Preferably, when the etching solution is a phosphoric acid solution, the mass fraction of the phosphoric acid solution is 10~80 wt%, the etching temperature is 40~80 ℃, and the etching time is 5~60 min.
[0040] Preferably, when the etching solution is a BOE mixture, the BOE mixture includes 10~30 wt% NH4F, 1~6 wt% HF and water (balance), the etching temperature is 10~50 ℃, and the etching time is 1~50 min.
[0041] Preferably, the aspect ratio of the obtained nanoscale vacuum channel structure is greater than 100:1, and the width is controlled in the range of 2~200 nm.
[0042] This invention leverages the precise controllability of nanoscale oxide film thickness in deposition technology to propose a laser-assisted fabrication process for large aspect ratio nanoscale vacuum channels controlled by an oxide sacrificial layer, thereby constructing such channels. Simultaneously, addressing the issue of numerous defects in electroplated layers, research is conducted on laser remelting processes for tungsten alloy surfaces to achieve metal surface densification and enhance the mechanical strength and ablation resistance of the electrode layer. Furthermore, to resolve the electrode overlap problem caused by photolithography positioning errors, research is carried out on femtosecond laser nanoscale removal processes, developing femtosecond laser spatiotemporal coordinated modulation technology to achieve highly selective and efficient removal of heterogeneous materials. By optimizing key factors such as process and structure, a wafer-level nanoplasma switch array fabrication method with high uniformity and high yield is formed. This solves the technical challenges of traditional technologies in thick-film electrode deposition, stress control, and surface quality, and significantly improves device performance and reliability.
[0043] Compared with the prior art, the present invention has the following beneficial effects: 1. High precision and high consistency: By precisely controlling processes such as metal electroplating, sacrificial layer deposition, and laser removal, high-precision manufacturing of nano-vacuum channel devices with large aspect ratios is achieved, ensuring the consistency of device dimensions.
[0044] 2. Excellent film quality: The combination of laser glazing and pulsed electroplating improves film quality, reduces defects, and enhances the electrical performance of the device.
[0045] 3. Superior stress control capability: Through vacuum annealing stress relief technology, the stress in the multilayer structure is effectively controlled, improving the reliability and stability of the device.
[0046] 4. Suitable for mass production: This process has good compatibility and scalability, and is suitable for large-scale production and the manufacturing of high-performance integrated circuits.
[0047] In summary, the manufacturing process provided by this invention can solve many problems in the prior art and provides a feasible technical route for the efficient, precise and mass production of high aspect ratio nano-vacuum channel devices. Attached Figure Description
[0048] Figure 1 This is a schematic diagram of the overall manufacturing process of Embodiment 1 of the present invention, showing 12 key steps from seed layer deposition to the final fabrication of nano-vacuum channels.
[0049] Figure 2 This is a scanning electron microscope (SEM) image of the nano-vacuum channel prepared in Example 1 of the present invention. Detailed Implementation
[0050] In the description of this invention, unless otherwise stated, the numerical range "a~b" represents a shortened representation of any combination of real numbers between a and b, and includes both a and b. "Multiple" includes two, three, four, five, or more.
[0051] The technical solution of the present invention will be further described and illustrated below with reference to specific embodiments and accompanying drawings. It should be understood that the specific embodiments described herein are only for the purpose of helping to understand the present invention and are not intended to limit the specific scope of the present invention. Furthermore, the accompanying drawings used herein are merely for better illustrating the content disclosed in the present invention and do not limit the scope of protection. Unless otherwise specified, the raw materials used in the embodiments of the present invention are all commonly used in the art, and the methods used in the embodiments are all conventional methods in the art.
[0052] Example 1 This embodiment aims to fabricate a type of high aspect ratio nano-vacuum channel device based on tungsten-copper (W-Cu) electrode material. The fabrication process is as follows: Figure 1 As shown, the details are as follows: Step 1: Deposition of Metal Seed Layer Using magnetron sputtering technology, a chromium (Cr) layer of about 15 nm thick is first deposited on a single surface of the cleaned glass substrate to improve adhesion; then a copper (Cu) layer of about 200 nm thick is deposited as a conductive seed layer for electroplating.
[0053] Step 2: Definition and insulation treatment of the first layer of electrodes A dual-layer photolithography structure using a combination of S1813 photoresist and LOR resist was employed: LOR3A was spin-coated onto the copper layer at 3000 rpm to a thickness of 0.33 μm, and baked at 100℃ for 5 min. Then, S1813 photoresist was spin-coated onto the LOR layer at 3000 rpm to a thickness of 1.5 μm, and baked at 100℃ for 10 min. The designed first-layer electrode pattern mask was aligned and placed over the photoresist, followed by UV exposure (30 s), development (12 s), and post-baking (160℃ for 5 min) to obtain the first-layer electrode pattern. Step 3: Electroplating and annealing of the first electrode layer Pulse electroplating is performed within the defined first-layer electrode pattern area. The electroplating solution is a composite electrolyte containing tungsten salt and copper salt. The wafer is immersed in the electroplating solution containing metal ions, and electroplating is performed in a constant current pulse mode with an average current density of 10 mA / cm². 2 A tungsten-copper alloy electrode was obtained at a frequency of 10 kHz, with the electrode thickness controlled at 20 μm. After electroplating, the wafer was immersed in acetone to remove the photoresist covering the non-patterned areas. Then, the wafer was subjected to a vacuum environment (10 kHz). -3The film is annealed at 600°C for 60 minutes to release internal stress and improve film density.
[0054] Step 4: Laser glazing treatment The surface of the first tungsten-copper alloy electrode was glazed using a 355 nm wavelength nanosecond laser at a scanning speed of 50 mm / s, a repetition rate of 100 kHz, and a power density of 4.5 × 10⁻⁶. 5 W / m 2 The spot diameter is 50 μm and the pulse width is 100 ns. It can significantly improve the uniformity of metal surfaces and remove microparticles and surface stress concentration areas.
[0055] Step 5: Remove redundant metal layers Inductively coupled plasma etching (ICP) was used with ICP power of 1500 W, Table power of 100 W, etching gases of SF6: 20 sccm, C4F8: 20 sccm, and O2: 10 sccm, and pressure of 10 mtorr. The copper layer in the non-electrode area and the bottom chromium reinforcement layer were removed, leaving only the first tungsten-copper alloy electrode structure.
[0056] Step 6: Sacrificial layer deposition Using chemical vapor deposition (CVD) with an RF power of 140 W, N2O 1000 sccm, and SiH4 530 sccm, a 15 nm thick silicon oxide (SiO2) film was grown on the entire device surface as a sacrificial layer required for the subsequent formation of the vacuum channel.
[0057] Step 7: Construction of the second electrode seed layer A 10 nm thick tungsten (W) adhesion layer and a 200 nm thick copper layer were sequentially sputtered onto the surface of the sacrificial layer as a seed layer for electroplating the second electrode.
[0058] Step 8: Definition and insulation treatment of the second layer electrode pattern A dual-layer photolithography structure using a combination of S1813 photoresist and LOR resist was employed: LOR3A with a thickness of 330 nm was spin-coated onto the copper layer and baked at 100℃ for 5 min; then, S1813 photoresist with a thickness of 1.5 μm was spin-coated onto the LOR layer and baked at 100℃ for 10 min; the designed second electrode pattern mask was aligned and covered onto the photoresist, followed by UV exposure (exposure time of 30 s), development (development time of 12 s), and post-baking (160℃ for 5 min) to obtain the second electrode pattern.
[0059] Step 9: Electroplating and annealing of the second electrode layer The same pulse electroplating process as the first electrode layer was used to deposit a tungsten-copper alloy within the patterned area of the second electrode layer, with an electrode thickness of approximately 20 μm. After electroplating, the photoresist covering the patterned area was removed; then, in a vacuum environment (10... - 3 The sample was annealed at 600 °C for 60 minutes.
[0060] Step 10: Remove redundant metal layers Inductively coupled plasma etching (ICP) was used with an ICP power of 1500 W, a Table power of 100 W, and etching gases of SF6: 20 sccm, C4F8: 20 sccm, and O2: 10 sccm, at a pressure of 10 mtorr, to precisely remove the copper and tungsten layers in the second non-electrode region.
[0061] Step 11: Femtosecond laser removal of overlapping areas The femtosecond laser was used with a wavelength of 1030 nm, a pulse width of 300 fs, a scanning repetition rate of 500 kHz, and a power density of 1.5 × 10⁻⁶. 8 W / cm 2 The spot diameter is 3 μm. The overlapping area of the first and second electrode layers is peeled off to expose the sacrificial layer.
[0062] Step 12: Wet removal of the sacrificial layer The device was placed in a BOE aqueous solution of 21 wt% NH4F and 3 wt% HF and etched at 20 °C for 1 min to remove the sacrificial layer, thus forming a nanoscale vacuum channel structure and completing the device fabrication.
[0063] Figure 2 Scanning electron microscope (SEM) image of the nano-vacuum channel prepared in Example 1.
[0064] Example 2 Step 1: Deposition of Metal Seed Layer Using magnetron sputtering technology, a titanium (Ti) layer of about 20 nm thick is first deposited on a single surface of a cleaned glass substrate to improve adhesion; then a copper (Cu) layer of about 250 nm thick is deposited as a conductive seed layer for electroplating.
[0065] Step 2: Definition and insulation treatment of the first layer of electrodes A dual-layer photolithography structure using a combination of S1813 photoresist and LOR resist was employed: LOR3A was spin-coated onto the copper layer at 3000 rpm to a thickness of 330 nm, followed by baking at 100℃ for 10 min. Then, S1813 photoresist was spin-coated onto the LOR layer at 3000 rpm to a thickness of 1.5 μm, followed by baking at 100℃ for 10 min. The designed first-layer electrode pattern mask was aligned and covered onto the photoresist, followed by UV exposure (exposure time of 30 s), development (development time of 12 s), and post-baking (100℃ for 5 min) to obtain the first-layer electrode pattern.
[0066] Step 3: Electroplating and annealing of the first electrode layer Pulse electroplating is performed within the defined first-layer electrode pattern area. The electroplating solution is a composite electrolyte containing tungsten salt and nickel salt. The wafer is immersed in the electroplating solution containing metal ions, and electroplating is performed in a constant current pulse mode with an average current density of 8 mA / cm². 2 A tungsten-nickel alloy electrode was obtained at a frequency of 15 kHz, with the electrode thickness controlled at 15 μm. After electroplating, the photoresist covering the non-patterned areas was removed. Then, the electrode was deposited in a vacuum environment (10 kHz). -3 The film is annealed at 550°C for 80 minutes to release internal stress and improve film density.
[0067] Step 4: Laser glazing treatment The surface of the first tungsten-nickel alloy electrode was glazed using a 355 nm wavelength nanosecond laser with a scanning speed of 250 mm / s, a repetition rate of 150 kHz, and a power density of 1.125 × 10⁻⁶. 6 w / m 2 With a spot diameter of 50 μm and a pulse width of 100 ns, it can significantly improve the uniformity of metal surfaces and remove microparticles and surface stress concentration areas.
[0068] Step 5: Remove redundant metal layers Inductively coupled plasma etching (ICP) was used with ICP power of 1500 W, Table power of 100 W, etching gases of SF6: 20 sccm, C4F8: 20 sccm, and O2: 10 sccm, and pressure of 10 mtorr. The copper layer and the bottom titanium reinforcement layer in the non-electrode area were removed, leaving only the first tungsten-nickel alloy electrode structure.
[0069] Step 6: Sacrificial layer deposition Using chemical vapor deposition (CVD) with an RF power of 140 W, N2O 1000 sccm, and SiH4 530 sccm, a 15 nm thick silicon oxide (SiO2) film was grown on the entire device surface as a sacrificial layer required for the subsequent formation of the vacuum channel.
[0070] Step 7: Construction of the second electrode seed layer A 15 nm thick titanium (Ti) adhesion layer and a 250 nm thick copper layer were sequentially sputtered onto the surface of the sacrificial layer as a seed layer for electroplating the second electrode.
[0071] Step 8: Definition and insulation treatment of the second layer electrode pattern A dual-layer photolithography structure using a combination of S1813 photoresist and LOR resist was employed: LOR3A with a thickness of 350 nm was spin-coated onto the copper layer and baked at 100℃ for 10 min; then, S1813 photoresist with a thickness of 1.8 μm was spin-coated onto the LOR layer and baked at 100℃ for 10 min; the designed second electrode pattern mask was aligned and covered on the photoresist, followed by UV exposure (exposure time of 32 s), development (development time of 10 s), and post-baking (165℃ for 5 min) to obtain the second electrode pattern.
[0072] Step 9: Electroplating and annealing of the second electrode layer The second electrode pattern area was deposited using the same pulse electroplating process as the first electrode, with an electrode thickness of approximately 15 μm. After electroplating, the photoresist covering the pattern area was removed; then, the plating was performed in a vacuum environment (10... - 3 The sample was annealed at 550 °C for 80 minutes.
[0073] Step 10: Remove redundant metal layers Inductively coupled plasma etching (ICP) was used with an ICP power of 1500 W, a Table power of 100 W, and etching gases of SF6: 20 sccm, C4F8: 20 sccm, and O2: 10 sccm, at a pressure of 10 mtorr, to precisely remove the copper and titanium layers in the second non-electrode region.
[0074] Step 11: Femtosecond laser removal of overlapping areas The femtosecond laser was used with a wavelength of 1030 nm, a pulse width of 200 fs, a scanning repetition rate of 300 kHz, and a power density of 1.0 × 10⁻⁶. 8 W / cm 2 The spot diameter is 5 μm. The overlapping area of the first and second electrode layers is peeled off to expose the sacrificial layer.
[0075] Step 12: Wet removal of the sacrificial layer The device was placed in a 30wt% phosphoric acid solution and etched at 60 °C for 10 min to remove the sacrificial layer, ultimately forming a nanoscale vacuum channel structure and completing the device fabrication.
[0076] All aspects, embodiments, and features of this invention should be considered illustrative in all respects and not limiting of the invention; the scope of the invention is defined only by the claims. Other embodiments, modifications, and uses will become apparent to those skilled in the art without departing from the spirit and scope of the invention as claimed.
[0077] In the preparation method of this invention, the order of the steps is not limited to the listed order. For those skilled in the art, variations in the order of the steps without creative effort are also within the scope of protection of this invention. Furthermore, two or more steps or actions can be performed simultaneously.
[0078] Finally, it should be noted that the specific embodiments described herein are merely illustrative examples of the invention and are not intended to limit the implementation of the invention. Those skilled in the art can make various modifications or additions to the described specific embodiments or use similar methods to replace them; it is neither necessary nor possible to exemplify all embodiments here. However, these obvious variations or modifications derived from the essential spirit of the invention still fall within the scope of protection of the invention, and interpreting them as any additional limitation would contradict the spirit of the invention.
Claims
1. A laser-assisted manufacturing process for a large aspect ratio nano-vacuum channel, characterized in that, Includes the following steps: (1) A first metal reinforcement layer and a first metal seed layer are sequentially deposited on a dielectric substrate; (2) Define the first layer electrode pattern using photoresist process; (3) A first metal electrode is deposited in the first layer electrode pattern area using a pulse electroplating process and then annealed in a vacuum; (4) Laser glazing treatment is performed on the surface of the first metal electrode to improve the film quality; (5) Remove excess first metal reinforcement layer and first metal seed layer by inductively coupled plasma etching, leaving only the first metal electrode structure; (6) An oxide sacrificial layer is deposited on the device surface using deposition technology; (7) A second metal reinforcement layer and a second metal seed layer are sequentially deposited on the surface of the sacrificial layer; (8) Define the second layer electrode pattern using photoresist process; (9) A second metal electrode is deposited in the second electrode pattern area using a pulse electroplating process and then annealed in a vacuum; (10) Remove excess second metal reinforcement layer and second metal seed layer by inductively coupled plasma etching; (11) The overlapping area between the first and second layer electrodes was removed by femtosecond laser to expose the structural gaps of the nano-vacuum channel; (12) The oxide sacrificial layer is removed by wet etching process to release and form a nano-vacuum channel structure.
2. The laser-assisted manufacturing process for a large aspect ratio nano-vacuum channel according to claim 1, characterized in that, The dielectric substrate is a glass substrate or a silicon substrate; And / or, the deposition method in steps (1) and (7) is magnetron sputtering; And / or, the first metal reinforcement layer and the second metal reinforcement layer are each independently formed of one or more of chromium, titanium, and tungsten; And / or, the first metal seed layer and the second metal seed layer are each independently formed of one or more metal layers selected from gold, copper, nickel, and platinum; And / or, the thicknesses of the first metal reinforcement layer and the second metal reinforcement layer are independently 1~50 nm; And / or, the thicknesses of the first metal seed layer and the second metal seed layer are independently 80~500 nm.
3. The laser-assisted manufacturing process for a large aspect ratio nano-vacuum channel according to claim 1, characterized in that, The first metal electrode and the first metal electrode are made of an alloy formed from one or more of the following materials: gold, copper, aluminum, tungsten, nickel, and platinum. And / or, the thickness of the first metal electrode and the second metal electrode is 5 to 50 μm.
4. The laser-assisted manufacturing process for a large aspect ratio nano-vacuum channel according to claim 1, characterized in that, The annealing temperature is 500–750 °C, and the annealing time is 10–100 min; Annealing is performed in a vacuum environment with a chamber pressure ≤1×10⁻⁶. -2 Pa.
5. The laser-assisted manufacturing process for a large aspect ratio nano-vacuum channel according to claim 1, characterized in that, Laser enamelting is performed using a nanosecond laser with a wavelength of 300~365 nm. The conditions for laser enamel treatment include: The scanning speed is 50~500 mm / s, the repetition rate is 50~200 kHz, and the power density is 0.1~7.64*10. 6 W / m 2 The spot diameter is 30~100 μm and the pulse width is 50~1000 ns.
6. The laser-assisted manufacturing process for a large aspect ratio nano-vacuum channel according to claim 1, characterized in that, The oxide sacrificial layer is a silicon oxide layer.
7. The laser-assisted manufacturing process for a large aspect ratio nano-vacuum channel according to claim 6, characterized in that, An oxide sacrificial layer is deposited on the device surface using chemical vapor deposition (CVD). The thickness of the oxide sacrificial layer is 2~200 nm.
8. The laser-assisted manufacturing process for a large aspect ratio nano-vacuum channel according to claim 1, characterized in that, The femtosecond laser has a wavelength of 1030 nm, a pulse width of 5~300 fs, a scan repetition rate >200 kHz, and a power density of 0.1~3*10⁻⁶. 8 W / cm 2 The spot diameter is 3~10 μm.
9. The laser-assisted manufacturing process for a large aspect ratio nano-vacuum channel according to claim 1, characterized in that, The wet etching process uses a phosphoric acid solution or a BOE mixture as the etching solution. When the etching solution is a phosphoric acid solution, the mass fraction of the phosphoric acid solution is 10~80 wt%, the etching temperature is 40~80 ℃, and the etching time is 5~60 min; When the etching solution is a BOE mixture, the BOE mixture includes 10~30 wt% NH4F, 1~6 wt% HF and water, the etching temperature is 10~50 ℃, and the etching time is 1~50 min.
10. The laser-assisted manufacturing process for a large aspect ratio nano-vacuum channel according to claim 1, characterized in that, The resulting nanoscale vacuum channel structure has an aspect ratio greater than 100:1 and a width controlled in the range of 2~200 nm.