Receiver, digital isolator and disconnection protection method thereof

Abstract

The invention discloses a receiver, a digital isolator and a disconnection protection method thereof. The digital isolator includes a transmitter and a receiver connected via a differential line. The receiver comprises an amplifier, an envelope detector and a driver which are connected in sequence, and the envelope detector is configured to perform envelope detection on a differential input signal received by the receiver so as to generate a corresponding envelope signal; the switch module is configured to control the on-off state of an input signal path of the envelope detector; and the broken line protection module is used for detecting the line fault of the differential line according to the signal change of the envelope signal in different on-off states during the power-on reset period, and stopping providing the output signal when the line fault exists in the differential line.

Description

Technical Field

[0001] This disclosure relates to digital circuits, and more specifically, to receivers with open-circuit protection, digital isolators, and open-circuit protection methods thereof. Background Technology

[0002] Digital isolators are key components widely used in industrial control, power management, medical equipment, and new energy vehicles. They are primarily used to enable the transmission of digital signals across isolation barriers under electrically isolated conditions. Their core function is to provide reliable signal transmission between high-voltage and low-voltage circuits, while simultaneously blocking ground loops, suppressing noise interference, and ensuring system safety.

[0003] A digital isolator comprises a transmitter and a receiver connected via differential lines, using a transmission medium that provides electrical isolation along the signal path through capacitors, transformers, or optocouplers. The transmitter modulates the input signal into a differential signal and transmits it to the receiver through an isolation barrier. The receiver demodulates the differential signal to restore it to its original logic level. In practical applications, a digital isolator includes a transmitter chip and a receiver chip integrated in the same package, with the differential lines between them being bonded wires. These bonded wires may break during manufacturing, packaging, or long-term use, leading to abnormal signal transmission.

[0004] Figure 1 A schematic circuit diagram of a digital isolator according to the prior art is shown. The digital isolator 100 includes a transmitter 110 and a receiver 120 connected via a bonding pair 101. The transmitter 110 converts the input signal into a differential signal and transmits it to the bonding pair 101 using capacitive coupling. The receiver 120 receives the differential signal from the bonding pair 101 using capacitive coupling and amplifies and demodulates it to recover the original input signal.

[0005] Using differential signals for communication can effectively improve the ability to resist common-mode interference, maintaining signal integrity even in complex electromagnetic environments. Figure 2 and Figure 3 The diagrams show the operating waveforms when the bonded wire pair is functioning normally and when one of the bonded wires is broken. Even if one of the bonded wires in bonded wire pair 101 is broken, receiver 120 can still correctly recover the input signal from transmitter 110.

[0006] While the differential signal communication design of digital isolators enhances their anti-interference capabilities, it also makes it impossible to determine whether a single bond wire breakage has occurred based on its operating status. A single bond wire breakage weakens the symmetry of the differential signal, leading to transmission errors under harsh conditions and extreme environments, thus degrading the reliability of the digital isolator. In automotive applications, failure to promptly detect and address such reliability failures can pose serious safety hazards.

[0007] Existing detection methods include providing interference signals to assess operational stability under harsh environments, or providing test signals offline to test for breakage in any bond wire. However, these testing methods are not only complex, but also require external test signals and can only be performed during the production process of digital isolators or in offline conditions. In actual working scenarios, they still cannot monitor bond wire faults in real time. Summary of the Invention

[0008] In view of the above problems, the purpose of this disclosure is to provide a receiver with disconnection protection function, a digital isolator and a disconnection protection method thereof, which uses differential signals to perform self-testing during power-on reset, and stops providing output signals when there is a line fault in the differential line, and can determine in real time whether there is a line fault in the differential line based on the output signal of the receiver.

[0009] According to one aspect of this disclosure, a receiver for receiving differential signals via a differential line is provided, comprising: an amplifier, an envelope detector, and a driver connected in sequence, wherein the envelope detector is configured to perform envelope detection on the differential signal received by the receiver to generate a corresponding envelope signal; a switching module configured to control the on / off state of the input signal path of the envelope detector; and a line breakage protection module configured to detect a line fault in the differential line during power-on reset based on signal changes of the envelope signal under different on / off states, and to stop providing an output signal when a line fault exists in the differential line.

[0010] Optionally, the switching module is coupled to the input terminal of the amplifier, or the switching module is located between the input terminal of the amplifier and the input terminal of the envelope detector.

[0011] Optionally, the disconnection protection module includes: a switch control module, configured to generate a switch control signal for the switch module based on the power-on reset signal of the receiver, and switch the on / off state according to a predetermined timing sequence; and a detection control module, configured to detect whether there is a line fault in the differential line based on the state change of the envelope signal under different on / off states, and to perform a protection action to stop providing the output signal when there is a line fault in the differential line.

[0012] Optionally, the detection control module generates a driver enable signal to disable the driver when a line fault exists on the differential line.

[0013] Optionally, the detection and control module generates a protection signal to disconnect the differential line when a line fault exists on the differential line.

[0014] Optionally, the disconnection protection module further includes: a delay module for generating at least one delay signal that is sequentially delayed relative to the power-on reset signal, wherein the switching module switches the connection state of the differential line at the time indicated by the at least one delay signal.

[0015] Optionally, the delay module generates first to third delay signals. During a first time period indicated by the first delay signal, the switching module connects the positive and negative signal lines of the differential line to the corresponding input terminals of the amplifier. During a second time period indicated by the second delay signal, the switching module disconnects the positive signal line of the differential line and connects only the negative signal line of the differential line to the corresponding input terminal of the amplifier. During a third time period indicated by the third delay signal, the switching module disconnects the negative signal line of the differential line and connects only the positive signal line to the corresponding input terminal of the amplifier.

[0016] Optionally, the switch control module includes: a first logic module, configured to perform a first combinational logic operation on the first delayed signal, the second delayed signal, and the power-on reset signal among the at least one delayed signal to generate a first switch control signal; and a second logic module, configured to perform a second combinational logic operation on the second delayed signal, the third delayed signal, and the power-on reset signal among the at least one delayed signal to generate a second switch control signal, wherein the first switch control signal and the second switch control signal respectively control the connection state of the positive phase signal line and the negative phase signal line of the differential line.

[0017] Optionally, the first logic module includes: a first NAND gate, which performs a NAND operation on the power-on reset signal and the inverted signal of the first delayed signal to generate a first intermediate signal; a first NOR gate, which performs a NOR operation on the first intermediate signal and the second delayed signal to generate a second intermediate signal; and a second NOR gate, which performs a NOR operation on the second delayed signal and the second intermediate signal to generate a third intermediate signal, wherein the first switch control signal is the inverted signal of the third intermediate signal.

[0018] Optionally, the second logic module includes: a second NAND gate, which performs a NAND operation on the power-on reset signal and the inverted signal of the second delayed signal to generate a fourth intermediate signal; and a third NOR gate, which performs a NOR operation on the third delayed signal and the inverted signal of the fourth intermediate signal to generate a fifth intermediate signal, wherein the second switch control signal is the inverted signal of the fifth intermediate signal.

[0019] Optionally, the detection control module includes: a fourth NOR gate, used to perform a NOR operation on the envelope signal and a third delayed signal among the at least one delayed signal to generate a sampling trigger signal; a first flip-flop, used to sample a predetermined level signal under the trigger of the sampling trigger signal to generate a disconnection indication signal; and a second flip-flop, used to latch the inverted signal of the disconnection indication signal under the trigger of the third delayed signal to generate a driver enable signal.

[0020] Optionally, the predetermined level signal is a logic high level.

[0021] Optionally, the delay module generates a first delay signal that lags behind the power-on reset signal, the first delay signal indicating a first time period.

[0022] Optionally, the switch control module includes: a first monostable circuit that, in response to the power-on reset signal, generates a first single pulse signal with a duration of a second time period after the first time period has elapsed, serving as a first switch control signal; and a second monostable circuit that, in response to the first single pulse signal, generates a second single pulse signal with a duration of a third time period after the second time period has elapsed, serving as a second switch control signal.

[0023] Optionally, the detection control module includes: a first to a third flip-flop, which samples the envelope signal to generate a first to a third sampled signal under the triggering of the first delayed signal, the first single pulse signal, and the second single pulse signal, respectively; and an AND gate, which performs an AND operation on the first to the third sampled signals to generate a disconnection indication signal, wherein the detection control module uses the inverted signal of the disconnection indication signal as a driver enable signal.

[0024] Optionally, the switching module includes a first switch and a second switch, wherein the first switch and the second switch are respectively used to connect the positive phase signal line and the negative phase signal line of the differential line to the corresponding input terminals of the amplifier, or the first switch and the second switch are respectively used to connect the positive phase output terminal and the negative phase output terminal of the amplifier to the corresponding input terminals of the envelope detector.

[0025] Optionally, the differential lines are bonding pairs inside the package structure.

[0026] According to another aspect of this disclosure, a digital isolator is provided, comprising: a transmitter for converting an input signal into a differential signal; the aforementioned receiver for converting the differential signal into an output signal consistent with the input signal; and a differential line connected between the transmitter and the receiver for transmitting the differential signal, wherein the differential line is coupled to at least one of the transmitter and the receiver in a DC-isolated manner.

[0027] According to another aspect of this disclosure, a method for protecting a differential line from disconnection is provided, the differential line being used to transmit differential signals, the method comprising: obtaining an envelope signal of the differential signal; switching the on / off state of the differential signal according to a predetermined timing sequence; determining whether there is a line fault in the differential line based on the state changes of the envelope signal under different on / off states; and if a line fault exists, performing a protection action to stop providing an output signal.

[0028] Optionally, obtaining the envelope signal of the differential signal includes: obtaining a first envelope signal of the differential signal in a first time period; obtaining a second envelope signal of the negative phase signal in the differential signal in a second time period; and obtaining a third envelope signal of the positive phase signal in the differential signal in a third time period, wherein determining whether there is a line fault in the differential line includes: logically combining the first to third envelope signals to obtain a line break indication signal.

[0029] Optionally, the protection action includes disconnecting the transmission path of the differential signal and / or disabling the driver of the output signal.

[0030] Optionally, the disconnection protection method generates the predetermined timing based on the power-on reset signal of the receiver during power-on reset to perform the disconnection protection method.

[0031] Optionally, the receiver switches the on / off state of the differential signal according to the first switch control signal and the second switch control signal. During power-on reset, the input signal of the receiver is a predetermined level signal. The first switch control signal and the second switch control signal are both valid in the first time period, valid and invalid in the second time period, and invalid and valid in the third time period. In normal communication state, the input signal of the receiver is a dynamic data signal, and the first switch control signal and the second switch control signal remain valid.

[0032] According to the receiver, digital isolator, and disconnection protection method of the present disclosure, a switching module and a disconnection protection module are integrated in the receiver. When detecting line faults, the provided test signal is compatible with normal communication signals and also utilizes the circuit modules in the receiver's existing signal restoration circuit. Compared with existing disconnection detection schemes that use interference signals as test signals, there is no need to use a dedicated signal source to generate test excitation, nor is there a need to use dedicated signal processing circuits to obtain disconnection indication signals. Therefore, integration can be significantly improved and hardware costs reduced.

[0033] Furthermore, the receiver performs line fault detection and executes line break protection during the power-on reset phase. This process requires no external intervention or control and is completed autonomously when the receiver system powers on. When the detection structure indicates that the line is normal, the receiver's output signal is automatically enabled without any interference to normal communication. Whether in the production process or in application scenarios, the receiver uses differential signals to perform self-testing during power-on reset and stops providing output signals when a line fault is found on the differential line. The presence of a differential line fault can be determined in real time based on the receiver's output signal. Compared with existing line break detection schemes that use interference signals as test signals, this allows for on-site line fault detection in application scenarios. Furthermore, when the detection result indicates a line fault on the differential line, the line break protection module in the receiver continues to disable the driver. This protection action prevents abnormal signals from being output to subsequent circuits, eliminating safety hazards caused by erroneous data generated under adverse conditions. Therefore, it can significantly improve communication reliability and application security.

[0034] In a preferred embodiment, the disconnection protection module uses combinational logic operations to generate a first switch control signal and a second switch control signal, which are used to control the on and off states of the corresponding switch units in the switch module, thereby achieving time-division switching of the differential input signal path. Therefore, the generation of the control signals does not depend on clock or storage elements, resulting in fast response speed, strong timing stability, and precise synchronization with the power-on reset process. Compared with switch control signal generation schemes using state machines, the circuit structure is simpler, has lower area overhead, is easier to port and reuse at different process nodes, and possesses good design scalability and process compatibility.

[0035] In a preferred embodiment, the disconnection protection module generates a sampling trigger signal based on the envelope signal, and samples the effective level signal at the edge of the envelope signal to generate a disconnection indication signal. Compared with fault detection schemes using state machines, this method not only has a simpler circuit structure and smaller area overhead, but also a faster response speed. It can quickly detect line faults during the receiver's power-on reset phase, minimizing interference with the receiver's normal communication function. Attached Figure Description

[0036] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments of this disclosure with reference to the accompanying drawings.

[0037] Figure 1 A schematic circuit diagram of a digital isolator according to the prior art is shown.

[0038] Figure 2 Show Figure 1 The diagram shows the waveform of the digital isolator operating normally on the line.

[0039] Figure 3 Show Figure 1 The diagram shows the operating waveform of the digital isolator when a single bond wire is broken.

[0040] Figure 4 A schematic circuit diagram of a digital isolator according to an embodiment of the present disclosure is shown.

[0041] Figure 5 Show Figure 4 The diagram shows the waveform of the digital isolator during the power-on reset phase when the line is normal.

[0042] Figure 6 Show Figure 4 The diagram shows the operating waveform of the digital isolator in the state of a broken positive bond line.

[0043] Figure 7 Show Figure 4 The diagram shows the operating waveform of the digital isolator in the state of a broken negative phase bond line.

[0044] Figure 8 Show Figure 4 The diagram shows the operating waveform of the digital isolator when both bond lines are broken.

[0045] Figure 9 Show Figure 4 The diagram shows a schematic circuit of the open circuit protection module in the digital isolator.

[0046] Figure 10 A flowchart illustrating a wire breakage protection method according to an embodiment of the present disclosure is shown. Detailed Implementation

[0047] Various embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by the same or similar reference numerals. For clarity, the various portions in the drawings are not drawn to scale.

[0048] This disclosure may be presented in various forms, some of which will be described below.

[0049] In this document, the term "bonded wire pair" refers to a pair of bonded wires used to transmit differential signals. Bonded wires are used to establish electrical connections between different chips or electronic components within a package structure. The term "differential signal line" refers to a pair of signal lines used to transmit differential signals; their physical form is not limited and can be any structure used for conducting or transmitting electrical signals, including but not limited to bonded wires, printed circuit board (PCB) traces, or cables. It is understood that, within a package structure, differential signals are typically implemented using bonded wire pairs.

[0050] The embodiments of this disclosure are applicable to any digital circuit that uses differential signals for data transmission, and their structure and packaging do not constitute a limitation of this disclosure. For example, in digital communication circuits, differential signals are widely used in various data interfaces and communication links, including high-speed serial interfaces, low-voltage differential signaling (LVDS) interfaces, RS-485 interfaces, etc. Therefore, the technical solutions of this disclosure can be applied to any of the above-mentioned types of digital communication circuits without limiting the communication protocol, data rate, or driving method. When applied to digital isolators, the embodiments of this disclosure are also not limited by the isolation method and packaging method. The isolation method can be any one of capacitive isolation, transformer isolation, or optocoupler isolation; the packaging method can be a single-chip package, a multi-chip package structure (e.g., system-in-package (SiP) or hybrid integrated package (MiP), or a multi-chip discrete device structure.

[0051] The following explanation mainly uses a multi-chip package structure as an example; however, this disclosure is not limited thereto.

[0052] Figure 4 A schematic circuit diagram of a digital isolator according to an embodiment of the present disclosure is shown.

[0053] The digital isolator 200 includes a transmitter 110, a receiver 220, and a bonding wire pair 101 connected between the two.

[0054] The input port of transmitter 110 receives an input signal from an external signal source. In digital communication, the input signal is, for example, a sequence of digital signals in level form, where high and low levels represent digital values. Transmitter 110 converts the input signal into a differential signal, using the polarity of the differential signal to represent the digital value. The output port of transmitter 110 is connected to the bonding pair 101 via a capacitor, thereby transmitting the differential signal to the bonding pair at the transmitting end in a capacitive coupling manner. The input port of receiver 220 is connected to the bonding pair 101 via a capacitor, thereby receiving the differential signal from the bonding pair at the receiving end in a capacitive coupling manner. Receiver 220 converts the received differential signal into an output signal, thereby restoring the level form of the input signal.

[0055] In the digital isolator 200, the DC voltage is isolated from the transmitter 110's supply voltage VCCL and ground GNDL by the capacitors at the transmitting and receiving ends, achieving electrical isolation between the receiver 220's supply voltage VCCR and ground GNDR. This electrical isolation structure effectively blocks the effects of ground loop interference and high-voltage transients on sensitive circuits, improving the system's safety and reliability.

[0056] The bonding wire pair 101 includes a positive phase signal line bw1 and a negative phase signal line bw2, which transmit signals differentially and have a symmetrical geometry and electrical characteristics. Figure 1In the diagram, the positive phase signal line bw1 is connected between the first coupling capacitor C11 at the transmitting end and the first coupling capacitor C12 at the receiving end, and the negative phase signal line bw2 is connected between the second coupling capacitor C21 at the transmitting end and the second coupling capacitor C22 at the receiving end.

[0057] In this embodiment, the digital isolator 200 is a multi-chip package structure, in which the transmitter 110 and receiver 220 are independent chips, and the two achieve high-speed transmission of differential signals through bonding wire pairs. Bonding wires are fine metal wires used for electrical connections, such as those made of gold, copper, or aluminum. Unlike conventional bonding wires within a package structure, the bonding wire pairs 101 in this package structure are used as differential signal lines, and their length, curvature, and spacing need to be precisely controlled to ensure impedance matching and signal integrity.

[0058] Furthermore, the receiver 220 includes a switch module SW, an amplifier 221, an envelope detector 222 and a driver 220 connected in sequence, as well as a disconnection protection module 10 for performing disconnection detection and protection control.

[0059] Amplifier 221, envelope detector 222 and driver 223 constitute a signal restoration circuit.

[0060] Amplifier 221 amplifies the differential signal with high gain, suppressing common-mode noise and enhancing signal amplitude. Envelope detector 222 extracts the envelope signal of the amplified differential signal to reconstruct the input signal received by the receiver of transmitter 110. This input signal is, for example, a sequence of digital signals in level form. Driver 223 performs level shaping and power amplification on the recovered digital signal sequence to drive subsequent loads or stably transmit the digital signal to subsequent circuitry for decoding, thereby obtaining data content corresponding to the original input signal.

[0061] The disconnection protection module 10 and the switch module SW together form a power-on self-test protection circuit.

[0062] The disconnection protection module 10 receives a power-on reset signal POR and an envelope signal OUT_EL generated by the envelope detector 222. The disconnection protection module 10 generates a first switch control signal swp and a second control signal swn based on the power-on reset signal POR to execute the disconnection detection logic. Further, the disconnection protection module 10 generates an enable signal DR_EN for controlling the driver 223 based on the envelope signal OUT_EL, used to enable or disable the driver 223.

[0063] In this embodiment, the switch module SW selectively couples the differential signal transmitted by the bonding wire pair 101 to the input terminal of the amplifier 221 according to the switch control signal. The switch module SW includes a first switch S1 connected between the first coupling capacitor C12 and the non-inverting input terminal of the amplifier 221, and a second switch S2 connected between the second coupling capacitor C22 and the non-inverting input terminal of the amplifier 221. However, this disclosure is not limited to this; the switch module SW can be configured to control the on / off state of the input signal path of the envelope detector 222.

[0064] In an alternative embodiment, the switching module SW includes a first switch S1 connected between the positive output terminal of amplifier 221 and the positive input terminal of envelope detector 222, and a second switch S2 connected between the negative output terminal of amplifier 221 and the negative input terminal of envelope detector 222.

[0065] During the power-on reset phase, the open circuit protection module 10 changes the on / off states of the first switches S1 and S2 according to a predetermined timing sequence to simulate a single-path bond wire breakage fault in the bond wire pair 101. During normal operation, the first switch S1 and the second switch S2 remain on to enable the differential signal input amplifier 221.

[0066] During the power-on reset phase of the digital isolator 200, the open-circuit protection module 10 disables the driver 223 and executes the open-circuit detection logic, thereby enabling online self-testing. This allows for timely detection of open-circuit faults in the digital isolator during both mass production testing and field applications. If the detection result indicates that the bonding wire is normal, the open-circuit protection module 10 enables the driver 223 to provide an output signal. If the detection result indicates a line fault in the bonding wire, the open-circuit protection module 10 continues to disable the driver 223. This protection action prevents abnormal signals from being output to subsequent circuits, eliminating potential safety hazards caused by erroneous data generated under adverse conditions.

[0067] Figure 5 Show Figure 4 The diagram shows the waveform of the digital isolator during the power-on reset phase when the line is normal. In the diagram, VCCL represents the power supply voltage at the transmitting end, IN represents the input signal received by the digital isolator from the outside, tp and tn represent the positive and negative phase signals of the differential signal at the transmitting end, respectively, VCCR represents the power supply voltage at the receiving end, POR is the power-on reset signal, swp and swn represent the first and second switch control signals of the switching module, respectively, rp and rn represent the positive and negative phase signals of the differential signal at the receiving end, OUT_EL is the envelope signal output by the envelope detector, DR_EN is the enable signal of the driver, and OUT represents the output signal of the digital isolator.

[0068] The following combination Figure 4The circuit structure shown is for Figure 5 The working waveform shown is explained in detail.

[0069] During the power-on reset phase of transmitter 110, the supply voltage VCCL at the transmitting end reaches a high level. Subsequently, digital isolator 200 receives the input signal IN, which is a continuously high-level test signal. Transmitter 110 converts the input signal IN into a differential signal, using the polarity relationship of the differential signals to characterize the digital value. In this embodiment, for a logic high level, the positive phase signal tp and the negative phase signal tn of the differential signal at the transmitting end are periodic signals of opposite polarities, used to characterize the logic high level of the input signal. In an alternative embodiment, the positive phase signal tp and the negative phase signal tn of the differential signal can also be periodic signals of the same polarity, used to characterize the logic high level of the input signal. This disclosure is not limited thereto; any polarity relationship can be selected to characterize the logic level state according to the actual design.

[0070] During the power-on reset phase of receiver 220, the supply voltage VCCR at the receiver rises to a high level. At time t0, the power-on reset signal POR of receiver 220 toggles from an invalid state to an active state. This active state of the power-on reset signal POR lasts for a period of time to allow the internal circuitry of the receiver to complete initialization and achieve stable operation. During the active state of the power-on reset signal POR, receiver 220 executes disconnection detection logic during time periods t1 to t4. In other embodiments, t1 and t0 can be the same time, as described below. Figure 9 The circuit shown in the embodiment generates times t1 and t0.

[0071] During the first time interval from time t1 to t2, both the switch control signals swp and swn are set to high level. At this time, both the first switch S1 and the second switch S2 in the switch module SW are in the on state, allowing the amplifier 221 in the receiver 220 to receive the positive phase signal rp and the negative phase signal rn of the differential signal received at the receiving end. The amplifier 221 performs differential amplification on the positive phase signal rp and the negative phase signal rn to obtain a unipolar signal with the same period as the positive phase signal. This unipolar signal is processed by the envelope detector 222 to generate an envelope signal OUT_EL. This envelope signal OUT_EL is, for example, a high-level signal corresponding to the input signal IN.

[0072] During the second time interval from time t2 to t3, the switch control signal swp is set to a low level, while the switch control signal swn remains high. At this time, the first switch S1 in the switch module SW is open, and the second switch S2 remains on, simulating a fault where the positive phase signal line is broken. At this time, the amplifier 221 in the receiver 220 only receives the negative phase signal rn of the differential signal. The amplifier 221 amplifies the single-ended input negative phase signal rn to obtain a unipolar signal with the same period as the negative phase signal. This unipolar signal is processed by the envelope detector 223 to generate an envelope signal OUT_EL. This envelope signal OUT_EL is, for example, a high-level signal corresponding to the input signal IN.

[0073] During the third time interval from time t3 to t4, the switch control signal swp is set to a high level, and the switch control signal swn is set to a low level. At this time, the first switch S1 in the switch module SW is turned on, and the second switch S2 is turned off to simulate a fault of a broken negative phase signal line. At this time, the amplifier 221 in the receiver 220 only receives the positive phase signal rp of the differential signal, performs single-ended amplification on it, and generates the envelope signal OUT_EL. This envelope signal OUT_EL is, for example, a high-level signal corresponding to the input signal IN.

[0074] Throughout the open circuit detection process, the envelope signal OUT_EL remains valid, indicating that there is no line fault in the bonding wires inside the digital isolator. At time t4, the enable signal DR_EN of driver 223 flips from invalid to valid, and driver 223 begins normal operation. At this time, the first switch S1 and the second switch S2 in the switch module SW remain on. Digital isolator 200 enters normal communication mode, transmitting the input signal IN from transmitter 110 to receiver 220, and providing the output signal OUT to subsequent circuits.

[0075] Figure 6 Show Figure 4 The diagram shows the operating waveform of the digital isolator in the state of a broken positive bond line.

[0076] exist Figure 6 The signal symbols used in Figure 5 The same applies, so I won't repeat it here. Figure 6 The signal waveform at the transmitting end and Figure 5 The same components are included, such as the input signal IN, the power supply voltage VCCL at the transmitting end, and the positive phase signal tp and negative phase signal tn of the differential signal at the transmitting end, which will not be elaborated here. The following only describes the signal waveform at the receiving end.

[0077] During the power-on reset phase of receiver 220, the supply voltage VCCR at the receiver rises to a high level. At time t0, the power-on reset signal POR of receiver 220 toggles from an invalid state to an active state. This active state of the power-on reset signal POR lasts for a period of time to allow the internal circuitry of the receiver to complete initialization and operate stably. During the active state of the power-on reset signal POR, receiver 220 executes the disconnection detection logic from time period t1 to t4.

[0078] During the first time interval from time t1 to t2, both the switch control signals swp and swn are set to high level. At this time, both the first switch S1 and the second switch S2 in the switch module SW are in the on state. Due to the breakage of the positive phase bonding wire, the positive phase signal tp of the transmitting differential signal cannot be transmitted to the receiver 220 via the positive phase bonding wire. At this time, the positive phase signal rp of the receiving differential signal remains in an invalid state, while the negative phase signal rn of the receiving differential signal is a normal signal transmitted via the negative phase bonding wire, consistent with the negative phase signal tn of the transmitting differential signal. The amplifier 221 in the receiver 220 performs differential amplification processing on the positive phase signal rp and the negative phase signal rn to obtain a unipolar signal with the same period as the negative phase signal. After processing by the envelope detector 223, this unipolar signal generates an envelope signal OUT_EL. This envelope signal OUT_EL is, for example, a high-level signal corresponding to the input signal IN.

[0079] During the second time interval from time t2 to t3, the switch control signal swp is set to a low level, while the switch control signal swn remains high. At this time, the first switch S1 in the switch module SW is open, and the second switch S2 remains on, simulating a fault where the positive phase signal line is broken. At this time, the amplifier 221 in the receiver 220 only receives the negative phase signal rn of the differential signal. The amplifier 221 amplifies the single-ended input negative phase signal rn to obtain a unipolar signal with the same period as the negative phase signal. This unipolar signal is processed by the envelope detector 223 to generate an envelope signal OUT_EL. This envelope signal OUT_EL is, for example, a high-level signal corresponding to the input signal IN.

[0080] During the third time interval from t3 to t4, the switch control signal swp is set to high and the switch control signal swn is set to low. At this time, the first switch S1 in the switch module SW is turned on, and the second switch S2 is turned off to simulate a fault of a broken negative phase signal line. However, due to the broken positive phase bond line, the positive phase signal tp of the transmitting differential signal cannot be transmitted to the receiver 220 via the positive phase bond line. At this time, the positive phase signal rp of the receiving differential signal remains invalid. The amplifier 221 in the receiver 220 performs single-ended amplification of the positive phase signal rp of the receiving differential signal, and then the envelope detector 222 generates the envelope signal OUT_EL. This envelope signal OUT_EL is, for example, a low-level signal opposite to the input signal IN.

[0081] Throughout the open circuit detection process, the level of the envelope signal OUT_EL dynamically changes with the switching control timing. When the positive bonding wire breaks, the envelope signal OUT_EL remains low for at least the third time period, opposite to the high level during normal transmission, indicating an open circuit fault in the positive bonding wire inside the digital isolator. At time t4, the enable signal DR_EN of driver 223 remains invalid, thus disabling driver 223 at all times. The digital isolator 200 cannot enter normal communication mode, and the output signal OUT remains invalid, preventing the fault signal from propagating further to subsequent circuits, thereby achieving the open circuit protection function.

[0082] Figure 7 Show Figure 4 The diagram shows the operating waveform of the digital isolator in the state of a broken negative phase bond line.

[0083] exist Figure 7 The signal symbols used in Figure 5 The same applies, so I won't repeat it here. Figure 7 The signal waveform at the transmitting end and Figure 5 The same components are included, such as the input signal IN, the power supply voltage VCCL at the transmitting end, and the positive phase signal tp and negative phase signal tn of the differential signal at the transmitting end, which will not be elaborated here. The following only describes the signal waveform at the receiving end.

[0084] During the power-on reset phase of receiver 220, the supply voltage VCCR at the receiver rises to a high level. At time t0, the power-on reset signal POR of receiver 220 toggles from an invalid state to an active state. This active state of the power-on reset signal POR lasts for a period of time to allow the internal circuitry of the receiver to complete initialization and operate stably. During the active state of the power-on reset signal POR, receiver 220 executes the disconnection detection logic from time period t1 to t4.

[0085] During the first time interval from time t1 to t2, both the switch control signals swp and swn are set to high level. At this time, both the first switch S1 and the second switch S2 in the switch module SW are in the on state. Due to the breakage of the negative phase bonding wire, the negative phase signal tn of the transmitting differential signal cannot be transmitted to the receiver 220 via the negative phase bonding wire. At this time, the negative phase signal rn of the receiving differential signal remains in an invalid state, while the positive phase signal rp of the receiving differential signal is a normal signal transmitted via the positive phase bonding wire, consistent with the positive phase signal tp of the transmitting differential signal. The amplifier 221 in the receiver 220 performs differential amplification processing on the positive phase signal rp and the negative phase signal rn to obtain a unipolar signal with the same period as the positive phase signal. After processing by the envelope detector 223, this unipolar signal generates an envelope signal OUT_EL. This envelope signal OUT_EL is, for example, a high-level signal corresponding to the input signal IN.

[0086] During the second time interval from time t2 to t3, the switch control signal swp is set to low, while the switch control signal swn remains high. At this time, the first switch S1 in the switch module SW is open, and the second switch S2 remains on, simulating a fault where the positive phase signal line is broken. However, since the negative phase bond line is actually broken, the negative phase signal tn of the transmitting differential signal cannot be transmitted to the receiver 220 via the negative phase bond line. At this time, the negative phase signal rn of the receiving differential signal remains invalid. The amplifier 221 in the receiver 220 performs single-ended amplification on the negative phase signal rn of the receiving differential signal, and then the envelope detector 222 generates the envelope signal OUT_EL. This envelope signal OUT_EL is, for example, a low-level signal opposite to the input signal IN.

[0087] During the third time interval from t3 to t4, the switch control signal swp is set to high level, and the switch control signal swn is set to low level. At this time, the first switch S1 in the switch module SW is turned on, and the second switch S2 is turned off to simulate a fault of a broken negative phase signal line. Although the positive phase bonding line is normal, the negative phase path is actively cut off because the second switch S2 is turned off, and the negative phase signal rn of the differential signal at the receiving end still cannot be input. At this time, the amplifier 221 only receives the positive phase signal rp transmitted through the first switch S1, and performs single-ended amplification on it to generate a unipolar signal with the same period as the positive phase signal rp. After being processed by the envelope detector 223, this signal generates an envelope signal OUT_EL. This envelope signal OUT_EL is, for example, a high-level signal corresponding to the input signal IN.

[0088] Throughout the open circuit detection process, the level of the envelope signal OUT_EL dynamically changes with the switching control timing. When the negative phase bond wire breaks, the envelope signal OUT_EL is low during the second time period, but remains high during the first and third time periods. Its level change characteristics are distinguishable from the response pattern when the positive phase bond wire breaks, indicating an open circuit fault in the negative phase bond wire within the digital isolator. At time t4, the enable signal DR_EN of driver 223 remains invalid, thus disabling driver 223. The digital isolator 200 cannot enter normal communication mode, and the output signal OUT remains invalid, preventing the fault signal from propagating further to subsequent circuits, thereby achieving the protection function against negative phase bond wire breakage.

[0089] Throughout the open circuit detection process, the level of the envelope signal OUT_EL dynamically changes with the switching control timing. When the negative phase bond wire breaks, the envelope signal OUT_EL remains low for at least the second time period, opposite to the high level during normal transmission, indicating an open circuit fault in the negative phase bond wire inside the digital isolator. At time t4, the enable signal DR_EN of driver 223 remains invalid, thus disabling driver 223 at all times. Digital isolator 200 cannot enter normal communication mode, and the output signal OUT remains invalid, preventing the fault signal from propagating further to subsequent circuits, thereby achieving the open circuit protection function.

[0090] Figure 8 Show Figure 4 The diagram shows the operating waveform of the digital isolator when both bond lines are broken.

[0091] exist Figure 8 The signal symbols used in Figure 5 The same applies, so I won't repeat it here. Figure 8 The signal waveform at the transmitting end and Figure 5 The same components are included, such as the input signal IN, the power supply voltage VCCL at the transmitting end, and the positive phase signal tp and negative phase signal tn of the differential signal at the transmitting end, which will not be elaborated here. The following only describes the signal waveform at the receiving end.

[0092] During the power-on reset phase of receiver 220, the supply voltage VCCR at the receiver rises to a high level. At time t0, the power-on reset signal POR of receiver 220 toggles from an invalid state to an active state. This active state of the power-on reset signal POR lasts for a period of time to allow the internal circuitry of the receiver to complete initialization and operate stably. During the active state of the power-on reset signal POR, receiver 220 executes the disconnection detection logic from time period t1 to t4.

[0093] During the first time interval from time t1 to t2, both switch control signals swp and swn are set to high level. At this time, the first switch S1 and the second switch S2 in the switch module SW are both in the on state. Since both the positive and negative bonding wires are broken, the positive phase signal tp and the negative phase signal tn of the differential signal at the transmitting end cannot be transmitted to the receiver 220. At this time, the positive phase signal rp and the negative phase signal rn of the differential signal at the receiving end remain in an invalid state. Because there is no valid input signal, the differential input terminal of the amplifier 221 in the receiver 220 is in a floating or default low level state, and after differential amplification, it outputs a signal close to zero or low level. After processing by the envelope detector 223, this signal generates an envelope signal OUT_EL. This envelope signal OUT_EL is low level, which is opposite to the high level that should correspond to the input signal IN.

[0094] During the second time interval from time t2 to t3, the switch control signal swp is set to low, while the switch control signal swn remains high. At this time, the first switch S1 in the switch module SW is open, and the second switch S2 remains on, simulating a broken positive phase signal line. However, since the negative phase bond line is actually broken, even with the second switch S2 on, the negative phase signal cannot be transmitted; simultaneously, the opening of the first switch S1 further blocks the positive phase path. Amplifier 221 still has no valid input signal, and its output remains low. The envelope signal OUT_EL generated after processing by envelope detector 223 continues to remain low.

[0095] During the third time interval from t3 to t4, the switch control signal swp is set to high and the switch control signal swn is set to low. At this time, the first switch S1 in the switch module SW is turned on, and the second switch S2 is turned off to simulate a fault of a broken positive signal line. Although the first switch S1 is turned on, the positive signal tp still cannot be transmitted due to the broken positive bond wire; while the second switch S2 being turned off further cuts off the already failed negative path. Amplifier 221 still has no valid input, and the output remains invalid. The envelope signal OUT_EL output by envelope detector 223 remains low.

[0096] Throughout the open circuit detection process, the envelope signal OUT_EL remains low across all time periods, the opposite of the high level during normal transmission, indicating an open circuit fault in both the positive and negative phase bond wires within the digital isolator. At time t4, the enable signal DR_EN of driver 223 remains inactive, thus disabling driver 223. Digital isolator 200 cannot enter normal communication mode, and the output signal OUT remains inactive, preventing the fault signal from propagating further to subsequent circuits, thereby achieving the open circuit protection function.

[0097] Figure 9 Show Figure 4The diagram shows a schematic circuit of the open circuit protection module 10 in the digital isolator. The open circuit protection module 10 includes a delay module 11, a switch control module 12, and a detection control module 13.

[0098] Delay module 11 includes a first delay unit 1, a second delay unit 2, and a third delay unit 3 connected in series. It is used to perform multi-stage delay on the power-on reset signal POR, generating sequentially delayed first delay signals TD1, TD2, and TD3. The first delay signals TD1, TD2, and TD3 are, for example, level signals, whose rising edges are used for indication. Figures 5 to 8 The end times of the three time periods are t2, t3, and t4.

[0099] The switch control module 12 includes multiple logic gates U11 to U20, which are used to generate a first switch control signal swp and a second switch control signal swn for the switch module SW based on the power-on reset signal POR, the first delay signal TD1, the second delay signal TD2, and the third delay signal TD3.

[0100] Logic gates U11, U12, U13, U14, and U15 are NOT gates, NAND gates, NOR gates, NOR gates, and NOT gates, respectively, and together perform the first combinational logic operation. In this first combinational logic operation, logic gate U11 generates the inverted signal of the first delayed signal TD1; logic gate U12 performs a NAND operation on the power-on reset signal POR and the inverted signal of the first delayed signal TD1 to generate the first intermediate signal A; logic gate U13 performs a NOR operation on the second delayed signal TD2 and the first intermediate signal to generate the second intermediate signal B; logic gate U14 performs a NOR operation on the second delayed signal TD2 and the second intermediate signal to generate the third intermediate signal C; and logic gate U15 generates the inverted signal of the third intermediate signal, which serves as the first switch control signal swp.

[0101] Logic gates U16, U17, U18, U19, and U20 are NOT gates, NAND gates, NOT gates, NOR gates, and NOT gates, respectively, and together perform the second combinational logic operation. In this operation, logic gate U16 generates the inverted signal of the second delayed signal TD2. Logic gate U17 performs a NAND operation on the power-on reset signal POR and the inverted signal to generate the fourth intermediate signal D. Logic gate U18 obtains the inverted signal of the fourth intermediate signal D. Logic gate U19 performs a NOR operation on the third delayed signal TD3 and the inverted signal of the fourth intermediate signal D to generate the fifth intermediate signal E. Logic gate U20 generates the inverted signal of the fifth intermediate signal E, which serves as the second switch control signal swn.

[0102] See Figures 5 to 8The waveform diagram shows that before time t1, the first delayed signal TD1, the second delayed signal TD2, and the third delayed signal TD3 are all in an invalid state.

[0103] At time t1, the power-on reset signal POR is active. As a result of the first and second combinational logic operations, the first switch control signal swp and the second switch control signal swn flip from an invalid state to an active state at time t1.

[0104] At time t2, the first delay unit 1 completes the set delay, and the first delay signal td1 flips from the invalid state to the valid state.

[0105] When one of the input signals of the first combinational logic operation (i.e., the first delayed signal TD1, the second delayed signal TD2, and the power-on reset signal POR) (i.e., the first delayed signal TD1) changes, logic gate U12 performs a NAND operation on the inverted signals of the power-on reset signal POR and the first delayed signal TD1, toggling the first intermediate signal A from an invalid state to an active state. Logic gate U13 performs a NOR operation on the second delayed signal TD2 and the first intermediate signal A, toggling the second intermediate signal B from an active state to an invalid state. Logic gate U14 performs a NOR operation on the second delayed signal TD2 and the second intermediate signal B, toggling the third intermediate signal C from an invalid state to an active state. Logic gate U15 generates the inverted signal of the third intermediate signal C, toggling the first switch control signal swp from an active state to an invalid state.

[0106] The input signals for the second combinational logic operation (i.e., the second delayed signal TD2, the third delayed signal TD2, and the power-on reset signal POR) remain unchanged. The second switch control signal swn remains valid.

[0107] At time t3, the second delay unit 2 completes the set delay, and the second delay signal TD2 flips from the invalid state to the valid state.

[0108] One of the input signals for the first combinational logic operation (i.e., the second delayed signal TD2) changes. Logic gate U12 performs a NAND operation on the power-on reset signal POR and the inverted signal of the first delayed signal TD1, keeping the first intermediate signal A valid. Logic gate U13 performs a NOR operation on the second delayed signal TD2 and the first intermediate signal A, keeping the second intermediate signal B invalid. Logic gate U14 performs a NOR operation on the second delayed signal TD2 and the second intermediate signal B. Due to the change in the valid state of the second delayed signal TD2, the third intermediate signal C flips from a valid state to an invalid state. Logic gate U15 generates the inverted signal of the third intermediate signal C, flipping the first switch control signal swp from an invalid state to a valid state.

[0109] One of the input signals for the second combinational logic operation (i.e., the second delayed signal TD2) changes. Logic gate U17 performs a NAND operation on the power-on reset signal POR and the inverted signal of the second delayed signal TD2. Due to the change in the valid state of the second delayed signal TD2, the fourth intermediate signal D flips from an invalid state to a valid state. Logic gate U19 performs a NOR operation on the inverted signal of the fourth intermediate signal D and the third delayed signal TD3, causing the fifth intermediate signal E to flip from an invalid state to a valid state. Logic gate U20 generates the inverted signal of the fifth intermediate signal E, causing the second switch control signal swn to flip from a valid state to an invalid state.

[0110] At time t4, the third delay unit 3 completes the set delay, and the third delay signal TD3 flips from the invalid state to the valid state.

[0111] The input signals for the first combinational logic operation (i.e., the first delayed signal TD1, the second delayed signal TD2, and the power-on reset signal POR) remain unchanged. The first switch control signal swp remains valid.

[0112] One of the input signals for the second combinational logic operation (i.e., the third delayed signal TD3) changes. Logic gate U17 performs a NAND operation on the power-on reset signal POR and the inverted signal of the second delayed signal TD2. Since the valid state of the second delayed signal TD2 remains unchanged, the fourth intermediate signal D remains valid. Logic gate U19 performs a NOR operation on the inverted signal of the fourth intermediate signal D and the third delayed signal TD3, causing the fifth intermediate signal E to flip from a valid state to an invalid state. Logic gate U20 generates the inverted signal of the fifth intermediate signal E, causing the second switch control signal swn to flip from an invalid state to a valid state.

[0113] Those skilled in the art should understand that Figure 9 In the illustrated embodiment, the signals generated by the circuit at time t1 and t0 are at the same time. However, in other embodiments, t1 and t0 can be as follows: Figures 5-8 The waveforms shown represent different moments. As an example, this can be achieved by... Figure 9 Based on the circuit shown, the power-on reset signal POR is first delayed before being sent to the delay module 11, the switch control module 12, and the detection control module 13.

[0114] The detection control module 13 includes multiple logic gates U21 and U23, as well as multiple flip-flops U22 and U24.

[0115] Logic gates U21 and U23 are a NOR gate and a NOT gate, respectively. Logic gate U21 performs a NOR operation on the third delayed signal TD3 and the envelope signal OUT_EL generated by the envelope detector 222, generating a sampling trigger signal F. The clock input of flip-flop U22 receives the sampling trigger signal F, its data input is connected to the power supply voltage, and its output provides a disconnection indication signal G. Logic gate U23 receives the inverted signal of the disconnection indication signal G. The data input of flip-flop U24 receives the inverted signal of the disconnection indication signal G, its clock input receives the third delayed signal TD3, and its output provides a driver enable signal DR_EN.

[0116] Before time t4, the third delayed signal TD3 is in an invalid state. Logic gate U21 performs an XOR operation on the third delayed signal TD3 and the envelope signal OUT_EL, and the resulting sampling trigger signal F is the inverted signal of the envelope signal OUT_EL.

[0117] When both bonding wires of the digital isolator are normally connected, during the three time periods (t1-t2, t2-t3, t3-t4) of the power-on reset self-test, the envelope signal OUT_EL remains valid throughout (see [link to relevant documentation]). Figure 5 Therefore, flip-flop U22 never receives a clock edge, there is no data latching action, and the disconnection indicator signal G remains invalid. Flip-flop U24 receives the third delayed signal TD3 at its clock input and receives a clock edge at time t4. It samples and latches the inverted signal of the disconnection indicator signal G. At this time, the inverted signal of the disconnection indicator signal G is valid. Therefore, the driver enable signal DR_EN flips from invalid to valid and remains valid after power-on reset, allowing the output driver to operate normally.

[0118] When all bonding wires of the digital isolator are normally connected, during the three time periods (t1-t2, t2-t3, t3-t4) of the power-on reset self-test, the envelope signal OUT_EL is invalid in one of these time periods. Therefore, flip-flop U22 receives a clock edge, samples and latches the supply voltage VCC, and the disconnection indicator signal G flips from invalid to valid. The inverted signal of the disconnection indicator signal G output by logic gate U23 is invalid. Flip-flop U24 receives the third delayed signal TD3 at its clock input and receives a clock edge at time t4, sampling and latching the inverted signal of the disconnection indicator signal G. At this time, the inverted signal of the disconnection indicator signal G is invalid. Therefore, the driver enable signal DR_EN remains invalid and remains invalid after the power-on reset, preventing the output driver from starting and causing the system to enter a protection state.

[0119] In the case where both bond wires of the digital isolator are broken, the envelope signal OUT_EL remains invalid throughout the three time periods (t1-t2, t2-t3, t3-t4) of the power-on reset self-test. The output sampling trigger signal F of logic gate U21 is the inverted signal of the envelope signal OUT_EL, i.e., it remains valid. The driver enable signal DR_EN remains invalid and is triggered to become valid by the power-on reset signal POR after the power-on reset is completed. At this time, although the disconnection protection module performs an erroneous protection action (enabling the driver), the receiver input signal is effectively disabled because both bond wires are broken. Therefore, the receiver will not provide an erroneous output signal to the subsequent stage.

[0120] In the above embodiments, the internal circuit modules of the disconnection protection module 10 are described. The delay module 11 generates sequentially delayed first delay signals TD1, TD2, and TD3. Further, the switch control module 12 performs logical combination operations on the first delayed signal TD1, the second delayed signal TD2, the third delayed signal TD3, and the power-on reset signal POR to generate a first switch control signal swp and a second switch control signal swn. The detection control module 13 generates a sampling trigger signal based on the third delayed signal TD3 and the envelope signal OUT_EL generated by the envelope detector 222, sampling the supply voltage to indicate that the envelope signal OUT_EL flips from an active state to an inactive state within a time period, thereby determining the active state change of the envelope signal OUT_EL during the disconnection self-test, and thus determining whether a disconnection fault exists.

[0121] However, it is understandable. Figure 9 The circuit structure shown is only a preferred embodiment for implementing open circuit detection, and this disclosure is not limited thereto. The switch control module 12 can generate switch control signals swp and swn using various logic combinations to adapt to different delay requirements and design flexibility under different process conditions. The detection control module 13 can also use various logic combinations to determine whether an open circuit fault exists based on the effective state change of the envelope signal OUT_EL during the open circuit self-test.

[0122] In an alternative embodiment, the switch control module includes, for example, a delay module and two monostable circuits. The delay module generates a delayed signal TD1. After a power-on reset signal POR, the first monostable circuit generates a first active-low single-pulse signal after a first delay time, serving as the first switch control signal swp. The duration of the first single-pulse signal corresponds to the low-level phase (second time period) of the switch control signal swp. The second monostable circuit uses the first single-pulse signal as a trigger signal to generate a second active-low single-pulse signal, serving as the second switch control signal swn. The duration of the second single-pulse signal corresponds to the low-level phase (third time period) of the switch control signal swn.

[0123] In another alternative embodiment, the detection control module includes, for example, three flip-flops and an AND gate. The three flip-flops are connected in parallel, with their data inputs all receiving an envelope signal OUT_EL, and their clock inputs receiving a first delayed signal TD1, a second delayed signal TD2, and a third delayed signal TD3, respectively. The envelope signal OUT_EL is sampled at corresponding times. The outputs of the three flip-flops are logically ANDed by the AND gate to generate a driver enable signal DR_EN. The driver enable signal DR_EN is valid only when the outputs of all three flip-flops are valid.

[0124] In another alternative embodiment, the detection control module generates not only a driver enable signal DR_EN but also a protection signal. When the disconnection indication signal indicates a line fault, the driver enable signal DR_EN is deactivated to prevent the output signal from being provided, and the protection signal is activated. This protection signal is used to shut off the first and second switches in the switching module and maintain the first and second switches in the off state to prevent the reception of input signals.

[0125] Figure 10 A flowchart of a line breakage protection method according to an embodiment of the present disclosure is shown. The method is used to detect whether a line fault, such as a single-wire or double-wire break, exists on the differential line connected to the receiver during power-on reset, and to perform a protection action when a fault is detected to prevent the output of abnormal signals.

[0126] The method for protecting against wire breakage includes the following steps S01-S05.

[0127] Step S01: Transmit differential signals on differential lines.

[0128] In a digital isolator, differential lines are connected between the transmitter and the receiver. These differential lines include positive and negative phase signal lines. The transmitter converts the input signal into a differential signal, which is then transmitted to the receiver via the differential lines. The receiver converts the differential signal into an output signal that matches the input signal.

[0129] During power-on reset, the receiver's input signal is a predetermined level signal; under normal communication conditions, the receiver's input signal is a dynamic data signal.

[0130] Step S02: Obtain the envelope signal of the differential signal.

[0131] The envelope detector in the receiver rectifies and low-pass filters the received differential input signal, extracts its amplitude envelope, and generates the corresponding DC level signal as the envelope signal OUT_EL.

[0132] The envelope detector is part of the signal restoration circuit in a digital isolator. In this method, existing circuit modules in the digital isolator are utilized to achieve open circuit detection, thereby reducing hardware costs and improving system integration.

[0133] Step S03: Switch the connection status of the differential line according to a predetermined timing sequence.

[0134] During the receiver's power-on reset (POR), a control switch module toggles the on / off state of the differential signal. For example, the switch module is connected between the differential line and the amplifier's input, switching the on / off state of the differential signal by controlling the connection state between the differential line and the amplifier. The switch module controls the connection state of the positive and negative signal lines in the differential line according to the first and second switch control signals, respectively.

[0135] During the first time period, both the first switch control signal and the second switch control signal are valid, and the positive and negative signal lines are connected to the corresponding input terminals of the amplifier.

[0136] During the second time period, the first switch control signal and the second switch control signal are in an invalid state and an effective state, respectively. The positive phase signal line is disconnected, and only the negative phase signal line is connected to the negative phase input terminal of the amplifier.

[0137] During the third time period, disconnect the negative phase signal line and connect only the positive phase signal line to the positive phase input of the amplifier.

[0138] The timing can be controlled by first to third delay signals generated by the delay module that are sequentially delayed relative to the power-on reset signal, or defined by first and second single-pulse signals generated by the monostable circuit.

[0139] Step S04: Determine whether there is a line fault in the differential line based on the state changes of the envelope signal under different on / off states.

[0140] The detection control module detects the response of the sampled envelope signal in each connection state. In one embodiment, this is achieved as follows:

[0141] In the first time period, the first envelope signal is sampled (corresponding to a two-wire connection);

[0142] In the second time period, the second envelope signal is sampled (only the negative phase signal line is connected).

[0143] In the third time period, the third envelope signal is sampled (only the positive phase signal line is connected).

[0144] If the envelope signal is valid (e.g., high) in all connection states, the line is considered normal. If the envelope signal is invalid (e.g., low) in any state, it indicates that at least one signal line of the differential line has a broken connection.

[0145] Step S05: If a line fault exists, execute a protection action to stop providing output signals.

[0146] When a line fault is detected, the detection control module generates a driver enable signal to disable the receiver driver, and / or generates a protection signal to disconnect the transmission path between the differential line and the amplifier. This prevents erroneous signals from reaching the output, thus achieving a line break protection function.

[0147] In one embodiment, the method is executed only once during power-on reset, and after completing the self-test, it enters the normal working mode and is no longer tested repeatedly to avoid interfering with normal signal transmission.

[0148] In the normal communication state of the receiver, the input signal of the receiver is a dynamic data signal, and the first switch control signal and the second switch control signal remain in an active state, thereby maintaining the continuous connection of the differential signal to realize the normal signal reception function of the receiver.

[0149] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0150] As described above, these embodiments of the present disclosure do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present disclosure, thereby enabling those skilled in the art to make good use of the present disclosure and modifications based on it. This disclosure is limited only by the claims and their full scope and equivalents.

Claims

1. A receiver that receives differential signals via differential lines, comprising: An amplifier, an envelope detector, and a driver are connected in sequence, wherein the envelope detector is configured to perform envelope detection on the differential signal received by the receiver to generate a corresponding envelope signal; A switching module is configured to control the on / off state of the input signal path of the envelope detector; and The line breakage protection module is used to detect line faults in the differential line based on the signal changes of the envelope signal under different on / off states during power-on reset, and to stop providing output signals when a line fault exists in the differential line.

2. The receiver according to claim 1, wherein, The switching module is coupled to the input terminal of the amplifier, or The switching module is located between the input terminal of the amplifier and the input terminal of the envelope detector.

3. The receiver according to claim 1, wherein, The disconnection protection module includes: A switch control module is configured to generate a switch control signal for the switch module based on the power-on reset signal of the receiver, and switch the on / off state according to a predetermined timing sequence; and The detection and control module is used to detect whether there is a line fault in the differential line based on the state change of the envelope signal under different on / off states, and to perform protection actions to stop providing output signals when there is a line fault in the differential line.

4. The receiver according to claim 3, wherein, The detection and control module generates a driver enable signal to disable the driver when a line fault exists on the differential line.

5. The receiver according to claim 3, wherein, The detection and control module generates a protection signal to disconnect the differential line when a line fault exists in the differential line.

6. The receiver according to claim 3, wherein, The disconnection protection module also includes: A delay module is used to generate at least one delay signal that is sequentially delayed relative to the power-on reset signal, and the switching module switches the connection state of the differential line at the time indicated by the at least one delay signal.

7. The receiver according to claim 6, wherein, The delay module generates first to third delay signals. During the first time period indicated by the first delay signal, the switching module connects the positive and negative signal lines of the differential line to the corresponding input terminals of the amplifier; during the second time period indicated by the second delay signal, the switching module disconnects the positive signal line of the differential line and connects only the negative signal line of the differential line to the corresponding input terminal of the amplifier. During the third time period indicated by the third delay signal, the switching module disconnects the negative phase signal line of the differential line and connects only the positive phase signal line to the corresponding input terminal of the amplifier.

8. The receiver according to claim 7, wherein, The switch control module includes: A first logic module is configured to perform a first combinational logic operation on the first delayed signal, the second delayed signal, and the power-on reset signal among the at least one delayed signal to generate a first switch control signal; and The second logic module is used to perform a second combinational logic operation on the second delayed signal, the third delayed signal, and the power-on reset signal among the at least one delayed signal, to generate a second switch control signal. The first switch control signal and the second switch control signal control the connection state of the positive phase signal line and the negative phase signal line of the differential line, respectively.

9. The receiver according to claim 8, wherein, The first logic module includes: The first NAND gate performs a NAND operation on the inverted signals of the power-on reset signal and the first delayed signal to generate a first intermediate signal; A first NOR gate performs a NOR operation on the first intermediate signal and the second delayed signal to generate a second intermediate signal; and The second NOR gate performs a NOR operation on the second delayed signal and the second intermediate signal to generate a third intermediate signal. The first switch control signal is the inverted signal of the third intermediate signal.

10. The receiver according to claim 8, wherein, The second logic module includes: The second NAND gate performs a NAND operation on the inverted signals of the power-on reset signal and the second delayed signal to generate a fourth intermediate signal; and The third NOR gate performs a NOR operation on the third delayed signal and the inverted signal of the fourth intermediate signal to generate the fifth intermediate signal. The second switch control signal is the inverted signal of the fifth intermediate signal.

11. The receiver according to claim 6, wherein, The detection control module includes: The fourth NOR gate is used to perform a NOR operation on the envelope signal and the third delayed signal of the at least one delayed signal to generate a sampling trigger signal; A first trigger is configured to sample a predetermined level signal upon triggering by the sampling trigger signal to generate a disconnection indication signal; and The second trigger is used to latch the inverted signal of the disconnection indication signal under the triggering of the third delay signal to generate a driver enable signal.

12. The receiver according to claim 11, wherein, The predetermined level signal is a logic high level.

13. The receiver according to claim 6, wherein, The delay module generates a first delay signal that lags behind the power-on reset signal, the first delay signal indicating a first time period.

14. The receiver according to claim 13, wherein, The switch control module includes: A first monostable circuit, in response to the power-on reset signal, generates a first single-pulse signal with a duration of a second time period after the first time period, as a first switch control signal; and The second monostable circuit responds to the first single pulse signal and generates a second single pulse signal with a duration of a third time period after the second time period, which serves as the second switching control signal.

15. The receiver according to claim 14, wherein, The detection control module includes: The first to third flip-flops, respectively triggered by the first delayed signal, the first single-pulse signal, and the second single-pulse signal, sample the envelope signal to generate the first to third sampled signals; and An AND gate performs an AND operation on the first to third sampled signals to generate a disconnection indication signal. The detection and control module uses the inverted signal of the disconnection indication signal as the driver enable signal.

16. The receiver according to claim 2, wherein, The switch module includes a first switch and a second switch. The first switch and the second switch are respectively used to connect the positive and negative signal lines of the differential line to the corresponding input terminals of the amplifier, or The first switch and the second switch are used to connect the positive and negative output terminals of the amplifier to the corresponding input terminals of the envelope detector, respectively.

17. The receiver according to claim 1, wherein, The differential lines are bonding wire pairs inside the packaging structure.

18. A digital isolator, comprising: A transmitter is used to convert an input signal into a differential signal; The receiver according to any one of claims 1 to 17 is configured to convert the differential signal into an output signal consistent with the input signal; and A differential line, connected between the transmitter and the receiver, is used to transmit the differential signal. The differential line is coupled to at least one of the transmitter and the receiver in a DC-isolated manner.

19. A method for protecting a differential line from disconnection, the differential line being used to transmit differential signals, the method comprising: Obtain the envelope signal of the differential signal; The on / off state of the differential signal is switched according to a predetermined timing sequence; Based on the state changes of the envelope signal under different on / off states, determine whether there is a line fault in the differential line; If a line fault is found, a protection action will be performed to stop providing output signals.

20. The wire breakage protection method according to claim 19, wherein, Obtaining the envelope signal of the differential signal includes: In the first time period, the first envelope signal of the differential signal is obtained; In the second time period, the second envelope signal of the negative phase signal in the differential signal is obtained; and In the third time period, the third envelope signal of the positive phase signal in the differential signal is obtained. Determining whether the differential line has a line fault includes: The first to third envelope signals are logically combined to obtain a disconnection indication signal.

21. The wire breakage protection method according to claim 20, wherein, The protection action includes disconnecting the transmission path of the differential signal and / or disabling the driver of the output signal.

22. The wire breakage protection method according to claim 20, wherein, The disconnection protection method generates the predetermined timing based on the power-on reset signal of the receiver during power-on reset to execute the disconnection protection method.

23. The wire breakage protection method according to claim 22, wherein, The receiver switches the on / off state of the differential signal according to the first switch control signal and the second switch control signal, wherein, During power-on reset, the input signal of the receiver is a predetermined level signal. The first switch control signal and the second switch control signal are both valid during the first time period, invalid and valid respectively during the second time period, and valid and invalid respectively during the third time period. In normal communication mode, the input signal of the receiver is a dynamic data signal, and the first switch control signal and the second switch control signal remain valid.

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