ADC nonlinear error calibration method based on KAN neural network

Abstract

The invention belongs to the technical field of analog-to-digital converter (ADC) digital calibration, and provides an ADC nonlinear error calibration method based on a KAN neural network. According to the method, a complete process of data acquisition, off-chip training, parameter fixed-point and on-chip calibration is constructed. The method specifically comprises the following steps: 1, network training: generating an ideal reference truth value from an original signal acquired by an ADC (Analog to Digital Converter) through a Matlab fitting tool so as to finish accurate training of the KAN; 2, hardware deployment: optimizing hardware overhead through a lookup table and piecewise polynomial fitting method; and 3, calculation and calibration are carried out, and real-time calibration can be completed after parameters are written into an on-chip calibration network. Compared with other neural network calibration algorithms, the method provided by the invention has the characteristics of lower hardware overhead, low power consumption and high calibration precision; the method is suitable for mainstream architectures such as a Piped ADC (Analog to Digital Converter), a Piped SAR (Synthetic Aperture Radar) ADC and the like; the method has the advantages of high universality and high calibration robustness.

Description

Technical Field

[0001] This invention belongs to the field of ADC digital calibration algorithms, and more specifically, relates to a calibration method for ADC nonlinear error based on KAN neural network. Background Technology

[0002] With the rapid development of wireless communication, the demand for high-speed and high-precision ADCs has exploded. Nonlinear errors caused by non-ideal factors in high-speed and high-precision ADCs are gradually becoming a major obstacle to performance improvement. While traditional calibration algorithms can calibrate target errors to some extent, their limitations are significant: most traditional algorithms can only address some of the non-ideal characteristics of ADCs, failing to achieve comprehensive coverage. Furthermore, these algorithms are limited by specific ADC architectures in their application scope, lacking flexibility and making them inadequate for diverse ADC application scenarios. In addition, traditional calibration algorithms are powerless to calibrate higher-order nonlinearities and errors that are difficult to model. Therefore, finding a more versatile digital calibration scheme has been a goal of the industry in recent years.

[0003] In recent years, the fields of machine learning and deep learning have witnessed rapid technological iteration and remarkable achievements. Neural network technology, in particular, has shone brightly, finding widespread and in-depth applications in computer vision, natural language processing, and many other fields, with its powerful learning and fitting capabilities attracting considerable attention. As a highly promising tool, neural networks hold promise for achieving high-precision calibration of ADCs. Compared to traditional calibration algorithms, neural networks offer a more efficient and universal calibration method. Neural networks possess excellent adaptive fitting capabilities and superior generalization abilities for nonlinear functions. A single neural network can be configured to perform various calibration tasks by directly learning the mapping from the observed output of the ADC to the desired calibration output. This flexibility enables the development of calibration models tailored to specific ADC architectures, error distributions, or input conditions. As future ADCs continue to evolve towards higher speeds and higher precision, more complex errors that are difficult to model may emerge. Furthermore, the interaction between different calibration algorithms may further degrade algorithm performance, thus affecting calibration results. Therefore, research into a universal error calibration network is of significant importance. Summary of the Invention

[0004] The main objective of this invention is to propose a novel neural network calibration module to address the shortcomings of traditional calibration algorithms, such as poor flexibility and limited versatility. Compared to other neural network calibration schemes, this scheme can achieve on-chip real-time calibration with lower hardware overhead and lower power consumption, and is effective against nonlinear errors present in mainstream architectures such as Pipelined ADC and Pipelined SAR ADC.

[0005] To achieve the above objectives, this invention proposes a neural network-based calibration scheme, establishing a process for data acquisition, network training, on-chip parameter writing, and calibration. The calibration scheme is as follows: Figure 1 As shown, the ADC acquires analog signals and outputs corresponding digital codewords. Before calibration, the network needs to be trained off-chip: the original signal is fitted into an ideal signal using fitting tools in the Matlab library, serving as the Ground Truth for subsequent network training. The trained network parameters are then fixed-pointed and written back to the chip via common peripheral communication interfaces such as SPI. After these effective parameters are calculated by the network, they will output the corresponding calibration values, thus completing real-time on-chip calibration. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of the overall architecture of the calibration method for nonlinear errors in an ADC based on a KAN neural network proposed in this invention.

[0007] Figure 2 This is a schematic diagram of the KAN network structure proposed in this invention.

[0008] Figure 3 This is a schematic diagram illustrating the calibration of single-tone signals at different frequencies in a specific embodiment of the present invention.

[0009] Figure 4 This is a statistical graph of SFDR results for calibrating a series of signals with normalized frequencies in the range of [0, 0.5] in a specific embodiment of the present invention.

[0010] Figure 5 This is a graph showing the SNDR statistical results of calibrating a series of signals with normalized frequencies in the range of [0, 0.5] in a specific embodiment of the present invention. Detailed Implementation

[0011] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0012] This invention proposes a neural network-based calibration scheme, establishing a process for data acquisition, network training, on-chip parameter writing, and calibration. Specifically, the method includes an ADC acquiring analog signals to obtain corresponding digital codeword outputs. Before calibration, the network needs to be trained off-chip. The trained network parameters are fixed-pointed and written back to the chip via common peripheral communication interfaces such as SPI. These valid parameters, after being calculated by the network, will output corresponding calibration values, thereby completing real-time on-chip calibration. This is one possible implementation method.

[0013] The specific steps of the calibration method of the present invention are as follows: S1, collect sufficient raw signal data of multiple frequency points, multiple temperature conditions, and multiple power-ups of the ADC, and use it as the training and test set of the network.

[0014] S2. Using the fitting tools in the Matlab library, the collected original signal with error is fitted into an ideal signal, which is used as the Ground Truth to train the network and obtain each activation function in the network.

[0015] S3. The Piecewise Polynomial Approximation (PPA) method simplifies the implementation of KAN and reduces hardware overhead. For any nonlinear activation function, after training the KAN network, the PPA coefficients are solved using the KAN training dataset. All activation functions can be replaced with configurable PPA modules, enabling more efficient design and integration. The PPA module in the input layer is replaced with a lookup table (LUT), further reducing hardware overhead.

[0016] The input of the S4 and KAN networks contains 3 sampling points, each corresponding to 6 sets of codes output from the six-stage pipelined ADC circuit. Therefore, the input layer of KAN has a total of 18 nodes. The hidden layer of the network contains 3 nodes, while the output layer is a single-node structure, specifically outputting the calibrated result of the third sampling point. The overall structure is as follows. Figure 2 As shown.

[0017] S5. Perform timing optimization on the hardware-implemented KAN and complete critical path delay compensation for register-level timing buffers, enabling the calibration scheme to be calibrated in real time under the 1.3G clock domain.

[0018] S6. Write the valid network parameters into the register via SPI or other peripheral interfaces. The hardware-implemented KAN network will then perform calculations and inferences based on the corresponding parameters, thereby outputting calibration data in real time.

[0019] The above calibration method was used to calibrate a 14-bit 1.3GS / s Pipelined ADC that had been fabricated and verified, and the following results were obtained.

[0020] B1. The input signal is a single-tone signal, and the aforementioned technique is used for calibration. Figure 3 The comparison of the measured spectrum of the ADC output signal before and after calibration is shown. Figure 3 As shown in (a), the signal-to-noise ratio (SNDR) and spurious-free dynamic range (SFDR) of the ADC increased from 47.9 dB and 55.1 dB to 62.5 dB and 82.2 dB, respectively; as the input signal frequency increases, such as Figure 3 As shown in (b), the two indicators mentioned above were optimized from 47.6 dB and 55.3 dB to 63.2 dB and 81.2 dB.

[0021] B2. Apply the aforementioned calibration technique to calibrate a series of signals with normalized frequencies in the range [0.0, 0.5]. The calibration results are statistically analyzed as follows: Figure 4 As shown, both SFDR and SNDR exhibit stable calibration results, with SFDR showing an average improvement of 23 dB and SNDR an average improvement of 15 dB.

[0022] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for calibrating the nonlinear error of an ADC based on a KAN neural network, characterized by: (1) The improved KAN (Kolmogorov-Arnold Network) neural network is used as the core calibration network of the calibration method; (2) The hardware implementation of the network is optimized for low power consumption using methods such as Piecewise Polynomial Approximation (PPA); (3) It has strong robustness and the calibration scheme based on the neural network is effective against a variety of nonlinear errors.

2. The ADC nonlinear error calibration method based on KAN neural network according to claim 1, characterized in that, The KAN network has three input sampling points, each corresponding to six sets of codes output from a six-stage pipelined ADC circuit. Therefore, the KAN input layer has a total of 18 nodes. The hidden layer of the network has three nodes, while the output layer is a single-node structure, specifically outputting the calibrated result of the third sampling point.

3. The ADC nonlinear error calibration method based on KAN neural network according to claim 1, characterized in that, Replacing the original activation function in the network with a piecewise polynomial simplifies hardware implementation and reduces hardware overhead and power consumption.

4. The ADC nonlinear error calibration method based on KAN neural network according to claim 1, characterized in that, In this calibration method, the network parameters are configurable. If the error range shifts, it can be adapted to new error scenarios by retraining and updating the parameters.

5. The ADC nonlinear error calibration method based on KAN neural network according to claim 1, characterized in that, If the ADC output is a low-bit binary codeword, a lookup table can be used instead of a multiplier and adder to reduce hardware overhead and power consumption.

6. The ADC nonlinear error calibration method based on KAN neural network according to claim 1, characterized in that, The training data for the network is obtained by collecting raw data. The codewords with error information are used as the training dataset for the KAN network. The raw signal is fitted into an ideal signal using fitting tools in the Matlab library, which is used as the ground truth.

7. The ADC nonlinear error calibration method based on KAN neural network according to claim 1, characterized in that, Timing optimization in the KAN hardware implementation enables real-time calibration under high-speed clock conditions.

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