High-speed communication method based on embedded instrument

Abstract

The invention discloses a high-speed communication method based on an embedded instrument. The high-speed communication method comprises the following steps that S1, the instrument receives protocol data; s2, analyzing the protocol data, and extracting effective instructions in the protocol data; s3, setting an instruction buffer pool, and storing the effective instruction into the instruction buffer pool; s4, sending a protocol data receiving response to the test system; and S5, the instrument analyzes and responds to the effective instruction in the instruction buffer pool when the resource is idle, and then waits for receiving the instruction next time. According to the method, the cache thread is additionally arranged, so that temporary storage of the ASCII instruction after the instrument equipment completes VXI-11 unpacking is realized, and resource scheduling is facilitated to complete analysis and response of the ASCII instruction when the instrument is idle. Through the method, the instrument responds to the message when the resource is idle, and message blocking or instruction response failure caused by a high-priority task is avoided. The problems of instruction failure and error response during rapid receiving of instrument equipment during high-speed VXI-11 communication are effectively solved.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and more specifically to a high-speed communication method based on embedded instruments. Background Technology

[0002] In distributed and hybrid test systems, network communication is typically used to connect to test instruments for acquiring data and controlling them. The VXI-11 protocol allows embedded instruments to access the test system via a LAN bus, providing a lower-cost, higher-bandwidth, and faster data transmission rate hardware platform access method. The instrument implements the VXI-11 protocol using a client / server-based RPC mechanism, enabling it to be discovered on the network and thus access the computer system to call the VISA library.

[0003] However, in practical applications, due to the limited communication resources of small embedded instruments, it is difficult to guarantee stable communication between the instrument and the test system with high bandwidth throughput during operation. Specifically, embedded instruments experience problems such as communication command response errors and control command failures when using the VXI-11 protocol for high-speed communication.

[0004] In summary, there is a need to design and develop a high-speed communication method based on embedded instruments to address the problems in the existing technology. Summary of the Invention

[0005] To address the problems in the prior art, this invention provides a high-speed communication method based on embedded instruments, which solves the problem of VXI-11 protocol communication failure caused by insufficient network communication resources in embedded instruments.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: A high-speed communication method based on embedded instruments includes the following steps: S1. The instrument receives protocol data; S2. Parse the protocol data and extract the valid instructions from the protocol data; S3. Set up an instruction buffer pool and store the valid instructions into the instruction buffer pool; S4. Send a protocol data reception response to the test system; S5. When resources are idle, the instrument parses and responds to valid instructions in the instruction buffer pool, and then waits for the next instruction to be received.

[0007] In some embodiments of the present invention, step S1 involves receiving protocol data by setting up an independently running communication task.

[0008] In some embodiments of the present invention, the instruction cache pool is implemented using a circular queue, and each queue unit contains at least the following fields: sequence number, instruction string pointer, instruction length, and status flag.

[0009] In some embodiments of the present invention, step S3 includes: The valid instructions are stored in the instruction cache pool in the order of the queue. Record the storage address and length of the valid instruction; Mark the valid instructions in the queue as "to be parsed"; The instruction cache pool enters the instruction receiving state.

[0010] In some embodiments of the present invention, the step S5 of parsing and responding to the valid instructions in the instruction buffer pool includes: The instruction cache pool is protected against write and read operations. Query the unparsed tags in each queue of the instruction cache pool; Respond to each valid instruction according to the principle of first-to-cache, first-to-respond.

[0011] In some embodiments of the present invention, step S5 further includes storing the response result in the response buffer and updating the status of the valid instruction to "responded" after the valid instruction has been responded to.

[0012] In some embodiments of the present invention, the instruction cache pool adopts a circular queue structure.

[0013] In some embodiments of the present invention, a high-speed communication device based on embedded instruments is provided, comprising: The instruction receiving module is used to acquire protocol data and extract valid instructions from it; A caching module is used to cache the valid instructions; The instruction response module is used to respond to valid instructions when resources are idle; The communication module is used to communicate with external devices.

[0014] In some embodiments of the present invention, the caching module is further configured to return a response and release the communication link after the valid instruction has been cached.

[0015] In some embodiments of the present invention, a computer-readable storage medium is provided, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the high-speed communication method described above.

[0016] The technical solution of the present invention has the following technical effects compared with the prior art: This invention adds a caching thread to temporarily store ASCII commands after the instrument completes VXI-11 unpacking, facilitating resource scheduling to complete ASCII command parsing and response when the instrument is idle. This method enables the instrument to respond to messages when resources are available, avoiding message blocking or command response failures due to high-priority tasks. It effectively solves the problem of command failure and erroneous responses during rapid reception in high-speed VXI-11 communication. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram illustrating the high-speed communication method based on the VXI-11 protocol communication of embedded instruments in this embodiment; Figure 2 This is a flowchart of the ASCII instruction caching program shown in this embodiment; Figure 3 This is a flowchart of the ASCII instruction parsing program shown in this embodiment; Figure 4 This is a schematic diagram of the structure of the high-speed communication device shown in this embodiment.

[0019] Reference numerals: 100, high-speed communication device; 110, instruction receiving module; 120, buffer module; 130, instruction response module; 140, communication module. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0022] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0023] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections, direct connections, or indirect connections through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0024] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0025] The following disclosure provides many different embodiments or examples for implementing different structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the invention. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0026] In Example 1, the instrument uses a synchronous request-response model of RPC to complete the VXI-11 protocol. Therefore, when the instrument receives a protocol packet, it needs to process it immediately and return a response before it can receive the next protocol packet. When the main CPU of the embedded instrument is occupied by high-priority tasks (such as real-time data acquisition and signal processing), its network communication thread (or task) may be suspended, resulting in the inability to process incoming VXI-11 protocol packets in a timely manner. This phenomenon will lead to two main consequences: first, TCP buffer overflow, causing subsequent data packets to be lost, thus inducing "instruction failure"; second, RPC call timeout, the client (test system) does not receive the expected response, judges it as a "communication error", and then triggers instruction retransmission or connection interruption, significantly weakening the reliability of communication and the actual effective bandwidth.

[0027] Therefore, this embodiment provides a high-speed communication method based on embedded instruments, which effectively solves the problem of VXI-11 protocol communication failure caused by insufficient network communication resources in embedded instruments. Specifically, the protocol parsing and execution part of the VXI-11 protocol communication process is decomposed into tasks, and an instruction buffer pool is introduced as an intermediate buffer to handle instruction responses asynchronously. That is, the network receiving thread with high real-time requirements is separated from the main control thread, which may be subject to brief blocking risks due to high-priority operations such as computation and data acquisition. The receiving thread is responsible for quickly completing VXI-11 protocol parsing and instruction extraction, storing the instructions in the buffer pool, and immediately returning a response to release the communication link; the main control thread parses and responds to instructions in sequence from the buffer pool when resources are idle. This essentially transforms the synchronous request-response model into a quasi-asynchronous model of "receiving-buffering-asynchronous processing", fundamentally avoiding problems such as instruction timeouts, loss, or communication interruptions caused by the instrument's main processor being temporarily busy and unable to process communication requests in a timely manner.

[0028] Reference Figure 1 As shown, a high-speed communication method based on embedded instruments includes the following steps: Step S1: The instrument receives protocol data; The instrument uses the RPC mechanism to receive VXI-11 protocol data. The instrument starts an independent network listening thread or task to receive VXI-11 protocol data packets in real time, ensuring lossless reception of TCP layer data.

[0029] Step S2: Parse the protocol data and extract the valid instructions from the protocol data; specifically, parse the VXI-11 protocol packet and extract the valid instructions carried therein—ASCII-encoded SCPI (Programmable Instrument Standard Command) instruction strings.

[0030] Step S3: Set up an instruction buffer pool and store the valid instructions in the instruction buffer pool. For the instruction buffer pool, an instruction buffer pool that can hold 50 instructions can be set up in the instrument firmware. The instruction buffer pool adopts a circular queue structure, and each queue unit contains at least the following fields: sequence number, instruction string pointer, instruction length, and status flag. Among them, the status flags are such as "idle", "pending parsing", and "parsing".

[0031] Reference Figure 2 As shown, the cache of valid instructions specifically includes the following: S31. The valid instructions are stored in the instruction cache pool in the order of the queue; specifically, the ASCII instructions extracted from the VXI-11 protocol are stored in the instruction cache pool in the order of the queue, and each instruction has its own queue number. S32. Record the storage address and length of the valid instruction; this facilitates subsequent reading of instructions from the cache pool. S33. Mark the valid instructions in the queue as "to be parsed"; S34. The queue reception of this instruction is completed, and the instruction buffer pool enters the instruction reception state.

[0032] Step S4: The instrument responds to the completed VXI-11 message reception according to the RPC mechanism, indicating to the network client that the instrument has completed the instruction reception.

[0033] Step S5: When resources are idle, the instrument parses and responds to valid instructions in the instruction buffer pool, and then waits for the next instruction to be received. Specifically, when resources are idle, the instrument starts an instruction parsing and response task or thread. Instructions marked "to be parsed" are semantically parsed sequentially using the corresponding command parser in the instrument firmware, and the corresponding instrument operation (such as parameter setting, data query, status reading, etc.) is executed. After execution, the result is stored in the response buffer, and the instruction queue status is updated to "responded".

[0034] Reference Figure 3 As shown, it includes the following steps: S51, Write and read protection of the instruction cache pool; This step can prevent the instrument from failing to parse instructions due to changes in the contents of the cache area. Therefore, it is necessary to confirm that the cache pool will not be changed before entering this process.

[0035] S52. Query the unparsed flags in each queue of the instruction cache pool; that is, read the message parsing enable flags in each queue of the instruction cache pool. The parsing enable flags of the instruction queues are marked in step S33.

[0036] S53. Respond to each valid instruction according to the principle of first-to-cache, first-to-respond.

[0037] S54. After a valid instruction is responded to, the response result is stored in the response buffer and the status of the valid instruction is updated to "responded".

[0038] Step S6: The instrument returns to the communication receiving state and waits for the next command response.

[0039] The technical solution of the present invention has the following technical effects compared with the prior art: This invention adds a caching thread to temporarily store ASCII commands after the instrument completes VXI-11 unpacking, facilitating resource scheduling to complete ASCII command parsing and response when the instrument is idle. This method enables the instrument to respond to messages when resources are available, avoiding message blocking or command response failures due to high-priority tasks. It effectively solves the problem of command failure and erroneous responses during rapid reception in high-speed VXI-11 communication.

[0040] Let's take an embedded power analyzer based on the ARM Cortex-M7 core as an example for a detailed explanation: In this power analyzer, the main control thread needs to continuously execute high-priority real-time tasks, such as waveform calculation and power calculation of high-speed ADC sampling data (each intensive calculation process may last from several milliseconds to tens of milliseconds). Without this invention, if a VXI-11 communication command is received during this calculation process, the instrument will be unable to respond to the RPC call in a timely manner, which can easily lead to a response timeout (e.g., exceeding 2 seconds). As a result, in scenarios where the host computer is sending test commands at full load, the communication failure rate can be as high as 30% or more.

[0041] The workflow and effect comparison of the asynchronous reception and buffering processing method described in this invention are as follows: 1. System configuration: Create an instruction buffer pool (using a circular queue structure) in the instrument firmware that can hold 50 instructions.

[0042] 2. Communication Task: A standalone, medium-priority network communication task specifically responsible for listening to, receiving, and parsing VXI-11 protocol packets. This task can complete protocol parsing, extract ASCII instructions, and store them in a buffer pool within 1 millisecond, and then immediately return a "successful reception" acknowledgment to the host computer, thereby quickly releasing TCP connection resources.

[0043] 3. Instruction Parsing and Response Task: After completing a period of intensive power calculation (e.g., lasting 10 milliseconds), the main control thread typically enters a resource idle window of approximately 1 millisecond. During this time, the instruction parsing and response task checks the instruction cache pool and sequentially processes one or two cached instructions.

[0044] Implementation Results: Comparative testing showed that, under the same host computer command transmission rate and instrument workload, the following results were observed after adopting this method: The communication failure rate has been significantly reduced from over 30% to below 0.1%. The average command response time perceived by the host computer has been significantly stabilized between 10 and 50 milliseconds, compared to the previously unpredictable range of over 0 to 2000 milliseconds. This method effectively eliminates the problem of unresponsive or lost commands caused by the busy state of the instrument's main control thread, greatly improving the determinism and reliability of the VXI-11 communication connection, all without requiring any increase in hardware costs.

[0045] Example 2, Reference Figure 4 As shown, this embodiment provides a high-speed communication device based on embedded instruments, including: The instruction receiving module 110 is used to acquire protocol data and extract valid instructions from it; Cache module 120 is used to cache the valid instructions; The instruction response module 130 is used to respond to valid instructions when resources are idle; Communication module 140 is used to communicate with external devices.

[0046] In some embodiments of the present invention, the caching module is further configured to return an acknowledgment and release the communication link after the valid instruction has been cached. Specifically, the instruction receiving module and the caching module operate as an independent, medium-priority network communication task, specifically responsible for listening to, receiving, and parsing VXI-11 protocol packets. This task can complete protocol parsing, extract ASCII instructions, and store them in the cache pool within 1 millisecond, and then immediately return a "successful reception" acknowledgment to the host computer, thereby quickly releasing TCP connection resources.

[0047] It should be understood that the high-speed communication device 100 here is embodied in the form of a functional module. The term "module" here can refer to application-specific integrated circuits (ASICs), electronic circuits, processors (e.g., shared processors, proprietary processors, or group processors, etc.) and memories for executing one or more software or firmware programs, integrated logic circuits, and / or other suitable components supporting the described functions. In an alternative example, those skilled in the art will understand that the high-speed communication device 100 can be specifically the electronic device in the above embodiments, or the functions of the electronic device can be integrated into the high-speed communication device 100. The high-speed communication device 100 can be used to execute the various processes and / or steps corresponding to the electronic device in the above method embodiments; to avoid repetition, these will not be described again here.

[0048] The high-speed communication device 100 described above has the function of implementing the corresponding steps of the electronic device executing the high-speed communication method in Embodiment 1; the above functions can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions. For example, the above acquisition module can be a communication interface, such as a transceiver interface.

[0049] In the embodiments of this application, Figure 4 The high-speed communication device 100 in the middle can also be a chip or a chip system, such as a system on chip (SoC).

[0050] Example 3: In this example, a computer-readable storage medium is provided. The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the high-speed communication method in Embodiment 1.

[0051] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0052] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0053] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0054] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0055] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0056] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0057] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0058] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A high-speed communication method based on embedded instruments, characterized in that, Includes the following steps: S1. The instrument receives protocol data; S2. Parse the protocol data and extract the valid instructions from the protocol data; S3. Set up an instruction buffer pool and store the valid instructions into the instruction buffer pool; S4. Send a protocol data reception response to the test system; S5. When resources are idle, the instrument parses and responds to valid instructions in the instruction buffer pool, and then waits for the next instruction to be received.

2. The high-speed communication method according to claim 1, characterized in that, In step S1, protocol data is received by setting up an independently running communication task.

3. The high-speed communication method according to claim 1, characterized in that, The instruction cache pool is implemented using a circular queue, and each queue unit contains at least the following fields: sequence number, instruction string pointer, instruction length, and status flag.

4. The high-speed communication method according to claim 1, characterized in that, Step S3 includes: The valid instructions are stored in the instruction cache pool in the order of the queue. Record the storage address and length of the valid instruction; Mark the valid instructions in the queue as "to be parsed"; The instruction cache pool enters the instruction receiving state.

5. The high-speed communication method according to claim 1, characterized in that, The step S5 of parsing and responding to valid instructions in the instruction buffer pool includes: The instruction cache pool is protected against write and read operations. Query the unparsed tags in each queue of the instruction cache pool; Respond to each valid instruction according to the principle of first-to-cache, first-to-respond.

6. The high-speed communication method according to claim 1, characterized in that, Step S5 further includes storing the response result in the response buffer after the valid instruction has been responded to, and updating the status of the valid instruction to "responded".

7. The high-speed communication method according to claim 1, characterized in that, The instruction cache pool adopts a circular queue structure.

8. A high-speed communication device based on embedded instruments, characterized in that, For implementing the high-speed communication method as described in any one of claims 1-7, comprising: The instruction receiving module is used to acquire protocol data and extract valid instructions from it; A caching module is used to cache the valid instructions; The instruction response module is used to respond to valid instructions when resources are idle; The communication module is used to communicate with external devices.

9. The high-speed communication device according to claim 8, characterized in that, The caching module is also used to return a response and release the communication link after the valid instruction has been cached.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the high-speed communication method as described in any one of claims 1-7.

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