Infrared detector driving imaging method based on InterlanceBinning mode
By using the method of storing odd and even frame data separately and reorganizing images in the infrared detector, the problem of imaging delay in the Interlance & Binning mode is solved, achieving high-quality imaging while reducing delay and improving the real-time performance of the system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING INST OF REMOTE SENSING EQUIP
- Filing Date
- 2025-12-23
- Publication Date
- 2026-04-21
AI Technical Summary
Existing infrared detectors have long imaging delays in Interlance & Binning mode, making it difficult to meet real-time requirements.
By using a method of storing odd and even frame data separately, the subframe data after integration processing by the infrared detector is stored in different RAM storage areas according to odd and even rows. The image is sorted and time-series reassembled row by row in the second storage area to reduce latency.
While ensuring image quality, it significantly reduces image transmission latency and improves the real-time performance of the imaging system.
Smart Images
Figure CN121908153A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of infrared imaging, specifically an infrared detector-driven imaging method based on the Interlance & Binning mode. Background Technology
[0002] Traditionally, infrared detectors output a complete image after one integration operation. To improve image quality and reduce the signal-to-noise ratio (SNR), the detector is configured in an interlance and binning mode. In this mode, the charge storage capacity is increased by 1x2 (the charge of adjacent rows in the same column is superimposed, e.g., row 0 is superimposed with row 1, row 2 with row 3, and so on). This increased charge storage capacity effectively improves the dynamic range and SNR of the imaging system, thereby enhancing image quality and the detector's environmental adaptability. The increased dynamic range allows for better capture of details in both bright and dark areas of the image, reducing noise. Furthermore, the increased charge storage capacity improves the spatial resolution of the image, providing richer information and resulting in a clearer and more detailed image.
[0003] To improve the imaging quality of the detector, it is set to the interlance & binning working mode. This design provides an imaging method for this mode. The traditional imaging method in the interlacing mode is to output the odd and even subframe sets completely and then reassemble the image. This will cause a large time delay in the real-time image. This method is not suitable for those with strict real-time requirements. The new imaging method can reduce the image delay time while ensuring the imaging quality, thereby enhancing the real-time performance of the data image transmission generated in this mode. Summary of the Invention
[0004] This invention provides an infrared detector-driven imaging method based on the Interlance & Binning mode, solving the problem of latency in existing infrared detector-driven imaging. This solution allows for complete image transmission only after the even-numbered frames have been completed and the odd-numbered subframes begin to be generated. The method involves real-time padding of the subset of rows containing zeros based on the TA (Transmission Aspect). The specific technical solution is as follows:
[0005] An infrared detector-driven imaging method based on the Interlance & Binning mode, the method being applied to a processor chip equipped with registers, the method comprising:
[0006] The subframe data after integration processing by the infrared detector is stored in different storage areas of the register according to odd rows and even rows. The storage area that stores all odd rows or even rows first is called the first storage area, and the other storage area is called the second storage area.
[0007] When storing subframe data line by line in the second storage area, the processor chip retrieves the subframe data already stored in the second memory and the corresponding subframe data in the first storage area to perform image sorting and temporal reassembly, thereby obtaining image data for the corresponding number of lines.
[0008] After the second memory area stores all the subframe data, the processor chip sequentially sorts and reassembles the image data and timing of all the subframe data in the second memory area with the corresponding subframe data in the first memory area, thus obtaining all the image data.
[0009] Specifically, the register is a RAM register, divided into RAMA and RAMB storage areas. RAMA is used to store subframe data for odd-numbered rows, and RAMB is used to store subframe data for even-numbered rows.
[0010] Furthermore, the step of storing the subframe data after integration processing by the infrared detector into different storage areas of the register according to odd-numbered rows and even-numbered rows specifically includes:
[0011] The write enable interface ena_1 of the RAMA memory area is used to receive the line valid signal lval_in for subframe data.
[0012] The write data interface dina_1 of the RAMA storage area is used to receive the data signal dina_in of subframe data;
[0013] The write enable interface ena_2 of the RAMB memory area is used to receive the line valid signal lval_in for subframe data.
[0014] The write data interface dina_2 of the RAMA storage area is used to receive the data signal dina_in of subframe data;
[0015] The subframe type determination signal `img_even` is used to determine the direction of data flow.
[0016] When the subframe type determination signal img_even is 0, the data flows to the RAMA storage area;
[0017] When the subframe type determination signal img_even is 1, the data flows to the RAMB storage area.
[0018] Furthermore, the step of storing the subframe data after integration processing by the infrared detector into different storage areas of the register according to odd-numbered rows and even-numbered rows specifically includes:
[0019] The frame validity signal fval_in for subframe data is used to determine whether an address reset is needed.
[0020] When the frame valid signal fval_in is 0, the write address signal addra is reset to zero.
[0021] When the frame valid signal fval_in is 1, it is determined whether the size of the write address signal addra is less than the maximum address RAM_addr of the set RAM register;
[0022] Furthermore, determining whether the size of the write address signal addra is less than the maximum address RAM_addr of the set RAM register includes:
[0023] If the write address signal addra is not less than the maximum address RAM_addr, then the write address signal addra is reset to zero.
[0024] If the write address signal addra is less than the maximum address RAM_addr, then check if the write enable signal ena is 1.
[0025] Furthermore, determining whether the write enable signal ena is 1 includes:
[0026] If the write enable signal ena is 1, then the write address signal addra is incremented;
[0027] If the write enable signal ena is 0, the write address signal addra remains unchanged.
[0028] Furthermore, when storing subframe data line by line in the second storage area, the processor chip retrieves the subframe data already stored in the second storage area and the corresponding subframe data in the first storage area to perform image sorting and temporal reassembly, obtaining image data for the corresponding number of rows, including:
[0029] When the subframe type determination signal ram_cnt is 1, read the odd number of rows of data from the RAMB storage area;
[0030] When the subframe type determination signal ram_cnt is 0, read the odd number of rows of data from the RAMA storage area;
[0031] When the signal Fval_out is 0, the subframe type determination signal ram_cnt is reset to zero.
[0032] When the signal Fval_out is 0, determine the rising edge of the signal lval_out;
[0033] When the rising edge of the lval_out signal is detected, the subframe type determination signal ram_cnt is incremented by 1.
[0034] When no rising edge of the lval_out signal is detected, the subframe type determination signal ram_cnt remains unchanged.
[0035] Furthermore, when storing subframe data line by line in the second storage area, the processor chip retrieves the subframe data already stored in the second storage area and the corresponding subframe data in the first storage area to perform image sorting and temporal reassembly to obtain image data for the corresponding number of lines, which also includes:
[0036] The address signal addrb_1 is connected to the RAMA address interface, and the signal doub_1 is connected to the RAMA data interface.
[0037] The address signal addrb_2 is connected to the RAMB address interface, and the signal doutb_2 is connected to the RAMB register data interface.
[0038] The RAM_addr signal is the address size set in the RAM register;
[0039] When the output frame valid signal fval_out_f1 is 0 (invalid), the address signals addrb_1 and addrb_2 will be reset to zero.
[0040] When the output frame valid signal fval_out_f1 is valid, check whether the RAMA memory area address signal addrb_1 is greater than the signal RAM_addr, and check whether the RAMB memory area address signal addrb_2 is greater than the signal RAM_addr.
[0041] If address signal addrb_1 is greater than signal RAM_addr or address signal addrb_2 is greater than signal RAM_addr, then signal RAM_addr is reset to zero;
[0042] If the address signal addrb_1 is less than the signal RAM_addr and the address signal addrb_2 is less than the signal RAM_addr, then the row valid signal lval_out_f1 is judged.
[0043] If the row valid signal lval_out_f1 is 0, the address signal addrb_1 remains unchanged, and the address signal addrb_2 remains unchanged.
[0044] If the row valid signal lval_out_f1 is 1, then the signal ram_cnt is checked;
[0045] If the signal ram_cnt is 1, the address signal addrb_1 remains unchanged, and the address signal addrb_2 is incremented by 1.
[0046] If the signal ram_cnt is 0, the address signal addrb_1 is incremented by 1, while the address signal addrb_2 remains unchanged.
[0047] When odd-numbered frames begin to be output, the images are sorted and reassembled.
[0048] The beneficial effects of this invention are as follows:
[0049] This invention discloses an infrared detector-driven imaging method based on the Interlance & Binning mode, and designs corresponding image sorting and recombination methods. This method stores image data of two different sub-frame types generated by the detector separately, performs image sorting and temporal recombination of odd and even frames, and finally outputs complete image data. This method fuses pixels in adjacent rows of the image to improve the imaging quality. While improving imaging quality, this causes image transmission delay. This method significantly reduces the delay time while maintaining image quality. Data is read out by controlling the change of RAM register address to complete the image sorting and recombination of odd and even rows, thus obtaining a complete 640x512 image. This method performs image sorting and recombination after the output of even-numbered frames and when the output of odd-numbered frames begins, greatly reducing the processing delay. Attached Figure Description
[0050] Figure 1 This is the timing diagram of the detector output used in this invention.
[0051] Figure 2 This is the system control flowchart of the present invention.
[0052] Figure 3 This is a schematic diagram of the dual-port RAM register interface used in this invention.
[0053] Figure 4 This is a flowchart illustrating the operation of writing data to the RAM register used in this invention.
[0054] Figure 5 This is a schematic diagram of the generation of the subframe type determination signal img_even proposed in this invention.
[0055] Figure 6 This is a flowchart of the data writing operation proposed in this invention.
[0056] Figure 7 This is a diagram showing the change in the written data address proposed in this invention.
[0057] Figure 8 This is a flowchart of the RAM register read data operation proposed in this invention.
[0058] Figure 9This is a schematic diagram illustrating the generation of the subframe type determination signal ram_cnt proposed in this invention.
[0059] Figure 10 This is the data readout address change diagram proposed in this invention. Detailed Implementation
[0060] To make the objectives, technical solutions, and advantages of this specification clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments in this specification, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments in this application without creative effort are within the scope of protection of this document. Specific Implementation Example 1:
[0062] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0063] This invention proposes an infrared detector-driven imaging method based on the Interlance & Binning mode. The output timing diagram of the infrared detector in the Interlance & Binning interlaced merging mode is shown below. Figure 1 As shown. After the detector is powered on, it first performs an integration operation. INT is the integration signal; when INT is high, it indicates that the detector is integrating, and when INT is low, it indicates that integration is complete. After integration, the detector outputs data. The signal HSYNC is the data row valid signal; when it is high, it indicates that the output data is valid. The signal FRAME is the odd / even subframe determination signal; after integration, the type of the output subframe is determined by detecting whether this signal is pulled high.
[0064] The system control flowchart of the present invention is as follows: Figure 2As shown, the infrared detector outputs two different types of subframe images after integration in the Interlance & Binning mode. The first subframe, consisting of all even-numbered rows of data, is output after the first integration. The second subframe, consisting of all odd-numbered rows of data, is output after the second integration. The two subframes are distinguished by the Frame odd / even subframe signal, where frame_rf is the even-numbered subframe flag signal and the rising edge of the Frame odd / even subframe signal. If the frame_rf even-numbered subframe flag is detected after integration, the output subframe is the first subframe; otherwise, the second subframe is output. After subframe differentiation, the two subframe data are temporarily stored in two dual-port RAM memories: even-numbered frame data in RAMA and odd-numbered frame data in RAMB. After data storage, the data is read from both RAM memories and sorted by odd / even rows.
[0065] The data size of a complete image is 640 x 512 = 327680, where 512 is the number of rows and 640 is the number of pixels in each row, for a total of 327680 valid pixels. There are 256 rows of even-numbered subframes and 256 rows of odd-numbered subframes. The even-numbered subframe dataset is represented as follows:
[0066]
[0067] A1 to A256 are subsets of the even-numbered subframe dataset. Each number in this subset represents a line of valid data. Each subset has a data size of 1 x 640. Taking A1 as an example, A1 = [a1 a2 … a639 a640] where a1-a640 represent valid pixels, and the numbers 1 to 640 represent the position of the pixel in that line.
[0068] The data representation of odd-numbered rows of subframes is as follows:
[0069]
[0070] B1 to B256 are subsets of the odd-numbered subframe dataset. Each number in this subset represents a line of valid data. Each subset has a data size of 1 x 640. Taking B1 as an example, B1 = [b1 b2 … b639 b640] where b1-b640 represent valid pixels, and the numbers 1 to 640 represent the position of the pixel in that line.
[0071] Both datasets contain data of 256x640. The data in the two subframe datasets is padded to change its format from 256x640 to 512x640. The padding template is T, and the expression is as follows:
[0072]
[0073] The data A* and B* obtained through this processing are shown below:
[0074]
[0075] After preliminary processing, the data were arranged separately. The even-numbered subset was arranged using the T1 model to obtain data TA, and the odd-numbered subset was arranged using the T2 model to obtain data TB. The expressions are as follows:
[0076]
[0077] The processed subset A and subset B data are then merged row by row, resulting in a merged data image.
[0078]
[0079] The previous method required all odd and even subframes to be output before data processing could begin, which would cause a delay in the image output. The improved method only requires the even-numbered frames to be output before the odd-numbered subframes start to be output, and then the complete image transmission can be performed. This method is based on TA and fills the 0 subset rows in real time.
[0080] The specific implementation is as follows: the subframe data output by the detector is temporarily stored in the dual-port RAM register inside the FPGA. The interface diagram of the dual-port RAM register is shown below. Figure 3 As shown in the diagram, the left side of the schematic represents the data interface for writing to the RAM registers. Data can be stored by controlling this interface. The interface signals for this part are clk_a (write clock, providing timing for register write operations), ena (write enable), wea (write control), addra (write address), and dina (write data). The right side of the schematic represents the data interface for reading from the RAM. Data stored in the RAM can be read by controlling this interface. The interface signals for this part are clk_b (read clock), enb (read enable), addrb (read address), and doub (read data).
[0081] The flowchart for writing data to the RAM register is as follows: Figure 4As shown. When valid data arrives, the type of the input subframe needs to be determined. The signal img_even is the subframe type determination signal. When it is 1, the input data stream is determined to be the first subframe data (even-numbered rows). When it is 0, the input data stream is considered to be the second subframe data (odd-numbered rows). The purpose of this is to distinguish the data type of the transmitted data in preparation for subsequent image processing.
[0082] The following diagram illustrates the generation of the subframe type determination signal img_even. Figure 5 As shown. When the integration signal INT is 1, the detector performs integration, and the subframe type judgment signal img_even is reset to zero. When the integration signal INT is 0, the detector completes integration. At this time, the odd / even subframe signal Frame is detected. If a valid odd / even subframe signal Frame is detected, the subframe type judgment signal img_even is incremented by one; if no valid signal is detected, the subframe type judgment signal img_even remains unchanged. After the input subframe data is classified, the data is written to the corresponding dual-port RAM registers. The first subframe (even-numbered rows) data is stored in register RAMB, and the second subframe (odd-numbered rows) data is stored in register RAMA.
[0083] The data writing operation process is as follows: Figure 6 As shown, the row enable signal lval_in from the image data is connected to the write enable interface ena_1 of the RAMA register and the write enable interface ena_2 of the RAMB register, respectively. This signal is active high. The data signal dina_in is connected to the write data interface dina_1 of the RAMA register and the write data interface dina_2 of the RAMB register, respectively. The data output direction is determined by the subframe type determination signal img_even. When it is 0, the data flows to the RAMA register; when it is 1, the data flows to the RAMB register. The address signal addra of the RAM register changes as follows when the transmitted data is stored. Figure 7 As shown, first, it checks if the frame valid signal fval_in is valid. This signal is invalid when it is 0, and the write address signal addra is reset to zero. When the frame valid signal is 1, it is valid. Then, it checks if the address size is less than the maximum address RAM_addr of the set RAM register. If it is not less than, the address is reset to zero. If it is less than, the address is incremented when the enable signal ena is 1. Otherwise, the address remains unchanged.
[0084] The flowchart for reading data from the RAM register is as follows: Figure 8As shown, when reading data, the ram_cnt subframe type determination signal determines the source of the data to be read. When the ram_cnt subframe type determination signal is 1, odd-numbered rows of data are read from the RAMB register; when it is 0, even-numbered rows of data are read from the RAMA register. The generation diagram of the ram_cnt subframe type determination signal is as follows. Figure 9 As shown. When the signal Fval_out is zero, ram_cnt reads the subframe type judgment signal and sets it to zero; when it is 1 and valid, it judges the rising edge of the signal lval_out. When the rising edge is detected, ram_cnt reads the subframe type judgment signal and increments it by one. If it is not detected, ram_cnt reads the subframe type judgment signal and holds it.
[0085] The connection relationships for the read data section of the RAM register are as follows: the addrb_1 address signal is connected to the RAMA address interface, and the doutb_1 signal is connected to the RAMA data interface. The addrb_2 address signal is connected to the RAMB address interface, and the doutb_2 signal is connected to the RAMB register data interface. The RAM_addr signal represents the address size set in the RAM register. The specific changes of the addrb_1 and addrb_2 address signals are as follows: Figure 10 As shown. When the output frame valid signal fval_out_f1 is zero (invalid), the address signals addrb_1 and addrb_2 will be reset to zero. When fval_out_f1 is 1 (valid), the RAMA register address signal addrb_1 and the RAMB register address signal addrb_2 are compared with the maximum address of the RAM_addr register. If they are greater than the maximum address of the RAM_addr register, they will be reset to zero. If they are less than the maximum address, the next step is to judge the output row valid signal lval_out_f1. If this signal is 0 (invalid), the address signals addrb_1 and addrb_2 will remain unchanged. If this signal is 1 (valid), the odd / even row signal is judged. The judgment is determined by the signal ram_cnt. When it is 1, the address signal addrb_1 remains unchanged and the address signal addrb_2 is incremented by one. If the subframe type judgment signal read by ram_cnt is zero, the address signal addrb_1 is incremented by one, and the address signal addrb_2 remains unchanged. By controlling the changes in the RAM register address, data is read out to complete the sorting and recombination of odd and even rows of images, thus obtaining a complete 640x512 image. This method performs image sorting and recombination after the even-numbered frames have been output and the odd-numbered frames have begun to be output, greatly reducing the processing delay.
[0086] This invention discloses an infrared detector-driven imaging method based on an interlaced merging mode, and designs corresponding image sorting and reassembly methods. This method stores image data of two different sub-frame types generated by the detector separately, performs image sorting and temporal reassembly of odd and even frames, and finally outputs complete image data. This method fuses pixels in adjacent rows of the image to improve the detector's imaging quality. While improving imaging quality causes image transmission delay, this method significantly reduces the delay time while maintaining image quality. Specific Implementation Example 2:
[0088] An infrared detector-driven imaging method based on the Interlance & Binning mode, the method being applied to a processor chip with registers, the method comprising:
[0089] The subframe data after integration processing by the infrared detector is stored in different storage areas of the register according to odd rows and even rows. The storage area that stores all odd rows or even rows first is called the first storage area, and the other storage area is called the second storage area.
[0090] When storing subframe data line by line in the second storage area, the processor chip retrieves the subframe data already stored in the second memory and the corresponding subframe data in the first storage area to perform image sorting and temporal reassembly, thereby obtaining image data for the corresponding number of lines.
[0091] After the second memory area stores all the subframe data, the processor chip sequentially sorts and reassembles the image data and timing of all the subframe data in the second memory area with the corresponding subframe data in the first memory area, thus obtaining all the image data.
[0092] Furthermore, the register specifically refers to:
[0093] The register is a RAM register, divided into RAMA and RAMB storage areas. RAMA is used to store subframe data for odd-numbered rows, and RAMB is used to store subframe data for even-numbered rows.
[0094] Furthermore, the step of storing the subframe data after integration processing by the infrared detector into different storage areas of the register according to odd-numbered rows and even-numbered rows specifically includes:
[0095] The write enable interface ena_1 of the RAMA memory area is used to receive the line valid signal lval_in for subframe data.
[0096] The write data interface dina_1 of the RAMA storage area is used to receive the data signal dina_in of subframe data;
[0097] The write enable interface ena_2 of the RAMB memory area is used to receive the line valid signal lval_in for subframe data.
[0098] The write data interface dina_2 of the RAMA storage area is used to receive the data signal dina_in of subframe data;
[0099] The subframe type determination signal `img_even` is used to determine the direction of data flow.
[0100] When the subframe type determination signal img_even is 0, the data flows to the RAMA storage area;
[0101] When the subframe type determination signal img_even is 1, the data flows to the RAMB storage area.
[0102] Furthermore, the step of storing the subframe data after integration processing by the infrared detector into different storage areas of the register according to odd-numbered rows and even-numbered rows specifically includes:
[0103] The frame validity signal fval_in for subframe data is used to determine whether an address reset is needed.
[0104] When the frame valid signal fval_in is 0, the write address signal addra is reset to zero.
[0105] When the frame valid signal fval_in is 1, it is determined whether the size of the write address signal addra is less than the maximum address RAM_addr of the set RAM register;
[0106] Furthermore, determining whether the size of the write address signal addra is less than the maximum address RAM_addr of the set RAM register includes:
[0107] If the write address signal addra is not less than the maximum address RAM_addr, then the write address signal addra is reset to zero.
[0108] If the write address signal addra is less than the maximum address RAM_addr, then check if the write enable signal ena is 1.
[0109] Furthermore, determining whether the write enable signal ena is 1 includes:
[0110] If the write enable signal ena is 1, then the write address signal addra is incremented;
[0111] If the write enable signal ena is 0, the write address signal addra remains unchanged.
[0112] Furthermore, when storing subframe data line by line in the second storage area, the processor chip retrieves the subframe data already stored in the second storage area and the corresponding subframe data in the first storage area to perform image sorting and temporal reassembly to obtain image data for the corresponding number of lines, which also includes:
[0113] The address signal addrb_1 is connected to the RAMA address interface, and the signal doub_1 is connected to the RAMA data interface.
[0114] The address signal addrb_2 is connected to the RAMB address interface, and the signal doutb_2 is connected to the RAMB register data interface.
[0115] The RAM_addr signal is the address size set in the RAM register;
[0116] When the output frame valid signal fval_out_f1 is 0 (invalid), the address signals addrb_1 and addrb_2 will be reset to zero.
[0117] When the output frame valid signal fval_out_f1 is valid, check whether the RAMA memory area address signal addrb_1 is greater than the signal RAM_addr, and check whether the RAMB memory area address signal addrb_2 is greater than the signal RAM_addr.
[0118] If address signal addrb_1 is greater than signal RAM_addr or address signal addrb_2 is greater than signal RAM_addr, then signal RAM_addr is reset to zero;
[0119] If the address signal addrb_1 is less than the signal RAM_addr and the address signal addrb_2 is less than the signal RAM_addr, then the row valid signal lval_out_f1 is judged.
[0120] If the row valid signal lval_out_f1 is 0, the address signal addrb_1 remains unchanged, and the address signal addrb_2 remains unchanged.
[0121] If the row valid signal lval_out_f1 is 1, then the signal ram_cnt is checked;
[0122] If the signal ram_cnt is 1, the address signal addrb_1 remains unchanged, and the address signal addrb_2 is incremented by 1.
[0123] If the signal ram_cnt is 0, the address signal addrb_1 is incremented by 1, while the address signal addrb_2 remains unchanged.
[0124] When odd-numbered frames begin to be output, the images are sorted and reassembled.
[0125] Secondly, an infrared detector-driven imaging system based on the Interlance & Binning mode, the system comprising: a detector integration module, RAM, and a sorting and reorganization module;
[0126] The detector integration module is used to integrate the infrared signals acquired by the infrared detector to form subframe data;
[0127] The RAM is internally divided into RAMA and RAMB storage areas. RAMA is used to store subframe data in odd-numbered rows, while RAMB is used to store subframe data in even-numbered rows.
[0128] The sorting and reorganization module is used to extract subframe data from RAM and perform image sorting and temporal reorganization to obtain image data.
[0129] Thirdly, an infrared detector is provided, wherein the infrared detector is equipped with a processor, and the processor processes and displays infrared signals using the method described in the first aspect.
[0130] Fourthly, an electronic device mounted on an infrared detector, the device including a processor and a memory electrically connected to the processor, the memory for storing a computer program, the processor for calling the computer program to perform the following steps:
[0131] The subframe data after integration processing by the infrared detector is stored in different storage areas of the register according to odd rows and even rows. The storage area that stores all odd rows or even rows first is called the first storage area, and the other storage area is called the second storage area.
[0132] When storing subframe data line by line in the second storage area, the processor chip retrieves the subframe data already stored in the second memory and the corresponding subframe data in the first storage area to perform image sorting and temporal reassembly, thereby obtaining image data for the corresponding number of lines.
[0133] After the second memory area stores all the subframe data, the processor chip sequentially sorts and reassembles the image data and timing of all the subframe data in the second memory area with the corresponding subframe data in the first memory area, thus obtaining all the image data.
[0134] Fifthly, a calculator program, the computer program product being used to perform the following steps:
[0135] The subframe data after integration processing by the infrared detector is stored in different storage areas of the register according to odd rows and even rows. The storage area that stores all odd rows or even rows first is called the first storage area, and the other storage area is called the second storage area.
[0136] When storing subframe data line by line in the second storage area, the processor chip retrieves the subframe data already stored in the second memory and the corresponding subframe data in the first storage area to perform image sorting and temporal reassembly, thereby obtaining image data for the corresponding number of lines.
[0137] After the second memory area stores all the subframe data, the processor chip sequentially sorts and reassembles the image data and timing of all the subframe data in the second memory area with the corresponding subframe data in the first memory area, thus obtaining all the image data.
[0138] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for general illustrative purposes only and should not be construed as limiting. In some embodiments, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of the invention as set forth by the appended claims.
Claims
1. An infrared detector-driven imaging method based on the Interlance & Binning mode, characterized in that, The method is applied to a processor chip equipped with registers, and the method includes: The subframe data after integration processing by the infrared detector is stored in different storage areas of the register according to odd rows and even rows. The storage area that stores all odd rows or even rows first is called the first storage area, and the other storage area is called the second storage area. When storing subframe data line by line in the second storage area, the processor chip retrieves the subframe data that has already been stored in the second storage area and the corresponding subframe data in the first storage area to perform image sorting and temporal reassembly to obtain the image data of the corresponding number of lines; After the second storage area stores all the subframe data, the processor chip performs image sorting and timing reassembly of all the subframe data in the second storage area and the corresponding subframe data in the first storage area line by line to obtain all the image data.
2. The infrared detector-driven imaging method based on the Interlance & Binning mode as described in claim 1, characterized in that, The register is specifically: The register is a RAM register, divided into RAMA and RAMB storage areas. RAMA is used to store subframe data for odd-numbered rows, and RAMB is used to store subframe data for even-numbered rows.
3. The infrared detector-driven imaging method based on the Interlance & Binning mode as described in claim 2, characterized in that, The step of storing the subframe data after integration processing by the infrared detector into different storage areas of the register according to odd-numbered rows and even-numbered rows specifically includes: The write enable interface ena_1 of the RAMA memory area is used to receive the line valid signal lval_in for subframe data. The write data interface dina_1 of the RAMA storage area is used to receive the data signal dina_in of subframe data; The write enable interface ena_2 of the RAMB memory area is used to receive the line valid signal lval_in for subframe data. The write data interface dina_2 of the RAMB storage area is used to receive the data signal dina_in of subframe data; The subframe type determination signal `img_even` is used to determine the direction of data flow. When the subframe type determination signal img_even is 0, the data flows to the RAMA storage area; When the subframe type determination signal img_even is 1, the data flows to the RAMB storage area.
4. The infrared detector-driven imaging method based on the Interlance & Binning mode as described in claim 3, characterized in that, The step of storing the subframe data after integration processing by the infrared detector into different storage areas of the register according to odd-numbered rows and even-numbered rows specifically includes: The frame validity signal fval_in for subframe data is used to determine whether an address reset is needed. When the frame valid signal fval_in is 0, the write address signal addra is reset to zero. When the frame valid signal fval_in is 1, it is determined whether the size of the write address signal addra is less than the maximum address RAM_addr of the set RAM register; If the write address signal addra is not less than the maximum address RAM_addr, then the write address signal addra is reset to zero. If the write address signal addra is less than the maximum address RAM_addr, then check if the write enable signal ena is 1; If the write enable signal ena is 1, then the write address signal addra is incremented; If the write enable signal ena is 0, the write address signal addra remains unchanged.
5. The infrared detector-driven imaging method based on the Interlance & Binning mode as described in claim 4, characterized in that, When storing subframe data line by line in the second storage area, the processor chip retrieves the subframe data already stored in the second storage area and the corresponding subframe data in the first storage area to perform image sorting and temporal reassembly, obtaining image data for the corresponding number of lines, including: When the subframe type determination signal ram_cnt is 1, read the odd number of rows of data from the RAMB storage area; When the subframe type determination signal ram_cnt is 0, read the odd number of rows of data from the RAMA storage area; When the signal Fval_out is 0, the subframe type determination signal ram_cnt is reset to zero. When the signal Fval_out is 0, determine the rising edge of the signal lval_out; When the rising edge of the lval_out signal is detected, the subframe type determination signal ram_cnt is incremented by 1. When no rising edge of the lval_out signal is detected, the subframe type determination signal ram_cnt remains unchanged.
6. The infrared detector-driven imaging method based on the Interlance & Binning mode as described in claim 5, characterized in that, When storing subframe data line by line in the second storage area, the processor chip retrieves the subframe data already stored in the second storage area and the corresponding subframe data in the first storage area to perform image sorting and temporal reassembly to obtain image data for the corresponding number of lines. This also includes: The address signal addrb_1 is connected to the RAMA address interface, and the signal doub_1 is connected to the RAMA data interface. The address signal addrb_2 is connected to the RAMB address interface, and the signal doutb_2 is connected to the RAMB register data interface. The RAM_addr signal is the address size set in the RAM register; When the output frame valid signal fval_out_f1 is 0 (invalid), the address signals addrb_1 and addrb_2 will be reset to zero. When the output frame valid signal fval_out_f1 is valid, check whether the RAMA memory area address signal addrb_1 is greater than the signal RAM_addr, and check whether the RAMB memory area address signal addrb_2 is greater than the signal RAM_addr. If address signal addrb_1 is greater than signal RAM_addr or address signal addrb_2 is greater than signal RAM_addr, then signal RAM_addr is reset to zero; If the address signal addrb_1 is less than the signal RAM_addr and the address signal addrb_2 is less than the signal RAM_addr, then the row valid signal lval_out_f1 is judged. If the row valid signal lval_out_f1 is 0, the address signal addrb_1 remains unchanged, and the address signal addrb_2 remains unchanged. If the row valid signal lval_out_f1 is 1, then the signal ram_cnt is checked; If the signal ram_cnt is 1, the address signal addrb_1 remains unchanged, and the address signal addrb_2 is incremented by 1. If the signal ram_cnt is 0, the address signal addrb_1 is incremented by 1, while the address signal addrb_2 remains unchanged. When odd-numbered frames begin to be output, the images are sorted and reassembled.
7. An infrared detector-driven imaging system based on the Interlance & Binning mode, characterized in that, The system is used to perform the method as described in claim 1, and the system includes: a detector integration module, RAM, and a sorting and reorganization module; The detector integration module is used to integrate the infrared signals acquired by the infrared detector to form subframe data; The RAM is internally divided into RAMA and RAMB storage areas. RAMA is used to store subframe data in odd-numbered rows, while RAMB is used to store subframe data in even-numbered rows. The sorting and reorganization module is used to extract subframe data from RAM and perform image sorting and temporal reorganization to obtain image data.
8. An infrared detector, characterized in that, The infrared detector is equipped with a processor, which processes and displays the infrared signal using the method described in claim 1.
9. An electronic device, characterized in that, The device, mounted on an infrared detector, includes a processor and a memory electrically connected to the processor. The memory stores a computer program, and the processor invokes the computer program to perform the following steps: The subframe data after integration processing by the infrared detector is stored in different storage areas of the register according to odd rows and even rows. The storage area that stores all odd rows or even rows first is called the first storage area, and the other storage area is called the second storage area. When storing subframe data line by line in the second storage area, the processor chip retrieves the subframe data already stored in the second memory and the corresponding subframe data in the first storage area to perform image sorting and temporal reassembly, thereby obtaining image data for the corresponding number of lines. After the second memory area stores all the subframe data, the processor chip sequentially sorts and reassembles the image data and timing of all the subframe data in the second memory area with the corresponding subframe data in the first memory area, thus obtaining all the image data.
10. A calculator program, characterized in that, The computer program product is used to perform the following steps: The subframe data after integration processing by the infrared detector is stored in different storage areas of the register according to odd rows and even rows. The storage area that stores all odd rows or even rows first is called the first storage area, and the other storage area is called the second storage area. When storing subframe data line by line in the second storage area, the processor chip retrieves the subframe data already stored in the second memory and the corresponding subframe data in the first storage area to perform image sorting and temporal reassembly, thereby obtaining image data for the corresponding number of lines. After the second memory area stores all the subframe data, the processor chip sequentially sorts and reassembles the image data and timing of all the subframe data in the second memory area with the corresponding subframe data in the first memory area, thus obtaining all the image data.