Line-level low-power-consumption high-precision Sigma Delta ADC (Analog to Digital Converter) circuit applied to CIS (Contact Image Sensor) and control method
By using a Sigma Delta modulator with a third-order CIFF structure and an inter-stage sharing strategy, the contradiction between high precision and low power consumption in CMOS image sensors is resolved, the design difficulty of column-level ADCs is reduced, and a balance between high precision and low power consumption is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIAN UNIV OF TECH
- Filing Date
- 2025-12-30
- Publication Date
- 2026-04-21
AI Technical Summary
Existing high-order Sigma Delta ADCs are difficult to simultaneously achieve high precision and low power consumption in CMOS image sensors, resulting in excessively large layout area for column-level ADCs and high design difficulty.
The Sigma Delta modulator employs a third-order CIFF structure, combining an integrator, digital-to-analog converter, feedforward adder, and quantizer in a 1-2-1 architecture. Through an inter-stage sharing strategy, the first and third stage switched-capacitor integrators operate alternately between two columns, and the second stage switched-capacitor integrator is split into two groups to reduce signal crosstalk.
It achieves the high precision and low power consumption requirements of column-level ADCs in CMOS image sensors and reduces the design difficulty of high-order Sigma Delta ADC layout.
Smart Images
Figure CN121908157A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of analog integrated circuit image sensor technology, specifically relating to a column-level low-power, high-precision Sigma Delta ADC circuit applied to CIS. This invention also relates to a control method for the column-level low-power, high-precision Sigma Delta ADC circuit applied to CIS. Background Technology
[0002] With the rapid development of the consumer electronics field, higher requirements have been placed on the imaging quality of CMOS image sensors. CMOS image sensors need to further develop their column-level readout circuits towards higher absolute accuracy, lower power consumption, and faster conversion speed.
[0003] As the core of the readout circuit, the ADC's performance determines the overall imaging quality of the CMOS image sensor. SigmaDelta ADCs, with their oversampling and noise shaping techniques, can achieve ultra-high quantization accuracy. Incremental Sigma Delta ADCs (IADCs) are particularly well-suited for DC measurements in CMOS image sensors. When quantization accuracy and conversion speed are simultaneously adapted to the low-noise, high-frame-rate requirements of CMOS image sensors, it is unavoidable to increase the order of the Sigma Delta modulator. This inevitably leads to additional power consumption. Furthermore, higher-order Sigma Delta modulators incur significant hardware overhead, resulting in excessively large layout areas for column-level ADCs. Therefore, high-order Sigma Delta ADCs are difficult to implement in column-level readout circuits with strict power consumption and column width limitations. Summary of the Invention
[0004] The purpose of this invention is to provide a column-level low-power, high-precision Sigma Delta ADC circuit for CIS, which solves the problem that existing high-order Sigma Delta ADCs cannot simultaneously meet the high precision and low power consumption requirements of CMOS image sensors for column-level ADCs, and greatly reduces the design difficulty of column-level high-order Sigma Delta ADC layout.
[0005] Another objective of this invention is to provide a control method for a column-level low-power, high-precision Sigma Delta ADC circuit applied to CIS.
[0006] The first technical solution adopted in this invention is a column-level low-power high-precision Sigma Delta ADC circuit applied to CIS, including a third-order CIFF structure Sigma Delta modulator. The input terminal of the third-order CIFF structure Sigma Delta modulator is connected to the output signal of two columns of pixel units, and the output terminal of the third-order CIFF structure Sigma Delta modulator is connected to a digital filter. The output of the digital filter module is the final quantization result Dout1 and Dout2 of the ADC.
[0007] The first technical solution of the present invention is further characterized in that, The third-order CIFF Sigma Delta modulator uses a 1-2-1 architecture consisting of an integrator, a digital-to-analog converter (DAC), a feedforward adder, and a quantizer. The three-stage integrator is structured as follows: the first stage is a set of switched-capacitor integrators; the second stage consists of two sets of switched-capacitor integrators (2-1 and 2-2); and the third stage is also a set of switched-capacitor integrators. The non-inverting output VOP1 of the first-stage integrator is connected to the inputs of sampling switches S21 and S23 in the second-stage integrator 2-1 and 2-2, respectively. VOP1 is also connected to the inputs of feedforward adders A and B. The inverting output VON1 of the first-stage integrator is connected to the inputs of sampling switches S22 and S24 in the second-stage integrator 2-1 and 2-2, respectively. VON1 is also connected to the inputs of feedforward adders A and B. The second-stage integrator 2... The non-inverting output VOP2 of the second-stage integrator 2-2 is connected to the input of sampling switch S37 in the third-stage integrator. VOP2 is also connected to the input of feedforward adder A. The inverting output VON2 is connected to the input of sampling switch S38. VON2 is also connected to the input of feedforward adder A. The non-inverting output VOP3 of the second-stage integrator 2-2 is connected to the input of sampling switch S39 in the third-stage integrator. VOP3 is also connected to the input of feedforward adder B. The inverting output terminal VON3 is connected to the input terminal of sampling switch S40. Output terminal VON3 is also connected to the input terminal of feedforward adder B. The non-inverting input terminal VOP4 of the third-stage switched-capacitor integrator is connected to the input terminals of feedforward adders A and B. The inverting input terminal VON4 is also connected to the input terminals of feedforward adders A and B. The output of feedforward adder A is connected to the input of quantizer A. The output of quantizer A is connected to the input of digital filter A. It is also connected to the control signal terminal Q of digital-to-analog converters DAC1 and DAC2. A The output of feedforward adder B is connected to the input of quantizer B, the output of quantizer B is connected to the input of digital filter B, and it is also connected to the control signal terminal Q of digital-to-analog converters DAC3 and DAC4. B .
[0008] The first-stage switched-capacitor integrator includes 20 CMOS switches S1~S20, 4 sampling capacitors Cs1~Cs4, 4 integrating capacitors Ci1~Ci4, and 1 operational amplifier OTA1. The pixel output signal is connected to the input terminals of switches S1~S4 respectively. The output terminal of switch S1 is connected to the upper stage board of sampling capacitor Cs1. The upper stage board of sampling capacitor Cs1 is also connected to the output terminal of switch S5. The input terminal of switch S5 is connected to the output of digital-to-analog converter DAC1. The lower stage board of sampling capacitor Cs1 is connected to the output terminal of switch S9 and the input terminal of switch S13. The input terminal of switch S9 is connected to the common-mode voltage Vcm. The output terminal of switch S13 is connected to the inverting input terminal of operational amplifier OTA1 and the upper stage board of integrating capacitor Ci1. The lower stage board of integrating capacitor Ci1 is connected to the input terminal of switch S17. The output terminal of switch S17 is connected to the non-inverting output terminal VOP1 of operational amplifier OTA1.
[0009] The output of switch S2 is connected to the upper stage board of sampling capacitor Cs2. The upper stage board of sampling capacitor Cs2 is also connected to the output of switch S6. The input of switch S6 is connected to the output of digital-to-analog converter DAC2. The lower stage board of sampling capacitor Cs2 is connected to the output of switch S10 and the input of switch S14. The input of switch S10 is connected to the common-mode voltage Vcm. The output of switch S14 is connected to the non-inverting input of op-amp OTA1 and the upper stage board of integrating capacitor Ci2. The lower stage board of integrating capacitor Ci2 is connected to the input of switch S18. The output of switch S18 is connected to the inverting output VON1 of op-amp OTA1.
[0010] The branch containing switch S3 has the same structure as the branch containing switch S1, and the branch containing switch S4 has the same structure as the branch containing switch S2.
[0011] The second-stage integrator consists of switched-capacitor integrator 2-1 and switched-capacitor integrator 2-2, comprising 16 CMOS switches S21~S36, 4 sampling capacitors Cs5~Cs8, 4 integrating capacitors Ci5~Ci8, and two operational amplifiers OTA2 and OTA3. The input of switch S21 is connected to the non-inverting output VOP1 of operational amplifier OTA1. The output of switch S21 is connected to the upper stage board of sampling capacitor Cs5. The upper stage board of sampling capacitor Cs5 is also connected to the output of switch S25. The input of switch S25 is connected to the common-mode voltage Vcm. The lower stage board of sampling capacitor Cs5 is connected to the output of switch S29 and the input of switch S33. The input of switch S29 is connected to the common-mode voltage Vcm. The output of switch S33 is connected to the inverting input of operational amplifier OTA2 and the upper stage board of integrating capacitor Ci5. The lower stage board of integrating capacitor Ci5 is connected to the non-inverting output VOP2 of operational amplifier OTA2.
[0012] The input of switch S22 is connected to the inverting output VON1 of op-amp OTA1. The output of switch S22 is connected to the upper stage board of sampling capacitor Cs6. The upper stage board of sampling capacitor Cs6 is also connected to the output of switch S26. The input of switch S26 is connected to the common-mode voltage Vcm. The lower stage board of sampling capacitor Cs6 is connected to the output of switch S30 and the input of switch S34. The input of switch S30 is connected to the common-mode voltage Vcm. The output of switch S34 is connected to the non-inverting input of op-amp OTA2 and the upper stage board of integrating capacitor Ci6. The lower stage board of integrating capacitor Ci6 is connected to the inverting output VON2 of op-amp OTA2.
[0013] Switched capacitor integrator 2-2 has the same structure as switched capacitor integrator 2-1; The third-stage switched-capacitor integrator has the same structure as the first-stage switched-capacitor integrator, except that the DAC module in the first-stage switched-capacitor integrator is replaced with the common-mode voltage Vcm. The outputs VOP1, VON1, VOP2, VON2, VOP4, and VON4 of the switched capacitor integrator are connected to the input of the feedforward adder A. The output of the feedforward adder A is connected to the input of the quantizer A. The output of the quantizer A is connected to the input of the digital filter A. The digital filter A outputs the final quantization result Dout1. The outputs VOP1, VON1, VOP3, VON3, VOP4, and VON4 of the switched capacitor integrator are connected to the input of the feedforward adder B. The output of the feedforward adder B is connected to the input of the quantizer B. The output of the quantizer B is connected to the input of the digital filter B. The digital filter B outputs the final quantization result Dout2.
[0014] The second technical solution adopted in this invention is a control method for a column-level low-power, high-precision Sigma Delta ADC circuit applied to CIS. Based on the column-level low-power, high-precision Sigma Delta ADC circuit applied to CIS, it is implemented according to the following steps: Step 1: The two-column pixel differential output signals VIP1, VIN1, VIP2, and VIN2 are respectively input to the input terminals of the four sampling switches S1 to S4; Step 2: The modulator operates under the control of four clocks.
[0015] The second technical solution of the present invention is further characterized in that, Step 2 is implemented in the following steps: Step 2.1 and For two non-overlapping clocks, and For complementary clocks with delay, in In the working state, for the differential output signals VIP1 and VIN1 of the first column of pixels, the three-stage switched capacitor integrator is in the sampling-integration-sampling working state, with the second-stage switched capacitor integrator 2-1 in the integration state and storing the output result of the switched capacitor integrator 2-1 at this time; for the differential output signals VIP2 and VIN2 of the second column of pixels, the three-stage switched capacitor integrator is in the integration-sampling-integration working state, with the second-stage switched capacitor integrator 2-2 in the sampling state; Step 2.2 In the working state, the output results VOP1, VON1, VOP3, VON3, VOP4, and VON4 of the switched capacitor integrator are input into the feedforward adder B. The output of the feedforward adder B is connected to the quantizer B. The output of the quantizer B is used as the control signal for DAC3 and DAC4. At the same time, the output of the quantizer B is used as the input of the digital filter B. Step 2.3, in In the working state, for the differential output signals VIP1 and VIN1 of the first column of pixels, the three-stage switched capacitor integrator is in the working state of integration-sampling-integration, with the second-stage switched capacitor integrator 2-1 in the sampling state; for the differential output signals VIP2 and VIN2 of the second column of pixels, the three-stage switched capacitor integrator is in the working state of sampling-integration-sampling, with the second-stage switched capacitor integrator 2-2 in the integration state, and the output result of the switched capacitor integrator 2-2 at this time is stored. Step 2.4 In the working state, the output results VOP1, VON1, VOP2, VON2, VOP4, and VON4 of the switched capacitor integrator are input into feedforward adder A. The output of feedforward adder A is connected to quantizer A. The output of quantizer A is used as the control signal for DAC1 and DAC2. At the same time, the output of quantizer A is used as the input of digital filter A. Step 2.5, Modulator The output of the modulator in the current state is input into digital filter B, and the output of digital filter B is used as the final quantization result Dout2 of the second column pixel signal. The output of the current state is input into digital filter A, and the output of digital filter A is used as the final quantization result Dout1 of the first column of pixel signals.
[0016] The beneficial effects of this invention are that the column-level low-power, high-precision Sigma Delta ADC circuit applied to CIS, based on an inter-stage sharing strategy, enables the first-stage switched-capacitor integrator and the third-stage switched-capacitor integrator to work alternately between the two columns, and splits the second-stage switched-capacitor integrator into two groups. This satisfies the feedforward summation of the output results of each stage integrator in the third-order CIFF structure, while reducing signal crosstalk between the two columns. This solves the problem that high-order Sigma Delta ADCs are difficult to simultaneously meet the high-precision and low-power requirements of CMOS image sensors for column-level ADCs, and greatly reduces the design difficulty of the column-level high-order Sigma Delta ADC layout. Attached Figure Description
[0017] Figure 1 A schematic diagram of a column-level low-power, high-precision Sigma Delta ADC structure for use in CMOS image sensors; Figure 2 This is the timing diagram of the low-power, high-precision Sigma Delta ADC of the present invention; Figure 3 This is a schematic diagram of the switched capacitor integrator using a 1-2-1 architecture in this invention. Figure 4 The circuit diagram of the Sigma Delta ADC with a third-order CIFF structure is shown. Detailed Implementation
[0018] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.
[0019] This invention applies to a column-level low-power, high-precision Sigma Delta ADC circuit for CIS, with the structure as follows: Figure 1 As shown, it includes a third-order CIFF structure Sigma Delta modulator. The input of the third-order CIFF structure Sigma Delta modulator is connected to the output signals of two columns of pixel units. The output of the third-order CIFF structure Sigma Delta modulator is connected to a digital filter. The output of the digital filter module is the final quantization result Dout1 and Dout2 of the ADC.
[0020] The third-order CIFF Sigma Delta modulator uses a 1-2-1 architecture consisting of an integrator, a digital-to-analog converter (DAC), a feedforward adder, and a quantizer. The three-stage integrator is structured as follows: the first stage is a set of switched-capacitor integrators; the second stage consists of two sets of switched-capacitor integrators (2-1 and 2-2); and the third stage is also a set of switched-capacitor integrators. The non-inverting output VOP1 of the first-stage integrator is connected to the inputs of sampling switches S21 and S23 in the second-stage integrator 2-1 and 2-2, respectively. VOP1 is also connected to the inputs of feedforward adders A and B. The inverting output VON1 of the first-stage integrator is connected to the inputs of sampling switches S22 and S24 in the second-stage integrator 2-1 and 2-2, respectively. VON1 is also connected to the inputs of feedforward adders A and B. The second-stage integrator 2... The non-inverting output VOP2 of the second-stage integrator 2-2 is connected to the input of sampling switch S37 in the third-stage integrator. VOP2 is also connected to the input of feedforward adder A. The inverting output VON2 is connected to the input of sampling switch S38. VON2 is also connected to the input of feedforward adder A. The non-inverting output VOP3 of the second-stage integrator 2-2 is connected to the input of sampling switch S39 in the third-stage integrator. VOP3 is also connected to the input of feedforward adder B. The inverting output terminal VON3 is connected to the input terminal of sampling switch S40. Output terminal VON3 is also connected to the input terminal of feedforward adder B. The non-inverting input terminal VOP4 of the third-stage switched-capacitor integrator is connected to the input terminals of feedforward adders A and B. The inverting input terminal VON4 is also connected to the input terminals of feedforward adders A and B. The output of feedforward adder A is connected to the input of quantizer A. The output of quantizer A is connected to the input of digital filter A. It is also connected to the control signal terminal Q of digital-to-analog converters DAC1 and DAC2. A The output of feedforward adder B is connected to the input of quantizer B, the output of quantizer B is connected to the input of digital filter B, and it is also connected to the control signal terminal Q of digital-to-analog converters DAC3 and DAC4. B .
[0021] The first-stage switched-capacitor integrator includes 20 CMOS switches S1~S20, 4 sampling capacitors Cs1~Cs4, 4 integrating capacitors Ci1~Ci4, and 1 operational amplifier OTA1. The pixel output signal is connected to the input terminals of switches S1~S4 respectively. The output terminal of switch S1 is connected to the upper stage board of sampling capacitor Cs1. The upper stage board of sampling capacitor Cs1 is also connected to the output terminal of switch S5. The input terminal of switch S5 is connected to the output of digital-to-analog converter DAC1. The lower stage board of sampling capacitor Cs1 is connected to the output terminal of switch S9 and the input terminal of switch S13. The input terminal of switch S9 is connected to the common-mode voltage Vcm. The output terminal of switch S13 is connected to the inverting input terminal of operational amplifier OTA1 and the upper stage board of integrating capacitor Ci1. The lower stage board of integrating capacitor Ci1 is connected to the input terminal of switch S17. The output terminal of switch S17 is connected to the non-inverting output terminal VOP1 of operational amplifier OTA1.
[0022] The output of switch S2 is connected to the upper stage board of sampling capacitor Cs2. The upper stage board of sampling capacitor Cs2 is also connected to the output of switch S6. The input of switch S6 is connected to the output of digital-to-analog converter DAC2. The lower stage board of sampling capacitor Cs2 is connected to the output of switch S10 and the input of switch S14. The input of switch S10 is connected to the common-mode voltage Vcm. The output of switch S14 is connected to the non-inverting input of op-amp OTA1 and the upper stage board of integrating capacitor Ci2. The lower stage board of integrating capacitor Ci2 is connected to the input of switch S18. The output of switch S18 is connected to the inverting output VON1 of op-amp OTA1.
[0023] The branch containing switch S3 has the same structure as the branch containing switch S1, and the branch containing switch S4 has the same structure as the branch containing switch S2.
[0024] The second-stage integrator consists of switched-capacitor integrator 2-1 and switched-capacitor integrator 2-2, comprising 16 CMOS switches S21~S36, 4 sampling capacitors Cs5~Cs8, 4 integrating capacitors Ci5~Ci8, and two operational amplifiers OTA2 and OTA3. The input of switch S21 is connected to the non-inverting output VOP1 of operational amplifier OTA1. The output of switch S21 is connected to the upper stage board of sampling capacitor Cs5. The upper stage board of sampling capacitor Cs5 is also connected to the output of switch S25. The input of switch S25 is connected to the common-mode voltage Vcm. The lower stage board of sampling capacitor Cs5 is connected to the output of switch S29 and the input of switch S33. The input of switch S29 is connected to the common-mode voltage Vcm. The output of switch S33 is connected to the inverting input of operational amplifier OTA2 and the upper stage board of integrating capacitor Ci5. The lower stage board of integrating capacitor Ci5 is connected to the non-inverting output VOP2 of operational amplifier OTA2.
[0025] The input of switch S22 is connected to the inverting output VON1 of op-amp OTA1. The output of switch S22 is connected to the upper stage board of sampling capacitor Cs6. The upper stage board of sampling capacitor Cs6 is also connected to the output of switch S26. The input of switch S26 is connected to the common-mode voltage Vcm. The lower stage board of sampling capacitor Cs6 is connected to the output of switch S30 and the input of switch S34. The input of switch S30 is connected to the common-mode voltage Vcm. The output of switch S34 is connected to the non-inverting input of op-amp OTA2 and the upper stage board of integrating capacitor Ci6. The lower stage board of integrating capacitor Ci6 is connected to the inverting output VON2 of op-amp OTA2.
[0026] Switched capacitor integrator 2-2 has the same structure as switched capacitor integrator 2-1; The third-stage switched-capacitor integrator has the same structure as the first-stage switched-capacitor integrator, except that the DAC module in the first-stage switched-capacitor integrator is replaced with the common-mode voltage Vcm. The outputs VOP1, VON1, VOP2, VON2, VOP4, and VON4 of the switched capacitor integrator are connected to the input of the feedforward adder A. The output of the feedforward adder A is connected to the input of the quantizer A. The output of the quantizer A is connected to the input of the digital filter A. The digital filter A outputs the final quantization result Dout1. The outputs VOP1, VON1, VOP3, VON3, VOP4, and VON4 of the switched capacitor integrator are connected to the input of the feedforward adder B. The output of the feedforward adder B is connected to the input of the quantizer B. The output of the quantizer B is connected to the input of the digital filter B. The digital filter B outputs the final quantization result Dout2.
[0027] Example 1 This invention discloses a column-level low-power, high-precision Sigma Delta ADC for use in CMOS image sensors, such as... Figure 1 As shown, it includes a third-order CIFF structure Sigma Delta modulator. The input of the third-order CIFF structure Sigma Delta modulator is connected to the output signals of two columns of pixel units. The output of the third-order CIFF structure Sigma Delta modulator is connected to digital filter A and digital filter B. The outputs of digital filter A and digital filter B are used as the final quantization result of the output signals of the two columns of pixel units ADC.
[0028] Example 2 The overall third-order CIFF Sigma Delta modulator consists of a 1-2-1 architecture comprising a switched-capacitor integrator, a DAC, a feedforward adder, and a 1-bit quantizer. The second-stage integrator comprises two sets of switched-capacitor integrators, while the first and third-stage switched-capacitor integrators are based on an inter-stage sharing strategy. Figure 2 and Figure 3 As shown, after the reset signal resets the modulator and digital filter, in When the signal is high, for the differential output signals VIP1 and VIN1 of the first column of pixels, the three-stage switched capacitor integrator is in the sampling-integration-sampling state and stores the output result of the switched capacitor integrator 2-1 at this time; for the differential output signals VIP2 and VIN2 of the second column of pixels, the three-stage switched capacitor integrator is in the integration-sampling-integration state, of which the second-stage switched capacitor integrator 2-2 is in the sampling state.
[0029] Simultaneously, the outputs VOP1, VON1, VOP3, VON3, VOP4, and VON4 of the switched capacitor integrator are input into feedforward adder B. The output of feedforward adder B is connected to quantizer B. The output of quantizer B serves as the control signal for DAC3 and DAC4. At the same time, the output of quantizer B serves as the input to digital filter B. When readout signal 1 arrives, digital filter B outputs Dout2.
[0030] exist When the signal is high, for the differential output signals VIP1 and VIN1 of the first column of pixels, the three-stage switched-capacitor integrator operates in an integration-sampling-integration state, with the second-stage switched-capacitor integrator 2-1 in sampling mode. For the differential output signals VIP2 and VIN2 of the second column of pixels, the three-stage switched-capacitor integrator operates in a sampling-integration-sampling state, with the second-stage switched-capacitor integrator 2-2 in integration mode, and its output is stored. The outputs VOP1, VON1, VOP2, VON2, VOP4, and VON4 of the switched-capacitor integrator are input to feedforward adder A. The output of feedforward adder A is connected to quantizer A, and the output of quantizer A serves as the control signal for DAC1 and DAC2. Simultaneously, the output of quantizer A serves as the input to digital filter A. When readout signal 2 arrives, digital filter A outputs Dout1.
[0031] Once the readout signal 2 ends, the reset signal arrives, and the next quantization cycle begins.
[0032] Example 3 The equivalent circuits of the third-order CIFF Sigma Delta ADC with the 1-2-1 architecture of this invention under different operating states are as follows: Figure 4 As shown, in In operation, the first-stage switched-capacitor integrator samples the differential input signals VIP1 and VIN1, and simultaneously integrates the differential signals VIP2 and VIN2 sampled in the previous cycle. The second-stage switched-capacitor integrator 2-2 samples the output of the first-stage integrator, and the second-stage switched-capacitor integrator 2-1 integrates the differential output signals VOP1 and VON1 sampled in the previous cycle from the first-stage switched-capacitor integrator. The third-stage switched-capacitor integrator samples the differential output signals VOP2 and VON2 from the second-stage switched-capacitor integrator 2-1, and integrates the differential output signals VOP3 and VON3 from the second-stage switched-capacitor integrator 2-2 in the previous cycle. Since the second-stage switched-capacitor integrator 2-2 can store the integration result from the previous cycle... In operation, feedforward adder B adds the outputs VOP1, VON1, VOP4, and VON4 of the switched-capacitor integrator, along with the integration results VOP3 and VON3 stored in the second-stage switched-capacitor integrator 2-2 from the previous cycle. The result is then input to quantizer B, which serves as both the control signal for DAC3 and DAC4 and the input to digital filter B. One signal modulation is completed within half a clock cycle.
[0033] Example 4 This invention applies to a column-level low-power, high-precision Sigma Delta ADC circuit for CIS, with the structure as follows: Figure 1 As shown, it includes a third-order CIFF structure Sigma Delta modulator. The input of the third-order CIFF structure Sigma Delta modulator is connected to the output signals of two columns of pixel units. The output of the third-order CIFF structure Sigma Delta modulator is connected to a digital filter. The output of the digital filter module is the final quantization result Dout1 and Dout2 of the ADC.
[0034] The third-order CIFF Sigma Delta modulator uses a 1-2-1 architecture consisting of an integrator, a digital-to-analog converter (DAC), a feedforward adder, and a quantizer. The three-stage integrator is structured as follows: the first stage is a set of switched-capacitor integrators; the second stage consists of two sets of switched-capacitor integrators (2-1 and 2-2); and the third stage is also a set of switched-capacitor integrators. The non-inverting output VOP1 of the first-stage integrator is connected to the inputs of sampling switches S21 and S23 in the second-stage integrator 2-1 and 2-2, respectively. VOP1 is also connected to the inputs of feedforward adders A and B. The inverting output VON1 of the first-stage integrator is connected to the inputs of sampling switches S22 and S24 in the second-stage integrator 2-1 and 2-2, respectively. VON1 is also connected to the inputs of feedforward adders A and B. The second-stage integrator 2... The non-inverting output VOP2 of the second-stage integrator 2-2 is connected to the input of sampling switch S37 in the third-stage integrator. VOP2 is also connected to the input of feedforward adder A. The inverting output VON2 is connected to the input of sampling switch S38. VON2 is also connected to the input of feedforward adder A. The non-inverting output VOP3 of the second-stage integrator 2-2 is connected to the input of sampling switch S39 in the third-stage integrator. VOP3 is also connected to the input of feedforward adder B. The inverting output terminal VON3 is connected to the input terminal of sampling switch S40. Output terminal VON3 is also connected to the input terminal of feedforward adder B. The non-inverting input terminal VOP4 of the third-stage switched-capacitor integrator is connected to the input terminals of feedforward adders A and B. The inverting input terminal VON4 is also connected to the input terminals of feedforward adders A and B. The output of feedforward adder A is connected to the input of quantizer A. The output of quantizer A is connected to the input of digital filter A. It is also connected to the control signal terminal Q of digital-to-analog converters DAC1 and DAC2. A The output of feedforward adder B is connected to the input of quantizer B, the output of quantizer B is connected to the input of digital filter B, and it is also connected to the control signal terminal Q of digital-to-analog converters DAC3 and DAC4. B .
[0035] The first-stage switched-capacitor integrator includes 20 CMOS switches S1~S20, 4 sampling capacitors Cs1~Cs4, 4 integrating capacitors Ci1~Ci4, and 1 operational amplifier OTA1. The pixel output signal is connected to the input terminals of switches S1~S4 respectively. The output terminal of switch S1 is connected to the upper stage board of sampling capacitor Cs1. The upper stage board of sampling capacitor Cs1 is also connected to the output terminal of switch S5. The input terminal of switch S5 is connected to the output of digital-to-analog converter DAC1. The lower stage board of sampling capacitor Cs1 is connected to the output terminal of switch S9 and the input terminal of switch S13. The input terminal of switch S9 is connected to the common-mode voltage Vcm. The output terminal of switch S13 is connected to the inverting input terminal of operational amplifier OTA1 and the upper stage board of integrating capacitor Ci1. The lower stage board of integrating capacitor Ci1 is connected to the input terminal of switch S17. The output terminal of switch S17 is connected to the non-inverting output terminal VOP1 of operational amplifier OTA1.
[0036] The output of switch S2 is connected to the upper stage board of sampling capacitor Cs2. The upper stage board of sampling capacitor Cs2 is also connected to the output of switch S6. The input of switch S6 is connected to the output of digital-to-analog converter DAC2. The lower stage board of sampling capacitor Cs2 is connected to the output of switch S10 and the input of switch S14. The input of switch S10 is connected to the common-mode voltage Vcm. The output of switch S14 is connected to the non-inverting input of op-amp OTA1 and the upper stage board of integrating capacitor Ci2. The lower stage board of integrating capacitor Ci2 is connected to the input of switch S18. The output of switch S18 is connected to the inverting output VON1 of op-amp OTA1.
[0037] The branch containing switch S3 has the same structure as the branch containing switch S1, and the branch containing switch S4 has the same structure as the branch containing switch S2.
[0038] Example 5 This invention applies to a column-level low-power, high-precision Sigma Delta ADC circuit for CIS, with the structure as follows: Figure 1 As shown, it includes a third-order CIFF structure Sigma Delta modulator. The input of the third-order CIFF structure Sigma Delta modulator is connected to the output signals of two columns of pixel units. The output of the third-order CIFF structure Sigma Delta modulator is connected to a digital filter. The output of the digital filter module is the final quantization result Dout1 and Dout2 of the ADC.
[0039] The third-order CIFF Sigma Delta modulator uses a 1-2-1 architecture consisting of an integrator, a digital-to-analog converter (DAC), a feedforward adder, and a quantizer. The three-stage integrator is structured as follows: the first stage is a set of switched-capacitor integrators; the second stage consists of two sets of switched-capacitor integrators (2-1 and 2-2); and the third stage is also a set of switched-capacitor integrators. The non-inverting output VOP1 of the first-stage integrator is connected to the inputs of sampling switches S21 and S23 in the second-stage integrator 2-1 and 2-2, respectively. VOP1 is also connected to the inputs of feedforward adders A and B. The inverting output VON1 of the first-stage integrator is connected to the inputs of sampling switches S22 and S24 in the second-stage integrator 2-1 and 2-2, respectively. VON1 is also connected to the inputs of feedforward adders A and B. The second-stage integrator 2... The non-inverting output VOP2 of the second-stage integrator 2-2 is connected to the input of sampling switch S37 in the third-stage integrator. VOP2 is also connected to the input of feedforward adder A. The inverting output VON2 is connected to the input of sampling switch S38. VON2 is also connected to the input of feedforward adder A. The non-inverting output VOP3 of the second-stage integrator 2-2 is connected to the input of sampling switch S39 in the third-stage integrator. VOP3 is also connected to the input of feedforward adder B. The inverting output terminal VON3 is connected to the input terminal of sampling switch S40. Output terminal VON3 is also connected to the input terminal of feedforward adder B. The non-inverting input terminal VOP4 of the third-stage switched-capacitor integrator is connected to the input terminals of feedforward adders A and B. The inverting input terminal VON4 is also connected to the input terminals of feedforward adders A and B. The output of feedforward adder A is connected to the input of quantizer A. The output of quantizer A is connected to the input of digital filter A. It is also connected to the control signal terminal Q of digital-to-analog converters DAC1 and DAC2. A The output of feedforward adder B is connected to the input of quantizer B, the output of quantizer B is connected to the input of digital filter B, and it is also connected to the control signal terminal Q of digital-to-analog converters DAC3 and DAC4. B .
[0040] The first-stage switched-capacitor integrator includes 20 CMOS switches S1~S20, 4 sampling capacitors Cs1~Cs4, 4 integrating capacitors Ci1~Ci4, and 1 operational amplifier OTA1. The pixel output signal is connected to the input terminals of switches S1~S4 respectively. The output terminal of switch S1 is connected to the upper stage board of sampling capacitor Cs1. The upper stage board of sampling capacitor Cs1 is also connected to the output terminal of switch S5. The input terminal of switch S5 is connected to the output of digital-to-analog converter DAC1. The lower stage board of sampling capacitor Cs1 is connected to the output terminal of switch S9 and the input terminal of switch S13. The input terminal of switch S9 is connected to the common-mode voltage Vcm. The output terminal of switch S13 is connected to the inverting input terminal of operational amplifier OTA1 and the upper stage board of integrating capacitor Ci1. The lower stage board of integrating capacitor Ci1 is connected to the input terminal of switch S17. The output terminal of switch S17 is connected to the non-inverting output terminal VOP1 of operational amplifier OTA1.
[0041] The output of switch S2 is connected to the upper stage board of sampling capacitor Cs2. The upper stage board of sampling capacitor Cs2 is also connected to the output of switch S6. The input of switch S6 is connected to the output of digital-to-analog converter DAC2. The lower stage board of sampling capacitor Cs2 is connected to the output of switch S10 and the input of switch S14. The input of switch S10 is connected to the common-mode voltage Vcm. The output of switch S14 is connected to the non-inverting input of op-amp OTA1 and the upper stage board of integrating capacitor Ci2. The lower stage board of integrating capacitor Ci2 is connected to the input of switch S18. The output of switch S18 is connected to the inverting output VON1 of op-amp OTA1.
[0042] The branch containing switch S3 has the same structure as the branch containing switch S1, and the branch containing switch S4 has the same structure as the branch containing switch S2.
[0043] The second-stage integrator consists of switched-capacitor integrator 2-1 and switched-capacitor integrator 2-2, comprising 16 CMOS switches S21~S36, 4 sampling capacitors Cs5~Cs8, 4 integrating capacitors Ci5~Ci8, and two operational amplifiers OTA2 and OTA3. The input of switch S21 is connected to the non-inverting output VOP1 of operational amplifier OTA1. The output of switch S21 is connected to the upper stage board of sampling capacitor Cs5. The upper stage board of sampling capacitor Cs5 is also connected to the output of switch S25. The input of switch S25 is connected to the common-mode voltage Vcm. The lower stage board of sampling capacitor Cs5 is connected to the output of switch S29 and the input of switch S33. The input of switch S29 is connected to the common-mode voltage Vcm. The output of switch S33 is connected to the inverting input of operational amplifier OTA2 and the upper stage board of integrating capacitor Ci5. The lower stage board of integrating capacitor Ci5 is connected to the non-inverting output VOP2 of operational amplifier OTA2.
[0044] The input of switch S22 is connected to the inverting output VON1 of op-amp OTA1. The output of switch S22 is connected to the upper stage board of sampling capacitor Cs6. The upper stage board of sampling capacitor Cs6 is also connected to the output of switch S26. The input of switch S26 is connected to the common-mode voltage Vcm. The lower stage board of sampling capacitor Cs6 is connected to the output of switch S30 and the input of switch S34. The input of switch S30 is connected to the common-mode voltage Vcm. The output of switch S34 is connected to the non-inverting input of op-amp OTA2 and the upper stage board of integrating capacitor Ci6. The lower stage board of integrating capacitor Ci6 is connected to the inverting output VON2 of op-amp OTA2.
[0045] Switched capacitor integrator 2-2 has the same structure as switched capacitor integrator 2-1; The third-stage switched-capacitor integrator has the same structure as the first-stage switched-capacitor integrator, except that the DAC module in the first-stage switched-capacitor integrator is replaced with the common-mode voltage Vcm. The outputs VOP1, VON1, VOP2, VON2, VOP4, and VON4 of the switched capacitor integrator are connected to the input of the feedforward adder A. The output of the feedforward adder A is connected to the input of the quantizer A. The output of the quantizer A is connected to the input of the digital filter A. The digital filter A outputs the final quantization result Dout1. The outputs VOP1, VON1, VOP3, VON3, VOP4, and VON4 of the switched capacitor integrator are connected to the input of the feedforward adder B. The output of the feedforward adder B is connected to the input of the quantizer B. The output of the quantizer B is connected to the input of the digital filter B. The digital filter B outputs the final quantization result Dout2.
[0046] Example 6 This invention relates to a control method for a column-level low-power, high-precision Sigma Delta ADC circuit applied to CIS. Based on this circuit, the method is characterized by the following steps: Step 1: The two-column pixel differential output signals VIP1, VIN1, VIP2, and VIN2 are respectively input to the input terminals of the four sampling switches S1 to S4; Step 2: The modulator operates under the control of four clocks.
[0047] Step 2 is implemented in the following steps: Step 2.1 and For two non-overlapping clocks, and For complementary clocks with delay, in In the working state, for the differential output signals VIP1 and VIN1 of the first column of pixels, the three-stage switched capacitor integrator is in the sampling-integration-sampling working state, with the second-stage switched capacitor integrator 2-1 in the integration state and storing the output result of the switched capacitor integrator 2-1 at this time; for the differential output signals VIP2 and VIN2 of the second column of pixels, the three-stage switched capacitor integrator is in the integration-sampling-integration working state, with the second-stage switched capacitor integrator 2-2 in the sampling state; Step 2.2 In the working state, the output results VOP1, VON1, VOP3, VON3, VOP4, and VON4 of the switched capacitor integrator are input into the feedforward adder B. The output of the feedforward adder B is connected to the quantizer B. The output of the quantizer B is used as the control signal for DAC3 and DAC4. At the same time, the output of the quantizer B is used as the input of the digital filter B. Step 2.3, in In the working state, for the differential output signals VIP1 and VIN1 of the first column of pixels, the three-stage switched capacitor integrator is in the working state of integration-sampling-integration, with the second-stage switched capacitor integrator 2-1 in the sampling state; for the differential output signals VIP2 and VIN2 of the second column of pixels, the three-stage switched capacitor integrator is in the working state of sampling-integration-sampling, with the second-stage switched capacitor integrator 2-2 in the integration state, and the output result of the switched capacitor integrator 2-2 at this time is stored. Step 2.4 In the working state, the output results VOP1, VON1, VOP2, VON2, VOP4, and VON4 of the switched capacitor integrator are input into feedforward adder A. The output of feedforward adder A is connected to quantizer A. The output of quantizer A is used as the control signal for DAC1 and DAC2. At the same time, the output of quantizer A is used as the input of digital filter A. Step 2.5, Modulator The output of the modulator in the current state is input into digital filter B, and the output of digital filter B is used as the final quantization result Dout2 of the second column pixel signal. The output of the current state is input into digital filter A, and the output of digital filter A is used as the final quantization result Dout1 of the first column of pixel signals.
[0048] This invention applies to column-level low-power, high-precision Sigma Delta ADCs for CMOS image sensors. Based on an inter-stage sharing strategy, it achieves inter-stage sharing between the first and third stage switched-capacitor integrators. Simultaneously, it splits the second-stage switched-capacitor integrator into two groups. This satisfies the requirement of accumulating the outputs of each stage integrator in a third-order CIFF modulator while also mitigating signal crosstalk between column stages. The circuit and control method of this invention solve the problem of high-order Sigma Delta ADCs simultaneously meeting the high-precision and low-power requirements of CMOS image sensors for column-level ADCs.
Claims
1. A column-level low-power, high-precision Sigma Delta ADC circuit for CIS, characterized in that, It includes a third-order CIFF structure Sigma Delta modulator. The input of the third-order CIFF structure Sigma Delta modulator is connected to the output signal of two columns of pixel units. The output of the third-order CIFF structure Sigma Delta modulator is connected to a digital filter. The output of the digital filter module is the final quantization result Dout1 and Dout2 of the ADC.
2. The column-level low-power, high-precision Sigma Delta ADC circuit for CIS as described in claim 1, characterized in that, The third-order CIFF Sigma Delta modulator uses a 1-2-1 architecture consisting of an integrator, a digital-to-analog converter (DAC), a feedforward adder, and a quantizer. The three-stage integrator is structured as follows: the first stage is a set of switched-capacitor integrators; the second stage consists of two sets of switched-capacitor integrators (2-1 and 2-2); and the third stage is also a set of switched-capacitor integrators. The non-inverting output VOP1 of the first-stage integrator is connected to the inputs of sampling switches S21 and S23 in the second-stage integrator 2-1 and 2-2, respectively. VOP1 is also connected to the inputs of feedforward adders A and B. The inverting output VON1 of the first-stage integrator is connected to the inputs of sampling switches S22 and S24 in the second-stage integrator 2-1 and 2-2, respectively. VON1 is also connected to the inputs of feedforward adders A and B. The second-stage integrator 2... The non-inverting output VOP2 of the second-stage integrator 2-2 is connected to the input of sampling switch S37 in the third-stage integrator. VOP2 is also connected to the input of feedforward adder A. The inverting output VON2 is connected to the input of sampling switch S38. VON2 is also connected to the input of feedforward adder A. The non-inverting output VOP3 of the second-stage integrator 2-2 is connected to the input of sampling switch S39 in the third-stage integrator. VOP3 is also connected to the input of feedforward adder B. The inverting output terminal VON3 is connected to the input terminal of sampling switch S40. Output terminal VON3 is also connected to the input terminal of feedforward adder B. The non-inverting input terminal VOP4 of the third-stage switched-capacitor integrator is connected to the input terminals of feedforward adders A and B. The inverting input terminal VON4 is also connected to the input terminals of feedforward adders A and B. The output of feedforward adder A is connected to the input of quantizer A. The output of quantizer A is connected to the input of digital filter A. It is also connected to the control signal terminal Q of digital-to-analog converters DAC1 and DAC2. A The output of feedforward adder B is connected to the input of quantizer B, the output of quantizer B is connected to the input of digital filter B, and it is also connected to the control signal terminal Q of digital-to-analog converters DAC3 and DAC4. B .
3. The column-level low-power, high-precision Sigma Delta ADC circuit for CIS as described in claim 2, characterized in that, The first-stage switched-capacitor integrator includes 20 CMOS switches S1~S20, 4 sampling capacitors Cs1~Cs4, 4 integrating capacitors Ci1~Ci4, and 1 operational amplifier OTA1. The pixel output signal is connected to the input terminals of switches S1~S4 respectively. The output terminal of switch S1 is connected to the upper stage board of sampling capacitor Cs1. The upper stage board of sampling capacitor Cs1 is also connected to the output terminal of switch S5. The input terminal of switch S5 is connected to the output of digital-to-analog converter DAC1. The lower stage board of sampling capacitor Cs1 is connected to the output terminal of switch S9 and the input terminal of switch S13. The input terminal of switch S9 is connected to the common-mode voltage Vcm. The output terminal of switch S13 is connected to the inverting input terminal of operational amplifier OTA1 and the upper stage board of integrating capacitor Ci1. The lower stage board of integrating capacitor Ci1 is connected to the input terminal of switch S17. The output terminal of switch S17 is connected to the non-inverting output terminal VOP1 of operational amplifier OTA1.
4. The column-level low-power, high-precision Sigma Delta ADC circuit for CIS according to claim 3, characterized in that, The output of switch S2 is connected to the upper board of sampling capacitor Cs2. The upper board of sampling capacitor Cs2 is also connected to the output of switch S6. The input of switch S6 is connected to the output of digital-to-analog converter DAC2. The lower board of sampling capacitor Cs2 is connected to the output of switch S10 and the input of switch S14. The input of switch S10 is connected to the common-mode voltage Vcm. The output of switch S14 is connected to the non-inverting input of operational amplifier OTA1 and the upper board of integrating capacitor Ci2. The lower board of integrating capacitor Ci2 is connected to the input of switch S18. The output of switch S18 is connected to the inverting output VON1 of operational amplifier OTA1.
5. The column-level low-power, high-precision Sigma Delta ADC circuit for CIS according to claim 4, characterized in that, The branch containing switch S3 has the same structure as the branch containing switch S1, and the branch containing switch S4 has the same structure as the branch containing switch S2.
6. The column-level low-power, high-precision Sigma Delta ADC circuit for CIS according to claim 5, characterized in that, The second-stage integrator includes switched-capacitor integrator 2-1 and switched-capacitor integrator 2-2, consisting of 16 CMOS switches S21~S36, 4 sampling capacitors Cs5~Cs8, 4 integrating capacitors Ci5~Ci8, and two operational amplifiers OTA2 and OTA3. The input of switch S21 is connected to the non-inverting output VOP1 of operational amplifier OTA1. The output of switch S21 is connected to the upper stage board of sampling capacitor Cs5. The upper stage board of sampling capacitor Cs5 is also connected to the output of switch S25. The input of switch S25 is connected to the common-mode voltage Vcm. The lower stage board of sampling capacitor Cs5 is connected to the output of switch S29 and the input of switch S33. The input of switch S29 is connected to the common-mode voltage Vcm. The output of switch S33 is connected to the inverting input of operational amplifier OTA2 and the upper stage board of integrating capacitor Ci5. The lower stage board of integrating capacitor Ci5 is connected to the non-inverting output VOP2 of operational amplifier OTA2.
7. The column-level low-power, high-precision Sigma Delta ADC circuit for CIS according to claim 6, characterized in that, The input terminal of switch S22 is connected to the inverting output terminal VON1 of operational amplifier OTA1. The output terminal of switch S22 is connected to the upper stage board of sampling capacitor Cs6. The upper stage board of sampling capacitor Cs6 is also connected to the output terminal of switch S26. The input terminal of switch S26 is connected to the common-mode voltage Vcm. The lower stage board of sampling capacitor Cs6 is connected to the output terminal of switch S30 and the input terminal of switch S34. The input terminal of switch S30 is connected to the common-mode voltage Vcm. The output terminal of switch S34 is connected to the non-inverting input terminal of operational amplifier OTA2 and the upper stage board of integrating capacitor Ci6. The lower stage board of integrating capacitor Ci6 is connected to the inverting output terminal VON2 of operational amplifier OTA2.
8. The column-level low-power, high-precision Sigma Delta ADC circuit for CIS according to claim 7, characterized in that, The switched capacitor integrator 2-2 has the same structure as the switched capacitor integrator 2-1; The third-stage switched-capacitor integrator has the same structure as the first-stage switched-capacitor integrator, except that the DAC module in the first-stage switched-capacitor integrator is replaced with the common-mode voltage Vcm. The outputs VOP1, VON1, VOP2, VON2, VOP4, and VON4 of the switched capacitor integrator are connected to the input of the feedforward adder A. The output of the feedforward adder A is connected to the input of the quantizer A. The output of the quantizer A is connected to the input of the digital filter A. The digital filter A outputs the final quantization result Dout1. The outputs VOP1, VON1, VOP3, VON3, VOP4, and VON4 of the switched capacitor integrator are connected to the input of the feedforward adder B. The output of the feedforward adder B is connected to the input of the quantizer B. The output of the quantizer B is connected to the input of the digital filter B. The digital filter B outputs the final quantization result Dout2.
9. A control method for a column-level low-power, high-precision Sigma Delta ADC circuit applied to CIS, based on the column-level low-power, high-precision Sigma Delta ADC circuit applied to CIS as described in claim 8, characterized in that, The specific steps are as follows: Step 1: The two-column pixel differential output signals VIP1, VIN1, VIP2, and VIN2 are respectively input to the input terminals of the four sampling switches S1 to S4; Step 2: The modulator operates under the control of four clocks.
10. The control method for a column-level low-power, high-precision Sigma Delta ADC circuit applied to CIS according to claim 9, characterized in that, Step 2 is implemented in the following steps: Step 2.1 and For two non-overlapping clocks, and For complementary clocks with delay, in In the working state, for the differential output signals VIP1 and VIN1 of the first column of pixels, the three-stage switched capacitor integrator is in the sampling-integration-sampling working state, with the second-stage switched capacitor integrator 2-1 in the integration state and storing the output result of the switched capacitor integrator 2-1 at this time; for the differential output signals VIP2 and VIN2 of the second column of pixels, the three-stage switched capacitor integrator is in the integration-sampling-integration working state, with the second-stage switched capacitor integrator 2-2 in the sampling state; Step 2.2 In the working state, the output results VOP1, VON1, VOP3, VON3, VOP4, and VON4 of the switched capacitor integrator are input into the feedforward adder B. The output of the feedforward adder B is connected to the quantizer B. The output of the quantizer B is used as the control signal for DAC3 and DAC4. At the same time, the output of the quantizer B is used as the input of the digital filter B. Step 2.3, in In the working state, for the differential output signals VIP1 and VIN1 of the first column of pixels, the three-stage switched capacitor integrator is in the working state of integration-sampling-integration, with the second-stage switched capacitor integrator 2-1 in the sampling state; for the differential output signals VIP2 and VIN2 of the second column of pixels, the three-stage switched capacitor integrator is in the working state of sampling-integration-sampling, with the second-stage switched capacitor integrator 2-2 in the integration state, and the output result of the switched capacitor integrator 2-2 at this time is stored. Step 2.4 In the working state, the output results VOP1, VON1, VOP2, VON2, VOP4, and VON4 of the switched capacitor integrator are input into feedforward adder A. The output of feedforward adder A is connected to quantizer A. The output of quantizer A is used as the control signal for DAC1 and DAC2. At the same time, the output of quantizer A is used as the input of digital filter A. Step 2.5, Modulator The output of the modulator in the current state is input into digital filter B, and the output of digital filter B is used as the final quantization result Dout2 of the second column pixel signal. The output of the current state is input into digital filter A, and the output of digital filter A is used as the final quantization result Dout1 of the first column of pixel signals.