Signal processing circuit and switch
By combining the design of expansion chips, NMOS transistors and voltage comparators, the complexity and high maintenance cost of the signal processing circuit between the switch motherboard and the optical module are solved, enabling accurate reset and status detection of the optical module, simplifying the hardware structure and reducing maintenance costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- GUANGDONG PURUI YUNCHUANG TECHNOLOGY CO LTD
- Filing Date
- 2026-01-07
- Publication Date
- 2026-04-21
AI Technical Summary
In the existing technology, the signal processing circuit design between the switch motherboard and the optical module is complex and the maintenance cost is high, especially due to the large number of cross-board signals, which leads to the complexity of circuit design and high maintenance cost.
By employing a combination design of an extension chip, an NMOS transistor, and a voltage comparator, the on/off state of the NMOS transistor is precisely controlled through the level clamping effect of the control signal and the resistor, thereby realizing the reset state regulation and working state detection of the optical module. This integrates the reset state control and working state detection functions of the optical module, simplifying the hardware structure and reducing maintenance costs.
It enables precise reset control and status detection of optical modules, simplifies the hardware structure of signal processing circuits, reduces circuit construction and maintenance costs, and improves circuit reliability and control accuracy.
Smart Images
Figure CN121908169A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of signal processing technology, and more particularly to a signal processing circuit and a switch. Background Technology
[0002] As the core optoelectronic device in an optical communication system, the optical module needs to establish a stable signal interaction link with the switch motherboard to realize core functions such as optical module reset control, working mode switching, on-site status detection, and working status feedback.
[0003] In related technologies, when the signal processing circuit between the switch motherboard and the optical module is implemented using CPLD or FPGA, it suffers from the drawbacks of complex circuit design and high maintenance costs due to the large number of cross-board signals.
[0004] Therefore, reducing the complexity and maintenance cost of signal processing circuits has become an urgent technical problem to be solved. Summary of the Invention
[0005] This application provides a signal processing circuit and a switch to address the problems of complex design and high maintenance costs associated with signal processing circuits in related technologies.
[0006] In a first aspect, embodiments of this application provide a signal processing circuit connected to an optical module, comprising:
[0007] The first expansion chip, the first NMOS transistor, and the first voltage comparator;
[0008] The first terminal of the first expansion chip is connected to the gate of the first NMOS transistor; the drain of the first NMOS transistor is connected to the optical module and the inverting input terminal of the first voltage comparator respectively, and the source of the first NMOS transistor is grounded; the non-inverting input terminal of the first voltage comparator is connected to the first reference voltage of the circuit; the output terminal of the first voltage comparator is connected to the second terminal of the first expansion chip.
[0009] The first expansion chip is used to send a first control signal to the first NMOS transistor, and the first control signal is used to put the first NMOS transistor in a cut-off state or a conduction state.
[0010] The first NMOS transistor is used to control itself to be in a cut-off state or a conduction state based on the first control signal, so that the optical module is in the target reset state.
[0011] The first voltage comparator is used to obtain a voltage comparison result based on the output voltage of the optical module and the first reference voltage, so that the first expansion chip can determine whether the optical module is in an interrupted or normal state based on the voltage comparison result.
[0012] In one possible implementation, the circuit further includes a first power supply, a first resistor, and a second resistor; the first end of the first resistor and the first end of the second resistor are both grounded; the second end of the first resistor is connected to the gate of the first NMOS transistor; the second end of the second resistor is connected to the first signal pin of the optical module and the inverting input of the first voltage comparator, respectively.
[0013] The first resistor is used to pull the gate of the first NMOS transistor low to a low level when the first control signal is low, so that the first NMOS transistor is in the off state.
[0014] The second resistor is used to pull the first signal pin low to a low level when the first NMOS transistor is in the on state.
[0015] In one possible implementation, the circuit further includes a third resistor and a fourth resistor; the first and second ends of the third resistor are respectively connected to the first power supply and the positive input of the first voltage comparator; the first end of the fourth resistor is grounded, and the second end of the fourth resistor is connected to the positive input of the first voltage comparator.
[0016] The fourth resistor works in conjunction with the third resistor to ensure that the voltage supplied by the first power source is a preset first reference voltage.
[0017] In one possible implementation, the circuit further includes: a second extension chip, a second NMOS transistor, a third NMOS transistor, and a second voltage comparator;
[0018] The first terminal of the second expansion chip is connected to the gate of the second NMOS transistor; the drain of the second NMOS transistor is connected to the gate of the third NMOS transistor, and the source of the second NMOS transistor is grounded; the source of the third NMOS transistor is connected to the second signal pin, and the drain of the third NMOS transistor is connected to the second reference voltage of the circuit; the non-inverting input terminal of the second voltage comparator is connected to the second signal pin, the inverting input terminal of the second voltage comparator is connected to the second reference voltage of the circuit, and the output terminal of the second voltage comparator is connected to the second terminal of the second expansion chip.
[0019] The second expansion chip is used to send a second control signal to the optical module. The second control signal is used to put the optical module into the target mode and to put the gate of the second NMOS transistor into the target level state.
[0020] The second NMOS transistor is used to keep the second NMOS transistor in a cutoff state or a conduction state when the gate of the second NMOS transistor is in a target level state.
[0021] The third NMOS transistor is used to make the third NMOS transistor either cut off or on when its gate is at the target level.
[0022] The second voltage comparator is used to obtain a voltage comparison result based on the output voltage of the optical module and the second reference voltage, so that the second expansion chip can determine whether the optical module is in place based on the voltage comparison result.
[0023] In one possible implementation, the circuit further includes a first power supply, a second power supply, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor.
[0024] The first end of the fifth resistor is connected to the first power supply, and the second end of the fifth resistor is connected to the gate of the second NMOS transistor; the first end of the sixth resistor is connected to the second power supply, and the second end of the sixth resistor is connected to the gate of the third NMOS transistor; the first end of the seventh resistor is connected to the first power supply, and the second end of the seventh resistor is connected to the drain of the third NMOS transistor; the first end of the eighth resistor is connected to the second signal pin, and the second end of the eighth resistor is connected to the source of the third NMOS transistor.
[0025] The fifth resistor, based on the first power supply, keeps the gate of the second NMOS transistor at the target level.
[0026] The sixth resistor, based on the second power supply, keeps the gate of the third NMOS transistor at the target level.
[0027] The seventh and eighth resistors are used to set the inverting input of the second voltage comparator to the second reference voltage.
[0028] In one possible implementation, the circuit further includes a third power supply, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor;
[0029] The first end of the ninth resistor is connected to the third power supply, and the second end of the ninth resistor is connected to the second signal pin; the first end of the tenth resistor is connected to the third power supply, and the second end of the tenth resistor is connected to the inverting input of the second voltage comparator; the first end of the eleventh resistor is grounded, and the second end of the eleventh resistor is connected to the inverting input of the second voltage comparator; the first end of the twelfth resistor is connected to the third power supply, and the second end of the twelfth resistor is connected to the output of the second voltage comparator.
[0030] The ninth resistor keeps the source of the third NMOS transistor at the target level based on the voltage provided by the third power supply.
[0031] The tenth and eleventh resistors, based on the voltage provided by the third power supply, keep the inverting input of the second voltage comparator at the second reference voltage;
[0032] The twelfth resistor stabilizes the voltage at the output of the second voltage comparator at the output voltage of the third power supply, based on the voltage provided by the third power supply.
[0033] In one possible implementation, the target reset state is either a reset state or a de-reset state.
[0034] In one possible implementation, the target mode is either a low-power mode or a normal mode.
[0035] In one possible implementation, the target level state is either high or low.
[0036] Secondly, embodiments of this application provide a switch connected to an optical module, wherein the switch is provided with a signal processing circuit as described in any of the first aspects.
[0037] The signal processing circuit and switch provided in this application embodiment include a first expansion chip, a first NMOS transistor, and a first voltage comparator. A first terminal of the first expansion chip is connected to the gate of the first NMOS transistor; the drain of the first NMOS transistor is connected to both the optical module and the inverting input of the first voltage comparator; the source of the first NMOS transistor is grounded; the non-inverting input of the first voltage comparator is connected to a first reference voltage of the circuit; and the output of the first voltage comparator is connected to a second terminal of the first expansion chip. The first expansion chip sends a first control signal to the first NMOS transistor, which causes the first NMOS transistor to be in a cutoff or on state. The first NMOS transistor controls itself to be in a cutoff or on state based on the first control signal, so that the optical module is in a target reset state. The first voltage comparator obtains a voltage comparison result based on the output voltage of the optical module and the first reference voltage, so that the first expansion chip determines whether the optical module is in an interrupted or normal state based on the voltage comparison result. This technical solution integrates the reset status control and working status detection functions of the optical module through a simple hardware combination of extended chips, NMOS transistors and voltage comparators and a reasonable pin connection design. It simplifies the hardware structure of the signal processing circuit, reduces the number of components used, and while accurately realizing the reset control and interruption and normal status determination of the optical module, it reduces the circuit construction and maintenance costs and improves the reliability of the circuit. Attached Figure Description
[0038] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.
[0039] Figure 1 Schematic diagram of the signal processing circuit of the related technology provided in the embodiments of this application Figure 1 ;
[0040] Figure 2 Schematic diagram of the signal processing circuit of the related technology provided in the embodiments of this application Figure 2 ;
[0041] Figure 3A schematic diagram of the signal processing circuit provided in the embodiments of this application. Figure 1 ;
[0042] Figure 4 A schematic diagram of the signal processing circuit provided in the embodiments of this application. Figure 2 ;
[0043] Figure 5 This is a schematic diagram of the structure of the switch provided in an embodiment of this application.
[0044] The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation
[0045] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0046] Before introducing the embodiments of this application, the application background of the embodiments of this application will be explained first:
[0047] As a core optoelectronic device in an optical communication system, the optical module needs to establish a stable signal interaction link with the switch motherboard to realize core functions such as reset control, working mode switching, presence status detection, and working status feedback. Among these, the switching between reset and de-reset states, and the switching between low-power mode and normal working mode, are crucial to ensuring stable operation and reducing energy consumption of the optical module. Meanwhile, the determination of the optical module's presence status and the feedback of interrupt and normal working status are prerequisites for the switch motherboard to effectively manage the optical module.
[0048] In existing technologies, the signal processing circuits between the switch motherboard and the optical module often use a single switching device to achieve simple level control, or separate detection circuits to implement reset control, mode switching, and status detection functions. This not only leads to complex circuit structures and a large number of components, but also results in low signal control accuracy and untimely status feedback. Existing circuits lack precise level matching design for controlling the on and off states of NMOS transistors, and lack stable voltage divider links to support the reference voltage configuration of voltage comparators. This easily leads to technical defects such as optical module reset failure, false triggering of mode switching, and inaccurate determination of the in-situ status, which in turn affects the reliability of signal interaction between the optical module and the switch motherboard, and may even cause abnormal operation of the optical module.
[0049] For example, Figure 1 Schematic diagram of the signal processing circuit of the related technology provided in the embodiments of this application Figure 1 ,like Figure 1 As shown, after the optical module's low-level active interrupt / reset (INT / RSTn) pin is connected to the switch motherboard, reset control is implemented through the GPIO interface of the CPLD / FPGA: when the CPLD / FPGA outputs a control signal to pull the INT / RSTn pin low, the optical module is triggered to enter the reset state. When the CPLD / FPGA releases the pin level, the P3V3_OP power supply pulls the INT / RSTn pin up through a 2kΩ resistor. Combined with the voltage division effect of the 68kΩ pull-down resistor, the pin level returns to the high level range, and the optical module completes the reset. Simultaneously, a 2kΩ and a 6.34kΩ resistor divide the P3V3_OP (3.3V) voltage to generate a 2.5V reference voltage, which is then connected to the non-inverting input of the voltage comparator. The inverting input of the voltage comparator is connected to the INT / RSTn pin. If the optical module is working normally, the INT / RSTn pin outputs a high level greater than 2.5V, the level at the inverting input of the comparator is higher than the non-inverting input, and the output is low. The CPLD / FPGA determines that the optical module is in a normal state based on this. If the optical module triggers an interrupt, its INT / RSTn pin is actively pulled low to a level less than 2.5V, the level at the inverting input of the voltage comparator is lower than the non-inverting input, and the output is high. The CPLD / FPGA then determines that the optical module is in an interrupt state. In addition, a 68kΩ pull-down resistor can prevent level fluctuations when the INT / RSTn pin is floating.
[0050] Figure 2 Schematic diagram of the signal processing circuit of the related technology provided in the embodiments of this application Figure 2 ,like Figure 2As shown, after the Low Power / Present negative (LPW / PRSn) pin of the optical module is connected to the switch motherboard, the operating mode is controlled through the GPIO interface of the CPLD / FPGA: when the CPLD / FPGA outputs a control signal to pull the LPW / PRSn pin low, the optical module is triggered to enter the low power mode. When the CPLD / FPGA releases the pin level, the P3V3_OP power supply pulls up the LPW / PRSn pin through a 2kΩ resistor. Combined with the voltage division effect of the 25kΩ resistor, the pin level is restored to the high level range, and the optical module switches to normal operating mode. Simultaneously, the 2kΩ and 6.34kΩ resistors divide the P3V3_OP voltage to generate a 2.5V reference voltage, which is then connected to the non-inverting input of the voltage comparator. The inverting input of the voltage comparator is connected to the LPW / PRSn pin. If the optical module is in place, its LPW / PRSn pin will output a low level less than 2.5V. The level at the inverting input of the voltage comparator will be lower than the level at the non-inverting input, resulting in a high level output. The CPLD / FPGA determines that the optical module is in place based on this. If the optical module is not in place, the level at the LPW / PRSn pin will be pulled up to a high level greater than 2.5V by the 25kΩ resistor. The level at the inverting input of the comparator will be higher than the level at the non-inverting input, resulting in a low level output. The CPLD / FPGA then determines that the optical module is not in place.
[0051] The above Figure 1 and Figure 2 The relevant technologies use Complex Programmable Logic Devices (CPLDs) or Field Programmable Gate Arrays (FPGAs) to implement signal processing in circuits. However, the number of pins of optical modules on the input / output boards (IOs) of servers and hyper-converged projects is small, making it impractical to add CPLDs or FPGAs to the IO boards. The manpower cost of maintaining CPLD or FPGA firmware versions is high. At the same time, when using CPLDs to process low-speed signals from optical modules, the number of cross-board signals is large, the number of connector pins increases, and the design becomes more complex.
[0052] Therefore, reducing the complexity and maintenance cost of signal processing circuits has become an urgent technical problem to be solved.
[0053] To address the technical problems existing in related technologies, the inventors of this application propose the following solution: To address the issues of complex signal processing circuit design and high maintenance costs, a control signal is output from a first expansion chip to a first NMOS transistor. Combined with the level clamping effect of a resistor, the on / off state of the first NMOS transistor is precisely controlled, thereby regulating the reset or de-reset state of the optical module. Simultaneously, a first voltage comparator compares the output voltage of the optical module with a reference voltage to determine the interrupted or normal state of the optical module and feeds this information back to the first expansion chip, achieving circuit multiplexing for reset control and operational status detection. Furthermore, through the cascaded control logic of the second expansion chip, the second NMOS transistor, and the third NMOS transistor, along with the matching design of the voltage divider resistor and the reference voltage, the switching between low-power and normal modes of the optical module is achieved. The second voltage comparator is used to accurately determine the optical module's presence status, integrating mode switching and presence detection functions into the same hardware link. By adopting a design approach that integrates functions and simplifies the architecture, the hardware architecture and signal links of the signal processing circuit are effectively simplified while achieving full-dimensional control of the optical module. This reduces circuit failure points, lowers the difficulty and cost of hardware construction and subsequent maintenance, and simultaneously ensures the control precision and practicality of the circuit.
[0054] The parts not described in detail are disclosed in the following embodiments.
[0055] The technical solution of this application will now be described in detail through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.
[0056] It is worth noting that the application fields of the signal processing circuits and switches in this application are not limited.
[0057] Figure 3 A schematic diagram of the signal processing circuit provided in the embodiments of this application. Figure 1 ,like Figure 3 As shown, the circuit 10 includes: a first expansion chip 100, a first NMOS transistor 101, and a first voltage comparator 102;
[0058] The first terminal of the first expansion chip 100 is connected to the gate (G) of the first NMOS transistor 101; the drain (D) of the first NMOS transistor 101 is connected to the optical module and the inverting input of the first voltage comparator 102, respectively; the source (S) of the first NMOS transistor 101 is grounded; the non-inverting input of the first voltage comparator 102 is connected to the first reference voltage of the circuit 10; the output of the first voltage comparator 102 is connected to the second terminal of the first expansion chip 100.
[0059] The first expansion chip 100 is used to send a first control signal to the first NMOS transistor 101, and the first control signal is used to put the first NMOS transistor 101 into a cut-off state or a conduction state.
[0060] The first NMOS transistor 101 is used to control itself to be in a cut-off state or a conduction state based on the first control signal, so that the optical module is in a target reset state.
[0061] The target reset state can be either the reset state or the de-reset state.
[0062] The first voltage comparator 102 is used to obtain a voltage comparison result based on the output voltage of the optical module and the first reference voltage, so that the first expansion chip 100 can determine whether the optical module is in an interrupted or normal state based on the voltage comparison result.
[0063] For example, the first reference voltage is 2.5V.
[0064] For example, the first expansion chip 100 is a PCA9555 IO expansion chip. The first terminal of the first expansion chip 100 is directly connected to the gate (G) of the first NMOS transistor 101 through a copper foil line, and is used to output the first control signal. The first NMOS transistor 101 is an N-channel enhancement-mode MOS transistor. Its drain (D) is connected to the first signal pin of the optical module through a signal interface. At the same time, the drain is connected to the inverting input terminal of the first voltage comparator 102 through a branch line, and the source (S) is directly grounded to form a level reference. The first voltage comparator 102 is an LM339. Its non-inverting input terminal is connected to the 2.5V reference voltage of circuit 10, and its output terminal is connected to the second terminal of the first expansion chip 100 through a feedback line, forming a control-feedback closed loop.
[0065] Accordingly, during circuit operation, the first expansion chip 100 sends a first control signal in the form of a high level or a low level to the first NMOS transistor 101. When the first control signal is high, the voltage difference between the gate (G) and source (S) of the first NMOS transistor 101 is greater than the conduction threshold (approximately 2V), the first NMOS transistor conducts, pulling the pin level of the first signal pin of the optical module low to near ground potential. That is, the level at the first signal pin is less than or equal to the reset trigger threshold (e.g., 1.25V), and the optical module enters the reset state. When the first control signal is low, the voltage difference between the gate (G) and source (S) of the first NMOS transistor 101 is close to 0V, the first NMOS transistor is cut off, and the pin level of the first signal pin of the optical module is pulled high by its own pull-up resistor. That is, the level at the first signal pin is greater than the reset trigger threshold, and the optical module enters the de-reset state.
[0066] Meanwhile, the first voltage comparator 102 continuously acquires the output voltage of the first signal pin of the optical module (i.e., the voltage of the drain of the first NMOS transistor 101) and compares it with the 2.5V reference voltage at the non-inverting input terminal. If the output voltage of the optical module is greater than the interrupt trigger threshold (e.g., 2.5V), the first voltage comparator 102 outputs a high level, and the first expansion chip 100 determines that the optical module is in an interrupted working state after receiving the signal. If the output voltage of the optical module is less than or equal to the interrupt trigger threshold, the comparator outputs a low level, and the first expansion chip 100 determines that the optical module is in a normal working state.
[0067] The high level is a voltage range of 2.0V-3.3V, and the low level is a voltage range of 0V-0.8V.
[0068] Furthermore, the circuit 10 also includes a first power supply 103, a first resistor 104, and a second resistor 105; the first end of the first resistor 104 and the first end of the second resistor 105 are both grounded; the second end of the first resistor 104 is connected to the gate of the first NMOS transistor 101; the second end of the second resistor 105 is connected to the first signal pin of the optical module and the inverting input of the first voltage comparator 102, respectively.
[0069] The first resistor 104 is used to pull the gate of the first NMOS transistor 101 low to a low level when the first control signal is low, so that the first NMOS transistor 101 is in the off state.
[0070] The second resistor 105 is used to pull the first signal pin low to a low level when the first NMOS transistor 101 is in the on state.
[0071] Specifically, the first resistor 104 is a pull-down resistor. When the first control signal output by the first expansion chip 100 is low, it can stably pull the gate of the first NMOS transistor 101 low, ensuring that the voltage difference between the gate and source of the first NMOS transistor 101 meets the cutoff condition, thereby reliably keeping the first NMOS transistor 101 in the cutoff state and avoiding conduction abnormalities caused by gate level floating. The second resistor 105 is a pull-down resistor. When the first NMOS transistor 101 is in the conduction state, it can work with the drain-source path of the first NMOS transistor 101 to stably pull the first signal pin of the optical module low, making the low level at the first signal pin less than or equal to the reset trigger threshold, and the optical module adjusts its working state to the reset state.
[0072] Furthermore, circuit 10 also includes a third resistor 106 and a fourth resistor 107; the first and second ends of the third resistor 106 are respectively connected to the first power supply 103 and the positive input terminal of the first voltage comparator 102; the first end of the fourth resistor 107 is grounded, and the second end of the fourth resistor 107 is connected to the non-inverting input terminal of the first voltage comparator 102.
[0073] The fourth resistor 107 works in conjunction with the third resistor 106 to ensure that the voltage provided by the first power supply 103 is a preset first reference voltage.
[0074] The third resistor 106 and the fourth resistor 107 constitute a voltage divider circuit. Based on the ratio of their resistance values, they work together to divide the supply voltage output by the first power supply 103, so as to form a stable preset first reference voltage at the non-inverting input terminal of the first voltage comparator 102. This provides a precise and fixed reference voltage for the voltage comparison operation of the first voltage comparator 102, ensuring the accuracy of the voltage comparison result.
[0075] The signal processing circuit provided in this application includes a first expansion chip, a first NMOS transistor, and a first voltage comparator. A first terminal of the first expansion chip is connected to the gate of the first NMOS transistor; the drain of the first NMOS transistor is connected to both the optical module and the inverting input of the first voltage comparator; the source of the first NMOS transistor is grounded; the non-inverting input of the first voltage comparator is connected to a first reference voltage of the circuit; and the output of the first voltage comparator is connected to a second terminal of the first expansion chip. The first expansion chip sends a first control signal to the first NMOS transistor, which causes the first NMOS transistor to be in a cutoff or on state. The first NMOS transistor controls itself to be in a cutoff or on state based on the first control signal, so that the optical module is in a target reset state. The first voltage comparator obtains a voltage comparison result based on the output voltage of the optical module and the first reference voltage, so that the first expansion chip determines whether the optical module is in an interrupted or normal state based on the voltage comparison result. This technical solution integrates the reset status control and working status detection functions of the optical module through a simple hardware combination of extended chips, NMOS transistors and voltage comparators and a reasonable pin connection design. It simplifies the hardware structure of the signal processing circuit, reduces the number of components used, and while accurately realizing the reset control and interruption and normal status determination of the optical module, it reduces the circuit construction and maintenance costs and improves the reliability of the circuit.
[0076] Based on the above embodiments, Figure 4 A schematic diagram of the signal processing circuit provided in the embodiments of this application. Figure 2 ,like Figure 4As shown, the circuit 10 also includes: a second expansion chip 108, a second NMOS transistor 109, a third NMOS transistor 1010, and a second voltage comparator 1011.
[0077] The first expansion chip and the second expansion chip can be integrated into the same physical chip, and the physical chip can realize all the functions of the first expansion chip and the second expansion chip.
[0078] The first terminal of the second expansion chip 108 is connected to G1 (gate) of the second NMOS transistor 109; D1 (drain) of the second NMOS transistor 109 is connected to G2 (gate) of the third NMOS transistor 1010, and S1 (source) of the second NMOS transistor 109 is grounded; S2 (source) of the third NMOS transistor 1010 is connected to the second signal pin, and D2 (drain) of the third NMOS transistor 1010 is connected to the second reference voltage of the circuit 10; the non-inverting input terminal of the second voltage comparator 1011 is connected to the second signal pin, the inverting input terminal of the second voltage comparator 1011 is connected to the second reference voltage of the circuit 10, and the output terminal of the second voltage comparator 1011 is connected to the second terminal of the second expansion chip 108.
[0079] For example, the second reference voltage is 2.5V.
[0080] The second expansion chip 108 is used to send a second control signal to the optical module. The second control signal is used to put the optical module into the target mode and to put the gate of the second NMOS transistor 109 into the target level state.
[0081] The target mode can be either low-power mode or normal mode. The target voltage level can be either high or low.
[0082] The second NMOS transistor 109 is used to make the second NMOS transistor 109 either in a cutoff state or a conduction state when the gate of the second NMOS transistor 109 is in a target level state.
[0083] The third NMOS transistor 1010 is used to make the third NMOS transistor 1010 in the off state or the on state when the gate of the third NMOS transistor 1010 is in the target level state.
[0084] The second voltage comparator 1011 is used to obtain a voltage comparison result based on the output voltage of the optical module and the second reference voltage, so that the second expansion chip 108 can determine whether the optical module is in place based on the voltage comparison result.
[0085] For example, the second expansion chip 108 outputs a second control signal in the form of a high level or a low level:
[0086] When the second control signal is low, the voltage difference between the gate and source of the second NMOS transistor 109 is less than the turn-on threshold, so that the second NMOS transistor 109 is turned off. At the same time, the gate level of the third NMOS transistor 1010 is pulled high, and the third NMOS transistor 1010 is turned on. The subsequent voltage divider circuit makes the voltage at the second signal pin of the optical module the first preset reference voltage (e.g., any value greater than 1.25V set in the circuit design). The optical module determines that the first preset reference voltage is greater than the low power trigger threshold (e.g., 1.25V), and the optical module adjusts its working mode to the normal working mode.
[0087] When the second control signal is high, the second control signal makes the voltage difference between the gate and the source of the second NMOS transistor 109 greater than the conduction threshold, so that the second NMOS transistor 109 is turned on. The gate level of the third NMOS transistor 1010 is pulled down to a low level by the pull-down resistor, so that the third NMOS transistor 1010 is in the off state. The voltage divider resistor pulls the second signal pin down to the second preset reference voltage. The optical module determines that the second preset voltage is less than or equal to the low power trigger threshold, and the optical module adjusts the working mode to low power mode.
[0088] Meanwhile, the second voltage comparator 1011 continuously acquires the output voltage of the second signal pin of the optical module and compares it with the second reference voltage at the inverting input of the second voltage comparator 1011: if the output voltage is greater than the in-position trigger threshold (i.e., the second reference voltage), the comparator outputs a high level, and the second expansion chip 108 determines that the optical module is not in position; if the output voltage is less than or equal to the in-position trigger threshold, the second voltage comparator 1011 outputs a low level, the second expansion chip 108 determines that the optical module is in position, and feeds back the in-position status to the main control board of the switch, thus completing the accurate detection of the in-position status of the optical module.
[0089] Furthermore, circuit 10 also includes a first power supply 1012, a second power supply 1013, a fifth resistor 1014, a sixth resistor 1015, a seventh resistor 1016, and an eighth resistor 1017.
[0090] For example, the first power supply 1012 is a 3.3V power supply, and the second power supply 1013 is a 12V power supply.
[0091] The first end of the fifth resistor 1014 is connected to the first power supply 1012, and the second end of the fifth resistor 1014 is connected to the gate of the second NMOS transistor 109; the first end of the sixth resistor 1015 is connected to the second power supply 1013, and the second end of the sixth resistor 1015 is connected to the gate of the third NMOS transistor 1010; the first end of the seventh resistor 1016 is connected to the first power supply 1012, and the second end of the seventh resistor 1016 is connected to the drain of the third NMOS transistor 1010; the first end of the eighth resistor 1017 is connected to the second signal pin, and the second end of the eighth resistor 1017 is connected to the source of the third NMOS transistor 1010.
[0092] The fifth resistor 1014, based on the first power supply 1012, keeps the gate of the second NMOS transistor 109 at the target level.
[0093] The sixth resistor 1015, based on the second power supply 1013, keeps the gate of the third NMOS transistor 1010 at the target level.
[0094] The seventh resistor 1016 and the eighth resistor 1017 are used to set the inverting input of the second voltage comparator 1011 to the second reference voltage.
[0095] For example, the fifth resistor 1014 is powered by the 3.3V of the first power supply 1012. When the second extension chip 108 outputs a low-level control signal, it keeps the gate of the second NMOS transistor 109 at a low level of 0V, ensuring that the second NMOS transistor 109 is reliably turned off. The sixth resistor 1015 is powered by the 12V of the second power supply 1013. When the second NMOS transistor 109 is turned off, it clamps the gate of the third NMOS transistor 1010 to a stable high level, ensuring that the third NMOS transistor 1010 is turned on. The seventh resistor 1016 and the eighth resistor 1017 form a voltage divider link. Through a precise resistance ratio (e.g., using a combination of 100 ohms and 2kΩ), the 3.3V voltage of the first power supply 1012 is divided, forming a stable voltage at the positive input terminal of the second voltage comparator 1011.
[0096] Furthermore, circuit 10 also includes a third power supply 1018, a ninth resistor 1019, a tenth resistor 1020, an eleventh resistor 1021, and a twelfth resistor 1022.
[0097] For example, the third power supply 1018 is a 3.3V power supply.
[0098] The first terminal of the ninth resistor 1019 is connected to the third power supply 1018, and the second terminal of the ninth resistor 1019 is connected to the second signal pin; the first terminal of the tenth resistor 1020 is connected to the third power supply 1018, and the second terminal of the tenth resistor 1020 is connected to the inverting input terminal of the second voltage comparator 1011; the first terminal of the eleventh resistor 1021 is grounded, and the second terminal of the eleventh resistor 1021 is connected to the inverting input terminal of the second voltage comparator 1011; the first terminal of the twelfth resistor 1022 is connected to the third power supply 1018, and the second terminal of the twelfth resistor 1022 is connected to the output terminal of the second voltage comparator 1011.
[0099] The ninth resistor 1019 uses the voltage provided by the third power supply 1018 to keep the source of the third NMOS transistor 1010 at the target level.
[0100] The tenth resistor 1020 and the eleventh resistor 1021, based on the voltage provided by the third power supply 1018, cause the inverting input of the second voltage comparator 1011 to be at the second reference voltage.
[0101] The twelfth resistor 1022 stabilizes the voltage at the output of the second voltage comparator 1011 at the output voltage of the third power supply 1018 based on the voltage provided by the third power supply 1018.
[0102] For example, the ninth resistor 1019 acts as a pull-up resistor, providing a stable level to the source of the third NMOS transistor 1010 and the second signal pin based on the 3.3V power supply of the third power supply 1018. This ensures that when the third NMOS transistor 1010 is turned off, the level of the second signal pin can quickly stabilize to the target high level, guaranteeing the reliability of the optical module's normal operating mode switching. The tenth resistor 1020 and the eleventh resistor 1021 form a precise voltage divider circuit. Through a reasonable resistance ratio (e.g., using a combination of 2kΩ and 6.34kΩ), the 3.3V voltage of the third power supply 1018 is divided, stabilizing the circuit's preset reference voltage (e.g., 2.5V) at the inverting input of the second voltage comparator 1011. The twelfth resistor 1022 is a pull-up resistor, using the power supply of the third power supply 1018 to stabilize and clamp the output voltage of the second voltage comparator 1011 at 3.3V, preventing the second expansion chip 108 from being falsely triggered due to a floating comparator output level, and ensuring the stability and accuracy of the optical module's on-state feedback signal.
[0103] The signal processing circuit provided in this application embodiment further includes a second expansion chip, a second NMOS transistor, a third NMOS transistor, and a second voltage comparator. A first terminal of the second expansion chip is connected to the gate of the second NMOS transistor; the drain of the second NMOS transistor is connected to the gate of the third NMOS transistor, and the source of the second NMOS transistor is grounded; the source of the third NMOS transistor is connected to a second signal pin, and the drain of the third NMOS transistor is connected to a second reference voltage of the circuit; the non-inverting input terminal of the second voltage comparator is connected to the second signal pin, the inverting input terminal of the second voltage comparator is connected to the second reference voltage of the circuit, and the output terminal of the second voltage comparator is connected to a second terminal connected to the second expansion chip. The second expansion chip is used to send a second control signal to the optical module, the second control signal being used to put the optical module into a target mode and to put the gate of the second NMOS transistor into a target level state. The second NMOS transistor is used to be in a cutoff state or a conduction state when its gate is in the target level state. The third NMOS transistor is used to be in a cutoff state or a conduction state when its gate is in the target level state. The second voltage comparator is used to obtain a voltage comparison result based on the output voltage of the optical module and the second reference voltage, so that the second expansion chip can determine whether the optical module is in place based on the voltage comparison result. This technical solution integrates the low-power and normal mode switching of the optical module, as well as the presence status detection function, through the collaborative architecture of the second expansion chip, two NMOS transistors and the second voltage comparator. It eliminates the need for discrete circuits, simplifies the hardware structure, reduces complexity and maintenance costs, and ensures accurate mode switching and reliable presence determination.
[0104] For example, Table 1 is a schematic diagram of the optical module operating mode determination corresponding to different signals provided in the embodiments of this application:
[0105] Table 1:
[0106]
[0107] Figure 5 This is a schematic diagram of the structure of the switch provided in the embodiments of this application, such as... Figure 5 As shown, the switch is connected to the optical module, and the switch is equipped with the following: Figure 1 or Figure 2 The signal processing circuit is shown. The circuit structure and performance of this switch are as described above. Figure 1 or Figure 2 As shown in the embodiments, they will not be described here.
[0108] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.
Claims
1. A signal processing circuit, connected to an optical module, characterized in that, The circuit includes: a first expansion chip, a first NMOS transistor, and a first voltage comparator; The first terminal of the first expansion chip is connected to the gate of the first NMOS transistor; the drain of the first NMOS transistor is connected to the optical module and the inverting input of the first voltage comparator, respectively, and the source of the first NMOS transistor is grounded; the non-inverting input of the first voltage comparator is connected to the first reference voltage of the circuit; the output of the first voltage comparator is connected to the second terminal of the first expansion chip. The first expansion chip is used to send a first control signal to the first NMOS transistor, and the first control signal is used to put the first NMOS transistor into a cut-off state or a conduction state. The first NMOS transistor is used to control itself to be in the cut-off state or the conduction state based on the first control signal, so that the optical module is in the target reset state; The first voltage comparator is used to obtain a voltage comparison result based on the output voltage of the optical module and the first reference voltage, so that the first expansion chip can determine whether the optical module is in an interrupted or normal state based on the voltage comparison result.
2. The circuit according to claim 1, characterized in that, The circuit also includes a first power supply, a first resistor, and a second resistor; the first end of the first resistor and the first end of the second resistor are both grounded; the second end of the first resistor is connected to the gate of the first NMOS transistor; the second end of the second resistor is connected to the first signal pin of the optical module and the inverting input of the first voltage comparator, respectively. The first resistor is used to pull the gate of the first NMOS transistor low to a low level when the first control signal is low, so that the first NMOS transistor is in the cut-off state. The second resistor is used to pull the first signal pin low to a low level when the first NMOS transistor is in the on state.
3. The circuit according to claim 2, characterized in that, The circuit further includes a third resistor and a fourth resistor; the first and second ends of the third resistor are respectively connected to the first power supply and the positive input terminal of the first voltage comparator; the first end of the fourth resistor is grounded, and the second end of the fourth resistor is connected to the positive input terminal of the first voltage comparator. The fourth resistor works in conjunction with the third resistor to ensure that the voltage provided by the first power supply is a preset first reference voltage.
4. The circuit according to claim 1, characterized in that, The circuit also includes: a second extension chip, a second NMOS transistor, a third NMOS transistor, and a second voltage comparator; The first terminal of the second expansion chip is connected to the gate of the second NMOS transistor; the drain of the second NMOS transistor is connected to the gate of the third NMOS transistor, and the source of the second NMOS transistor is grounded; the source of the third NMOS transistor is connected to the second signal pin, and the drain of the third NMOS transistor is connected to the second reference voltage of the circuit; the non-inverting input terminal of the second voltage comparator is connected to the second signal pin, the inverting input terminal of the second voltage comparator is connected to the second reference voltage of the circuit, and the output terminal of the second voltage comparator is connected to the second terminal of the second expansion chip. The second expansion chip is used to send a second control signal to the optical module. The second control signal is used to put the optical module into the target mode and to put the gate of the second NMOS transistor into the target level state. The second NMOS transistor is used to make the second NMOS transistor either in a cutoff state or a conduction state when the gate of the second NMOS transistor is at the target level state; The third NMOS transistor is used to make the third NMOS transistor either in a cutoff state or a conduction state when the gate of the third NMOS transistor is in the target level state. The second voltage comparator is used to obtain a voltage comparison result based on the output voltage of the optical module and the second reference voltage, so that the second expansion chip can determine whether the optical module is in place based on the voltage comparison result.
5. The circuit according to claim 4, characterized in that, The circuit also includes a first power supply, a second power supply, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor; The first end of the fifth resistor is connected to the first power supply, and the second end of the fifth resistor is connected to the gate of the second NMOS transistor; the first end of the sixth resistor is connected to the second power supply, and the second end of the sixth resistor is connected to the gate of the third NMOS transistor; the first end of the seventh resistor is connected to the first power supply, and the second end of the seventh resistor is connected to the drain of the third NMOS transistor; the first end of the eighth resistor is connected to the second signal pin, and the second end of the eighth resistor is connected to the source of the third NMOS transistor. The fifth resistor, based on the first power supply, causes the gate of the second NMOS transistor to be in a target level state; The sixth resistor, based on the second power supply, causes the gate of the third NMOS transistor to be in a target level state; The seventh resistor and the eighth resistor are used to bring the inverting input of the second voltage comparator to the second reference voltage.
6. The circuit according to claim 5, characterized in that, The circuit also includes a third power supply, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor; The first end of the ninth resistor is connected to the third power supply, and the second end of the ninth resistor is connected to the second signal pin; the first end of the tenth resistor is connected to the third power supply, and the second end of the tenth resistor is connected to the inverting input of the second voltage comparator; the first end of the eleventh resistor is grounded, and the second end of the eleventh resistor is connected to the inverting input of the second voltage comparator; the first end of the twelfth resistor is connected to the third power supply, and the second end of the twelfth resistor is connected to the output of the second voltage comparator. The ninth resistor, based on the voltage provided by the third power supply, keeps the source of the third NMOS transistor at the target level. The tenth resistor and the eleventh resistor, based on the voltage provided by the third power supply, cause the inverting input of the second voltage comparator to be at the second reference voltage; The twelfth resistor stabilizes the voltage at the output of the second voltage comparator at the output voltage of the third power supply based on the voltage provided by the third power supply.
7. The circuit according to claim 1, characterized in that, The target reset state is either a reset state or a de-reset state.
8. The circuit according to claim 6, characterized in that, The target mode is either a low-power mode or a normal mode.
9. The circuit according to claim 6, characterized in that, The target level state is either high level or low level.
10. A switch, connected to an optical module, characterized in that, The switch is equipped with a signal processing circuit as described in any one of claims 1-9.