Semiconductor device

Abstract

A semiconductor device includes: an active pattern disposed on a substrate; a source / drain pattern disposed on the active pattern; a channel pattern disposed on the active pattern and connected to the source / drain pattern; a gate electrode disposed on the channel pattern; an active contact disposed on the source / drain pattern; an interlayer insulating layer disposed on the gate electrode; a wiring layer disposed on the interlayer insulating layer and including a plurality of lines; and a node connection pattern connected to a gate electrode on one active pattern and an active contact on the other active pattern. The interlayer insulating layer is provided between the wiring layer and the node connection pattern to insulate the node connection pattern from the wiring layer. A height of an upper surface of the node connection pattern is different from a height of an upper surface of other active contacts not connected to the node connection pattern.

Description

Technical Field

[0001] The embodiments of this disclosure described herein relate to semiconductor devices and methods of manufacturing the same, and more specifically, to an SRAM cell of a semiconductor device and a method of manufacturing the semiconductor device. Background Technology

[0002] Semiconductor devices include integrated circuits with metal-oxide-semiconductor field-effect transistors (MOSFETs). As the size and design rules of semiconductor devices continue to shrink, the size reduction of MOSFETs and the wiring structures connected to them is also accelerating. Therefore, various methods are being investigated to more easily fabricate semiconductor devices while overcoming the limitations associated with their high integration density. Summary of the Invention

[0003] Embodiments of this disclosure provide semiconductor devices with reduced dimensions.

[0004] The embodiments of this disclosure provide a method for easily manufacturing semiconductor devices.

[0005] According to an embodiment, a semiconductor device includes: an active pattern disposed on a front surface of a substrate; a source / drain pattern disposed on the active pattern; a channel pattern disposed on the active pattern and connected to the source / drain pattern; a gate electrode disposed on the channel pattern; an active contact disposed on the source / drain pattern; an interlayer insulating layer disposed on the gate electrode; a first wiring layer disposed on the interlayer insulating layer and including a plurality of lines; and a node connection pattern connected to the gate electrode located on one of the active patterns and the active contact located on another active pattern. The interlayer insulating layer is disposed between the first wiring layer and the node connection pattern to insulate the node connection pattern from the first wiring layer. The height of the upper surface of the node connection pattern is different from the height of the upper surfaces of other active contacts not connected to the node connection pattern.

[0006] According to an embodiment, a semiconductor device includes: a first active pattern and a second active pattern, the first active pattern and the second active pattern being disposed on a PMOS region of a substrate; a third active pattern and a fourth active pattern, the third active pattern and the fourth active pattern being disposed on an NMOS region of the substrate; a first source / drain pattern, a second source / drain pattern, a third source / drain pattern and a fourth source / drain pattern, the first source / drain pattern, the second source / drain pattern, the third source / drain pattern and the fourth source / drain pattern being disposed on the first active pattern, the second active pattern, the third active pattern and the fourth active pattern; an active contact, the active contact being disposed on the first source / drain pattern to the fourth source / drain pattern; a first channel pattern, a second channel pattern, a third channel pattern and a fourth channel pattern, the first channel pattern, the second channel pattern, the third channel pattern and the fourth channel pattern being disposed on the substrate. On a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern; a first common gate electrode, which intersects with and covers the first and third active patterns; a second common gate electrode, which intersects with and covers the second and fourth active patterns; a first node contact, which connects the second common gate electrode and an active contact on the first source / drain pattern adjacent to the second common gate electrode; a second node contact, which connects the first common gate electrode and an active contact on the second source / drain pattern adjacent to the first common gate electrode; an interlayer insulating layer, which is disposed on the first common gate electrode and the second common gate electrode; and a first wiring layer, which is disposed on the interlayer insulating layer and includes multiple wirings. The height of the upper surface of the first node contact and the second node contact is different from the height of the upper surface of other active contacts not connected to the first node contact and the second node contact.

[0007] According to an embodiment, a semiconductor device includes: an active pattern disposed on a front surface of a substrate; a source / drain pattern disposed on the active pattern; a channel pattern disposed on the active pattern and connected to the source / drain pattern; a gate electrode disposed on the channel pattern; an active contact disposed on the source / drain pattern; an interlayer insulating layer disposed on the gate electrode; a wiring layer disposed on the interlayer insulating layer and including a plurality of lines; and a node connection pattern connected to the gate electrode located on one of the active patterns and the active contact located on another active pattern. The interlayer insulating layer is disposed between the wiring layer and the node connection pattern, and the active contact connected to the node connection pattern protrudes further than one of the active contacts not connected to the node connection pattern relative to the substrate.

[0008] According to an embodiment, a method of manufacturing a semiconductor device includes: forming an active pattern on a substrate, a source / drain pattern disposed on the active pattern, a channel pattern connected to the source / drain pattern, a gate electrode disposed on the channel pattern, and an active contact disposed on the source / drain pattern; removing a portion of the gate electrode and a portion of the active pattern to form a via, the portion of the gate electrode and the portion of the active pattern being exposed through the via; filling the via to form a node connection pattern; forming pillars on the node connection pattern; etching the active contact and the gate electrode using the pillars as a mask to form a recessed region; forming an interlayer insulating layer to fill the recessed region; removing the pillars; filling the region where the pillars were removed with an insulating material; and forming a first wiring layer on the interlayer insulating layer.

[0009] According to embodiments, a semiconductor device with reduced size is provided. Furthermore, a method for easily manufacturing the semiconductor device is provided. Attached Figure Description

[0010] The above and other objects and features of this disclosure will become clear from the detailed description of embodiments thereof with reference to the accompanying drawings.

[0011] Figure 1 This is an equivalent circuit diagram illustrating an SRAM cell of a semiconductor device according to an embodiment of the present disclosure; Figure 2 This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure; Figures 3A to 3D They are respectively along Figure 2Cross-sectional views taken from lines A-A', B-B', C-C', and D-D'; Figure 4A It is shown Figure 3A Enlarged cross-sectional view of part P1; Figure 4B It is shown Figure 3C A magnified cross-sectional view of part P2; Figure 5 This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure; Figures 6A to 6D They are respectively along Figure 5 Cross-sectional views taken from lines A-A', B-B', C-C', and D-D'; Figure 7 This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure; Figures 8A to 8D They are respectively along Figure 7 Cross-sectional views taken from lines A-A', B-B', C-C', and D-D'; Figure 9 This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure; Figures 10A to 10D They are respectively along Figure 9 Cross-sectional views taken from lines A-A', B-B', C-C', and D-D'; Figure 11 This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure; Figures 12A to 12D They are respectively along Figure 11 Cross-sectional views taken from lines A-A', B-B', C-C', and D-D'; Figure 13 This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure; Figures 14A to 14D They are respectively along Figure 13 Cross-sectional views taken from lines A-A', B-B', C-C', and D-D'; Figures 15 to 37D This is a view showing, in sequence, a method of manufacturing a semiconductor device according to embodiments of the present disclosure. Detailed Implementation

[0012] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0013] Figure 1 This is an equivalent circuit diagram illustrating an SRAM cell according to an embodiment of the present disclosure. (Refer to...) Figure 1An SRAM cell according to embodiments of this disclosure may include a first pull-up transistor TU1, a first pull-down transistor TD1, a second pull-up transistor TU2, a second pull-down transistor TD2, a first access transistor TA1, and a second access transistor TA2. The first pull-up transistor TU1 and the second pull-up transistor TU2 may be PMOS transistors. The first pull-down transistor TD1, the second pull-down transistor TD2, and the first access transistor TA1 and the second access transistor TA2 may be NMOS transistors.

[0014] The first source / drain of the first pull-up transistor TU1 and the first source / drain of the first pull-down transistor TD1 can be connected to the first node N1. The second source / drain of the first pull-up transistor TU1 can be connected to the power supply line Vdd, and the second source / drain of the first pull-down transistor TD1 can be connected to the ground line Vss. The gates of the first pull-up transistor TU1 and the first pull-down transistor TD1 can be electrically connected to each other. The first pull-up transistor TU1 and the first pull-down transistor TD1 can form a first inverter. The gates of the first pull-up transistor TU1 and the first pull-down transistor TD1 connected to each other can correspond to the input terminals of the first inverter, and the first node N1 can correspond to the output terminals of the first inverter.

[0015] The first source / drain of the second pull-up transistor TU2 and the first source / drain of the second pull-down transistor TD2 can be connected to the second node N2. The second source / drain of the second pull-up transistor TU2 can be connected to the power supply line Vdd, and the second source / drain of the second pull-down transistor TD2 can be connected to the ground line Vss. The gates of the second pull-up transistor TU2 and the second pull-down transistor TD2 can be electrically connected to each other. Accordingly, the second pull-up transistor TU2 and the second pull-down transistor TD2 can form a second inverter. The gates of the second pull-up transistor TU2 and the second pull-down transistor TD2 connected to each other can correspond to the input terminals of the second inverter, and the second node N2 can correspond to the output terminals of the second inverter.

[0016] The first inverter and the second inverter can be coupled to each other to form a latch structure. That is, the gates of the first pull-up transistor TU1 and the first pull-down transistor TD1 can be electrically connected to the second node N2, and the gates of the second pull-up transistor TU2 and the second pull-down transistor TD2 can be electrically connected to the first node N1. The first source / drain of the first access transistor TA1 can be connected to the first node N1, and the second source / drain of the first access transistor TA1 can be connected to the first bit line BL1. The first source / drain of the second access transistor TA2 can be connected to the second node N2, and the second source / drain of the second access transistor TA2 can be connected to the second bit line BL2. The gates of the first access transistor TA1 and the second access transistor TA2 can be electrically connected to the word line WL. Therefore, an SRAM cell according to this disclosure can be implemented.

[0017] Figure 2 This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure, and shows corresponding to... Figure 1 The circuit diagram of the SRAM cell. Figures 3A to 3D They are respectively along Figure 2 The cross-sectional views taken from lines A-A', B-B', C-C' and D-D'.

[0018] refer to Figure 1 , Figure 2 and Figures 3A to 3D SRAM cells can be disposed on substrate 100.

[0019] According to embodiments of this disclosure, multiple SRAM cells may be disposed on substrate 100; however, in the following figures, only one SRAM cell is shown for ease of explanation. When viewed in a plane, the SRAM cells may be arranged in a matrix on substrate 100, and two SRAM cells adjacent to each other in the row direction and / or column direction may have a mirror-symmetric shape.

[0020] Substrate 100 may be a semiconductor substrate or a compound semiconductor substrate, including silicon, germanium, silicon-germanium, etc. Substrate 100 may include, but is not limited to, single-crystal semiconductor materials, such as Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In an embodiment, substrate 100 may be a silicon substrate.

[0021] The first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 can be defined by a trench TR formed in the substrate 100. The first active pattern AP1 and the second active pattern AP2 can correspond to a PMOS transistor region, and the third active pattern AP3 and the fourth active pattern AP4 can correspond to an NMOS transistor region. The first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 can extend in a second direction D2. The first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 can be part of the substrate 100 and can protrude vertically. The first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 can be arranged along the first direction D1 in the order of third active pattern AP3, first active pattern AP1, second active pattern AP2, and fourth active pattern AP4, and can be spaced apart from each other by a predetermined distance.

[0022] The first channel pattern CH1, located below the second gate electrode GE2, forms the channel region of the first pull-up transistor TU1. The third channel pattern CH3, located below the second gate electrode GE2, forms the channel region of the first pull-down transistor TD1. The third channel pattern CH3, located below the first gate electrode GE1, forms the channel region of the first access transistor TA1. The second channel pattern CH2, located below the third gate electrode GE3, forms the channel region of the second pull-up transistor TU2. The fourth channel pattern CH4, located below the third gate electrode GE3, forms the channel region of the second pull-down transistor TD2. The fourth channel pattern CH4, located below the fourth gate electrode GE4, forms the channel region of the second access transistor TA2.

[0023] The device isolation layer ST can fill the trench TR. The device isolation layer ST can include a silicon oxide layer. The upper portions of the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 can protrude vertically above the device isolation layer ST. The device isolation layer ST may not cover the upper portions of the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4. The device isolation layer ST may cover the lower surfaces of the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4.

[0024] The first channel pattern CH1, the second channel pattern CH2, the third channel pattern CH3, and the fourth channel pattern CH4 can be disposed above the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4, respectively. The first channel pattern CH1 and the second channel pattern CH2 can be disposed in the PMOS transistor regions where the first active pattern AP1 and the second active pattern AP2 are disposed, and the third channel pattern CH3 and the fourth channel pattern CH4 can be disposed in the NMOS transistor regions where the third active pattern AP3 and the fourth active pattern AP4 are disposed. Each of the first channel pattern CH1, the second channel pattern CH2, the third channel pattern CH3, and the fourth channel pattern CH4 can include a first semiconductor pattern S1, a second semiconductor pattern S2, a third semiconductor pattern S3, and a fourth semiconductor pattern S4 stacked sequentially. The first semiconductor pattern S1, the second semiconductor pattern S2, the third semiconductor pattern S3, and the fourth semiconductor pattern S4 can be spaced apart from each other in the vertical direction (i.e., the third direction D3).

[0025] Each of the first semiconductor pattern S1, the second semiconductor pattern S2, the third semiconductor pattern S3, and the fourth semiconductor pattern S4 may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). As an example, each of the first semiconductor pattern S1, the second semiconductor pattern S2, the third semiconductor pattern S3, and the fourth semiconductor pattern S4 may include crystalline silicon.

[0026] Multiple first recesses RC1 can be formed in the upper part of the first active pattern AP1. First source / drain patterns SD1 can be respectively disposed in the first recesses RC1. The first source / drain patterns SD1 can be impurity regions of a first conductivity type (e.g., p-type). A first channel pattern CH1 can be located between a pair of first source / drain patterns SD1. The first channel pattern CH1 can include a first semiconductor pattern S1, a second semiconductor pattern S2, a third semiconductor pattern S3, and a fourth semiconductor pattern S4 stacked on top of each other. A pair of first source / drain patterns SD1 can be connected to each other through the first channel pattern CH1.

[0027] Similarly, the second recess RC2, the third recess RC3, and the fourth recess RC4 can be formed in the upper portions of the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4, respectively. The second source / drain pattern SD2, the third source / drain pattern SD3, and the fourth source / drain pattern SD4 can be disposed in the second recess RC2, the third recess RC3, and the fourth recess RC4, respectively. The second source / drain pattern SD2 can be an impurity region of a first conductivity type (e.g., p-type). The third source / drain pattern SD3 and the fourth source / drain pattern SD4 can be impurity regions of a second conductivity type (e.g., N-type).

[0028] The first source / drain pattern SD1, the second source / drain pattern SD2, the third source / drain pattern SD3, and the fourth source / drain pattern SD4 can be epitaxial patterns formed by a selective epitaxial growth (SEG) process. As an example, the upper surface of each of the first source / drain pattern SD1, the second source / drain pattern SD2, the third source / drain pattern SD3, and the fourth source / drain pattern SD4 can be located at substantially the same height as the upper surface of the fourth semiconductor pattern S4, which is the uppermost semiconductor pattern. In an embodiment, the upper surface of each of the first source / drain pattern SD1, the second source / drain pattern SD2, the third source / drain pattern SD3, and the fourth source / drain pattern SD4 can be higher than the upper surface of the uppermost semiconductor pattern SP.

[0029] The first source / drain pattern SD1, the second source / drain pattern SD2, the third source / drain pattern SD3, and the fourth source / drain pattern SD4 may comprise the same semiconductor material as the substrate 100 or a different semiconductor material. The first source / drain pattern SD1 and the second source / drain pattern SD2 may comprise a semiconductor material (e.g., SiGe) with a lattice constant greater than that of the substrate 100. In this case, a pair of first source / drain patterns SD1 may apply compressive stress to a first channel pattern CH1 disposed therebetween. Furthermore, a pair of second source / drain patterns SD2 may apply compressive stress to a second channel pattern CH2 disposed therebetween. The third source / drain pattern SD3 and the fourth source / drain pattern SD4 may comprise the same semiconductor material as the substrate 100 (e.g., Si). As an example, the third source / drain pattern SD3 and the fourth source / drain pattern SD4 may comprise single-crystal silicon.

[0030] Although not shown in the figures, each first source / drain pattern SD1 may include a buffer layer covering the inner surface of the first recess RC1 and a main layer filling the remaining space of the first recess RC1. Furthermore, each second source / drain pattern SD2 may include a buffer layer covering the inner surface of the second recess RC2 and a main layer filling the remaining space of the second recess RC2.

[0031] The buffer layer may have a U-shape corresponding to the contour of each of the first recess RC1 and the second recess RC2. Each of the buffer layer and the main layer may include silicon germanium (SiGe). Specifically, the buffer layer may contain a relatively low concentration of germanium (Ge). In embodiments, the buffer layer may contain only silicon (Si) and no germanium (Ge). The germanium (Ge) concentration in the buffer layer may range from about 0 at% to about 10 at%. The main layer may contain a relatively high concentration of germanium (Ge). The germanium (Ge) concentration in the main layer may range from about 30 at% to about 70 at%. The germanium (Ge) concentration in the main layer may increase along the third direction D3. For example, the portion of the main layer adjacent to the buffer layer may have a germanium (Ge) concentration of about 40 at%, while the upper portion of the main layer may have a germanium (Ge) concentration of about 60 at%. The buffer layer and the main layer may contain p-type impurities (e.g., boron) that allow the first source / drain pattern SD1 and the second source / drain pattern SD2 to have p-type conductivity. The impurity concentration in the main layer (e.g., in atomic percentage) can be higher than that in the buffer layer.

[0032] The first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4 may intersect with the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4, and may extend in the first direction D1. When viewed in a plane, the first gate electrode GE1 may intersect with the third active pattern AP3, the second gate electrode GE2 may intersect with both the third active pattern AP3 and the first active pattern AP1, the third gate electrode GE3 may intersect with both the second active pattern AP2 and the fourth active pattern AP4, and the fourth gate electrode GE4 may intersect with the fourth active pattern AP4. In this disclosure, the second gate electrode GE2 may be referred to as the first common gate electrode, and the third gate electrode GE3 may be referred to as the second common gate electrode.

[0033] The first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4 may include at least one of a conductive metal nitride (e.g., titanium nitride or tantalum nitride) and a metallic material (e.g., titanium, tantalum, tungsten, copper, or aluminum).

[0034] The first gate electrode GE1 and the third gate electrode GE3 can be aligned with each other in the first direction D1. The second gate electrode GE2 and the fourth gate electrode GE4 can be aligned with each other in the first direction D1. The gap between the first gate electrode GE1 and the third gate electrode GE3 can be referred to as a gate dicing region, and a second interlayer insulating layer 120 including a gate dicing pattern GCT can be disposed in the gate dicing region to separate the first gate electrode GE1 and the third gate electrode GE3. Furthermore, the gap between the second gate electrode GE2 and the fourth gate electrode GE4 can be referred to as a gate dicing region, and a second interlayer insulating layer 120 including a gate dicing pattern GCT can be disposed in the gate dicing region to separate the second gate electrode GE2 and the fourth gate electrode GE4.

[0035] The first gate electrode GE1 may overlap perpendicularly with the third channel pattern CH3, and the second gate electrode GE2 may overlap perpendicularly with the third channel pattern CH3, the first channel pattern CH1, and the second channel pattern CH2 in the first direction D1. The third gate electrode GE3 may overlap perpendicularly with the first channel pattern CH1, the second channel pattern CH2, and the fourth channel pattern CH4, and the fourth gate electrode GE4 may overlap perpendicularly with the fourth channel pattern CH4.

[0036] The first gate electrode GE1 located above the third active pattern AP3 can be the gate of the first access transistor TA1. The second gate electrode GE2 located above the third active pattern AP3 can be the gate of the second pull-down transistor TD2, and the second gate electrode GE2 located above the first active pattern AP1 can be the gate of the first pull-up transistor TU1. The third gate electrode GE3 located above the second active pattern AP2 can be the gate of the second pull-up transistor TU2, and the third gate electrode GE3 located above the fourth active pattern AP4 can be the gate of the first pull-down transistor TD1. The fourth gate electrode GE4 located above the fourth active pattern AP4 can be the gate of the second access transistor TA2.

[0037] Each of the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4 may include: a first portion P1 between the substrate 100 and the first semiconductor pattern S1, a second portion P2 between the first semiconductor pattern S1 and the second semiconductor pattern S2, a third portion P3 between the second semiconductor pattern S2 and the third semiconductor pattern S3, a fourth portion P4 between the third semiconductor pattern S3 and the fourth semiconductor pattern S4, and a fifth portion P5 disposed on the fourth semiconductor pattern S4. In this embodiment, each of the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4 may be disposed on the upper surface, the bottom surface, and the opposite side surface of each of the first semiconductor pattern S1, the second semiconductor pattern S2, the third semiconductor pattern S3, and the fourth semiconductor pattern S4. In other words, the SRAM transistor according to this embodiment may be a three-dimensional field-effect transistor (e.g., an MBCFET) in which the gate electrode is configured to three-dimensionally surround the channel.

[0038] A pair of gate spacers GS may be disposed on opposite side surfaces of the fifth portion of each of the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4. The gate spacers GS may extend along the gate electrode GE and in a first direction D1. The gate spacers GS may include at least one of SiCN, SiCON, and SiN. In embodiments, the gate spacers GS may be a multilayer structure comprising at least two different materials selected from SiCN, SiCON, and SiN.

[0039] The gate insulating layer GI may be located between each of the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4 and each of the first channel pattern CH1, the second channel pattern CH2, the third channel pattern CH3, and the fourth channel pattern CH4. The gate insulating layer GI may cover the upper surface, bottom surface, and opposite side surface of each of the first semiconductor pattern S1, the second semiconductor pattern S2, the third semiconductor pattern S3, and the fourth semiconductor pattern S4. The gate insulating layer GI may cover the upper surface of the device insulating layer ST located below the gate electrode GE.

[0040] The gate insulating layer GI may include an interface layer that directly covers the surfaces of the first channel pattern CH1, the second channel pattern CH2, the third channel pattern CH3, and the fourth channel pattern CH4, and a high-k dielectric layer disposed on the interface layer. According to an embodiment, the thickness of the high-k dielectric layer may be greater than the thickness of the interface layer. The interface layer may include a silicon oxide layer or a silicon oxynitride layer.

[0041] The high-k dielectric layer may comprise a high-k dielectric material with a dielectric constant higher than that of silicon oxide. For example, the high-k dielectric material may comprise at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0042] Each of the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4 may include a first metal pattern, a second metal pattern, and an electrode pattern. The first metal pattern may be disposed on the gate insulating layer GI. As an example, the gate insulating layer GI may be disposed between the first metal pattern and the second channel pattern CH2.

[0043] The gate insulating layer GI and the first metal pattern can be chamfered, so that the upper portion of the gate insulating layer GI and the first metal pattern can be lower than the upper surface of the gate electrode GE. As an example, the first metal pattern may include a recessed upper surface, and the recessed upper surface may be lower than the lowest portion of the upper surface of the gate electrode GE.

[0044] The first metal pattern may include a metal nitride having a relatively high work function. In other words, the first metal pattern may include a p-type work function metal. As an example, the first metal pattern may include titanium nitride (TiN), tantalum nitride (TaN), titanium oxynitride (TiON), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tungsten carbonitride (WCN), or molybdenum nitride (MoN).

[0045] A second metal pattern may be disposed on the first metal pattern. The second metal pattern may cover the upper surface of the recess of the first metal pattern. The second metal pattern may include a metal carbide with a relatively low work function. In other words, the second metal pattern may include an N-type work function metal. The second metal pattern may include a silicon- and / or aluminum-doped metal carbide or a metal carbide containing silicon and / or aluminum. As an example, the second metal pattern may include aluminum-doped titanium carbide (TiAlC), aluminum-doped tantalum carbide (TaAlC), aluminum-doped vanadium carbide (ValC), silicon-doped titanium carbide (TiSiC), or silicon-doped tantalum carbide (TaSiC). In an embodiment, the second metal pattern may include aluminum-doped titanium (TiAl).

[0046] In the second metal pattern, the work function of the second metal pattern can be controlled by controlling the doping concentration of the dopant (e.g., silicon or aluminum). As an example, the concentration of the impurity (e.g., silicon or aluminum) in the second metal pattern can be in the range of about 0.1 at% to about 25 at%.

[0047] The electrode pattern can be disposed on the second metal pattern. The resistance of the electrode pattern can be lower than that of the first and second metal patterns. As an example, the electrode pattern may include at least one low-resistance metal selected from aluminum (Al), tungsten (W), titanium (Ti), and tantalum (Ta).

[0048] The internal spacer IP can be disposed between the first source / drain pattern SD1, the second source / drain pattern SD2, the third source / drain pattern SD3, and the fourth source / drain pattern SD4. The internal spacer IP can be located between the first portion P1 to the fifth portion P5 of some of the gate electrodes GE1, GE2, GE3, and GE4 and the first source / drain pattern SD1, SD2, SD3, and SD4. The internal spacer IP can be in direct contact with the first source / drain pattern SD1, SD2, SD3, and SD4, respectively. Each of the first portion P1, second portion P2, third portion P3, fourth portion P4, and fifth portion P5 of some gate electrodes may be spaced apart from each of the first source / drain patterns SD1, second source / drain pattern SD2, third source / drain pattern SD3, and fourth source / drain pattern SD4 by an internal spacer IP. The internal spacer IP may include one of SiN, SiCN, or SiOCN.

[0049] The first interlayer insulating layer 110 can be disposed above the substrate 100. The first interlayer insulating layer 110 can be disposed on the device isolation layer ST and can cover portions of the first source / drain pattern SD1, the second source / drain pattern SD2, the third source / drain pattern SD3 and the fourth source / drain pattern SD4.

[0050] A second interlayer insulating layer 120, including a gate dicing pattern GCT, may be disposed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may be disposed on a portion of the first interlayer insulating layer 110. For example, the second interlayer insulating layer 120 may be disposed in a region other than the region forming the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4, as well as the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0051] An active contact separation pattern ISN may be disposed on the first interlayer insulating layer 110. The active contact separation pattern ISN may be disposed in a region other than the regions forming the first active contact AC1, the second active contact AC2, the third active contact AC3, the fourth active contact AC4, the fifth active contact AC5, the sixth active contact AC6, the seventh active contact AC7, and the eighth active contact AC8, to isolate the first active contacts AC1 through the eighth active contacts AC8 from each other. The second interlayer insulating layer 120 may include one or more dielectric layers. According to an embodiment, the second interlayer insulating layer 120 may include one or more layers of SiO2, SiN, SiCN, SiOC, SiOCN, or other suitable dielectric materials.

[0052] The first active contact AC1 to the eighth active contact AC8 can be disposed on the first source / drain pattern SD1, the second source / drain pattern SD2, the third source / drain pattern SD3, and the fourth source / drain pattern SD4. The first active contact AC1 to the eighth active contact AC8 can be electrically connected to the corresponding source / drain pattern among the first source / drain pattern SD1, the second source / drain pattern SD2, the third source / drain pattern SD3, and the fourth source / drain pattern SD4.

[0053] Each of the first active contact AC1 to the eighth active contact AC8 can be a self-aligned contact. In other words, the first active contact AC1 to the eighth active contact AC8 can be formed in a self-aligned manner using the gate spacer GS.

[0054] The silicide pattern SC may be located between each of the first active contacts AC1 to the eighth active contacts AC8 and a corresponding source / drain pattern among the first source / drain patterns SD1, the second source / drain pattern SD2, the third source / drain pattern SD3, and the fourth source / drain pattern SD4. Each of the first active contacts AC1 to the eighth active contacts AC8 may be electrically connected to a corresponding source / drain pattern among the first source / drain patterns SD1, the second source / drain pattern SD2, the third source / drain pattern SD3, and the fourth source / drain pattern SD4 via the silicide pattern SC. The silicide pattern SC may include a metal silicide, for example, it may include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0055] Each of the first active contacts AC1 to the eighth active contacts AC8 may include a conductive pattern CP and a blocking pattern BP surrounding the conductive pattern CP. As an example, the conductive pattern CP may include at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt. The blocking pattern BP may cover the side and bottom surfaces of the conductive pattern CP. The blocking pattern BP may include a metal layer / metal nitride layer. The metal layer may include at least one selected from titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may include at least one selected from titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0056] In the first active contacts AC1 to the eighth active contacts AC8, spacers SP can be disposed on the outer surface of the blocking pattern BP. Spacers SP can cover the side surfaces of the active contacts, such that a portion of spacers SP is disposed between the active contacts and the interlayer insulating layer 130. Spacers SP can be formed on the upper surfaces of the first source / drain patterns SD1, the second source / drain pattern SD2, the third source / drain pattern SD3, and the fourth source / drain pattern SD4, which are not covered by the silicide pattern SC, and can be disposed between the blocking pattern BP and the gate spacer GS. Due to the spacers SP, the conductive pattern CP and the blocking pattern BP do not need to be in direct contact with the corresponding source / drain patterns.

[0057] Among the first active contacts AC1 to the eighth active contacts AC8, the upper surfaces of the first active contact AC1, the third active contact AC3, the fourth active contact AC4, the sixth active contact AC6, the seventh active contact AC7, and the eighth active contact AC8 can be coplanar with the upper surface of the second interlayer insulation layer 120 and the upper surface of the active contact separator pattern ISN. The upper surfaces of the second active contact AC2 and the fifth active contact AC5 can be located at a different height than the upper surfaces of the first active contact AC1, the third active contact AC3, the fourth active contact AC4, the sixth active contact AC6, the seventh active contact AC7, and the eighth active contact AC8. As an example, the upper surfaces of the second active contact AC2 and the fifth active contact AC5 can be located at a position higher than the upper surfaces of the first active contact AC1, the third active contact AC3, the fourth active contact AC4, the sixth active contact AC6, the seventh active contact AC7, and the eighth active contact AC8.

[0058] The first node connection pattern NP1 can be disposed on the third gate electrode GE3 and the second active contact AC2, and the second node connection pattern NP2 can be disposed on the second gate electrode GE2 and the fifth active contact AC5. The first node connection pattern NP1 can connect the third gate electrode GE3 and the second active contact AC2, and the second node connection pattern NP2 can connect the second gate electrode GE2 and the fifth active contact AC5. In this disclosure, the first node connection pattern NP1 can be referred to as the first node contact. Furthermore, the second node connection pattern NP2 can be referred to as the second node contact.

[0059] The first node connection pattern NP1 can correspond to Figure 1 The first node N1 connects the source / drain of the first pull-up transistor TU1 and the first pull-down transistor TD1 to the gate of the second pull-up transistor TU2 and the second pull-down transistor TD2.

[0060] The second node connection pattern NP2 can correspond to Figure 1 The second node N2 connects the source / drain of the second pull-up transistor TU2 and the second pull-down transistor TD2 to the gate of the first pull-up transistor TU1 and the first pull-down transistor TD1.

[0061] The third interlayer insulation layer 130 can be disposed on the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3 and the fourth gate electrode GE4, the first node connection pattern NP1, the second node connection pattern NP2 and the first active contact AC1 to the eighth active contact AC8.

[0062] The fourth interlayer insulation layer 140 can be disposed on the third interlayer insulation layer 130.

[0063] The first wiring layer M1 can be disposed within the fourth interlayer insulation layer 140. The first wiring layer M1 may include a word line WL, a first bit line BL1, a second bit line BL2, a power line Vdd, and a ground line Vss. One or more wiring layers may be disposed on the first wiring layer M1.

[0064] The first wiring layer M1 may include various conductive materials. The first wiring layer M1 may include at least one of conductive metal nitrides (e.g., titanium nitride or tantalum nitride) and metallic materials (e.g., titanium, tantalum, tungsten, copper or aluminum).

[0065] The first bit line BL1, the second bit line BL2, and the power line Vdd can extend along the second direction D2 and can be parallel to each other. The word line WL and the ground line Vss can be aligned parallel to each other along the second direction D2.

[0066] Each of the word line WL, the first bit line BL1, the second bit line BL2, the power line Vdd, and the ground line Vss can be electrically connected via a via TH defined through the third interlayer insulation layer 130 to a corresponding contact or electrode among the first active contacts AC1 to the eighth active contacts AC8 and the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4. A first passage V1 and a second passage V2 that are in contact with each other can be provided in each via. The first passage V1 can protrude upward from one of the first active contacts AC1 to the eighth active contacts AC8 and the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4, and the second passage V2 can protrude downward from the first wiring layer M1.

[0067] As an example, the word line WL can be connected to the first gate electrode GE1 and the fourth gate electrode GE4 via the via TH. The ground line Vss can be connected to the eighth active contact AC8 and the first active contact AC1 via the via TH. The power line Vdd can be connected to the sixth active contact AC6 and the fourth active contact AC4 via the via TH. The first bit line BL1 can be connected to the third active contact AC3 via the via TH, and the second bit line BL2 can be connected to the seventh active contact AC7 via the via TH.

[0068] Figure 4A It is shown Figure 3A A magnified cross-sectional view of part P1. Figure 4B It is shown Figure 3C A magnified cross-sectional view of part P2.

[0069] Reference Figure 1 , Figure 2 , Figures 3A to 3D , Figure 4A and Figure 4B The first node connection pattern NP1 and the second node connection pattern NP2 can be respectively set on the third gate electrode GE3 and the second gate electrode GE2.

[0070] The first node connection pattern NP1 can connect to the third gate electrode GE3 and the second active contact AC2. The first node connection pattern NP1 can have a strip extending in the second direction D2. When viewed in a plane, one end of the first node connection pattern NP1 can overlap with the third gate electrode GE3, and the other end of the first node connection pattern NP1 can overlap with the second active contact AC2. When viewed in a cross-section, a portion of one side surface and the lower surface of the first node connection pattern NP1 can contact the third gate electrode GE3, and another portion of the other side surface and the lower surface of the first node connection pattern NP1 can contact the second active contact AC2. As an example, the side surface of the first node connection pattern NP1 can directly contact the conductive pattern CP of the second active contact AC2, and the lower surface of the first node connection pattern NP1 can contact the conductive pattern CP and the blocking pattern BP of the second active contact AC2. The lower surface of the first node connection pattern NP1 can also contact the gate insulating layer GI and the gate spacer GS. The upper surface of the first node connection pattern NP1 can be coplanar with the upper surface of the third gate electrode GE3 and the upper surface of the second active contact AC2.

[0071] According to an embodiment, the first node connection pattern NP1 can be separately disposed from the third gate electrode GE3 and the second active contact AC2, and can contact each of the third gate electrode GE3 and the second active contact AC2. That is, the interface between the first node connection pattern NP1 and the third gate electrode GE3, and the interface between the first node connection pattern NP1 and the second active contact AC2, can be clearly present. However, according to an embodiment, the first node connection pattern NP1 can be combined with the third gate electrode GE3 and / or the second active contact AC2 through a single metal contact. As an example, according to an embodiment, the first node connection pattern NP1 can be combined with the second active contact AC2 through a single metal contact.

[0072] According to an embodiment, the first node connection pattern NP1 may include at least a portion of the same material as the second active contact AC2. As an example, the first node connection pattern NP1 may include the same material as the conductive pattern CP of the second active contact AC2.

[0073] The second node connection pattern NP2 can connect the second gate electrode GE2 and the fifth active contact AC5. The second node connection pattern NP2 can have a strip extending in the second direction D2. When viewed in a plane, one end of the second node connection pattern NP2 can overlap with the fifth active contact AC5, and the other end of the second node connection pattern NP2 can overlap with the second gate electrode GE2.

[0074] The second node connection pattern NP2 can contact each of the second gate electrode GE2 and the fifth active contact AC5. Alternatively, the second node connection pattern NP2 can be combined with the second gate electrode GE2 and / or the fifth active contact AC5 via a single metal contact.

[0075] Although not shown in the figure, when viewed in cross-section, a portion of one side surface and the lower surface of the second node connection pattern NP2 can contact the fifth active contact AC5, and another portion of the other side surface and the lower surface of the second node connection pattern NP2 can contact the second gate electrode GE2. According to an embodiment, the side surface of the second node connection pattern NP2 can directly contact the conductive pattern CP of the fifth active contact AC5, and the lower surface of the second node connection pattern NP2 can contact the conductive pattern CP and the blocking pattern BP of the fifth active contact AC5. The lower surface of the second node connection pattern NP2 can also contact the gate insulating layer GI and the gate spacer GS. The upper surface of the second node connection pattern NP2 can be coplanar with the upper surface of the second gate electrode GE2 and the upper surface of the fifth active contact AC5.

[0076] The second node connection pattern NP2 may include at least a portion of the same material as the fifth active contact AC5. As an example, the second node connection pattern NP2 may include the same material as the conductive pattern CP of the fifth active contact AC5.

[0077] The third interlayer insulating layer 130 can be disposed on the first node connection pattern NP1 and the second node connection pattern NP2, the first active contact AC1 to the eighth active contact AC8, and the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4. Specifically, the third interlayer insulating layer 130 can cover the upper surface of the first node connection pattern NP1 and the second node connection pattern NP2.

[0078] The third interlayer insulating layer 130 may include: a main interlayer insulating layer 130b disposed between the first wiring layer M1 and the first node connection pattern NP1 and the second node connection pattern NP2, and a recessed filling insulating layer 130a disposed below the main interlayer insulating layer 130b. The main interlayer insulating layer 130b may be disposed on the first node connection pattern NP1 and the second node connection pattern NP2, and the recessed filling insulating layer 130a may be disposed between the main interlayer insulating layer 130b and the upper surface of the gate electrode and active contact not connected to the first node connection pattern NP1 and the second node connection pattern NP2. In this embodiment, for ease of explanation, the third interlayer insulating layer 130 is shown as including the main interlayer insulating layer 130b and the recessed filling insulating layer 130a; however, the main interlayer insulating layer 130b and the recessed filling insulating layer 130a may be integrally formed with each other without being separate from each other. The recessed filling insulating layer 130a can be disposed in a recessed region RR that is recessed downward from the plane corresponding to the upper surface of the first node connection pattern NP1 and the second node connection pattern NP2. The recessed region RR can correspond to the region between the main interlayer insulating layer and the upper surfaces of the first to fourth gate electrodes GE1 to GE4 and the upper surfaces of the first active contact AC1 to the eighth active contact AC8.

[0079] A via TH perpendicularly penetrating the third interlayer insulating layer 130 can be disposed within the third interlayer insulating layer 130. A first path V1 and a second path V2 can be sequentially disposed in each via TH. The first path V1 in each via TH can be connected to one of the first active contacts AC1 to the eighth active contact AC8, and one of the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4; and the second path V2 in each via TH can be connected to one of the first wiring layers M1. The upper surface of the first path V1 can be substantially coplanar with the upper surfaces of the first node connection pattern NP1 and the second node connection pattern NP2. The upper surface of the second path V2 can be substantially coplanar with the upper surface of the third interlayer insulating layer 130.

[0080] Although not shown in the figures, in embodiments of this disclosure, the first node connection pattern NP1 and / or the second node connection pattern NP2 may include a conductive pattern and a blocking pattern surrounding the conductive pattern. In this case, the first node connection pattern NP1 and / or the second node connection pattern NP2 may include the same material as the blocking pattern BP and the conductive patterns of the first active contacts AC1 to the eighth active contacts AC8.

[0081] According to some embodiments, the first wiring layer M1 can be used for node connections on the circuitry of SRAM cells. That is, node connection lines may be needed to connect some gate electrodes and some active contacts, and the node connection lines can be some lines in the first wiring layer M1.

[0082] When a line is formed as the first wiring layer M1, the node connection line CCL is formed by... Figure 4A and Figure 4B The dashed line in the middle represents...

[0083] Reference Figure 4A and Figure 4B A node connection line CCL connecting the third gate electrode GE3 and the second active contact AC2 can be formed, and a node connection line CCL connecting the second gate electrode GE2 and the fifth active contact AC5 can also be formed. The node connection line CCL can be included in the first wiring layer M1 and formed on the third interlayer insulating layer 130 together with the first bit line BL1, the second bit line BL2, the word line WL, the power line Vdd, and the ground line Vss. In this embodiment, a portion of the gate electrode (e.g., the third gate electrode GE3) and a portion of the active contact (the second active contact AC2) connected by the node connection line CCL can be disposed below the third interlayer insulating layer 130. Therefore, to connect a portion of the gate electrode and a portion of the active contact, it is necessary to remove the gate spacer GS and other components. Furthermore, a process is required to form a connection path in the third interlayer insulating layer 130 by removing a portion of the third interlayer insulating layer 130. The process of removing a portion of the third interlayer insulating layer 130 implies the need for an additional masking process.

[0084] According to embodiments of this disclosure, the first node connection pattern NP1 and the second node connection pattern NP2 can connect a portion of the gate and a portion of the active pattern without connecting to the first wiring layer M1. That is, the first node connection pattern NP1 can be disposed separately from the first wiring layer M1 between the third gate electrode GE3 and the second active contact AC2, and can connect the third gate electrode GE3 and the second active contact AC2. Furthermore, the second node connection pattern NP2 can be disposed separately from the first wiring layer M1 between the second gate electrode GE2 and the fifth active contact AC5, and can connect the second gate electrode GE2 and the fifth active contact AC5. In this embodiment, when viewed in cross-section, the first node connection pattern NP1 and the second node connection pattern NP2 are physically and electrically insulated from the first wiring layer M1, and the third interlayer insulating layer 130 can be disposed between the first node connection pattern NP1 and the second node connection pattern NP2 and the first wiring layer M1. Therefore, according to this disclosure, the first node connection pattern NP1 and the second node connection pattern NP2 can be disposed below the third interlayer insulating layer 130, and the process of removing a portion of the third interlayer insulating layer 130 can be omitted. According to an embodiment, a pillar PL (referencing) is used to form pathways V1 and V2 connecting the gate electrode and the active contact. Figures 31A to 31DThe first wiring layer M1 and the first wiring layer M1 can easily form the first node connection pattern NP1 and the second node connection pattern NP2 instead of the node connection line CCL.

[0085] The semiconductor device according to the embodiments of the present disclosure can be modified in various forms without departing from the concept of the present disclosure.

[0086] Figure 5 This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure. Figures 6A to 6D They are respectively along Figure 5 The cross-sectional views taken from lines A-A', B-B', C-C' and D-D'.

[0087] According to this embodiment, the SRAM cell may include... Figure 2 and Figures 3A to 3D The components of the SRAM cell shown are substantially the same; however, the SRAM cell according to this embodiment differs from the above embodiment in the size and arrangement of some components. In the following description, for ease of explanation, the features that differ from the above embodiment will be primarily described.

[0088] refer to Figure 5 and Figures 6A to 6D The first active pattern AP1, the second active pattern AP2, the third active pattern AP3 and the fourth active pattern AP4 can be defined by the trench TR formed in the substrate 100.

[0089] The first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4 may intersect with the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4, and may extend in the first direction D1.

[0090] The first node connection pattern NP1 can be disposed on the third gate electrode GE3, and the second node connection pattern NP2 can be disposed on the second gate electrode GE2. The first node connection pattern NP1 can connect the third gate electrode GE3 and the second active contact AC2, and the second node connection pattern NP2 can connect the second gate electrode GE2 and the fifth active contact AC5.

[0091] The third interlayer insulation layer 130 can be disposed on the first node connection pattern NP1 and the second node connection pattern NP2. The fourth interlayer insulation layer 140 can be disposed on the third interlayer insulation layer 130, and the first wiring layer M1 can be disposed in the fourth interlayer insulation layer 140. The first wiring layer M1 may include a word line WL, a first bit line BL1, a second bit line BL2, a power line Vdd, and a ground line Vss.

[0092] In this embodiment, when viewed in a plane, at least one of the first node connection pattern NP1 and the second node connection pattern NP2 can overlap with at least one of the elements of the first wiring layer M1. As an example, the first node connection pattern NP1 can overlap with the first bit line BL1, and the second node connection pattern NP2 can overlap with the second bit line BL2. Figure 5 , Figure 6A and Figure 6B In the cross section, when observed, the area where the first node connection pattern NP1 overlaps with the first bit line BL1 and the area where the second node connection pattern NP2 overlaps with the second bit line BL2 are respectively designated as the first overlapping area OV1 and the second overlapping area OV2.

[0093] According to embodiments of this disclosure, it is not necessary to form separate node connection lines in the first wiring layer M1 to connect some gate electrodes and some active contacts. Since the node connection lines of the first wiring layer M1 are omitted, the gap between the first bit line BL1 and the power line, and the gap between the power line and the second bit line BL2, can be reduced. Furthermore, the first node connection pattern NP1 and the second node connection pattern NP2 can be formed to overlap with one or more lines in the first wiring layer M1. Therefore, the size of the SRAM cell, for example, the width of the SRAM cell in the first direction D1, can be reduced.

[0094] Figure 7 This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure. Figures 8A to 8D They are respectively along Figure 7 The cross-sectional views taken from lines A-A', B-B', C-C' and D-D'.

[0095] refer to Figure 7 and Figures 8A to 8D The first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 can be defined by trenches TR formed in the substrate 100. The first active pattern AP1 and the second active pattern AP2 can correspond to PMOS transistor regions, and the third active pattern AP3 and the fourth active pattern AP4 can correspond to NMOS transistor regions.

[0096] The first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 can extend in the second direction D2. The device isolation layer ST can fill the trench TR. The device isolation layer ST can penetrate the front and rear surfaces of the substrate 100. In order for the device isolation layer ST to penetrate the front and rear surfaces of the substrate 100, the substrate 100 can be patterned to form a trench TR with a selected depth in the substrate 100, the device isolation layer ST can be formed in the trench TR, and the rear surface of the substrate 100 can be patterned until the device isolation layer ST is exposed.

[0097] The first source / drain pattern SD1, the second source / drain pattern SD2, the third source / drain pattern SD3, and the fourth source / drain pattern SD4 can be connected to the word line WL, the first bit line BL1, the second bit line BL2, the ground line Vss, and the power line Vdd through corresponding active contacts. In this embodiment, the first wiring layer M1 may include the first bit line BL1, the second bit line BL2, the word line WL, and the ground line Vss, and the power line Vdd may not be included in the first wiring layer M1. Specifically, the first bit line BL1, the second bit line BL2, the word line WL, and the ground line Vss may be formed on the front surface of the substrate 100, and the power line Vdd may be formed on the rear surface of the substrate 100. In this embodiment, when the surface of the substrate 100 forming the transistor including the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3 and the fourth gate electrode GE4, and the first channel pattern CH1, the second channel pattern CH2, the third channel pattern CH3 and the fourth channel pattern CH4 is referred to as the front surface, the rear surface may be the surface opposite to the front surface.

[0098] Since the power line Vdd is formed on the rear surface of the substrate 100, the fourth active contact AC4 and the sixth active contact AC6, which are connected to the power line Vdd among the first active contacts AC1 to the eighth active contacts AC8 in the above embodiment, can have a rear surface active contact structure. A rear surface active contact structure refers to a line connecting the source / drain pattern to the rear surface of the substrate 100. The rear surface active contact structure may include: a fourth rear surface active contact AC4_B that connects one of the first source / drain patterns SD1 to the power line Vdd, and a sixth rear surface active contact AC6_B that connects one of the second source / drain patterns SD2 to the power line Vdd. The fourth rear surface active contact AC4_B and the sixth rear surface active contact AC6_B can be disposed in the substrate 100 and can extend along a third direction D3 from the rear surface of the substrate 100 to the lower part of the first source / drain pattern SD1.

[0099] One or more back surface wiring layers may be disposed on the back surface of substrate 100. A back surface wiring layer may include at least one wiring. For example, a back surface wiring layer may include a back-side power delivery network. A power line Vdd may be part of the back surface wiring layer, and specifically, may be part of the back-side power delivery network.

[0100] The power line Vdd may extend in the second direction D2. However, the direction in which the power line Vdd extends should not be limited to this, and the power line Vdd may extend in various directions depending on the configuration of the back-side power delivery network. The power line Vdd may include various conductive materials. The power line Vdd may include at least one of conductive metal nitrides (e.g., titanium nitride or tantalum nitride) and metallic materials (e.g., titanium, tantalum, tungsten, copper, or aluminum).

[0101] Each of the fourth rear surface active contact AC4_B and the sixth rear surface active contact AC6_B may include a conductive pattern CP and a blocking pattern BP.

[0102] A first back surface interlayer insulating layer 110B may be disposed between the power line Vdd and the back surface of the substrate 100. The power line Vdd may be electrically connected to the fourth back surface active contact AC4_B and the sixth back surface active contact AC6_B via a back surface path BV that penetrates the first back surface interlayer insulating layer 110B and is disposed in the first back surface interlayer insulating layer 110B. The wiring of the back surface wiring layer (e.g., the power line Vdd) may be electrically connected to one of the source / drain patterns via the back surface path BV.

[0103] According to this embodiment, the power line Vdd is disposed on the rear surface of the substrate 100; however, this disclosure is not limited thereto. According to an embodiment, another line of the first wiring layer M1 may be disposed on the rear surface of the substrate 100. As an example, the ground line Vss may be disposed on the rear surface. In this case, in addition to the line applying a power supply voltage to the power line Vdd, the power delivery network layer PDN may also include a line applying a ground voltage to the ground line Vss.

[0104] In addition to the power line Vdd, the word line WL, the first bit line BL1, the second bit line BL2, and the ground line Vss can be connected to the corresponding first source / drain pattern SD1, second source / drain pattern SD2, third source / drain pattern SD3, and fourth source / drain pattern SD4 through the first active contact AC1, the second active contact AC2, the third active contact AC3, the fifth active contact AC5, the seventh active contact AC7, and the eighth active contact AC8.

[0105] According to an embodiment, when viewed in a plane, at least one of the first node connection pattern NP1 and the second node connection pattern NP2 may overlap with at least one of the elements of the first wiring layer M1. As an example, the first node connection pattern NP1 may overlap with the first bit line BL1, and the second node connection pattern NP2 may overlap with the second bit line BL2.

[0106] According to this embodiment, since the power line Vdd is disposed on the rear surface, the gap between the lines of the first wiring layer M1 can be reduced. Specifically, since the power line Vdd is omitted from the lines of the first wiring layer M1, the gap between the first bit line BL1 and the second bit line BL2 can be reduced. Furthermore, since the first node connection pattern NP1 and the second node connection pattern NP2 overlap with some lines of the first wiring layer M1 (e.g., the first bit line BL1 and / or the second bit line BL2), the gap between the lines of the first wiring layer M1 can be further reduced. Therefore, the size of the SRAM cell, for example, the width of the SRAM cell in the first direction D1, can be reduced.

[0107] Figure 9 This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure. Figures 10A to 10D They are respectively along Figure 9 The cross-sectional views taken from lines A-A', B-B', C-C' and D-D'.

[0108] Reference Figure 9 and Figures 10A to 10D Semiconductor devices can have a forksheet structure. A forksheet structure can include a dielectric wall (FSW) that does not extend between two adjacent channel patterns of the source / drain.

[0109] The first active pattern AP1, the second active pattern AP2, the third active pattern AP3 and the fourth active pattern AP4 can be defined by the trench TR formed in the substrate 100.

[0110] The first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4 may intersect with the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4, and may extend in the first direction D1. The first active pattern AP1 and the second active pattern AP2 may be disposed in the PMOS transistor region, and the third active pattern AP3 and the fourth active pattern AP4 may be disposed in the NMOS transistor region. The first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 may extend in the second direction D2.

[0111] The first channel pattern CH1, the second channel pattern CH2, the third channel pattern CH3, and the fourth channel pattern CH4 can be disposed on the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4, respectively. That is, the first channel pattern CH1 and the second channel pattern CH2 can be disposed in the PMOS transistor region, and the third channel pattern CH3 and the fourth channel pattern CH4 can be disposed in the NMOS transistor region. Each of the first channel pattern CH1, the second channel pattern CH2, the third channel pattern CH3, and the fourth channel pattern CH4 can include a first semiconductor pattern S1, a second semiconductor pattern S2, a third semiconductor pattern S3, and a fourth semiconductor pattern S4 stacked sequentially. The first semiconductor pattern S1, the second semiconductor pattern S2, the third semiconductor pattern S3, and the fourth semiconductor pattern S4 can be spaced apart from each other in the vertical direction (i.e., the third direction D3).

[0112] The dielectric wall FSW can be disposed between some active regions and can extend in the second direction D2. The dielectric wall FSW can be disposed between a first active pattern AP1 formed in the PMOS transistor region and a third active pattern AP3 formed in the NMOS transistor region, and can also be disposed between a second active pattern AP2 formed in the PMOS transistor region and a fourth active pattern AP4 formed in the NMOS transistor region.

[0113] A dielectric wall FSW may include one or more dielectric layers. According to an embodiment, the dielectric wall FSW may include one or more layers comprising a low-k dielectric material. According to an embodiment, the dielectric wall FSW may include one or more layers comprising SiO2, SiN, SiCN, SiOC, SiOCN, or other suitable dielectric materials having a low dielectric constant. Although not shown in the figures, the dielectric wall FSW may include a dielectric pad layer and a dielectric filler layer. The dielectric pad layer may be formed of a dielectric material that can be selectively removed from the dielectric filler layer. According to an embodiment, the dielectric pad layer may be a SiN layer, and the dielectric filler layer may include SiO2.

[0114] The dielectric wall FSW can separate the channel pattern disposed in the PMOS transistor region and the channel pattern disposed in the NMOS transistor region. Specifically, the dielectric wall FSW can separate the first channel pattern CH1 from the third channel pattern CH3, and can separate the second channel pattern CH2 from the fourth channel pattern CH4.

[0115] Furthermore, the dielectric wall FSW can separate the gate electrodes from each other. Specifically, the dielectric wall FSW can separate the first gate electrode GE1 from the third gate electrode GE3, and can separate the second gate electrode GE2 from the fourth gate electrode GE4. Additionally, the dielectric wall FSW can divide the third gate electrode GE3 into two third sub-gate electrodes GE3a and GE3b, and can divide the second gate electrode GE2 into two second sub-gate electrodes GE2a and GE2b. The gate insulating layer GI can be located between the dielectric wall FSW and each gate electrode.

[0116] According to an embodiment, the dielectric wall FSW may comprise the same material as the second interlayer insulating layer 120. The dielectric wall FSW may be formed using the same process as the second interlayer insulating layer 120.

[0117] Two gate electrodes with a dielectric wall FSW in between and two channel patterns with a dielectric wall FSW in between can form a single fork structure together with the dielectric wall FSW.

[0118] The two second sub-gate electrodes GE2a and GE2b can be connected to each other via a bridge BR. The bridge BR can overlap with a portion of each of the second sub-gate electrodes GE2a and GE2b, and can be disposed on the dielectric wall FSW located between the second sub-gate electrodes GE2a and GE2b. In the same manner, the third sub-gate electrodes GE3a and GE3b can also be connected to each other via a bridge BR.

[0119] The gate insulating layer GI may be located between each of the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4 and each of the first channel pattern CH1, the second channel pattern CH2, the third channel pattern CH3, and the fourth channel pattern CH4. The gate insulating layer GI may cover the upper surface, bottom surface, and opposite side surface of each of the first semiconductor pattern S1, the second semiconductor pattern S2, the third semiconductor pattern S3, and the fourth semiconductor pattern S4. The gate insulating layer GI may cover the upper surface of the device isolation layer ST. In this embodiment, the gate insulating layer GI may not be disposed between the first channel pattern CH1 and the dielectric wall FSW.

[0120] Multiple first recesses RC1, multiple second recesses RC2, multiple third recesses RC3, and multiple fourth recesses RC4 can be formed on the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4, respectively. The first source / drain pattern SD1, the second source / drain pattern SD2, the third source / drain pattern SD3, and the fourth source / drain pattern SD4 can be respectively disposed in the first recesses RC1, the second recesses RC2, the third recesses RC3, and the fourth recesses RC4.

[0121] The first node connection pattern NP1 can be disposed on the third gate electrode GE3, and the second node connection pattern NP2 can be disposed on the second gate electrode GE2. The first node connection pattern NP1 can connect the third gate electrode GE3 and the second active contact AC2, and the second node connection pattern NP2 can connect the second gate electrode GE2 and the fifth active contact AC5.

[0122] According to an embodiment, the bridge BR connecting the second sub-gate electrodes GE2a and GE2b and the bridge BR connecting the third sub-gate electrodes GE3a and GE3b can be disposed at the same height as the first node connection pattern NP1 and the second node connection pattern NP2. According to an embodiment, the upper surfaces of the second sub-gate electrodes GE2a and GE2b and the third sub-gate electrodes GE3a and GE3b can be coplanar with the upper surfaces of the first node connection pattern NP1 and the second node connection pattern NP2.

[0123] The third interlayer insulation layer 130 can be disposed on the first node connection pattern NP1, the second node connection pattern NP2, and the bridge BR.

[0124] The fourth interlayer insulation layer 140 can be disposed on the third interlayer insulation layer 130, and the first wiring layer M1 can be disposed in the fourth interlayer insulation layer 140. The first wiring layer M1 may include a word line WL, a first bit line BL1, a second bit line BL2, a power line Vdd, and a ground line Vss.

[0125] According to embodiments of this disclosure, since the transistors constituting the semiconductor device have a forked structure, the distance between adjacent gate electrodes and between adjacent channel patterns can be reduced. Furthermore, since the first node connection pattern NP1 and the second node connection pattern NP2 overlap with a portion of the first wiring layer M1 (e.g., the first bit line BL1 and / or the second bit line BL2), the gap between lines in the first wiring layer M1 can be further reduced. Therefore, the size of the SRAM cell, for example, the width of the SRAM cell in the first direction D1, can be reduced.

[0126] Figure 11 This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure. Figures 12A to 12D They are along Figure 11 The cross-sectional views taken from lines A-A', B-B', C-C' and D-D'.

[0127] Reference Figure 11 and Figures 12A to 12D Semiconductor devices may have a fork structure, but may be provided in a structure different from the embodiments described above.

[0128] The first active pattern AP1, the second active pattern AP2, the third active pattern AP3 and the fourth active pattern AP4 can be defined by a trench TR formed in the substrate 100.

[0129] The first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4 may intersect with the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4, and may extend in the first direction D1. The first active pattern AP1 and the second active pattern AP2 may be disposed in the PMOS transistor region, and the third active pattern AP3 and the fourth active pattern AP4 may be disposed in the NMOS transistor region. The first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 may extend in the second direction D2.

[0130] The first channel pattern CH1, the second channel pattern CH2, the third channel pattern CH3, and the fourth channel pattern CH4 can be disposed on the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4, respectively. That is, the first channel pattern CH1 and the second channel pattern CH2 can be disposed in the PMOS transistor region, and the third channel pattern CH3 and the fourth channel pattern CH4 can be disposed in the NMOS transistor region. Each of the first channel pattern CH1, the second channel pattern CH2, the third channel pattern CH3, and the fourth channel pattern CH4 can include a first semiconductor pattern S1, a second semiconductor pattern S2, a third semiconductor pattern S3, and a fourth semiconductor pattern S4 stacked sequentially. The first semiconductor pattern S1, the second semiconductor pattern S2, the third semiconductor pattern S3, and the fourth semiconductor pattern S4 can be spaced apart from each other in the vertical direction (i.e., the third direction D3).

[0131] The dielectric wall FSW can be disposed between some active regions and can extend in the second direction D2. The dielectric wall FSW can be disposed between a first active pattern AP1 formed in the PMOS transistor region and a second active pattern AP2 formed in the PMOS transistor region.

[0132] According to an embodiment, the dielectric wall FSW can be disposed between the third active pattern AP3 and the third active pattern AP4 formed in the NMOS transistor region, which are adjacent cells with mirror-symmetric shapes. Furthermore, the dielectric wall FSW can be disposed between the fourth active pattern AP4 and the fourth active pattern AP4 formed in the NMOS transistor region, which are adjacent cells with mirror-symmetric shapes.

[0133] The dielectric wall FSW can be disposed on the device isolation layer ST, and can separate the channel pattern disposed in the PMOS transistor region from the channel pattern disposed in the NMOS transistor region. Specifically, each dielectric wall FSW can separate the first channel pattern CH1 from the third channel pattern CH3, and can separate the second channel pattern CH2 from the fourth channel pattern CH4.

[0134] Furthermore, the dielectric wall FSW can separate the gate electrodes from each other. Specifically, the dielectric wall FSW can separate the first gate electrode GE1 from the third gate electrode GE3, and can separate the second gate electrode GE2 from the fourth gate electrode GE4. Additionally, the dielectric wall FSW can divide the third gate electrode GE3 into two third sub-gate electrodes GE3a and GE3b, and can divide the second gate electrode GE2 into two second sub-gate electrodes GE2a and GE2b. The gate insulating layer GI can be located between the dielectric wall FSW and each corresponding gate electrode.

[0135] Two gate electrodes with a dielectric wall FSW in between and two channel patterns with a dielectric wall FSW in between can form a single fork structure together with the dielectric wall FSW.

[0136] The two second sub-gate electrodes GE2a and GE2b can be connected to each other via a bridge BR. The bridge BR can overlap with a portion of each of the second sub-gate electrodes GE2a and GE2b, and can be disposed on the dielectric wall FSW located between the second sub-gate electrodes GE2a and GE2b. In the same manner, the third sub-gate electrodes GE3a and GE3b can also be connected to each other via a bridge BR.

[0137] The gate insulating layer GI may be located between each of the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4 and each of the first channel pattern CH1, the second channel pattern CH2, the third channel pattern CH3, and the fourth channel pattern CH4. The gate insulating layer GI may cover the upper surface, bottom surface, and opposite side surface of each of the first semiconductor pattern S1, the second semiconductor pattern S2, the third semiconductor pattern S3, and the fourth semiconductor pattern S4. The gate insulating layer GI may cover the upper surface of the device isolation layer ST. In this embodiment, the gate insulating layer GI may not be disposed between the first channel pattern CH1 and the dielectric wall FSW.

[0138] Multiple first recesses RC1, multiple second recesses RC2, multiple third recesses RC3, and multiple fourth recesses RC4 can be formed on the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4, respectively. The first source / drain pattern SD1, the second source / drain pattern SD2, the third source / drain pattern SD3, and the fourth source / drain pattern SD4 can be respectively disposed in the first recesses RC1, the second recesses RC2, the third recesses RC3, and the fourth recesses RC4.

[0139] The first node connection pattern NP1 can be disposed on the third gate electrode GE3, and the second node connection pattern NP2 can be disposed on the second gate electrode GE2. The first node connection pattern NP1 can connect the third gate electrode GE3 and the second active contact AC2, and the second node connection pattern NP2 can connect the second gate electrode GE2 and the fifth active contact AC5.

[0140] According to an embodiment, the bridge BR connecting the second sub-gate electrodes GE2a and GE2b to each other, and the bridge BR connecting the third sub-gate electrodes GE3a and GE3b to each other, can be disposed at the same height as the first node connection pattern NP1 and the second node connection pattern NP2. According to an embodiment, the upper surfaces of the second sub-gate electrodes GE2a and GE2b and the third sub-gate electrodes GE3a and GE3b can be coplanar with the upper surfaces of the first node connection pattern NP1 and the second node connection pattern NP2.

[0141] The third interlayer insulation layer 130 can be disposed on the first node connection pattern NP1, the second node connection pattern NP2, and the bridge BR.

[0142] The fourth interlayer insulation layer 140 can be disposed on the third interlayer insulation layer 130, and the first wiring layer M1 can be disposed in the fourth interlayer insulation layer 140. The first wiring layer M1 may include a word line WL, a first bit line BL1, a second bit line BL2, a power line Vdd, and a ground line Vss.

[0143] According to embodiments of this disclosure, since the transistors constituting the semiconductor device have a forked structure, the distance between adjacent gate electrodes and between adjacent channel patterns can be reduced. Furthermore, since the first node connection pattern NP1 and the second node connection pattern NP2 overlap with a portion of the first wiring layer M1 (e.g., the first bit line BL1 and / or the second bit line BL2), the gap between lines in the first wiring layer M1 can be further reduced. As a result, the size of the SRAM cell can be reduced, for example, the width of the SRAM cell in the first direction D1.

[0144] In this embodiment, only one SRAM cell is shown for ease of explanation; however, this disclosure should not be limited thereto. A semiconductor device may include multiple SRAM cells, and two SRAM cells adjacent to each other in the row direction and / or column direction may have a mirror-symmetric shape relative to each other. Furthermore, two adjacent SRAM cells may share a portion of a fork structure. As an example, the dielectric wall FSW disposed at the uppermost position relative to the first direction D1 may be part of the fork structure of another cell disposed above in the first direction D1. Similarly, the dielectric wall FSW disposed at the lowermost position relative to the first direction D1 may be part of the fork structure of another cell disposed below in the first direction D1.

[0145] Figure 13 This is a plan view illustrating a semiconductor device according to an embodiment of the present disclosure. Figures 14A to 14D They are respectively along Figure 13 The cross-sectional views taken from lines A-A', B-B', C-C' and D-D'.

[0146] Reference Figure 13 and Figures 14A to 14D Semiconductor devices may have a fork structure, but may be provided in a structure different from the embodiments described above.

[0147] The first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 can be defined by a trench TR formed in the substrate 100. The first active pattern AP1 and the second active pattern AP2 can be disposed in the PMOS transistor region, and the third active pattern AP3 and the fourth active pattern AP4 can be disposed in the NMOS transistor region.

[0148] The first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 can extend in the second direction D2. The device isolation layer ST can fill the trench TR. The device isolation layer ST can penetrate the front and rear surfaces of the substrate 100. In order for the device isolation layer ST to penetrate the front and rear surfaces of the substrate 100, the substrate 100 can be patterned to form a trench TR with a selected depth in the substrate 100, the device isolation layer ST can be formed in the trench TR, and the rear surface of the substrate 100 can be patterned until the device isolation layer ST is exposed.

[0149] The first channel pattern CH1, the second channel pattern CH2, the third channel pattern CH3, and the fourth channel pattern CH4 can be disposed on the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4, respectively. That is, the first channel pattern CH1 and the second channel pattern CH2 can be disposed in the PMOS transistor region, and the third channel pattern CH3 and the fourth channel pattern CH4 can be disposed in the NMOS transistor region. Each of the first channel pattern CH1, the second channel pattern CH2, the third channel pattern CH3, and the fourth channel pattern CH4 can include a first semiconductor pattern S1, a second semiconductor pattern S2, a third semiconductor pattern S3, and a fourth semiconductor pattern S4 stacked sequentially.

[0150] The dielectric wall FSW can be disposed between some active regions and can extend in the second direction D2. The dielectric wall FSW can be disposed between a first active pattern AP1 disposed in the PMOS transistor region and a second active pattern AP2 disposed in the PMOS transistor region.

[0151] According to an embodiment, the dielectric wall FSW can be disposed between the third active pattern AP3 and the third active pattern AP4 formed in the NMOS transistor region, which are adjacent cells with mirror-symmetric shapes. Furthermore, the dielectric wall FSW can be disposed between the fourth active pattern AP4 and the fourth active pattern AP4 formed in the NMOS transistor region, which are adjacent cells with mirror-symmetric shapes.

[0152] The dielectric wall FSW can be disposed on the device isolation layer ST, and can separate the channel pattern disposed in the PMOS transistor region from the channel pattern disposed in the NMOS transistor region. Specifically, the dielectric wall FSW can separate the first channel pattern CH1 from the third channel pattern CH3, and can separate the second channel pattern CH2 from the third channel pattern CH3.

[0153] Furthermore, the dielectric wall FSW can separate the gate electrodes from each other. Specifically, the dielectric wall FSW can separate the first gate electrode GE1 from the third gate electrode GE3, and can separate the second gate electrode GE2 from the fourth gate electrode GE4. Additionally, the dielectric wall FSW can divide the third gate electrode GE3 into two third sub-gate electrodes GE3a and GE3b, and can divide the second gate electrode GE2 into two second sub-gate electrodes GE2a and GE2b. The gate insulating layer GI can be located between the dielectric wall FSW and each gate electrode.

[0154] Two gate electrodes with a dielectric wall FSW in between and two channel patterns with a dielectric wall FSW in between can form a single fork structure together with the dielectric wall FSW.

[0155] The two second sub-gate electrodes GE2a and GE2b can be connected to each other via a bridge BR. The bridge BR can overlap with a portion of each of the second sub-gate electrodes GE2a and GE2b, and can be disposed on the dielectric wall FSW located between the second sub-gate electrodes GE2a and GE2b. In the same manner, the third sub-gate electrodes GE3a and GE3b can also be connected to each other via a bridge BR.

[0156] The gate insulating layer GI may be located between each of the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4 and each of the first channel pattern CH1, the second channel pattern CH2, the third channel pattern CH3, and the fourth channel pattern CH4. The gate insulating layer GI may cover the upper surface, bottom surface, and opposite side surface of each of the first semiconductor pattern S1, the second semiconductor pattern S2, the third semiconductor pattern S3, and the fourth semiconductor pattern S4. The gate insulating layer GI may cover the upper surface of the device isolation layer ST. In this embodiment, the gate insulating layer GI may not be disposed between the first channel pattern CH1 and the dielectric wall FSW.

[0157] Multiple first recesses RC1, multiple second recesses RC2, multiple third recesses RC3, and multiple fourth recesses RC4 can be formed on the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4, respectively. The first source / drain pattern SD1, the second source / drain pattern SD2, the third source / drain pattern SD3, and the fourth source / drain pattern SD4 can be respectively disposed in the first recesses RC1, the second recesses RC2, the third recesses RC3, and the fourth recesses RC4.

[0158] The first node connection pattern NP1 can be disposed on the third gate electrode GE3, and the second node connection pattern NP2 can be disposed on the second gate electrode GE2. The first node connection pattern NP1 can connect the third gate electrode GE3 and the second active contact AC2, and the second node connection pattern NP2 can connect the second gate electrode GE2 and the fifth active contact AC5.

[0159] The first source / drain pattern SD1, the second source / drain pattern SD2, the third source / drain pattern SD3, and the fourth source / drain pattern SD4 can be connected to the word line WL, the first bit line BL1, the second bit line BL2, the ground line Vss, and the power line Vdd through multiple active contacts. In this embodiment, the first wiring layer M1 may include the first bit line BL1, the second bit line BL2, the word line WL, and the ground line Vss, and the power line Vdd may not be included in the first wiring layer M1. Specifically, the first bit line BL1, the second bit line BL2, the word line WL, and the ground line Vss may be formed on the front surface of the substrate 100, and the power line Vdd may be formed on the rear surface of the substrate 100.

[0160] Since the power line Vdd is formed on the back surface of the substrate 100, the fourth active contact AC4 and the sixth active contact AC6, which are connected to the power line Vdd among the first active contacts AC1 to the eighth active contacts AC8, can have a back surface active contact structure.

[0161] One or more back surface wiring layers may be disposed on the back surface of substrate 100. The back surface wiring layers may include a back-side power delivery network. Power lines Vdd may be part of the back surface wiring layers, and specifically, may be part of the back-side power delivery network.

[0162] The first rear surface interlayer insulating layer 110B can be disposed between the power line Vdd and the rear surface of the substrate 100. The power line Vdd can be electrically connected to the fourth rear surface active contact AC4_B and the sixth rear surface active contact AC6_B through a rear surface path that penetrates the rear surface of the first rear surface interlayer insulating layer 110B and is disposed in the first rear surface interlayer insulating layer 110B.

[0163] According to this embodiment, the power line Vdd is disposed on the rear surface of the substrate 100; however, this disclosure is not limited thereto. According to an embodiment, another line of the first wiring layer M1 may be disposed on the rear surface of the substrate 100. As an example, the ground line Vss may be disposed on the rear surface. In this case, in addition to the line that applies a power supply voltage to the power line Vdd, the power delivery network layer PDN may also include a line that applies a ground voltage to the ground line Vss.

[0164] According to this embodiment, since the semiconductor device has a fork structure and the power line Vdd is disposed on the rear surface, the gap between the lines of the first wiring layer M1 can be further reduced, and the size of the SRAM cell can be reduced, for example, the width of the SRAM cell in the first direction D1.

[0165] Hereinafter, a method for manufacturing a semiconductor device according to embodiments of the present disclosure will be described. Reference will be made to representative examples. Figure 1 , Figure 2 and Figures 3A to 3D The embodiments shown are used to describe a method for manufacturing a semiconductor device in order to avoid redundancy in the explanation.

[0166] refer to Figure 15 and Figures 16A to 16D The first semiconductor layer SM1 and the second semiconductor layer SM2 may be stacked alternately on the substrate 100. The second semiconductor layer SM2 may comprise a material having etch selectivity or a different oxidation rate relative to the first semiconductor layer SM1. The number of the first semiconductor layer SM1 and the number of the second semiconductor layer SM2 may be greater than or less than the numbers shown.

[0167] The first semiconductor layer SM1 may include one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and the second semiconductor layer SM2 may include another of silicon (Si), germanium (Ge), and silicon-germanium (SiGe). As an example, the first semiconductor layer SM1 may include silicon (Si), and the second semiconductor layer SM2 may include silicon-germanium (SiGe). The germanium (Ge) concentration in each second semiconductor layer SM2 may be in the range of about 10 at% to about 30 at%.

[0168] The first semiconductor layer SM1 and the second semiconductor layer SM2 can be formed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD) and / or other suitable epitaxial growth processes.

[0169] The mask pattern can be formed over the PMOS transistor region and the NMOS transistor region of the substrate 100. The mask pattern can have a line or strip shape extending in the second direction D2.

[0170] A patterning process can be performed using a mask pattern as an etching mask to form a trench TR defining a first active pattern AP1, a second active pattern AP2, a third active pattern AP3, and a fourth active pattern AP4. The trench TR can be formed between the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4. Due to the trench TR, the first active pattern AP1 and the second active pattern AP2 can be formed in the PMOS transistor region, and the third active pattern AP3 and the fourth active pattern AP4 can be formed in the NMOS transistor region. When viewed in a plane, the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 can extend parallel to each other in a second direction D2 and can have a stripe shape. The first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 can be arranged along the first direction D1 in the order of the third active pattern AP3, the first active pattern AP1, the second active pattern AP2, and the fourth active pattern AP4, and can be spaced apart from each other.

[0171] A stacked pattern STP can be formed on each of the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4. The stacked pattern STP may include alternately stacked first semiconductor layer SM1 and second semiconductor layer SM2. The stacked pattern STP can be formed together during the process of forming the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4.

[0172] A device isolation layer ST can be formed to fill the trench TR. Specifically, an insulating layer can be formed on the front surface of the substrate 100 to cover the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4, as well as the stacked pattern STP. The insulating layer can be recessed until the stacked pattern STP is exposed, and thus the device isolation layer ST can be formed. The device isolation layer ST can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), or other suitable deposition processes.

[0173] The device isolation layer ST may comprise silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, or a combination thereof. According to an embodiment, the device isolation layer ST may comprise a silicon oxide layer. A stacked pattern STP may be exposed above the device isolation layer ST. In other words, the stacked pattern STP may protrude vertically above the device isolation layer ST.

[0174] refer to Figure 17 and Figures 18A to 18DA sacrificial pattern SF can be formed on the substrate 100 to intersect with the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4. The sacrificial pattern SF can include various materials, for example, it can include polycrystalline silicon.

[0175] Each sacrificial pattern SF may have a line or strip shape extending in a first direction D1. The sacrificial pattern SF may include a gate sacrificial pattern SF1 and a dummy sacrificial pattern SF2. The gate sacrificial pattern SF1 may be formed in the region where the gate electrode is to be formed. The gate sacrificial pattern SF1 may cover the top and side surfaces of the stacked pattern STP. The dummy sacrificial pattern SF2 may cover the side surfaces of the stacked pattern STP in the region where the gate sacrificial pattern SF1 is not formed.

[0176] Specifically, the formation of the sacrificial pattern SF may include: forming a sacrificial layer on the front surface of the substrate 100, forming a hard mask pattern MP on the sacrificial layer, and using the hard mask pattern MP as an etch mask to pattern the sacrificial layer. The sacrificial layer may be deposited using CVD, PVD, ALD, or other suitable processes, including LPCVD and PECVD. A portion of the sacrificial layer may be removed by a plasma dry etching process and / or a wet etching process. In some embodiments, the sacrificial layer may comprise polysilicon. When the sacrificial layer comprises polysilicon, a wet etching process may be performed to selectively remove portions of the sacrificial layer, and various etching solutions may be used, such as tetramethylammonium hydroxide (TMAH) solution.

[0177] A pair of gate spacers GS can be formed on opposite side surfaces of each sacrificial pattern SF. Forming the gate spacers GS may include: conformally forming a gate spacer layer on the front surface of the substrate 100, and anisotropically etching the gate spacer layer. The gate spacer layer may include at least one of SiCN, SiCON, and SiN. In embodiments, the gate spacer layer may have a multilayer structure of at least two of SiCN, SiCON, and SiN.

[0178] The first recess RC1 can be formed in the stacked pattern STP on the first active pattern AP1. The second recess RC2 can be formed in the stacked pattern STP on the second active pattern AP2, and in the same manner, the third recess RS3 and the fourth recess RS4 can be formed in the stacked patterns STP on the third active pattern AP3 and the fourth active pattern AP4, respectively. Specifically, the stacked patterns STP on the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 can be etched using a hard mask pattern MP and a gate spacer GS as an etching mask to form the first recess RC1, the second recess RC2, the third recess RC3, and the fourth recess RC4. The first recess RC1 can be formed between a pair of sacrificial patterns SF. The second recess RC2, the third recess RC3, and the fourth recess RC4 in the stacked patterns STP on the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4 can be formed using the same method as the first recess RC1. The first recess RC1, the second recess RC2, the third recess RC3 and the fourth recess RC4 can be formed by a dry etching process and / or a wet etching process suitable for removing the first semiconductor layer SM1 and the second semiconductor layer SM2 together or separately.

[0179] A first semiconductor pattern S1, a second semiconductor pattern S2, a third semiconductor pattern S3, and a fourth semiconductor pattern S4, sequentially stacked between adjacent first recesses RC1, can be formed by a first semiconductor layer SM1. Similarly, a first semiconductor pattern S1, a second semiconductor pattern S2, a third semiconductor pattern S3, and a fourth semiconductor pattern S4, sequentially stacked between adjacent second recesses RC2, can be formed by the first semiconductor layer SM1. Likewise, a first semiconductor pattern S1, a second semiconductor pattern S2, a third semiconductor pattern S3, and a fourth semiconductor pattern S4, sequentially stacked between adjacent third recesses RC3 and adjacent fourth recesses RC4, can be formed by the first semiconductor layer SM1.

[0180] The first source / drain pattern SD1 can be formed in the first recess RC1. The first source / drain pattern SD1 can be formed on each side of the gate sacrificial pattern SF1 in the sacrificial pattern SF, either on one side or the opposite side. Specifically, a first SEG process using the inner sidewall of the first recess RC1 as a seed layer can be performed to form a buffer layer. The first semiconductor pattern S1, the second semiconductor pattern S2, the third semiconductor pattern S3, and the fourth semiconductor pattern S4 exposed by the first recess RC1, as well as the substrate 100, can be used as seed layers to grow the buffer layer. As an example, the first SEG process can include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0181] The buffer layer may include a semiconductor material (e.g., SiGe) with a lattice constant greater than that of the substrate 100. The buffer layer may include a relatively low concentration of germanium (Ge). The germanium concentration of the buffer layer may range from about 0 at% to about 10 at%. In embodiments, the buffer layer may consist only of silicon (Si) and exclude germanium (Ge).

[0182] A second SEG process can be performed on the buffer layer to form the main layer. The main layer can be formed to completely or almost completely fill the first recess RC1. The main layer may include a relatively high concentration of germanium (G3). In embodiments, the germanium concentration of the main layer may be in the range of about 30 at% to about 70 at%.

[0183] During the formation of the buffer layer and the main layer, impurities (e.g., boron, gallium, or indium) that give the first source / drain pattern SD1 P-type conductivity can be implanted into the first source / drain pattern SD1 using an in-situ method. In an embodiment, impurities can be implanted into the first source / drain pattern SD1 after its formation.

[0184] In the same manner as the first source / drain pattern SD1, the second source / drain pattern SD2 can be formed in the second recess RC2.

[0185] The third source / drain pattern SD3 can be formed in the third recess RS3. The third source / drain pattern SD3 can be formed on each side opposite to the gate sacrificial pattern SF1 in the sacrificial pattern SF. Specifically, the third source / drain pattern SD3 can be formed by performing a selective epitaxial growth (SEG) process using the inner sidewall of the third recess RS3 as a seed layer. As an example, the third source / drain pattern SD3 can include the same semiconductor material as the substrate 100, such as Si.

[0186] During the formation of the third source / drain pattern SD3, impurities (e.g., phosphorus, arsenic, or antimony) that give the third source / drain pattern SD3 N-type conductivity can be implanted into the third source / drain pattern SD3 using an in-situ method. In an embodiment, impurities can be implanted into the third source / drain pattern SD3 after its formation.

[0187] In the same manner as the third source / drain pattern SD3, the fourth source / drain pattern SD4 can be formed in the fourth recess RC4.

[0188] According to embodiments of this disclosure, before forming the first source / drain pattern SD1, the second source / drain pattern SD2, the third source / drain pattern SD3, and the fourth source / drain pattern SD4, a portion of the second semiconductor layer SM2 exposed through the first recess RC1, the second recess RC2, the third recess RC3, and the fourth recess RC4 can be replaced with an insulating material to form an internal spacer IP. Therefore, the internal spacer IP can be formed between each of the first source / drain pattern SD1, the second source / drain pattern SD2, the third source / drain pattern SD3, and the fourth source / drain pattern SD4 and the second semiconductor layer SM2, respectively.

[0189] According to embodiments of this disclosure, the first source / drain pattern SD1, the second source / drain pattern SD2, the third source / drain pattern SD3, and the fourth source / drain pattern SD4 can be formed sequentially using different processes. In other words, the first source / drain pattern SD1, the second source / drain pattern SD2, the third source / drain pattern SD3, and the fourth source / drain pattern SD4 can be formed substantially at different times.

[0190] When forming the first source / drain pattern SD1, a first channel pattern CH1 can be defined between a pair of first source / drain patterns SD1. When forming the second source / drain pattern SD2, a second channel pattern CH2 can be defined between a pair of second source / drain patterns SD2. When forming the third source / drain pattern SD3, a third channel pattern CH3 can be defined between a pair of third source / drain patterns SD3. When forming the fourth source / drain pattern SD4, a fourth channel pattern CH4 can be defined between a pair of fourth source / drain patterns SD4.

[0191] Reference Figure 17 and Figures 19A to 19D The first interlayer insulating layer 110 can be formed to cover a first source / drain pattern SD1, a second source / drain pattern SD2, a third source / drain pattern SD3, a fourth source / drain pattern SD4, a hard mask pattern MP, and a gate spacer GS. As an example, the first interlayer insulating layer 110 may include a silicon oxide layer. The first interlayer insulating layer 110 may include a contact etch-prevention layer and an interlayer dielectric layer. The contact etch-prevention layer may include Si3N4, SiON, SiCN, or any other suitable material, and can be formed by CVD, PVD, or ALD processes. The interlayer dielectric layer may include compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC.

[0192] The first interlayer insulating layer 110 can be planarized until the upper surface of the sacrificial pattern SF is exposed. Planarization of the first interlayer insulating layer 110 can be performed by etch-back or chemical mechanical polishing (CMP) processes. The hard mask pattern MP can be removed during the planarization process. Therefore, the upper surface of the first interlayer insulating layer 110 can be coplanar with the upper surface of the sacrificial pattern SF and the upper surface of the gate spacer GS.

[0193] The sacrificial pattern SF can then be selectively removed using photolithography. When the sacrificial pattern SF is selectively removed, an external region OR exposing the first channel pattern CH1 and the second channel pattern CH2 can be formed. The sacrificial pattern SF can then be removed using a wet etching process. In the wet etching process, an etchant for selectively etching polysilicon can be used.

[0194] Then, the second semiconductor layer SM2 exposed through the outer region OR can be selectively removed, thus forming the inner region IR. The outer region OR can be the region that meets the upper region of the fourth semiconductor pattern S4 and the side surfaces of the first semiconductor pattern S1, the second semiconductor pattern S2, the third semiconductor pattern S3, and the fourth semiconductor pattern S4. The inner region IR can be the region between the substrate 100 and the first semiconductor pattern S1, and between the first semiconductor patterns S1, the second semiconductor pattern S2, the third semiconductor pattern S4, and the fourth semiconductor pattern S4 that are adjacent to each other. Specifically, an etching process that selectively etches the second semiconductor layer SM2 can be performed, and thus, only the second semiconductor layer SM2 can be removed, while the first semiconductor pattern S1, the second semiconductor pattern S2, the third semiconductor pattern S3, and the fourth semiconductor pattern S4 remain intact. The etching process can have a high etching rate for silicon-germanium with a relatively high germanium concentration. As an example, for silicon-germanium with a germanium concentration higher than about 10 at%, the etching process can have a high etching rate. At the same time, due to the buffer layer with a relatively low germanium concentration, the first source / drain pattern SD1 can be protected during the etching process. According to an embodiment, a wet etchant can be used to selectively etch the second semiconductor layer SM2. The wet etchant includes, but is not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution.

[0195] When the second semiconductor layer SM2 is selectively etched, only the first semiconductor pattern S1, the second semiconductor pattern S2, the third semiconductor pattern S3, and the fourth semiconductor pattern S4 stacked on top of each other can remain on each of the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4.

[0196] refer to Figure 20 and Figures 21A to 21DThe sacrificial pattern SF can be replaced by a gate pattern GP and a dummy gate pattern DM. Specifically, the gate pattern GP can be formed in the region where the gate sacrificial pattern SF1 is formed, and the dummy gate pattern DM can be formed in the region where the dummy sacrificial pattern SF2 is formed.

[0197] The internal spacer IP can be formed in the internal regions of the first active pattern AP1, the second active pattern AP2, the third active pattern AP3, and the fourth active pattern AP4. The internal spacer IP can be formed by forming an insulating layer covering the first source / drain pattern SD1, the second source / drain pattern SD2, the third source / drain pattern SD3, and the fourth source / drain pattern SD4, and then etching the insulating layer. The internal spacer IP can include at least one of SiO2, SiN, SiC, SiOC, and AlOx.

[0198] The gate insulating layer GI can be conformally formed in the inner region IR (see [reference]). Figure 19C and Figure 19D ) and the external region OR exposed above the first active pattern AP1, the second active pattern AP2, the third active pattern AP3 and the fourth active pattern AP4.

[0199] The gate insulating layer GI may include an interface layer and a high-k dielectric layer located on the interface layer. The high-k dielectric layer may be thicker than the interface layer. The interface layer may include a silicon oxide layer or a silicon oxynitride layer. The high-k dielectric layer may include a high-k material with a dielectric constant higher than that of silicon oxide. As an example, the high-k material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0200] A gate pattern GP and a dummy gate pattern DM can be formed on a gate insulating layer GI. The gate pattern GP and the dummy gate pattern DM can be formed to fill an outer region OR and an inner region IR. Each of the gate pattern GP and the dummy gate pattern DM may include a first portion P1, a second portion P2, a third portion P3, and a fourth portion P4 formed in the inner region IR, and a fifth portion P5 formed in the outer region OR, respectively.

[0201] The gate pattern GP may include a first metal pattern, a second metal pattern, and an electrode pattern. The first metal pattern may be formed on the gate insulating layer GI. The second metal pattern may be disposed on the first metal pattern. The second metal pattern may include a metal carbide having a relatively low work function. The electrode pattern may be disposed on the second metal pattern. The resistance of the electrode pattern may be lower than the resistance of the first metal pattern and the second metal pattern.

[0202] refer to Figure 22 and Figures 23A to 23D A second interlayer insulating layer 120 may be formed on the substrate 100. Prior to forming the second interlayer insulating layer 120, recesses may be formed for forming a gate dicing pattern in the gate dicing region. Furthermore, recesses may be formed in the region where a dummy gate pattern DM is formed to remove the dummy gate pattern DM. According to an embodiment, the recesses may be formed using a dry etching process; however, this disclosure is not limited thereto, and the recesses may be formed using other suitable processes. The bottom surface of the recesses in the gate dicing region and the region where the dummy gate pattern DM is formed may be positioned below the upper surface of the device isolation layer ST.

[0203] An insulating material can be provided in the recess and on the substrate 100 to form a second interlayer insulating layer 120. A gate dicing pattern GCT can be formed in the gate dicing region, and a dummy gate pattern DM can be removed. Through the gate dicing pattern GCT, the gate pattern GP can be divided into a first gate electrode GE1, a second gate electrode GE2, a third gate electrode GE3, and a fourth gate electrode GE4.

[0204] refer to Figure 22 and Figures 24A to 24D The second interlayer insulating layer 120 can be planarized until the upper surfaces of the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4, as well as the upper surface of the first interlayer insulating layer 110, are exposed. Planarization of the second interlayer insulating layer 120 can be performed by etching back or chemical mechanical polishing (CMP) processes. Therefore, the upper surface of the second interlayer insulating layer 120 can be coplanar with the upper surfaces of the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4, as well as the upper surface of the first interlayer insulating layer 110.

[0205] Reference Figure 22 and Figures 25A to 25D It can form an active contact separation pattern (ISN).

[0206] An active contact separator pattern (ISN) can be formed by creating multiple recesses in the first interlayer insulating layer 110 and filling the recesses with an insulating material. The active contact separator pattern (ISN) may include SiO2, SiN, SiC, SiOC, and AlO. x At least one of them.

[0207] The active contact separator pattern ISN can be planarized until the upper surface of the first interlayer insulating layer 110 is exposed. Planarization of the active contact separator pattern ISN can be performed using an etch-back process or a chemical mechanical polishing (CMP) process. Therefore, the upper surface of the active contact separator pattern ISN can be coplanar with the upper surface of the first interlayer insulating layer 110. The lower surface of the active contact separator pattern ISN can be positioned above the upper surface of the device isolation layer ST and below the upper surfaces of the first source / drain patterns SD1 to the fourth source / drain patterns SD4.

[0208] Reference Figure 26 and Figures 27A to 27D The first interlayer insulating layer 110 disposed between the active contact separator patterns ISN can be removed to expose the first source / drain patterns SD1 to the fourth source / drain patterns SD4. Then, the first active contact AC1 to the eighth active contact AC8 can be formed on the first source / drain patterns SD1 to the fourth source / drain patterns SD4.

[0209] The formation of the first active contact AC1 to the eighth active contact AC8 may include forming a barrier pattern BP and forming a conductive pattern CP on the barrier pattern BP. The barrier pattern BP may be formed conformally and may include a metal layer / metal nitride layer. The conductive pattern CP may include a low-resistance metal.

[0210] Forming the first active contact AC1 through the eighth active contact AC8 may include sequentially forming a barrier pattern BP and a conductive pattern CP and performing a planarization process. The planarization process may be performed until the upper surfaces of the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4 are exposed. The barrier pattern BP may include a metal layer / metal nitride layer. The conductive pattern CP may include at least one of aluminum, copper, tungsten, molybdenum, and cobalt.

[0211] When the first active contacts AC1 to the eighth active contacts AC8 are formed, silicide patterns SC can be formed between each active contact and the first source / drain pattern SD1, the second source / drain pattern SD2, the third source / drain pattern SD3, and the fourth source / drain pattern SD4, respectively. As an example, the silicide pattern SC may include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide. Spacers SP can be formed on the upper surfaces of the first source / drain patterns SD1, SD2, SD3, and SD4 that are not covered by the silicide pattern SC, and can be disposed between the barrier pattern BP and the gate spacer GS. Spacers SP can also be formed on the silicide pattern SC, and the barrier pattern BP and the conductive pattern CP can be formed on the silicide pattern SC where spacers SP are not formed.

[0212] refer to Figure 26 and Figures 28A to 28D Vias HL can be formed in the second gate electrode GE2 and the third gate electrode GE3. Vias HL can be positioned at the locations where the first node connection pattern NP1 and the second node connection pattern NP2 are to be formed. The formation of vias HL can be part of a single damascene process or a general photolithography process.

[0213] One of the vias HL can be formed at the location where the first node connection pattern NP1 is set, and the other via HL can be formed at the location where the second node connection pattern NP2 is set. As an example, a via HL can be formed by removing a portion of the third gate electrode GE3 and a portion of the second active contact AC2. Another via HL can be formed by removing a portion of the second gate electrode GE2 and a portion of the fifth active contact AC5. When removing a portion of the third gate electrode GE3 and a portion of the second active contact AC2, the gate insulating layer GI and the gate spacer GS between the third gate electrode GE3 and the second active contact AC2 can also be removed. Furthermore, when removing a portion of the second gate electrode GE2 and a portion of the fifth active contact AC5, the gate insulating layer GI and the gate spacer GS between the second gate electrode GE2 and the fifth active contact AC5 can also be removed.

[0214] Reference Figure 29 and Figures 30A to 30D Conductive metal can be filled into the through-hole HL to form a first node connection pattern NP1 and a second node connection pattern NP2.

[0215] The first node connection pattern NP1 and the second node connection pattern NP2 can be formed using a single damascene process or a general photolithography process. In this case, the barrier pattern BP can be formed before the conductive pattern is formed in the via HL; however, this disclosure is not limited thereto. In embodiments, the conductive pattern can be formed directly in the via HL without forming the barrier pattern BP.

[0216] Therefore, the first node connection pattern NP1 can connect to the third gate electrode GE3 and the second active contact AC2. When viewed in cross-section, a portion of one side surface and the lower surface of the first node connection pattern NP1 can contact the third gate electrode GE3, and another portion of the other side surface and the lower surface of the first node connection pattern NP1 can contact the second active contact AC2. As an example, the side surface of the first node connection pattern NP1 can directly contact the conductive pattern CP of the second active contact AC2, and the lower surface of the first node connection pattern NP1 can contact the conductive pattern CP and the blocking pattern BP of the second active contact AC2. Although not shown in the figure, when viewed in cross-section, a portion of one side surface and the lower surface of the second node connection pattern NP2 can contact the fifth active contact AC5, and another portion of the other side surface and the lower surface of the second node connection pattern NP2 can contact the second gate electrode GE2. As an example, the side surface of the second node connection pattern NP2 can directly contact the conductive pattern CP of the fifth active contact AC5, and the lower surface of the second node connection pattern NP2 can contact the conductive pattern CP and the blocking pattern BP of the fifth active contact AC5.

[0217] After filling the via HL with conductive metal, the first node connection pattern NP1 and the second node connection pattern NP2 can be planarized until the upper surfaces of the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4, as well as the upper surfaces of the first active contacts AC1 to the eighth active contacts AC8, are exposed. Therefore, the first node connection pattern NP1 and the second node connection pattern NP2 can be coplanar with the upper surfaces of the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4, as well as the upper surfaces of the first active contacts AC1 to the eighth active contacts AC8.

[0218] The lower surface of the first node connection pattern NP1 can also contact the gate insulating layer GI and the gate spacer GS. The upper surface of the first node connection pattern NP1 can be coplanar with the upper surface of the third gate electrode GE3 and the upper surface of the second active contact AC2.

[0219] refer to Figure 29 and Figures 31A to 31DA pillar PL for forming a first path V1 can be formed on the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4, as well as on the first active contacts AC1 to the eighth active contacts AC8. The pillar PL can be disposed in the region where the first path V1 is to be provided. The pillar PL can also be disposed on the first node connection pattern NP1 and the second node connection pattern NP2, a portion of the upper surface of the second gate electrode GE2 and the third gate electrode GE3 adjacent to the first node connection pattern NP1 and the second node connection pattern NP2, and a portion of the upper surface of the second active contact AC2 and the fifth active contact AC5. The pillar PL disposed on the first node connection pattern NP1 and the second node connection pattern NP2 can protect the first node connection pattern NP1 and the second node connection pattern NP2 during subsequent etching processes.

[0220] The pillar PL may include at least one of photoresist, silicon nitride, silicon oxide, and silicon oxynitride.

[0221] refer to Figure 32 and Figures 33A to 33D The upper portions of the first to fourth gate electrodes GE1, GE2, GE3, and GE4, which are exposed due to the absence of pillar PL, and the upper portions of the first to eighth active contacts AC1 to AC8, can be etched to form a recessed region RR. Therefore, the first passage V1 can protrude from the upper portions of the first gate electrode GE1, the second gate electrode GE2, the third gate electrode GE3, and the fourth gate electrode GE4, as well as the upper portions of the first active contacts AC1 to the eighth active contacts AC8.

[0222] The recessed region RR can be formed using dry etching and / or wet etching processes. According to an embodiment, the recessed region can also be formed using a non-selective etching process.

[0223] Reference Figure 32 and Figures 34A to 34D An insulating layer can be formed to fill the recessed region RR while maintaining the pillar PL. Then, a planarization process can be performed on the insulating layer to form a third interlayer insulating layer 130. The upper surface of the third interlayer insulating layer 130 can be located at the same height as the upper surface of the pillar PL. The third interlayer insulating layer 130 may include SiO2, SiN, SiC, SiOC, and AlO. x At least one of them.

[0224] refer to Figure 32 and Figures 35A to 35D After removing the pillar PL, an insulating layer is formed to fill the area where the pillar PL was removed, and a planarization process can be performed. When viewed in a plane, the area where the pillar PL was removed can correspond to the area overlapping with the first path V1 and the area overlapping with the first node connection pattern NP1 and the second node connection pattern NP2.

[0225] According to an embodiment, the insulating layer filling the region where the pillar PL has been removed may comprise the same material as the third interlayer insulating layer 130. The insulating layer filling the region where the pillar PL has been removed may be integral with the third interlayer insulating layer 130. Therefore, the upper surface of the first passage V1 and the upper surfaces of the first node connection pattern NP1 and the second node connection pattern NP2 may be covered by the third interlayer insulating layer 130.

[0226] refer to Figure 36 and Figures 37A to 37D A fourth interlayer insulating layer 140 can be formed on the third interlayer insulating layer 130. The second path V2 and the first wiring layer M1 can be formed in the fourth interlayer insulating layer 140. The first wiring layer M1 may include a word line WL, a power line Vdd, a ground line Vss, and a first bit line BL1 and a second bit line BL2. The second path V2 and the first wiring layer M1 can be formed together using a dual damascene process. The second path V2 can be formed to correspond to the area where the first path V1 is located.

[0227] The first wiring layer M1 may include at least one metallic material selected from aluminum, copper, tungsten, molybdenum and cobalt.

[0228] Although embodiments of the present disclosure have been described, it should be understood that the present disclosure is not intended to be limited to these embodiments, but rather that various changes and modifications can be made by those skilled in the art within the spirit and scope of the present disclosure as claimed herein. As examples, although the embodiments described in this disclosure are described in the context of MBCFET or fork-type FET, implementations of the above embodiments of the present disclosure can also be applied to other processes and / or other devices having at least some different configurations from the foregoing embodiments, such as planar FETs, FinFETs, horizontal full-gate all-around (HGAA) FETs, vertical full-gate all-around (VGAA) FETs, and other suitable devices.

[0229] Therefore, the subject matter disclosed herein should not be limited to any single embodiment described herein, and the scope of the inventive concept should be determined in accordance with the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: An active pattern is disposed on the front surface of a substrate; Source / drain pattern, wherein the source / drain pattern is disposed on the active pattern; A channel pattern, wherein the channel pattern is disposed on the active pattern and connected to the source / drain pattern; A gate electrode, wherein the gate electrode is disposed on the channel pattern; An active contact is disposed on the source / drain pattern; An interlayer insulating layer is disposed on the gate electrode; A first wiring layer is disposed on the interlayer insulation layer and includes multiple lines; A node connection pattern, wherein the node connection pattern is connected to the gate electrode located on one of the active patterns and the active contact located on the other active pattern. The interlayer insulation layer is disposed between the first wiring layer and the node connection pattern to insulate the node connection pattern from the first wiring layer; and The height of the upper surface of the node connection pattern is different from the height of the upper surface of other active contacts not connected to the node connection pattern.

2. The semiconductor device according to claim 1, wherein, The upper surface of the node connection pattern is coplanar with the upper surface of the gate electrode connected to the node connection pattern and the upper surface of the active contact connected to the node connection pattern.

3. The semiconductor device according to claim 1, wherein, The node connection pattern includes: A first node connection pattern is connected to the gate electrode located on one active pattern and the active contact located on the other active pattern; and The second node connection pattern is connected to the gate electrode located on the other active pattern and the active contact located on the first active pattern.

4. The semiconductor device of claim 1, further comprising a gate insulating layer between the gate electrode and the channel pattern. in, The gate insulating layer extends between the gate electrode located on one active pattern and the active contact located on the other active pattern, and the upper end of the extended portion of the gate insulating layer contacts the lower surface of the node connection pattern.

5. The semiconductor device according to claim 1, wherein, Each of the active contacts includes a conductive pattern and a blocking pattern surrounding the conductive pattern, and the lower surface of the node connection pattern contacts the upper end of at least a portion of the blocking pattern of the active contact connected to the node connection pattern.

6. The semiconductor device according to claim 1, wherein, The interlayer insulation layer includes: A primary interlayer insulating layer, wherein the primary interlayer insulating layer is disposed between the node connection pattern and the first wiring layer, and is disposed on the node connection pattern; and A recessed filling layer is disposed between the interlayer insulating layer and the upper surface of the active contact not connected to the node connection pattern; and The interlayer insulation layer and the recess filling layer are integrally formed and not separated from each other.

7. The semiconductor device according to claim 1, wherein, In the plan view, at least a portion of the node connection pattern overlaps with at least one of the plurality of lines in the first wiring layer.

8. The semiconductor device according to claim 1, wherein, Each of the channel patterns includes a plurality of semiconductor patterns that are vertically stacked and spaced apart from each other, and each of the gate electrodes surrounds each of the semiconductor patterns of the corresponding channel pattern in the channel pattern.

9. The semiconductor device according to claim 1, further comprising: A rear surface wiring layer is disposed on the rear surface of the substrate and includes at least one wiring. as well as A rear surface path, the rear surface path being connected to at least one wiring of the rear surface wiring layer, wherein the at least one wiring of the rear surface wiring layer is electrically connected to one of the source / drain patterns via the rear surface path.

10. The semiconductor device according to claim 9, wherein, The at least one wiring in the rear surface wiring layer is a power line.

11. The semiconductor device according to claim 1, wherein, At least one of the gate electrodes includes a first passage that penetrates the lower portion of the interlayer insulating layer, and at least one of the plurality of lines of the first wiring layer includes a second passage that penetrates the upper portion of the interlayer insulating layer and is connected to the first passage.

12. The semiconductor device according to claim 1, wherein, The active pattern includes a first active pattern and a second active pattern arranged in the PMOS transistor region, and a third active pattern and a fourth active pattern arranged in the NMOS transistor region. The channel pattern includes a first channel pattern and a second channel pattern arranged in the PMOS transistor region, and a third channel pattern and a fourth channel pattern arranged in the NMOS transistor region. The third channel pattern, the first channel pattern, the second channel pattern and the fourth channel pattern are arranged sequentially along a first direction.

13. The semiconductor device of claim 12, further comprising at least one dielectric wall disposed between two adjacent channel patterns among the third channel pattern, the first channel pattern, the second channel pattern, and the fourth channel pattern.

14. The semiconductor device according to claim 13, wherein, The gate electrode includes: A first sub-gate electrode and a second sub-gate electrode, wherein at least one dielectric wall is disposed between the first sub-gate electrode and the second sub-gate electrode; and A bridge is disposed on the dielectric wall and connects the first sub-gate electrode and the second sub-gate electrode.

15. The semiconductor device of claim 12, further comprising: A rear surface wiring layer is disposed on the rear surface of the substrate and includes at least one wiring. as well as A rear surface path, the rear surface path being connected to at least one wiring of the rear surface wiring layer, wherein the at least one wiring of the rear surface wiring layer is connected via the rear surface path to one of a first source / drain pattern, a second source / drain pattern, a third source / drain pattern, and a fourth source / drain pattern.

16. The semiconductor device according to claim 15, wherein, The at least one wiring in the rear surface wiring layer is a power line.

17. A semiconductor device, the semiconductor device comprising: A first active pattern and a second active pattern are disposed on the PMOS region of the substrate; A third active pattern and a fourth active pattern are disposed on the NMOS region of the substrate; A first source / drain pattern, a second source / drain pattern, a third source / drain pattern, and a fourth source / drain pattern are respectively disposed on the first active pattern, the second active pattern, the third active pattern, and the fourth active pattern. An active contact is disposed on the first source / drain pattern to the fourth source / drain pattern; A first channel pattern, a second channel pattern, a third channel pattern, and a fourth channel pattern are respectively disposed on the first active pattern, the second active pattern, the third active pattern, and the fourth active pattern. A first common gate electrode, which intersects with the first active pattern and the third active pattern and covers the first channel pattern and the third channel pattern; The second common gate electrode intersects with the second active pattern and the fourth active pattern and covers the second channel pattern and the fourth channel pattern; The first node contact connects the second common gate electrode and the active contact on the first source / drain pattern adjacent to the second common gate electrode; The second node contact connects the first common gate electrode and the active contact on the second source / drain pattern adjacent to the first common gate electrode; An interlayer insulating layer is disposed on the first common gate electrode and the second common gate electrode; as well as A first wiring layer is disposed on the interlayer insulation layer and includes multiple wirings; The height of the upper surface of the first node contact and the second node contact is different from the height of the upper surface of other active contacts not connected to the first node contact and the second node contact.

18. The semiconductor device according to claim 17, wherein, At least one of the first node contact and the second node contact overlaps with at least one of the plurality of wirings in the first wiring layer.

19. A semiconductor device, the semiconductor device comprising: An active pattern is disposed on the front surface of a substrate; Source / drain pattern, wherein the source / drain pattern is disposed on the active pattern; A channel pattern, wherein the channel pattern is disposed on the active pattern and connected to the source / drain pattern; A gate electrode, wherein the gate electrode is disposed on the channel pattern; An active contact is disposed on the source / drain pattern; An interlayer insulating layer is disposed on the gate electrode; A wiring layer disposed on the interlayer insulation layer and comprising multiple lines; as well as A node connection pattern, wherein the node connection pattern is connected to the gate electrode located on one of the active patterns and the active contact located on the other active pattern. The interlayer insulation layer is disposed between the wiring layer and the node connection pattern, and The active contact connected to the node connection pattern protrudes further than one of the active contacts not connected to the node connection pattern relative to the substrate.

20. The semiconductor device of claim 19, further comprising a spacer covering a side surface of the active contact such that a portion of the spacer is disposed between the active contact and the interlayer insulating layer.

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