Semiconductor device, manufacturing method thereof and electronic equipment
By forming a protective layer on the substrate during the semiconductor device manufacturing process, and utilizing the low etching rate of the protective layer to protect the substrate, the problem of corrosion pit formation during single-crystal silicon etching is solved, ensuring the integrity and performance of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING SUPERSTRING ACAD OF MEMORY TECH
- Filing Date
- 2024-10-18
- Publication Date
- 2026-04-21
AI Technical Summary
In the semiconductor device manufacturing process, single-crystal silicon substrates have a potential risk of peeling due to the formation of corrosion pits during wet etching, which can affect device performance and potentially damage the device.
A protective layer is formed on the substrate. The etching rate of the protective layer is lower than that of the first sacrificial structure to protect the substrate during the etching process. By forming the protective layer 200 on the substrate, it is ensured that the protective layer 200 is not completely removed when the first sacrificial structure 101 is etched, thus avoiding damage to the substrate.
It effectively protects the substrate, ensures the integrity and performance of semiconductor devices, avoids substrate damage caused by etching, and improves the reliability and performance of devices.
Smart Images
Figure CN121908555A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor device technology, and more specifically, to a semiconductor device and its manufacturing method, and an electronic device. Background Technology
[0002] With the development of integrated circuit technology, the critical dimensions of semiconductor devices are shrinking, and the types and number of semiconductor devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of semiconductor devices.
[0003] To minimize product costs, the goal is to fabricate as many semiconductor devices as possible on a substrate with limited area. Since the advent of Moore's Law, the industry has proposed various structural designs and process optimizations for semiconductor devices to meet current product demands. Summary of the Invention
[0004] This application addresses the shortcomings of existing methods by proposing a semiconductor device, its manufacturing method, and an electronic device, which can effectively improve the performance of the semiconductor device.
[0005] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor device, comprising: A protective layer is formed on the substrate; A stacked structure is formed on the protective layer, the stacked structure comprising alternating layers of first dielectric layers and layers of first insulating layers; The stacked structure has a plurality of first trenches extending along a second direction and spaced apart in a first direction, a plurality of first vias and a plurality of second vias, wherein the first vias and second vias are sequentially moved away from the first trenches along the first direction; the first direction intersects the second direction and is parallel to the substrate; Based on the first trench, the multilayer first insulating layer on both sides of the first trench is etched to form a multilayer first conductive layer extending along the second direction. Based on the second via, the multilayer first insulating layer around the second via is etched to form a multilayer first electrode structure; Based on the first via, the first dielectric layer between any two first conductive layers and between any two first electrode structures on the outer periphery of the first via is replaced with a first sacrificial structure. A conformal semiconductor material layer, a gate insulating layer, and a gate layer are sequentially deposited within the first via. The first sacrificial structure is removed based on the second via and the first trench, exposing the semiconductor material layer; the etching rate of the first sacrificial structure is greater than the etching rate of the protective layer; The exposed semiconductor material layer is removed, and the remaining semiconductor material layer forms a semiconductor structure.
[0006] In some possible embodiments, a protective layer is formed on one side of the substrate, including: A protective layer is epitaxially grown on one side of the substrate, and the material of the protective layer includes silicon and germanium.
[0007] In some possible embodiments, a protective layer is formed on one side of the substrate, including: Germanium or boron is implanted into the substrate surface to form an amorphous layer; The amorphous layer is heat-treated to obtain a protective layer, the material of which includes silicon germanium or borosilicate.
[0008] In some possible embodiments, the first sacrificial structure is removed based on the second via and the first trench, exposing the semiconductor material layer; the etching rate of the first sacrificial structure is greater than the etching rate of the protective layer, including: Based on the second via and the first trench, the first sacrificial structure is removed by wet etching to expose the semiconductor material layer; the wet etching rate of the first sacrificial structure is greater than the wet etching rate of the protective layer.
[0009] In some possible embodiments, the ratio of the wet etching rate of the first sacrificial structure to the wet etching rate of the protective layer is greater than 45:1.
[0010] In some possible embodiments, based on the first trench, multiple layers of first insulating layers on both sides of the first trench are etched to form multiple layers of first conductive layers extending along a second direction, including: The first insulating layer exposed on the sidewall of the first trench is etched back to form a multi-layer first groove located on both sides of the first trench and extending along the second direction. A first conductive layer extending in a second direction is formed in the first groove, and the portion of the first conductive layer that overlaps with the first via in the first direction forms a first source and drain electrode. A second insulating layer is deposited in the first trench and the first recess, covering the exposed surface of the first conductive layer.
[0011] In some possible embodiments, based on the second via, the multilayer first insulating layer around the second via is etched to form a multilayer first electrode structure, including: The multiple layers of the first insulating layer exposed on the sidewall of the second via are etched back to form multiple layers of the second groove located on the outer periphery of the second via. A conformal first conductive material and a second sacrificial structure are sequentially deposited in the second via and the second groove; The second sacrificial structure and the first conductive material in the second via are removed sequentially, and the first conductive material in the second groove forms the first electrode structure. A third insulating layer is deposited inside the second via.
[0012] In some possible embodiments, removing the first sacrificial structure based on the second via and the first trench includes: Remove the third insulating layer in the second via and the second insulating layer in the first trench to expose the first sacrificial structure and the second sacrificial structure. Replace the second sacrificial structure with the second medium structure; Remove the second via and the first trench to expose the first sacrificial structure, exposing the semiconductor material layer; the etching rate of the first sacrificial structure is greater than the etching rate of the second dielectric structure.
[0013] In some possible embodiments, it also includes: A third dielectric layer and a second electrode structure are sequentially formed within the second via. The first electrode structure, the third dielectric layer, and the second electrode structure form a capacitor.
[0014] Secondly, embodiments of this application provide a semiconductor device, including: A protective layer is disposed on the substrate; A semiconductor stacked structure disposed on a protective layer includes alternating layers of first dielectric layers and multiple transistors; the stacked structure has a plurality of first trenches extending along a second direction and spaced apart in a first direction, a plurality of first vias and a plurality of second vias, wherein the first vias and second vias are sequentially moved away from the first trenches along the first direction; the first direction intersects the second direction and is parallel to the substrate. The first via is sequentially filled with the semiconductor structure of the transistor, the gate insulating layer, and the gate layer; The outer periphery of the second via is provided with a multilayer first electrode structure that is connected to the semiconductor structure of the multilayer transistor.
[0015] In some possible embodiments, the material of the protective layer includes at least one of silicon germanium and borosilicate.
[0016] In some possible embodiments, the protective layer is made of silicon-germanium, with a germanium concentration of not less than 5% and not more than 20%.
[0017] In some possible embodiments, multiple layers of first conductive layers extending along the second direction are provided on both sides of the first trench; Along the first direction, the first conductive layer corresponding to the first via forms the first source and drain of the transistor.
[0018] In some possible embodiments, it also includes: The capacitor includes a first electrode structure, a third dielectric layer located within a second via, and a second electrode structure.
[0019] Thirdly, embodiments of this application provide an electronic device, including: a semiconductor device manufactured by any of the semiconductor device manufacturing methods provided in the first aspect above, or any of the semiconductor devices provided in the second aspect above.
[0020] The beneficial technical effects of the technical solutions provided in this application include: Before fabricating the stacked structure, a protective layer is formed on the substrate to protect it. During subsequent semiconductor device fabrication processes, when the first sacrificial structure needs to be etched, the etching rate of the first sacrificial structure is greater than that of the protective layer. This ensures that the protective layer is not completely removed or is just removed after the first sacrificial structure is etched, preventing damage to the substrate during etching and thus guaranteeing the integrity and effective performance of the semiconductor device.
[0021] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description
[0022] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application; Figure 2 A cross-sectional schematic diagram of the film structure after forming a protective layer 200 on a substrate 100 in a method for manufacturing a semiconductor device according to an embodiment of this application; Figure 3 A cross-sectional schematic diagram of the film structure after forming alternating layers of first dielectric layers 310 and first insulating layers 320 on the protective layer 200 in a semiconductor device manufacturing method provided in this application embodiment; Figure 4 This is a top view of the film structure after the stacked structure 300 is formed on the protective layer 200 in a method for manufacturing a semiconductor device according to an embodiment of this application. Figure 5 for Figure 4 Schematic diagram of the cross section at point AA'; Figure 6 A cross-sectional schematic diagram of the film structure after etching back the sidewall of the first trench 301 to expose the multilayer first insulating layer 320 in a semiconductor device manufacturing method provided in this application embodiment; Figure 7 A cross-sectional schematic diagram of the film structure after depositing a first initial conductive layer 410 in the first groove 304 and the first trench 301 in a semiconductor device manufacturing method provided in this application embodiment; Figure 8This is a cross-sectional schematic diagram of the film structure after multiple first conductive layers 400 extending in the second direction are manufactured at the multiple first insulating layers 320 on both sides of the first trench 301 in a semiconductor device manufacturing method provided in this application embodiment. Figure 9 A cross-sectional schematic diagram of the film structure after depositing a second insulating layer 102 in the first trench 301 and the first groove 304 in a semiconductor device manufacturing method provided in this application embodiment; Figure 10 A top view schematic diagram of the film structure after filling the first trench 301 with a sacrificial material layer 106 in a method for manufacturing a semiconductor device according to an embodiment of this application; Figure 11 for Figure 10 Schematic diagram of the cross section at point AA'; Figure 12 for Figure 10 Schematic diagram of the cross section at point BB'; Figure 13 A cross-sectional schematic diagram of the film structure after removing the sacrificial material layer 106 in the second via 303 in a semiconductor device manufacturing method provided in this application embodiment; Figure 14 A cross-sectional schematic diagram of the film structure after etching back the sidewall of the second via 303 to expose the multilayer first insulating layer 320 in a semiconductor device manufacturing method provided in this application embodiment; Figure 15 A cross-sectional schematic diagram of the film structure after depositing a conformal first electrode structure 610 in the second via 303 and the second groove 305 in a semiconductor device manufacturing method provided in this application embodiment; Figure 16 A cross-sectional schematic diagram of the film structure after depositing a conformal second sacrificial structure 103 in the second via 303 and the second groove 305 in a semiconductor device manufacturing method provided in this application embodiment; Figure 17 A cross-sectional schematic diagram of the film structure after removing the deposited second sacrificial structure 103 in the second via 303 in a semiconductor device manufacturing method provided in this application embodiment; Figure 18 A cross-sectional schematic diagram of the film structure after removing the deposited first electrode structure 610 in the second via 303 in a semiconductor device manufacturing method provided in this application embodiment; Figure 19 A cross-sectional schematic diagram of the film structure after depositing a third insulating layer 104 in a second via 303 in a semiconductor device manufacturing method provided in this application embodiment; Figure 20A cross-sectional schematic diagram of the film structure after filling the second via 303 with a sacrificial material layer 106 in a method for manufacturing a semiconductor device according to an embodiment of this application; Figure 21 A cross-sectional schematic diagram of the film structure after the fourth insulating layer 107 is deposited on top in a method for manufacturing a semiconductor device according to an embodiment of this application; Figure 22 A cross-sectional schematic diagram of the film structure when the first via 302 is opened using the first mask structure 108 in a semiconductor device manufacturing method provided in this application embodiment; Figure 23 A cross-sectional schematic diagram of the film structure after the first via 302 is opened using the first mask structure 108 in a semiconductor device manufacturing method provided in this application embodiment; Figure 24 A cross-sectional schematic diagram of the film structure after etching back the first dielectric layer 310 exposed on the sidewall of the first via 302 in a semiconductor device manufacturing method provided in this application embodiment; Figure 25 A cross-sectional schematic diagram of the film structure after conformal deposition of a first sacrificial structure 101 in a first via 302 in a semiconductor device manufacturing method provided in this application embodiment; Figure 26 A cross-sectional schematic diagram of the film structure after removing the first sacrificial structure 101 in the first via 302 in a semiconductor device manufacturing method provided in this application embodiment; Figure 27 A cross-sectional schematic diagram of the film structure after sequentially depositing a conformal semiconductor material layer 521, a gate insulating layer 531, and a gate layer 541 in a first via 302 in a semiconductor device manufacturing method provided in this application embodiment; Figure 28 A cross-sectional schematic diagram of the film structure after removing the sacrificial material layer 106 in the first via 302, the second via 303 and the first trench 301 in a semiconductor device manufacturing method provided in this application embodiment; Figure 29 A cross-sectional schematic diagram of the film structure after removing the third insulating layer 104 in the second via 303 and the second insulating layer 102 in the first trench 301 in a semiconductor device manufacturing method provided in this application embodiment; Figure 30 A cross-sectional schematic diagram of the film structure after replacing the second sacrificial structure 103 with the second dielectric structure 105 in a semiconductor device manufacturing method provided in this application embodiment; Figure 31A cross-sectional schematic diagram of the film structure after the first sacrificial structure 101 exposed by removing the second via 303 and the first trench 301 using wet etching in a semiconductor device manufacturing method provided in this application embodiment; Figure 32 A top cross-sectional view of the film structure after the third dielectric layer 620 and the second electrode structure 630 are sequentially formed in the second via 303 in a semiconductor device manufacturing method provided in this application embodiment; Figure 33 for Figure 32 A schematic diagram of the cross-section at point BB'.
[0023] Figure label: 100-substrate; 200 - Protective layer; 300 - Stacked structure; 310 - First dielectric layer; 320 - First insulating layer; 301 - First trench; 302 - First via; 303 - Second via; 304 - First groove; 305 - Second groove; 400 - First conductive layer; 410 - First initial conductive layer; 500 - Transistor; 510 - First source / drain; 520 - Semiconductor structure; 521 - Semiconductor material layer; 530 - Gate insulating structure; 531 - Gate insulating layer; 540 - Gate; 541 - Gate layer; 550 - Second source / drain; 600 - Capacitor; 610 - First electrode structure; 611 - First conductive material; 620 - Third dielectric layer; 630 - Second electrode structure; 101 - First sacrificial structure; 102 - Second insulating layer; 103 - Second sacrificial structure; 104 - Third insulating layer; 105 - Second dielectric structure; 106 - Sacrificial material layer; 107 - Fourth insulating layer; 108 - First mask structure; 109 - Fifth insulating layer. Detailed Implementation
[0024] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.
[0025] Those skilled in the art will understand that, unless specifically stated otherwise, the terms "described" and "the" as used herein may also include plural forms. It should be further understood that the term "comprising" as used in this application's specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude implementations of other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by this art. It should be understood that when we say an element is "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or it may mean that the element and the other element are connected through an intermediate element. Furthermore, "connected" or "coupled" as used herein may include wireless connections or wireless coupling. The term "and / or" as used herein refers to at least one of the items defined by the term; for example, "A and / or B" may be implemented as "A," or as "B," or as "A and B."
[0026] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0027] The research and development approach of this application includes: to achieve higher storage density, better performance, and smaller device size, related technologies involve forming a stacked structure of alternating dielectric and insulating layers on a substrate. This stacked structure is then processed to form a multilayer transistor.
[0028] In related technologies, the dielectric layer around the first via is replaced with a first sacrificial structure. A semiconductor material layer, a gate insulating layer, and a gate layer are sequentially formed inside the first via that penetrates the stacked structure, covering the inner wall of the first via. By removing the first sacrificial structure, a portion of the semiconductor material layer corresponding to the first sacrificial structure is exposed. Removing the exposed semiconductor material layer breaks the initial semiconductor material layer, forming a multilayer semiconductor structure, and thus forming a multilayer transistor.
[0029] However, unlike amorphous and polycrystalline silicon, monocrystalline silicon exhibits anisotropic etching technology. The process of removing the first sacrificial structure often employs wet etching. Due to the differences in etching rates across the various crystal planes of monocrystalline silicon, etching pits may form on the silicon substrate, posing a potential risk of peeling off, affecting the performance of semiconductor devices, and even damaging them.
[0030] The semiconductor devices, manufacturing methods, and electronic devices provided in this application are intended to solve the aforementioned technical problems in related technologies.
[0031] The technical solution of this application and how it solves the above-mentioned technical problems will be described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, learned from or combined with each other, and the same terms, similar features and similar implementation steps in different embodiments will not be described again.
[0032] This application provides a method for manufacturing a semiconductor device, and the flowchart of the method is shown below. Figure 1 As shown, the method includes steps S101-S108: S101: A protective layer 200 is formed on the substrate 100.
[0033] Optionally, a schematic diagram of the membrane structure after step S101 is shown below. Figure 2 As shown.
[0034] Optionally, a protective layer 200 may be fabricated on the substrate 100 using a chemical vapor deposition process.
[0035] S102: A stacked structure 300 is formed on the protective layer 200, the stacked structure 300 including alternating layers of first dielectric layers 310 and layers of first insulating layers 320.
[0036] The stacked structure 300 has a plurality of first trenches 301 extending along a second direction and spaced apart in a first direction, a plurality of first vias 302, and a plurality of second vias 303; the first vias 302 and second vias 303 are sequentially moved away from the first trenches 301 along the first direction; the first direction intersects the second direction and is parallel to the substrate 100. A schematic diagram of the film structure after step S102 is shown below. Figure 5 As shown.
[0037] Alternatively, please refer to Figures 3-5 First, multiple layers of first dielectric layer 310 and multiple layers of first insulating layer 320 are alternately stacked on the protective layer 200. Then, the multiple layers of first dielectric layer 310 and multiple layers of first insulating layer 320 are etched to obtain the first trench 301, the first via 302 and the second via 303.
[0038] Optionally, the protective layer 200 includes a silicon-germanium material, which can serve as an etch stop layer to prevent the substrate 100 from being etched and thus affecting the support performance of the substrate 100.
[0039] S103: Based on the first trench 301, the multilayer first insulating layer 320 on both sides of the first trench 301 is etched to form a multilayer first conductive layer 400 extending along the second direction. A schematic diagram of the film structure after step S103 is shown below. Figure 8 As shown.
[0040] S104: Based on the second via 303, the multilayer first insulating layer 320 around the second via 303 is etched to form a multilayer first electrode structure 610. A schematic diagram of the film structure after step S104 is shown below. Figure 18 As shown.
[0041] S105: Based on the first via 302, replace the first dielectric layer 310 between any two first conductive layers 400 and between any two first electrode structures 610 on the outer periphery of the first via 302 with the first sacrificial structure 101. A schematic diagram of the film structure after step S105 is shown below. Figure 26 As shown.
[0042] S106: A conformal semiconductor material layer 521, a gate insulating layer 531, and a gate layer 541 are sequentially deposited within the first via 302. A schematic diagram of the film structure after step S106 is shown below. Figure 27 As shown.
[0043] S107: Remove the first sacrificial structure 101 based on the second via 303 and the first trench 301, exposing the semiconductor material layer 521; the etching rate of the first sacrificial structure 101 is greater than the etching rate of the protective layer 200. A schematic diagram of the film structure after step S107 is shown below. Figure 31 As shown.
[0044] S108: Remove the exposed semiconductor material layer 521, and the remaining semiconductor material layer 521 forms the semiconductor structure 520. A schematic diagram of the film structure after step S108 is shown below. Figures 32-33 As shown.
[0045] In this embodiment, a protective layer 200 is formed on the substrate 100 before fabricating the stacked structure 300, which protects the substrate 100. In subsequent semiconductor device fabrication processes, when the first sacrificial structure 101 needs to be etched, the etching rate of the first sacrificial structure 101 is greater than the etching rate of the protective layer 200. This ensures that the protective layer 200 is not completely removed or is just removed after the first sacrificial structure 101 is etched, preventing damage to the substrate 100 during etching and thus guaranteeing the integrity and effective performance of the semiconductor device.
[0046] Specifically, after replacing the first dielectric layer 310 between any two first conductive layers 400 and between any two first electrode structures 610 on the outer periphery of the first via 302 with the first sacrificial structure 101, the first sacrificial structure 101 becomes part of the sidewall of the first via 302. A semiconductor material layer 521, a gate insulating layer 531, and a gate layer 541 are sequentially deposited within the first via 302, covering the sidewall of the first via 302, with the first sacrificial structure 101 surrounding the outer periphery of the semiconductor material layer 521. The first sacrificial structure 101 is etched away from the outer periphery of the semiconductor material layer 521. The etching rate of the first sacrificial structure 101 is greater than the etching rate of the protective layer 200, thereby ensuring that the substrate 100 is not affected by the etchant during the etching of the first sacrificial structure 101, ensuring the integrity of the substrate 100, and thus ensuring the integrity and effective performance of the semiconductor device.
[0047] In some possible embodiments, forming a protective layer 200 on one side of the substrate 100 in step S101 above includes the following steps: A protective layer 200 is epitaxially grown on one side of the substrate 100. The material of the protective layer 200 includes silicon and germanium.
[0048] In this embodiment, a protective layer 200 containing silicon-germanium material can be formed on the silicon substrate 100 by an epitaxial growth process. The manufacturing process is mature and helps to control costs.
[0049] Optionally, the thickness of the epitaxially grown protective layer 200 is between 60 nanometers and 100 nanometers, which ensures a certain degree of flatness on the silicon-germanium surface, facilitating the fabrication of subsequent film layers. This reduces material usage and lowers costs while maintaining crystal quality. Moreover, within this thickness range, strain caused by lattice mismatch can be effectively controlled, thereby preventing the generation of dislocations due to strain relaxation. This is crucial for maintaining the crystal quality of the thin film and device performance.
[0050] In some possible embodiments, forming a protective layer 200 on one side of the substrate 100 in step S101 above includes the following steps: Germanium or boron is implanted into the surface of substrate 100 to form an amorphous layer; the amorphous layer is heat-treated to obtain a protective layer 200, the material of the protective layer 200 including silicon germanium or borosilicate.
[0051] In this embodiment, high concentration doses of germanium or boron can be injected multiple times with different energies to obtain a uniform amorphous layer in the injection area of the silicon substrate 100. After heat treatment, the damaged lattice of the amorphous layer is repaired, recrystallization is promoted, and a protective layer 200 is formed, which effectively protects the substrate 100 during the etching process.
[0052] Optionally, the amorphous layer is subjected to heat treatment, including: uniform annealing at 935 degrees Celsius for 30 seconds to ensure uniform temperature distribution inside the material, thereby completely repairing the damaged lattice of the amorphous layer and obtaining a protective layer 200.
[0053] In some possible embodiments, step S107 above includes: Based on the second via 303 and the first trench 301, the first sacrificial structure 101 is removed by wet etching to expose the semiconductor material layer 521; the wet etching rate of the first sacrificial structure 101 is greater than the wet etching rate of the protective layer 200.
[0054] In this embodiment, the etchant used in wet etching has a high etching selectivity for the protective layer 200, which includes materials such as silicon and germanium, when etching the first sacrificial structure 101. This ensures that after the first sacrificial structure 101 is etched, there is still a protective layer 200 of a certain thickness, which can guarantee the integrity of the substrate 100.
[0055] In some possible embodiments, the ratio of the wet etching rate of the first sacrificial structure 101 to the wet etching rate of the protective layer 200 is greater than 45:1.
[0056] In this embodiment, the ratio of the wet etching rate of the first sacrificial structure 101 to the wet etching rate of the protective layer 200 is greater than 45:1, that is, the etchant used in the wet etching has a high etching selectivity for silicon and germanium, so that after the first sacrificial structure 101 is etched, there is still a protective layer 200 of a certain thickness to ensure the integrity of the substrate 100.
[0057] In some possible embodiments, step S103 above, which involves etching the multilayer first insulating layer 320 on both sides of the first trench 301 to form a multilayer first conductive layer 400 extending along the second direction based on the first trench 301, includes the following steps: The exposed multilayer first insulating layer 320 on the sidewall of the first trench 301 is etched back to form a multilayer first groove 304 located on both sides of the first trench 301 and extending along the second direction. The resulting film structure is shown in the schematic diagram below. Figure 6 As shown.
[0058] A first conductive layer 400 extending in the second direction is formed within the first groove 304. The portion of the first conductive layer 400 overlapping with the first via 302 in the first direction forms the first source / drain electrode 510. A schematic diagram of the resulting film structure is shown below. Figure 8 As shown.
[0059] A second insulating layer 102 is deposited in the first trench 301 and the first groove 304 to cover the exposed surface of the first conductive layer 400. The resulting film structure is shown in the schematic diagram below. Figure 9 As shown.
[0060] In this embodiment, by etching back the first insulating layer 320, multiple first grooves 304 separated by the first dielectric layer 310 can be formed on the outer periphery of the first trench 301. Then, by deposition process, corresponding first conductive layers 400 are formed in multiple first grooves 304, so that the first conductive layers 400 are alternately stacked with the first dielectric layer 310 along a third direction, which facilitates the subsequent formation of multi-layer memory cells.
[0061] Optionally, the formation of a first conductive layer 400 extending in the second direction within the first groove 304 in the above steps may include: such as Figure 7 As shown, a first initial conductive layer 410 is deposited in the first groove 304 and the first trench 301, the first initial conductive layer 410 in the first trench 301 is removed, the first initial conductive layer 410 in the first groove 304 is etched back, and the remaining first initial conductive layer 410 in the first groove 304 forms the first conductive layer 400.
[0062] Optionally, the deposition of the second insulating layer 102 in the first trench 301 and the first recess 304 in the above steps includes: as follows Figure 9 As shown, a second insulating layer 102 is deposited conformally in the first groove 304 and the first trench 301, and the top is planarized by grinding, etc., to remove the second insulating layer 102 deposited on the first dielectric layer 310.
[0063] Optionally, the first conductive layer 400 can serve as a bit line of a semiconductor device.
[0064] Optionally, after step S103 above, the method further includes: Figures 10-11 As shown, a sacrificial material layer 106 is filled in the first trench 301 to prevent subsequent processes from contaminating the already formed first conductive layer 400.
[0065] Optionally, such as Figure 12 As shown, before the first conductive layer 400 is formed, the first via 302 and the second via 303 are also pre-filled with a sacrificial material layer 106 to avoid unnecessary impact on the interior of the first via 302 and the second via 303 by subsequent processes.
[0066] Optionally, the sacrificial material filling the first trench 301, the first via 302 and the second via 303 can be a material with a selective etching ratio to the dielectric layer and the insulating layer. For example, the sacrificial material can be polysilicon.
[0067] In some possible embodiments, step S104 above, which involves etching the multilayer first insulating layer 320 around the second via 303 to form a multilayer first electrode structure 610, includes the following steps: The multilayer first insulating layer 320 exposed on the sidewall of the second via 303 is etched back to form a multilayer second groove 305 located on the outer periphery of the second via 303. The resulting film structure is shown in the schematic diagram. Figure 14 As shown.
[0068] A conformal first conductive material 611 and a second sacrificial structure 103 are sequentially deposited in the second via 303 and the second groove 305.
[0069] The second sacrificial structure 103 and the first conductive material 611 within the second via 303 are removed sequentially, and the first conductive material 611 within the second groove 305 forms the first electrode structure 610. A schematic diagram of the resulting film structure is shown below. Figure 18 As shown.
[0070] A third insulating layer 104 is deposited within the second via 303, and the resulting film structure is shown in the schematic diagram. Figure 19 As shown.
[0071] In this embodiment, by etching back the first insulating layer 320, multiple second grooves 305 separated by the first dielectric layer 310 can be formed on the outer periphery of the second via 303. Then, by deposition process, corresponding first electrode structures 610 are formed in multiple second grooves 305, so that the first electrode structures 610 are alternately stacked with the first dielectric layer 310 along the third direction, which facilitates the subsequent formation of multilayer memory cells.
[0072] Optionally, before step S104 above, the method further includes: removing the sacrificial material layer 106 within the second via 303, resulting in a film structure schematic diagram as shown below. Figure 13 As shown.
[0073] Optionally, the membrane structure obtained after filling the first via 302 and the second via 303 with the sacrificial material layer 106 (e.g.) Figure 12 A mask structure is formed above the film structure shown to remove the sacrificial material layer 106 within the second via 303. The mask structure used to remove the sacrificial material layer 106 within the second via 303 is the same as the mask structure used to form the second via 303. This ensures that the exposed pattern remains consistent during each etching process, thereby guaranteeing the accuracy and integrity of removing the sacrificial material layer 106. It also improves production efficiency and reduces production costs.
[0074] Optionally, in the above steps, such as Figures 15-17As shown, a conformal first conductive material 611 and a second sacrificial structure 103 can be sequentially deposited in the second via 303 and the second groove 305. The second sacrificial structure 103 in the second via 303 is etched to expose the first conductive material 611 on the side of the first dielectric layer 310. The exposed first conductive material 611 is removed, and the remaining first conductive material 611 is sequentially broken along a third direction to form the first electrode structure 610. The surface of the first electrode structure 610 away from the first dielectric layer 310 and the first insulating layer 320 is covered by the second sacrificial structure 103.
[0075] Optionally, such as Figure 17 As shown, while removing the second sacrificial structure 103 inside the second via 303, the second sacrificial structure 103 on top of the first conductive material 611 is also removed.
[0076] Optionally, such as Figure 18 As shown, it also includes the removal of the second sacrificial structure 103 and the first conductive material 611 deposited on top.
[0077] Optionally, in step S105 above, replacing the first dielectric layer 310 between any two first conductive layers 400 and between any two first electrode structures 610 on the outer periphery of the first via 302 with the first sacrificial structure 101 includes: such as Figure 20 As shown, a sacrificial material layer 106 is filled within the second via 303; as Figure 21 As shown, a fourth insulating layer 107 is deposited on top; as Figures 22-23 As shown, the first through-hole 302 is opened using the first mask structure 108; as Figure 24 As shown, the first dielectric layer 310 exposed on the sidewall of the first via 302 is etched back until the third insulating layer 104 within the second via 303 is exposed. Figure 25 As shown, a first sacrificial structure 101 is conformally deposited within the first via 302, such that the first sacrificial structure 101 fills the area where the first dielectric layer 310 was originally etched back. Figure 26 As shown, the first sacrificial structure 101 within the first via 302 is removed.
[0078] In some possible embodiments, the removal of the first sacrificial structure 101 based on the second via 303 and the first trench 301 in step S107 above includes the following steps: After removing the third insulating layer 104 in the second via 303 and the second insulating layer 102 in the first trench 301, the first sacrificial structure 101 and the second sacrificial structure 103 are exposed. The schematic diagram of the resulting film structure is shown below. Figure 29 As shown.
[0079] The schematic diagram of the resulting film structure is shown below, where the second sacrificial structure 103 is replaced with the second dielectric structure 105. Figure 30 As shown.
[0080] The first sacrificial structure 101 is exposed by removing the second via 303 and the first trench 301, revealing the semiconductor material layer 521. The etching rate of the first sacrificial structure 101 is greater than the etching rate of the second dielectric structure 105. The resulting film structure is shown in the schematic diagram below. Figure 31 As shown.
[0081] In this embodiment, by replacing the second sacrificial structure 103 exposed by the first trench 301 and the second via 303 with the second dielectric structure 105, the etching selectivity ratio with that of the first sacrificial structure 101 is higher. This means that during the etching of the first sacrificial structure 101, the second dielectric structure 105 is basically not etched, which plays a certain protective role for the first electrode structure 610 and avoids the first electrode structure 610 from being affected during the etching of the first sacrificial structure 101.
[0082] Optionally, the first sacrificial structure 101 and the second sacrificial structure 103 are made of the same material, while the second medium structure 105 is made of a different material than the first sacrificial structure 101. By replacing the second sacrificial structure 103 with the second medium structure 105, it is not necessary to protect the second sacrificial structure 103 from being removed during the removal of the first sacrificial structure 101, which simplifies the process steps.
[0083] Optionally, before step S107, the method further includes: removing the sacrificial material layer 106 from the first via 302, the second via 303, and the first trench 301, resulting in a schematic diagram of the film structure as shown below. Figure 28 As shown.
[0084] Optionally, the film structure obtained after forming the semiconductor material layer 521, the gate insulating layer 531, and the gate layer 541 (such as...) Figure 27 Different mask structures are sequentially formed above the shown film structure to remove the sacrificial material layer 106 in the first via 302, the second via 303, and the first trench 301, respectively. The mask structure used to remove the sacrificial material layer 106 in the first via 302 can be the same as the mask structure used to form the first via 302; the mask structure used to remove the sacrificial material layer 106 in the second via 303 can be the same as the mask structure used to form the second via 303; and the mask structure used to remove the sacrificial material layer 106 in the first trench 301 can be the same as the mask structure used to form the first trench 301. This ensures that the exposed pattern remains consistent during each etching process, thereby guaranteeing the accuracy and integrity of removing the sacrificial material layer 106. It also improves production efficiency and reduces production costs.
[0085] In some possible embodiments, the method of manufacturing the semiconductor structure 520 further includes the following steps: A third dielectric layer 620 and a second electrode structure 630 are sequentially formed within the second via 303. The first electrode structure 610, the third dielectric layer 620, and the second electrode structure 630 form a capacitor 600.
[0086] like Figures 32-33 As shown, after forming the semiconductor structure 520, the manufacturing process of the transistor 500 is completed. Then, the capacitor 600 is fabricated, and the unfilled first trench 301 is filled with the fifth insulating layer 109, thereby completing the manufacturing of the semiconductor device.
[0087] Optionally, a third dielectric layer 620 and a second electrode structure 630 are sequentially formed in the second via 303, including: removing the second dielectric structure 105, forming the third dielectric layer 620 in the second groove 305 and the second via 303, filling the second groove 305 with the third dielectric layer 620, and filling the second electrode structure 630 in the second via 303.
[0088] It should be noted that, in the embodiments of this application, the structure of each film layer of the semiconductor device can be patterned by a patterning process to manufacture each corresponding film layer.
[0089] It should be noted that the "patterning process" mentioned in the embodiments of this application includes processes such as depositing film layers, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography process" mentioned in the embodiments of this application includes processes such as coating film layers, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods; no specific limitations are made here.
[0090] In the description of the embodiments of this application, it should be understood that a "layer" refers to a thin film of a certain material manufactured on a substrate 100 using a deposition or coating process. If the thin film does not require a patterning process or photolithography process during the entire manufacturing process, the thin film can also be called a layer. If the thin film requires a patterning process or photolithography process during the entire manufacturing process, it can be called a thin film before the patterning process and a layer after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern".
[0091] Based on the same inventive concept, such as Figure 33 As shown in the figure, this application provides a semiconductor device, including: a protective layer 200 and a semiconductor stacked structure.
[0092] A protective layer 200 is disposed on the substrate 100.
[0093] A semiconductor stacked structure is disposed on the protective layer 200, including alternating layers of first dielectric layers 310 and multiple transistors 500; the stacked structure 300 has a plurality of first trenches 301 extending along a second direction and spaced apart in a first direction, a plurality of first vias 302 and a plurality of second vias 303, the first vias 302 and the second vias 303 being sequentially moved away from the first trenches 301 along the first direction; the first direction intersects the second direction and is parallel to the substrate 100.
[0094] The first via 302 is sequentially filled with the semiconductor structure 520 of the transistor 500, the gate insulating layer 531, and the gate layer 541.
[0095] The outer periphery of the second via 303 is provided with a multilayer first electrode structure 610 that is connected to the semiconductor structure 520 of the multilayer transistor 500.
[0096] In this embodiment, multilayer transistors 500 are sequentially stacked on the protective layer 200. Each transistor layer 500 includes at least one transistor 500, and each transistor 500 is electrically connected to a capacitor 600 to form a memory cell. Each transistor 500 includes a semiconductor structure 520, a gate insulating layer 531, and a gate layer 541. During the manufacturing process of the semiconductor structure 520, etching is used to remove the first sacrificial structure 101 on the periphery of the semiconductor structure 520. The protective layer 200 includes at least one material selected from silicon, germanium, and borosilicate. The etching rate of the first sacrificial structure 101 is greater than the etching rate of the protective layer 200, which protects the substrate 100 from the etchant during the removal of the first sacrificial structure 101, ensuring the integrity of the substrate 100 and thus guaranteeing the integrity and effective performance of the semiconductor device.
[0097] Optionally, the portions of the gate insulating layer 531 and the gate layer 541 that are directly opposite the semiconductor structure 520 along a direction parallel to the substrate 100 are respectively the gate insulating structure 530 and the gate 540 of the transistor 500.
[0098] In some possible embodiments, the material of the protective layer 200 includes at least one of silicon germanium and borosilicate.
[0099] In some possible embodiments, the material of the protective layer 200 includes silicon germanium, with a germanium concentration of not less than 5% and not more than 20%.
[0100]
[0101] As shown in the table above, the table illustrates the wet etching rates of the protective layer 200 with different concentrations of germanium. Here, Ge represents germanium, and Si represents silicon. Columns 2 through 7 of the first row represent pure silicon (without germanium), germanium concentrations of 5%, 10%, 15%, 20%, 60%, and 80%, respectively. In the second row, ADM(1:20, 60°C)ER represents the etching rate at a ratio of ammonia to water of 1:20 in the etchant, at a temperature of 60°C, and APMER represents the etching rate at a ratio of ammonia, hydrogen peroxide, and water of 1:1:50 in the etchant, at a temperature of 60°C.
[0102] As can be seen from the chart, under ADM etching conditions, the etching rate of the pure silicon protective layer 200 is extremely high, reaching 50 nanometers per minute. The higher the concentration of germanium in silicon-germanium, the lower the etching rate. In fact, the etching rate of silicon-germanium with a germanium concentration of 20% is very low.
[0103] Under APM etching conditions, the lower the concentration of germanium in silicon-germanium, the lower the etching rate; when the concentration reaches 20% or more, the etching rate is relatively high.
[0104] Therefore, in this embodiment of the application, the concentration of germanium is controlled to be between 5% and 20% (including the endpoint value), which enables the etching rate of the protective layer 200 to be low, and can be used as an etching stop layer to protect the silicon substrate 100.
[0105] In some possible embodiments, multiple layers of first conductive layers 400 extending along the second direction are provided on both sides of the first trench 301. Along the first direction, the first conductive layer 400 corresponding to the first via 302 forms the first source and drain 510 of the transistor 500.
[0106] In this embodiment, the portions of the first conductive layers 400 extending along the second direction on both sides of the first trench 301 and the portion corresponding to the first via 302 can serve as the first source and drain 510 of the transistor 500, and can also connect multiple transistors 500 arranged along the second direction.
[0107] Optionally, the material of the semiconductor structure 520 includes metal oxide semiconductor materials or silicon-containing materials. Among them, metal oxide semiconductor materials include IGZO (Indium Gallium Zinc Oxide), ITO (Indium Tin Oxide), and IWO (Indium Wolfmium Oxide). Oxide (indium tungsten oxide), InGaO (indium gallium oxide), ZnO (zinc oxide), InO (indium oxide), InO (indium oxide), InWO (indium tungsten oxide), SnO (tin oxide), TiO (titanium oxide), InSnO (indium tin oxide), ZnON (nitrogen-doped zinc oxide), MgZnO (magnesium zinc oxide), InZnO (indium zinc oxide), InGaZnO (indium gallium zinc oxide), ZrInZnO (zinc zirconium oxide), HfInZnO (hafnium indium zinc oxide), SnInZnO (tin indium zinc oxide), AlZnO (zinc aluminum oxide), AlSnInZnO (zinc aluminum indium oxide), SiInZnO (zinc silicon oxide), ZnSnO (zinc tin oxide), AlZnSnO (zinc aluminum oxide), GaZnSnO (zinc gallium oxide), ZrZnSnO (zinc zirconium oxide), and InGaSiO (indium gallium silicon oxide), etc.
[0108] In some possible embodiments, the semiconductor device further includes: The capacitor 600 includes a first electrode structure 610, a third dielectric layer 620 located within a second via 303, and a second electrode structure 630.
[0109] In this embodiment, the first electrode structure 610 of capacitor 600 is electrically connected to the semiconductor structure 520 of transistor 500, so that capacitor 600 is electrically connected to transistor 500, and transistor 500 controls access to capacitor 600, that is, reading or writing data.
[0110] Optionally, the first electrode structure 610 can be reused as the second source-drain 550 of the transistor 500.
[0111] Optionally, the semiconductor device provided in the embodiments of this application includes a three-dimensional dynamic random access memory.
[0112] Thirdly, embodiments of this application provide an electronic device, including: a semiconductor device manufactured by any of the semiconductor device manufacturing methods provided in the foregoing embodiments, or any of the semiconductor devices provided in the foregoing embodiments.
[0113] In this embodiment, since the electronic device uses any of the semiconductor devices provided in the foregoing embodiments, the principle and technical effects are described in the foregoing embodiments and will not be repeated here.
[0114] Optionally, the electronic device includes a smartphone, computer, tablet, artificial intelligence device, wearable device, or power bank.
[0115] It should be noted that the electronic devices are not limited to the above-mentioned types. Those skilled in the art can set any of the semiconductor devices provided in the above embodiments of this application in different devices according to actual application needs, thereby obtaining the electronic devices provided in the embodiments of this application.
[0116] Those skilled in the art will understand that the electronic devices provided in the embodiments of this application can be specifically designed and manufactured for a desired purpose, or may include known devices in general-purpose computers. These devices have any of the semiconductor devices provided in the various embodiments described above.
[0117] By applying the embodiments of this application, at least the following beneficial effects can be achieved: 1. Before fabricating the stacked structure 300, a protective layer 200 is formed on the substrate 100 to protect the substrate 100. In subsequent semiconductor device fabrication processes, when the first sacrificial structure 101 needs to be etched, because the etching rate of the first sacrificial structure 101 is greater than the etching rate of the protective layer 200, the protective layer 200 is either not completely removed or just removed after the first sacrificial structure 101 is etched. This prevents damage to the substrate 100 during etching, thereby ensuring the integrity and effective performance of the semiconductor device.
[0118] 2. A protective layer 200 containing silicon-germanium material can be formed on the silicon substrate 100 through epitaxial growth process. The manufacturing process is mature and helps to control costs.
[0119] 3. The ratio of the wet etching rate of the first sacrificial structure 101 to the wet etching rate of the protective layer 200 is greater than 45:1. That is, the etchant used in the wet etching has a high etching selectivity for the protective layer, so that after the first sacrificial structure 101 is etched, there is still a protective layer 200 of a certain thickness, ensuring the integrity of the substrate 100.
[0120] 4. By replacing the second sacrificial structure 103 exposed by the first trench 301 and the second via 303 with the second dielectric structure 105, which is distinguished from the first sacrificial structure 101, the etching rate of the first sacrificial structure 101 is greater than that of the second dielectric structure 105. This ensures that the second dielectric structure 105 is still retained after the first sacrificial structure 101 is removed, thus providing a certain degree of protection for the first electrode structure 610 and preventing the first electrode structure 610 from being affected during the etching of the first sacrificial structure 101.
[0121] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in related technologies that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.
[0122] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0123] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0124] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.
[0125] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: A protective layer is formed on the substrate; A stacked structure is formed on the protective layer, the stacked structure comprising alternating layers of first dielectric layers and layers of first insulating layers; The stacked structure has a plurality of first grooves extending along a second direction and spaced apart in a first direction, a plurality of first vias and a plurality of second vias, wherein the first vias and the second vias are sequentially moved away from the first grooves along the first direction. The first direction intersects the second direction and is parallel to the substrate; Based on the first trench, the multilayer first insulating layer on both sides of the first trench is etched to form a multilayer first conductive layer extending along the second direction. Based on the second via, the multilayer first insulating layer around the second via is etched to form a multilayer first electrode structure; Based on the first via, the first dielectric layer between any two first conductive layers and between any two first electrode structures on the outer periphery of the first via is replaced with a first sacrificial structure. A conformal semiconductor material layer, a gate insulating layer, and a gate layer are sequentially deposited within the first via. The first sacrificial structure is removed based on the second via and the first trench, exposing the semiconductor material layer; The etching rate of the first sacrificial structure is greater than the etching rate of the protective layer; The exposed semiconductor material layer is removed, and the remaining semiconductor material layer forms a semiconductor structure.
2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, A protective layer is formed on one side of the substrate, including: The protective layer is epitaxially grown on one side of the substrate, and the material of the protective layer includes silicon and germanium.
3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, A protective layer is formed on one side of the substrate, including: Germanium or boron is implanted onto the surface of the substrate to form an amorphous layer; The amorphous layer is heat-treated to obtain the protective layer, wherein the material of the protective layer includes silicon germanium or borosilicate.
4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The first sacrificial structure is removed based on the second via and the first trench, exposing the semiconductor material layer; The etching rate of the first sacrificial structure is greater than the etching rate of the protective layer, including: Based on the second via and the first trench, the first sacrificial structure is removed by wet etching to expose the semiconductor material layer; the wet etching rate of the first sacrificial structure is greater than the wet etching rate of the protective layer.
5. The method for manufacturing a semiconductor device according to claim 4, characterized in that, The ratio of the wet etching rate of the first sacrificial structure to the wet etching rate of the protective layer is greater than 45:
1.
6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Based on the first trench, multiple layers of first insulating layers on both sides of the first trench are etched to form multiple layers of first conductive layers extending along the second direction, including: The first insulating layer exposed on the sidewall of the first trench is etched back to form a multi-layer first groove located on both sides of the first trench and extending along the second direction. A first conductive layer extending in the second direction is formed in the first groove, and the portion of the first conductive layer that overlaps with the first via in the first direction forms a first source and drain electrode. A second insulating layer is deposited within the first trench and the first recess, covering the exposed surface of the first conductive layer.
7. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Based on the second via, the multilayer first insulating layer around the second via is etched to form a multilayer first electrode structure, including: The exposed multilayer first insulating layer on the sidewall of the second via is etched back to form a multilayer second groove located on the outer periphery of the second via. A conformal first conductive material and a second sacrificial structure are sequentially deposited in the second via and the second groove; The second sacrificial structure and the first conductive material in the second via are removed sequentially, and the first conductive material in the second groove forms the first electrode structure. A third insulating layer is deposited within the second via.
8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, Removing the first sacrificial structure based on the second via and the first trench includes: Remove the third insulating layer in the second via and the second insulating layer in the first trench to expose the first sacrificial structure and the second sacrificial structure; Replace the second sacrificial structure with the second medium structure; Remove the first sacrificial structure exposed by the second via and the first trench to expose the semiconductor material layer; the etching rate of the first sacrificial structure is greater than the etching rate of the second dielectric structure.
9. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Also includes: A third dielectric layer and a second electrode structure are sequentially formed within the second via, and the first electrode structure, the third dielectric layer, and the second electrode structure form a capacitor.
10. A semiconductor device, characterized in that, include: A protective layer is disposed on the substrate; A semiconductor stacked structure is disposed on the protective layer, comprising alternating layers of first dielectric layers and multiple transistors; The stacked structure has a plurality of first grooves extending along a second direction and spaced apart in a first direction, a plurality of first vias and a plurality of second vias, wherein the first vias and the second vias are sequentially moved away from the first grooves along the first direction. The first direction intersects the second direction and is parallel to the substrate; The first via is sequentially filled with the semiconductor structure of the transistor, the gate insulating layer, and the gate layer; The outer periphery of the second via is provided with a multilayer first electrode structure that is connected to the semiconductor structure of the multilayer transistor.
11. The semiconductor device according to claim 10, characterized in that, The material of the protective layer includes at least one of silicon-germanium and borosilicate.
12. The semiconductor device according to claim 10, characterized in that, The protective layer is made of silicon and germanium, with a germanium concentration of not less than 5% and not more than 20%.
13. The semiconductor device according to claim 10, characterized in that, Multiple first conductive layers extending along the second direction are provided on both sides of the first trench. Along the first direction, the first conductive layer corresponding to the first via forms the first source and drain of the transistor.
14. The semiconductor device according to claim 10, characterized in that, Also includes: The capacitor includes the first electrode structure, a third dielectric layer located within the second via, and a second electrode structure.
15. An electronic device, characterized in that, include: A semiconductor device manufactured by the manufacturing method of any of the semiconductor devices described in claims 1-9 above, or a semiconductor device described in any of the semiconductor devices described in claims 10-14 above.