Semiconductor structure, preparation method thereof and semiconductor device

Abstract

The embodiment of the invention provides a semiconductor structure, a preparation method thereof and a semiconductor device, and relates to the technical field of semiconductors. The semiconductor structure comprises a plurality of wafer groups which are arranged in a stacked mode, and every two adjacent wafer groups are bonded. The wafer group comprises a wafer and a first interconnection part. The number of the wafers is multiple, the multiple wafers are arranged in a stacked mode, and every two adjacent wafers are bonded. The wafer comprises an insulating medium and a metal wire, and the metal wire is embedded in the insulating medium. The first interconnection part is coupled with the metal wire. Wherein the plurality of wafer groups comprise a first wafer group and a second wafer group which are arranged adjacently. The second wafer group further comprises a second interconnection part, and the second interconnection part penetrates through the plurality of wafers in the second wafer group along the stacking direction and avoids the metal wiring of the second wafer group. The second interconnection part of the second wafer group is coupled with the first interconnection part of the first wafer group. According to the embodiment of the invention, the limitation of the punching depth of the machine on the number of the laminated wafers can be reduced, and the integration level of the semiconductor structure is improved.

Description

Technical Field

[0001] This disclosure relates to the technical field of semiconductor devices, and more particularly to a semiconductor structure, a method for fabricating the same, and a semiconductor device. Background Technology

[0002] In the process of fabricating semiconductor structures, it is usually necessary to drill holes in multiple stacked wafers to expose the metal traces of the wafers. Then, metal is filled into the holes to form an interconnect structure, which enables the interconnect structure to lead out the metal traces of the wafers.

[0003] However, the limited drilling depth of the machine restricts the number of wafers that can be stacked, thus affecting the integration density of the semiconductor structure. Summary of the Invention

[0004] Embodiments of this disclosure provide semiconductor structures, methods for fabricating them, and semiconductor devices.

[0005] The embodiments of this disclosure adopt the following technical solutions:

[0006] On one hand, embodiments of this disclosure provide a semiconductor structure. The semiconductor structure includes multiple wafer groups stacked together, with adjacent wafer groups bonded together. Each wafer group includes a wafer and a first interconnect portion. There are multiple wafers stacked together, with adjacent wafers bonded together. Each wafer includes an insulating dielectric and metal traces embedded within the insulating dielectric. The first interconnect portion is coupled to the metal traces. The multiple wafer groups include a first wafer group and a second wafer group arranged adjacently. The second wafer group further includes a second interconnect portion. The second interconnect portion penetrates through the multiple wafers in the second wafer group along the stacking direction and avoids the metal traces of the second wafer group. The second interconnect portion of the second wafer group is coupled to the first interconnect portion of the first wafer group.

[0007] In some embodiments, the wafer includes a substrate and an interconnect medium, wherein the interconnect medium and an insulating medium are disposed in a direction parallel to the substrate to form an epitaxial layer. The epitaxial layer is stacked on one side of the substrate. The interconnect medium and the substrate are made of the same material. A second interconnect portion penetrates the interconnect medium and substrate of a plurality of wafers in the second wafer group along the stacking direction.

[0008] In some embodiments, the insulating medium includes a stepped portion that is close to the interconnect medium in a direction parallel to the substrate. Multiple stepped portions in the same wafer group are arranged in a stepped configuration along the stacking direction. A first interconnect portion extends along the stacking direction, and one end of the first interconnect portion is embedded within the stepped portion and coupled to a metal trace.

[0009] In some embodiments, multiple step portions in the same wafer group constitute a step group, and the step groups of multiple wafer groups are arranged in a step shape along the stacking direction.

[0010] In some embodiments, the wafer group includes a first wafer to an nth wafer, which are stacked sequentially. The first interconnect portion includes a first type of first interconnect portion and a second type of first interconnect portion. The first type of first interconnect portion is embedded in a step portion of the nth wafer and coupled to the metal traces of the nth wafer. The second type of first interconnect portion penetrates the interconnect medium and substrate of the nth to mth wafers, and one end of the second type of first interconnect portion is embedded in a step portion of the (m-1)th wafer and coupled to the metal traces of the (m-1)th wafer. Wherein, n and m are both positive integers, and both n and m are greater than or equal to 2. n is greater than or equal to m.

[0011] In some embodiments, the substrate material includes monocrystalline silicon, and the interconnect medium material includes polycrystalline silicon.

[0012] In some embodiments, along the stacking direction, the second interconnect portion and the first interconnect portion coupled to the second interconnect portion are partially offset.

[0013] In some embodiments, the wafer assembly further includes a first insulating layer located between the first interconnect portion and the wafer.

[0014] In some embodiments, the second wafer group further includes a second insulating layer located between the second interconnect and the wafer.

[0015] In some embodiments, the first wafer group and the second wafer group are bonded using at least one of hybrid bonding and microbump bonding.

[0016] In some embodiments, in any wafer group, two adjacent wafers are bonded using at least one of hybrid bonding and microbump bonding.

[0017] In some embodiments, the number of wafers in the first wafer group is equal to the number of wafers in the second wafer group.

[0018] On the other hand, embodiments of this disclosure provide a method for fabricating a semiconductor structure. The method includes: forming a first wafer group. The first wafer group includes wafers and a first interconnect portion. Multiple wafers are stacked, and adjacent wafers are bonded. Each wafer includes an insulating dielectric and metal traces embedded within the insulating dielectric. The first interconnect portion is coupled to the metal traces. A second wafer group is then formed. The first wafer group includes wafers, a first interconnect portion, and a second interconnect portion. Multiple wafers are stacked, and adjacent wafers are bonded. Each wafer includes an insulating dielectric and metal traces embedded within the insulating dielectric. The first interconnect portion is coupled to the metal traces. The second interconnect portion penetrates through the multiple wafers in the second wafer group along the stacking direction and avoids the metal traces of the second wafer group. The second interconnect portion of the second wafer group is coupled to the first interconnect portion of the first wafer group.

[0019] In some embodiments, forming a second wafer stack includes: providing a plurality of wafers. Each wafer includes an initial epitaxial layer of a substrate, the initial epitaxial layer being stacked on one side of the substrate. The initial epitaxial layer includes an insulating dielectric. A dielectric receiving via is formed in the initial epitaxial layer, the dielectric receiving via penetrating the initial epitaxial layer along the stacking direction. An interconnect dielectric is filled within the dielectric receiving via, the interconnect dielectric and the insulating dielectric forming an epitaxial layer. The interconnect dielectric and the substrate are made of the same material. The plurality of wafers are stacked, and adjacent wafers are bonded to form a second stack. A first interconnect portion and a second interconnect portion are formed.

[0020] In some embodiments, forming a first interconnect portion and a second interconnect portion includes: forming a first interconnect portion receiving hole extending along a stacking direction to expose metal traces; forming a second interconnect portion receiving hole penetrating the interconnect dielectric and substrate of a plurality of wafers in a second stack along the stacking direction; forming a first interconnect portion within the first interconnect portion receiving hole; and forming a second interconnect portion within the second interconnect portion receiving hole.

[0021] In some embodiments, the insulating medium includes a stepped portion that is close to the interconnect medium along a direction parallel to the substrate. Multiple stepped portions in the same wafer group are arranged in a stepped manner along the stacking direction. The second wafer group includes a first wafer to an nth wafer, which are stacked sequentially. Forming a first interconnect receiving via includes: forming a first type of receiving via, which is formed on the stepped portion of the nth wafer and exposes the metal traces of the nth wafer; forming a second type of receiving via, which penetrates the interconnect medium and substrate of the nth to mth wafers, extends to the stepped portion of the (m-1)th wafer, and exposes the metal traces of the (m-1)th wafer. Wherein, n and m are both positive integers, and both n and m are greater than or equal to 2. n is greater than or equal to m. A first type of first interconnect is formed within the first type of receiving via. A second type of first interconnect is formed within the second type of receiving via.

[0022] In some embodiments, forming a second type of receiving via includes: forming an initial second type of receiving via, the initial second type of receiving via penetrating the interconnect medium and substrate of the nth to mth wafers and exposing a step portion of the (m-1)th wafer; removing a portion of the step portion of the (m-1)th wafer to expose the metal traces of the (m-1)th wafer, thereby forming the second type of receiving via.

[0023] In some embodiments, before forming the second interconnect within the second interconnect receiving hole, the method further includes: bonding a temporary substrate to an epitaxial layer exposed in the second stack. The exposed substrate in the second stack is then removed to expose the second interconnect receiving hole.

[0024] In some embodiments, forming a first wafer group includes: providing a plurality of wafers. Each wafer includes an initial epitaxial layer of a substrate, the initial epitaxial layer being stacked on one side of the substrate. The initial epitaxial layer includes an insulating dielectric. A dielectric receiving via is formed in the initial epitaxial layer, the dielectric receiving via penetrating the initial epitaxial layer along the stacking direction. An interconnect dielectric is filled within the dielectric receiving via, the interconnect dielectric and the insulating dielectric forming an epitaxial layer. The interconnect dielectric and the substrate are made of the same material. The plurality of wafers are stacked, and adjacent wafers are bonded to form a first stack. A first interconnect portion is formed.

[0025] In another aspect, embodiments of this disclosure provide a semiconductor device. The aforementioned semiconductor structure includes multiple stacked structures. The semiconductor device includes a stacked structure and a package structure, wherein the package structure encapsulates the stacked structure. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0027] Figure 1 This is a schematic diagram of the structure of a wafer assembly provided in some embodiments of this disclosure;

[0028] Figure 2 This is a schematic diagram of the structure of a wafer assembly provided in some other embodiments of this disclosure;

[0029] Figure 3 Schematic diagram of a semiconductor structure provided for some embodiments of this disclosure;

[0030] Figure 4 Schematic diagram of a semiconductor structure provided for some embodiments of this disclosure;

[0031] Figure 5 A schematic diagram showing the positional relationship between the first interconnection section and the second interconnection section provided for some embodiments of this disclosure;

[0032] Figure 6 Schematic diagram of a semiconductor structure provided for further embodiments of this disclosure;

[0033] Figure 7 A flowchart illustrating the steps of a method for fabricating a semiconductor structure provided in some embodiments of this disclosure;

[0034] Figure 8 Flowcharts of steps for fabricating semiconductor structures provided in other embodiments of this disclosure;

[0035] Figure 9 This is a schematic diagram of the structure of multiple wafers provided in some embodiments of this disclosure;

[0036] Figure 10 This is a schematic diagram of the structure of multiple wafers provided in other embodiments of this disclosure;

[0037] Figure 11 This is a schematic diagram of the structure of multiple wafers provided in some embodiments of the present disclosure;

[0038] Figure 12 This is a schematic diagram of the structure of multiple wafers provided in some embodiments of the present disclosure;

[0039] Figure 13 This is a schematic diagram of the structure of a stack provided in some embodiments of this disclosure;

[0040] Figure 14 Flowchart of steps for fabricating a semiconductor structure provided in some embodiments of this disclosure;

[0041] Figure 15 Flowchart of steps for fabricating a semiconductor structure provided in some embodiments of this disclosure;

[0042] Figure 16 A schematic diagram of the structure of the first interconnect portion receiving hole provided in some embodiments of this application;

[0043] Figure 17 Flowchart of steps for fabricating a semiconductor structure provided in some embodiments of this disclosure;

[0044] Figure 18 This is a schematic diagram of the structure of the initial receiving hole provided in some embodiments of this disclosure;

[0045] Figure 19 Schematic diagrams of the structure of the first interconnect portion receiving hole and the second interconnect portion receiving hole provided in some embodiments of this disclosure;

[0046] Figure 20 Schematic diagrams of the structure of the first insulating layer and the second insulating layer provided in some embodiments of this application;

[0047] Figure 21 Schematic diagrams of the structure of the temporary substrate and the second stack provided in some embodiments of this application;

[0048] Figure 22 This is a schematic diagram of the structure of a semiconductor device provided in some embodiments of this disclosure;

[0049] Figure 23 This is a schematic diagram of the structure of a semiconductor device provided for other embodiments of this disclosure. Detailed Implementation

[0050] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0051] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0052] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0053] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0054] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0055] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0056] Figure 1 This is a schematic diagram of the structure of a wafer assembly provided in some embodiments of this disclosure. For example... Figure 1 As shown, some embodiments of this disclosure provide a semiconductor structure 100. The semiconductor structure 100 may include a wafer group 110, which may include wafers 113 and a first interconnect portion 111. There are multiple wafers 113, which are stacked and adjacent wafers 113 are bonded together.

[0057] For example, multiple wafers 113 may include memory wafers and logic wafers. For instance, multiple wafers 113 may include multiple memory wafers and one logic wafer, with the memory wafers stacked and located on one side of the logic wafer. Memory wafers may include DRAM dies, and logic wafers may include logic dies. The multiple wafers 113 are stacked such that wafer group 110 may include multiple stacked structures. It is understood that any stacked structure includes multiple stacked memory dies and one logic die.

[0058] For example, the stack structure can be a high bandwidth memory (HBM) stack. Alternatively, the stack structure can be other types of stacks. Multiple stack structures can be separated by dicing wafer group 110.

[0059] Understandably, wafer set 110 may also include wafers other than memory wafers and logic wafers, in which case the stack structure includes particles other than memory particles and logic particles. Embodiments of this disclosure do not further limit this.

[0060] The bonding of two adjacent wafers (113) can be called wafer-to-wafer bonding. Compared to die-to-die bonding, wafer-to-wafer bonding can improve bonding efficiency and reduce production costs.

[0061] In some examples, within any wafer group 110, two adjacent wafers 113 can be bonded using at least one of hybrid bonding (HB) and microbump bonding. This configuration improves the bonding flexibility between adjacent wafers 113. Understandably, adjacent wafers 113 can also be bonded using other bonding methods besides hybrid bonding and microbump bonding.

[0062] Understandably, the stacking of multiple wafers 113 and the bonding of adjacent wafers 113 can increase the connection density between the multiple wafers 113, shorten the distance of signal transmission between the multiple wafers 113, increase the signal transmission speed, and increase bandwidth and information transmission rate.

[0063] Continue to refer to Figure 1 In some examples, wafer 113 may include a substrate 1133 and an epitaxial layer 1135, the epitaxial layer 1135 being stacked on one side of the substrate 1133.

[0064] For example, the thickness of the epitaxial layer 1135 can be approximately 5 micrometers (μm), such as 4μm, 5μm, 6μm, or 7μm. The thickness of the epitaxial layer 1135 of multiple wafers 113 can be the same or different. The thickness of the substrate 1133 can be approximately 5μm, such as 4μm, 5μm, 6μm, or 7μm. The thickness of the substrate 1133 of multiple wafers 113 can be the same or different. The embodiments of this disclosure do not further limit the values ​​of the thickness of the epitaxial layer 1135 and the substrate 1133.

[0065] like Figure 1As shown, the epitaxial layer 1135 may include an insulating dielectric 1131, that is, the wafer 113 may include an insulating dielectric 1131. For example, the insulating dielectric 1131 may include an oxide, such as silicon oxide. Alternatively, the insulating dielectric 1131 may also include nitrides, such as silicon nitride. Or, the insulating dielectric 1131 may also include other insulating materials with high dielectric constants. The embodiments of this disclosure do not further limit the material of the insulating dielectric 1131.

[0066] Wafer 113 may also include metal traces 1132. For example, the material of the metal traces 1132 may include at least one of metals such as tungsten, cobalt, copper, and aluminum. Embodiments of this disclosure do not further limit the material of the metal traces 1132.

[0067] like Figure 1 As shown, the metal trace 1132 is embedded within the insulating medium 1131. This allows the insulating medium 1131 to electrically isolate two adjacent metal traces 1132, and also to electrically isolate the metal trace 1132 from other conductive components or conductive traces, thereby reducing the risk of short circuits.

[0068] Continue to refer to Figure 1 In some examples, the first interconnect 111 is coupled to the metal trace 1132. For example, there can be multiple first interconnects 111, and the number of first interconnects 111 can be equal to the number of wafers 113, so that multiple first interconnects 111 can be coupled to the metal traces 1132 of multiple wafers 113 in a one-to-one correspondence.

[0069] Understandably, the first interconnect portion 111 can conduct electricity. The first interconnect portion 111 is coupled to the metal trace 1132, so that the multiple first interconnect portions 111 can lead out the metal trace 1132 of each wafer 113 respectively, thereby enabling the metal trace 1132 of each wafer 113 to be coupled to other conductive components respectively.

[0070] For example, the material of the first interconnect portion 111 may include at least one selected from tungsten, cobalt, copper, aluminum, doped polysilicon, and metal silicides. Embodiments of this disclosure do not further limit the material of the first interconnect portion 111. The materials of the first interconnect portion 111 and the metal trace 1132 may be the same or different.

[0071] The following example illustrates the coupling method between the first interconnect 111 and the metal trace 1132 of the wafer 113.

[0072] Continue to refer to Figure 1In some examples, wafer group 110 may include wafers 1 through n, which are stacked sequentially. Here, n is a positive integer, and n is greater than or equal to 2. For example, the value of n can be 2, 3, 4, 5, 6, etc., and the embodiments of this disclosure do not further limit the value of n.

[0073] In some of the drawings in this disclosure, Figure 1 For example, in order to clearly show the structure of the attached figure, four wafers 113 contained in wafer group 110 are shown (i.e., the value of n is 4). The attached figure does not limit the number of wafers 113 contained in wafer group 110 (i.e., the value of n).

[0074] The first interconnect portion 111 may extend along the stacking direction Z (the direction in which the plurality of wafers 113 are stacked). For example, as shown... Figure 1 As shown, the first interconnection section 111 may include a first type of first interconnection section 1111 and a second type of first interconnection section 1112.

[0075] The first type of first interconnect 1111 is embedded in the insulating medium 1131 of the nth wafer and coupled to the metal trace 1132 of the nth wafer. The second type of first interconnect 1112 extends through the nth to mth wafers along the stacking direction Z and is coupled to the metal trace 1132 of the (m-1)th wafer. Understandably, there can be multiple second type first interconnects 1112, and multiple second type first interconnects 1112 are coupled to the metal traces 1132 of the 1st to (n-1)th wafers in a one-to-one correspondence.

[0076] Where m is a positive integer, and m is greater than or equal to 2. n is greater than or equal to m. For example, the value of m can be 2, 3, 4, 5, 6, etc., and the embodiments of this disclosure do not further limit the value of m.

[0077] Taking n = 4 and m = 2, 3, or 4 as an example, continue to refer to... Figure 1 The first type of first interconnect 1111 is coupled to the metal trace 1132 of the fourth wafer. When m is 2, the second type of first interconnect 1112 penetrates through the fourth to the second wafer and is coupled to the metal trace 1132 of the first wafer. When m is 3, the second type of first interconnect 1112 penetrates through the fourth to the third wafer and is coupled to the metal trace 1132 of the second wafer. When m is 4, the second type of first interconnect 1112 penetrates through the fourth wafer and is coupled to the metal trace 1132 of the third wafer. In this way, the metal traces 1132 of the multiple wafers 113 can be coupled to the multiple first interconnects 111 respectively.

[0078] Understandably, the end of the first interconnect portion 111 is embedded in the insulating medium 1131 and coupled to the metal trace 1132. For example, the depth to which the first interconnect portion 111 is embedded in the insulating medium 1131 can be approximately 0.3 μm. Alternatively, the depth to which the first interconnect portion 111 is embedded in the insulating medium 1131 can be other values; the embodiments of this disclosure do not further limit the depth to which the first interconnect portion 111 is embedded in the insulating medium 1131.

[0079] Continue to refer to Figure 1 In some examples, wafer assembly 110 further includes a first insulating layer 114 located between the first interconnect portion 111 and the wafer 113.

[0080] Understandably, the first insulating layer 114 surrounds the first interconnect portion 111 and is located between the first interconnect portion 111 and the wafer 113, exposing the end face of the first interconnect portion 111 along the stacking direction Z, so that the end face of the first interconnect portion 111 can be coupled to the metal trace 1132 and other conductive components. The first insulating layer 114 can provide electrical isolation, reducing the risk of short circuits between the first interconnect portion 111 and other metal traces 1132 or conductive structures.

[0081] For example, the material of the first insulating layer 114 may include one or more combinations of oxides, nitrides, and other high dielectric constant insulating materials. Embodiments of this disclosure do not further limit the material of the first insulating layer 114.

[0082] Understandably, during the formation of the first interconnect portion 111, it is necessary to open a first interconnect portion receiving hole 111a in the alternately stacked insulating medium 1131 and substrate 1133. Figure 1 Not shown in the image, see [link / reference]. Figure 16 The first interconnect receiving hole 111a exposes the metal traces 1132 of the wafer 113. Then, the first interconnect receiving hole 111a is filled with a conductive material, such as metal, to form the first interconnect 111.

[0083] Creating the first interconnect receiving hole 111a on the alternately stacked insulating medium 1131 and substrate 1133 is quite difficult and requires multiple processes. For example, multiple segmented photolithography, deposition, and etching processes are required, which affects the processing efficiency of the semiconductor structure 100 and increases the production cost.

[0084] Furthermore, when the depth of the first interconnect receiving hole 111a reaches 15μm or more, it is difficult for current equipment to simultaneously etch the insulating medium 1131 (e.g., oxide) and the substrate 1133 (e.g., poly, silicon), which limits the number of stacked wafers 113 and is not conducive to the high integration of the semiconductor structure 100.

[0085] Figure 2 This is a schematic diagram of the structure of a wafer assembly provided in other embodiments of this disclosure. To improve production efficiency and reduce production costs, in some examples, such as... Figure 2 As shown, the epitaxial layer 1135 also includes an interconnect dielectric 1134. In other words, the wafer 113 also includes an interconnect dielectric 1134. The interconnect dielectric 1134 and the insulating dielectric 1131 are disposed along a direction parallel to the substrate 1133 to form the epitaxial layer 1135. The interconnect dielectric 1134 and the substrate 1133 are made of the same material.

[0086] Understandably, the interconnecting medium 1134 and the insulating medium 1131 are respectively stacked on one side of the substrate 1133. The interconnecting medium 1134 and the insulating medium 1131 can be disposed adjacent to each other, or they can be disposed at intervals.

[0087] For example, both the interconnect dielectric 1134 and the substrate 1133 can be made of silicon. For instance, the substrate 1133 can be made of monocrystalline silicon, and the interconnect dielectric 1134 can be made of polycrystalline silicon. This arrangement improves the ease of obtaining the substrate 1133 and the interconnect dielectric 1134.

[0088] In other examples, the materials of interconnect medium 1134 and substrate 1133 may also be single-crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or at least one of other semiconductor materials known in the art.

[0089] Continue to refer to Figure 2 In some examples, the semiconductor structure 100 may also include a third insulating layer 116, which surrounds the outer periphery of the interconnect medium 1134 and is located between the interconnect medium 1134 and the insulating medium 1131.

[0090] Understandably, the third insulating layer 116 provides electrical isolation, reducing the risk of short circuits between the interconnect dielectric 1134 and the metal trace 1132 or other conductive structures. The material of the third insulating layer 116 may include one or more combinations of oxides, nitrides, and other high-dielectric-constant insulating materials. The embodiments of this disclosure do not further limit the material of the third insulating layer 116.

[0091] In some examples, such as Figure 2 As shown, the insulating medium 1131 may include a stepped portion 1131a, which is adjacent to the interconnect medium 1134 in a direction parallel to the substrate 1133. It can be understood that the stepped portion 1131a is the portion of the insulating medium 1131 adjacent to the interconnect medium 1134, and the third insulating layer 116 may be located between the stepped portion 1131a and the interconnect medium 1134.

[0092] Along the stacking direction Z, multiple stepped portions 1131a in the same wafer group 110 are arranged in a stepped shape. One end of the first interconnect portion 111 is embedded in the stepped portion 1131a and coupled to the metal trace 1132.

[0093] like Figure 2 As shown, along the stacking direction Z, the interconnect medium 1134 of the second wafer and the step portion 1131a of the first wafer can be partially disposed opposite each other, the interconnect medium 1134 of the third wafer and the step portion 1131a of the second wafer can be partially disposed opposite each other, the interconnect medium 1134 of the fourth wafer and the step portion 1131a of the third wafer can be partially disposed opposite each other, and so on.

[0094] In this way, the first interconnect portion 111 (e.g., the second type of first interconnect portion 1112) can penetrate the interconnect medium 1134 and substrate 1133 of at least a portion of the wafer 113 (other wafers 113 located on the side of the wafer 113 coupled to the first interconnect portion 111) and be embedded in the step portion 1131a and coupled to the metal trace 1132.

[0095] In other words, by adopting the above-described arrangement, at least one first interconnect portion 111 (e.g., a second type of first interconnect portion 1112) can avoid the insulating medium 1131 and metal traces 1132 of at least a portion of the wafer 113 (other wafers 113 located on the side of the wafer 113 coupled to the first interconnect portion 111), thereby improving the efficiency of opening the first interconnect portion receiving hole 111a (see...). Figure 14 Convenience when using it.

[0096] Continue to refer to Figure 2 In some examples, the first type of first interconnect portion 1111 is embedded in the step portion 1131a of the nth wafer and coupled to the metal trace 1132 of the nth wafer. The second type of first interconnect portion 1112 penetrates the interconnect medium 1134 and the substrate 1133 of the nth to mth wafers, and one end of the second type of first interconnect portion 1112 is embedded in the step portion 1131a of the (m-1)th wafer and coupled to the metal trace 1132 of the (m-1)th wafer.

[0097] For example, if n equals 4 and m equals 2, 3, or 4, please refer to [link / reference]. Figure 2The first type of first interconnect 1111 is embedded in the step portion 1131a of the fourth wafer and coupled to the metal trace 1132 of the fourth wafer. When m is 2, the second type of first interconnect 1112 penetrates the interconnect medium 1134 and substrate 1133 of the fourth to second wafers, and one end of the second type of first interconnect 1112 is embedded in the step portion 1131a of the first wafer and coupled to the metal trace 1132 of the first wafer. When m is 3, the second type of first interconnect 1112 penetrates the interconnect medium 1134 and substrate 1133 of the fourth to third wafers, and one end of the second type of first interconnect 1112 is embedded in the step portion 1131a of the second wafer and coupled to the metal trace 1132 of the second wafer. When m is 4, the second type of first interconnect 1112 penetrates the interconnect medium 1134 and substrate 1133 of the fourth wafer, and one end of the second type of first interconnect 1112 is embedded in the step portion 1131a of the third wafer and coupled to the metal trace 1132 of the third wafer.

[0098] That is, multiple stepped portions 1131a in the same wafer group 110 are arranged in a stepped shape, so that the second type of first interconnect portion 1112 can penetrate the interconnect medium 1134 and substrate 1133 of at least a portion of the wafer 113 (other wafers 113 located on the side of the wafer 113 coupled to the first interconnect portion 111) and be coupled to the metal trace 1132.

[0099] In this way, it is unnecessary to form the first interconnect receiving hole 111a on the alternately stacked insulating medium 1131 and substrate 1133. Instead, the first interconnect receiving hole 111a can be formed on the alternately stacked interconnect medium 1134 and substrate 1133. Since the interconnect medium 1134 and substrate 1133 are made of the same material, the convenience of forming the first interconnect receiving hole 111a is improved, thereby improving the production efficiency of the semiconductor structure 100 and reducing the interconnection cost of the wafer-to-wafer bonding method, which means reducing the production cost of the semiconductor structure 100.

[0100] Furthermore, both the interconnect medium 1134 and the substrate 1133 can be made of silicon. The silicon etching (poly etch) process can achieve deep hole etching, which reduces the limitation imposed by the drilling depth of the machine on the number of stacked wafers 113, and is conducive to improving the 100-degree integration of the semiconductor structure.

[0101] Figure 3 This is a schematic diagram of a semiconductor structure provided for some embodiments of this disclosure. In some examples, such as... Figure 3 As shown, the semiconductor structure 100 includes a plurality of wafer groups 110 stacked together, with adjacent wafer groups 110 bonded together.

[0102] Understandably, the number of wafers 113 contained in different wafer groups 110 may be the same or different.

[0103] Continue to refer to Figure 3 Multiple wafer groups 110 may include a first wafer group 110a and a second wafer group 110b arranged adjacent to each other. In some examples, the number of wafers 113 in the first wafer group 110a is equal to the number of wafers 113 in the second wafer group 110b, so as to improve the structural regularity of the semiconductor structure 100.

[0104] In some examples, the first wafer set 110a and the second wafer set 110b are bonded using at least one of hybrid bonding and microbump bonding. This improves the bonding flexibility of the first wafer set 110a and the second wafer set 110b. It is understood that the first wafer set 110a and the second wafer set 110b may also be bonded using other bonding methods besides hybrid bonding and microbump bonding.

[0105] For example, the first wafer group 110a may include a plurality of memory wafers stacked together, and the second wafer group 110b may include a plurality of memory wafers stacked together and a logic wafer. The stacked arrangement of the first wafer group 110a and the second wafer group 110b enables the formation of multiple stacked structures. In other words, the stacked arrangement of the first wafer group 110a and the second wafer group 110b allows the semiconductor structure 100 to include multiple stacked structures.

[0106] In some examples, such as Figure 3 As shown, the thickness of the substrate 1133 of the wafer 113 furthest from the second wafer group 110b in the first wafer group 110a is greater than the thickness of the substrate 1133 of the other wafers 113 in the first wafer group 110a and the second wafer group 110b, so that the substrate 1133 of the wafer 113 furthest from the second wafer group 110b in the first wafer group 110a can play a supporting role.

[0107] Continue to refer to Figure 3 In some examples, the second wafer group 110b further includes a second interconnect portion 112. Understandably, both the first wafer group 110a and the second wafer group 110b include a first interconnect portion 111, while the second wafer group 110b includes both the first interconnect portion 111 and the second interconnect portion 112. The number of first interconnect portions 111 and second interconnect portions 112 in the second wafer group 110b may be the same or different.

[0108] The second interconnect portion 112 can function as an conductor. For example, the material of the second interconnect portion 112 may include at least one selected from tungsten, cobalt, copper, aluminum, doped polysilicon, and metal silicides. The embodiments of this disclosure do not further limit the material of the second interconnect portion 112. The materials of the second interconnect portion 112, the first interconnect portion 111, and the metal trace 1132 may be the same or different.

[0109] like Figure 3 As shown, the second interconnect portion 112 penetrates multiple wafers 113 in the second wafer group 110b along the stacking direction Z, and avoids the metal traces 1132 of the second wafer group 110b.

[0110] Understandably, the second interconnect portion 112 penetrates through multiple wafers 113 in the second wafer group 110b along the stacking direction Z, allowing the end face of the second interconnect portion 112 to be exposed in the multiple wafers 113 of the second wafer group 110b, thereby enabling coupling with other conductive structures (such as the first interconnect portion 111 of the first wafer group 110a). Furthermore, the second interconnect portion 112 avoids the metal traces 1132 of the second wafer group 110b, reducing the mutual interference between the second interconnect portion 112 and the metal traces 1132 of the second wafer group 110b.

[0111] In some examples, such as Figure 3 As shown, the second interconnect portion 112 penetrates the interconnect medium 1134 and substrate 1133 of multiple wafers 113 in the second wafer group 110b along the stacking direction Z.

[0112] For example, such as Figure 3 As shown, along the stacking direction Z, in the second wafer group 110b, the interconnect medium 1134 portions of any two wafers 113 are arranged opposite each other, so that the second interconnect portion 112 can penetrate the interconnect medium 1134 and the substrate 1133 of multiple wafers 113 in the second wafer group 110b along the stacking direction Z.

[0113] Understandably, the second interconnect portion 112 is configured to penetrate the interconnect medium 1134 and substrate 1133 of multiple wafers 113 in the second wafer group 110b along the stacking direction Z, so that the second interconnect portion 112 can avoid the insulating medium 1131 and the metal traces 1132 embedded in the insulating medium 1131.

[0114] In this way, during the formation of the second interconnect portion 112, it is not necessary to form the second interconnect portion receiving hole 112a on the alternately stacked insulating medium 1131 and substrate 1133, but the second interconnect portion receiving hole 112a can be formed on the alternately stacked interconnect medium 1134 and substrate 1133 (see...). Figure 19The interconnect medium 1134 and the substrate 1133 are made of the same material. During etching, no multiple processes are required. The second interconnect receiving hole 112a can be formed in one process, which improves the convenience of forming the second interconnect receiving hole 112a, thereby improving the production efficiency of the semiconductor structure 100 and reducing the interconnection cost of the wafer to wafer bonding method, thus reducing the production cost of the semiconductor structure 100.

[0115] In some examples, the method of forming the second interconnect receiving hole 112a in one process and forming the second interconnect 112 within the second interconnect receiving hole 112a can be referred to as a "one-step lead".

[0116] Furthermore, both the interconnect medium 1134 and the substrate 1133 can be made of silicon. The silicon etching (poly etch) process can achieve deep hole etching, which reduces the limitation imposed by the drilling depth of the machine on the number of stacked wafers 113, allowing more wafers 113 to be bonded, which is beneficial for the high integration of the semiconductor structure 100.

[0117] Continue to refer to Figure 3 In some examples, the second interconnect portion 112 of the second wafer group 110b is coupled to the first interconnect portion 111 of the first wafer group 110a.

[0118] For example, there may be multiple second interconnect portions 112. The number of second interconnect portions 112 in the second wafer group 110b may be equal to the number of first interconnect portions 111 in the first wafer group 110a, so that the multiple second interconnect portions 112 in the second wafer group 110b can be coupled one-to-one with the multiple first interconnect portions 111 in the first wafer group 110a. Understandably, there is a coupling surface between the second interconnect portions 112 and the first interconnect portions 111.

[0119] The first interconnect portion 111 is coupled to the metal trace 1132 of wafer 113 in the first wafer group 110a, and the second interconnect portion 112 of the second wafer group 110b is coupled to the first interconnect portion 111 of the first wafer group 110a. This allows the second interconnect portion 112 to be coupled to the metal trace 1132 of wafer 113 in the first wafer group 110a, thereby enabling the metal trace 1132 of wafer 113 in the first wafer group 110a to be led out and coupled to other conductive components. It can be understood that the metal trace 1132 of the second wafer group 110b can be coupled to other conductive components through the first interconnect portion 111 of the second wafer group 110b.

[0120] Understandably, the metal traces 1132 of multiple wafers 113 in the first wafer group 110a can be led out separately, and the metal traces 1132 of multiple wafers in the second wafer group 110b can also be led out separately, so that each wafer 113 in the first wafer group 110a and the second wafer group 110b can be coupled to other conductive components respectively.

[0121] By adopting the above configuration, the metal traces 1132 of the first wafer group 110a can be led out through the first interconnect portion 111 of the first wafer group 110a and the second interconnect portion 112 of the second wafer group 110b. It is not necessary to form a conductive structure that penetrates each wafer 113 in the second wafer group 110b and extends to the first wafer group 110a. Therefore, it is not necessary to form interconnect portion receiving holes (contact holes) that penetrate each wafer 113 in the second wafer group 110b and extend to the first wafer group 110a. This reduces the requirement for the drilling depth of the operating machine when fabricating the semiconductor structure 100, thereby reducing the limitation of the drilling depth of the operating machine on the number of wafers 113 to be bonded. This facilitates the bonding of a larger number of wafers 113, thereby improving the integration of the semiconductor structure 100.

[0122] Continue to refer to Figure 3 In some examples, the second wafer group 110b further includes a second insulating layer 115 located between the second interconnect portion 112 and the wafer 113.

[0123] The second insulating layer 115 surrounds the second interconnect portion 112, is located between the second interconnect portion 112 and the wafer 113, and exposes the end face of the second interconnect portion 112 along the Z-direction of the stacking, allowing the second interconnect portion 112 to be coupled to other conductive components. The second insulating layer 115 provides electrical isolation, reducing the risk of short circuits between the second interconnect portion 112 and the metal trace 1132 or other conductive structures. The material of the second insulating layer 115 may include one or more combinations of oxides, nitrides, and other high dielectric constant insulating materials.

[0124] Understandably, the embodiments of this disclosure do not further limit the material of the second insulating layer 115. The materials of the first insulating layer 114, the second insulating layer 115, and the third insulating layer 116 may be the same or different.

[0125] Figure 4 This is a schematic diagram of a semiconductor structure provided for some embodiments of this disclosure. In some examples, such as... Figure 4 As shown, multiple step portions 1131a in the same wafer group 110 form a step group 1131b. Along the stacking direction Z, the step groups 1131b of multiple wafer groups 110 are arranged in a step shape.

[0126] Taking the first wafer group 110a and the second wafer group 110b as examples, see... Figure 4 The step group 1131b of the first wafer group 110a and the step group 1131b of the second wafer group 110b are arranged in a step shape. Along the stacking direction Z, the interconnect medium 1134 of each wafer 113 in the second wafer group 110b can be arranged opposite to the first interconnect portion 111 of the first wafer group 110a.

[0127] The second interconnect portion 112 penetrates the interconnect medium 1134 and substrate 1133 of each wafer in the second wafer group 110b, so that the second interconnect portion 112 can be disposed at least opposite to the first interconnect portion 111, thereby improving the convenience of coupling the second interconnect portion 112 and the first interconnect portion 111 of the first wafer group 110a.

[0128] It can be grounded, and the second interconnection section 112 and the first interconnection section 111 of the first wafer group 110a can be completely opposite to each other or partially offset.

[0129] Figure 5 This diagram illustrates the positional relationship between the first interconnection section and the second interconnection section, as provided in some embodiments of this disclosure. In some examples, such as... Figure 5 As shown, along the stacking direction Z, the second interconnection section 112 and the first interconnection section 111 coupled to the second interconnection section 112 are partially staggered.

[0130] Understandably, tolerances often exist during the fabrication of the semiconductor structure 100, causing the second interconnect portion 112 and the first interconnect portion 111 coupled to the second interconnect portion 112 to be partially offset along the stacking direction Z, so as to improve the fabrication convenience of the semiconductor structure 100.

[0131] During the fabrication of the semiconductor structure 100, if the tolerance is small, the second interconnect portion 112 and the first interconnect portion 111 coupled to the second interconnect portion 112 can be arranged relative to each other or approximately relative to each other along the stacking direction Z.

[0132] Figure 6 This is a schematic diagram of a semiconductor structure provided for further embodiments of the present disclosure. In some examples, such as... Figure 6 As shown, there can be multiple second wafer groups 110b. When there are multiple second wafer groups 110b, they are stacked on one side of the first wafer group 110a. For example, the number of second wafer groups 110b can be 2, 3, or 4, etc. The embodiments of this disclosure do not further limit the number of second wafer groups 110b.

[0133] Taking the second wafer group 110b as an example with two wafers, see [link / reference]. Figure 6The two second wafer groups 110b may include a first second wafer group 110b1 and a second second wafer group 110b2. The first second wafer group 110b1 may be disposed adjacent to the first wafer group 110a, and the second second wafer group 110b2 may be stacked on the side of the first second wafer group 110b1 away from the first wafer group 110a.

[0134] The second wafer group 110b2 may include a first type of second interconnect portion 1121 and a second type of second interconnect portion 1122. The first type of second interconnect portion 1121 is coupled to the first interconnect portion 111 of the first second wafer group 110b1, and the second type of second interconnect portion 1122 is coupled to the second interconnect portion 112 of the first second wafer group 110b1. The second interconnect portion 112 of the first second wafer group 110b1 is coupled to the first interconnect portion 111 of the first wafer group 110.

[0135] Understandably, the metal traces 1132 of the first wafer group 110a can be led out through the first interconnect portion 111 of the first wafer group 110a, the second interconnect portion 112 of the first second wafer group 110b1, and the second type of second interconnect portion 1122 of the second second wafer group 110b2. The metal traces 1132 of the first second wafer group 110b1 can be led out through the first interconnect portion 111 of the first second wafer group 110b1 and the first type of second interconnect portion 1121 of the second second wafer group 110b2. The metal traces 1132 of the second second wafer group 110b2 can be led out through the first interconnect portion 111 of the second second wafer group 110b2.

[0136] This allows the metal traces 1132 of each wafer 113 in the first wafer group 110a, the first second wafer group 110b1, and the second first wafer group 110b2 to be brought out and coupled to other conductive components.

[0137] Understandably, when the number of second wafer groups 110b is greater than two, a similar arrangement can be adopted to bring out the metal traces 1132 of each wafer 113 separately. This reduces the requirement for the drilling depth of the operating machine when fabricating the semiconductor structure 100, thereby reducing the limitation imposed by the drilling depth of the operating machine on the number of wafers 113 to be bonded. This facilitates the bonding of a larger number of wafers 113, thereby improving the integration of the semiconductor structure 100.

[0138] On the other hand, embodiments of this disclosure provide a method for fabricating a semiconductor structure. For example, the method for fabricating a semiconductor structure provided by embodiments of this disclosure can be used to fabricate the semiconductor structure 100 described above.

[0139] It is understood that the method for preparing the semiconductor structure provided in the embodiments of this disclosure can be used to prepare the semiconductor structure 100 as described above, and therefore has all the above-described beneficial effects, which will not be repeated here.

[0140] Figure 7 This is a flowchart illustrating the steps of a method for fabricating a semiconductor structure according to some embodiments of this disclosure. In some examples, such as... Figure 7 As shown, the method for fabricating a semiconductor structure includes:

[0141] Step S1: Forming a first wafer group. The first wafer group includes wafers and a first interconnect portion. Multiple wafers are stacked, and adjacent wafers are bonded together. Each wafer includes an insulating dielectric and metal traces, with the metal traces embedded within the insulating dielectric. The first interconnect portion is coupled to the metal traces.

[0142] Step S2: Forming a second wafer group. The first wafer group includes wafers, a first interconnect portion, and a second interconnect portion. Multiple wafers are stacked, with adjacent wafers bonded together. Each wafer includes an insulating dielectric and metal traces embedded within the insulating dielectric. The first interconnect portion is coupled to the metal traces. The second interconnect portion penetrates the multiple wafers in the second wafer group along the stacking direction, avoiding the metal traces of the second wafer group.

[0143] Step S3: Couple the second interconnect portion of the second wafer group to the first interconnect portion of the first wafer group.

[0144] Understandably, the above embodiments of this disclosure have already provided examples of components such as the wafer 113, wafer group 110 (first wafer group 110a and second wafer group 110b), first interconnect portion 111, and second interconnect portion 112 of the semiconductor structure 100, and will not be repeated here.

[0145] By stacking multiple wafers 113 and bonding adjacent wafers 113 together, the connection density between the multiple wafers 113 can be increased, the distance of signal transmission between the multiple wafers 113 can be shortened, the signal transmission speed can be increased, and the bandwidth and information transmission rate can be increased.

[0146] The first interconnect portion 111 is coupled to the metal traces 1132 of the wafer 113, so that the first interconnect portion 111 can lead out the metal traces 1132 of the wafer 113, thereby enabling the metal traces 1132 of each wafer 113 in the wafer group 110 to be coupled to other conductive components respectively, realizing the interconnection between the wafer 113 and other conductive components.

[0147] Furthermore, by coupling the second interconnect portion 112 to the first interconnect portion 111 of the first wafer group 110a, the metal traces 1132 of the first wafer group 110a can be led out through the first interconnect portion 111 and the second interconnect portion 112. This eliminates the need to form a conductive structure that penetrates each wafer 113 in the second wafer group 110b and extends to the first wafer group 110a. Consequently, it eliminates the need to form receiving holes that penetrate each wafer 113 in the second wafer group 110b and extend to the first wafer group 110a. This reduces the requirement for drilling depth of the operating machine when fabricating the semiconductor structure 100, thereby reducing the limitation imposed by the drilling depth of the operating machine on the number of wafers 113 to be bonded. This facilitates the bonding of a larger number of wafers 113, thereby improving the integration density of the semiconductor structure 100.

[0148] Figure 8 This is a flowchart illustrating the steps of a method for fabricating a semiconductor structure according to other embodiments of this disclosure. In some examples, such as... Figure 8 As shown, forming the first wafer set (step S1) includes:

[0149] Step S11: Provide a plurality of wafers. Each wafer includes an initial epitaxial layer of a substrate, which is stacked on one side of the substrate. The initial epitaxial layer includes an insulating dielectric.

[0150] Figure 9 This is a schematic diagram illustrating the structure of multiple wafers provided in some embodiments of this disclosure. For example, as shown... Figure 9 As shown, the initial epitaxial layer 1135a includes an insulating dielectric 1131. In some examples, the initial epitaxial layer 1135a can be formed on one side of the substrate 1133 using any of the following thin film deposition processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), so that the initial epitaxial layer 1135a can be stacked with the substrate 1133. It is understood that the embodiments of this disclosure do not further limit the process for forming the initial epitaxial layer 1135a.

[0151] Step S12: A dielectric receiving hole is formed on the initial epitaxial layer, and the dielectric receiving hole penetrates the initial epitaxial layer along the stacking direction.

[0152] Figure 10 This is a schematic diagram illustrating the structure of multiple wafers provided in other embodiments of this disclosure. For example, such as... Figure 10As shown, a photolithography process can be used to form a dielectric receiving hole 1134a on the initial epitaxial layer 1135a, thereby patterning the insulating dielectric 1131. Alternatively, other etching processes can be used to form the dielectric receiving hole 1134a on the initial epitaxial layer 1135a.

[0153] For example, such as Figure 10 As shown, along the stacking direction Z, the dielectric receiving holes 1134a of a plurality of wafers 113 are staggered in sequence, and the dielectric receiving holes 1134a of any two wafers 113 are partially arranged opposite each other.

[0154] In some examples, such as Figure 9 and Figure 10 As shown, a metal trace 1132 can be formed in the insulating medium 1131 before forming the dielectric receiving hole 1134a. When forming the dielectric receiving hole 1134a, part of the insulating medium 1131 and part of the metal trace 1132 are removed to expose the substrate 1133.

[0155] In other examples, the metal trace 1132 may be formed within the insulating medium 1131 after the dielectric receiving hole 1134a is formed. In this way, it is not necessary to remove the metal trace 1132 when forming the dielectric receiving hole 1134a.

[0156] Step S13: Fill the dielectric receiving hole with interconnect dielectric, and the interconnect dielectric and insulating dielectric form an epitaxial layer. The interconnect dielectric and the substrate are made of the same material.

[0157] Figure 11 This is a schematic diagram of the structure of multiple wafers provided in some embodiments of this disclosure. Figure 12 This is a schematic diagram of the structure of multiple wafers provided in some embodiments of this disclosure. For example... Figure 11 and Figure 12 As shown, after forming the dielectric receiving hole 1134a, an interconnect dielectric 1134 can be filled into the dielectric receiving hole 1134a, and the interconnect dielectric 1134 and the insulating dielectric 1131 form an epitaxial layer 1135. The interconnect dielectric 1134 and the substrate 1133 are made of the same material; for example, both materials may include silicon. For example, the material of the interconnect dielectric 1134 may include polysilicon, and the material of the substrate 1133 may include polysilicon.

[0158] For example, a deposition process can be used to fill the interconnect medium 1134a into the dielectric receiving hole 1134a. Alternatively, other processes can be used to fill the interconnect medium 1134a into the dielectric receiving hole 1134a. The embodiments of this disclosure do not further limit the specific method of filling the interconnect medium 1134a into the dielectric receiving hole 1134a.

[0159] After the interconnect dielectric 1134 is filled into the dielectric receiving hole 1134a, the insulating dielectric 1131 and the interconnect dielectric 1134 can be smoothed by chemical mechanical polishing (CMP) process to improve the surface smoothness of the wafer 113.

[0160] Understandably, by forming a dielectric receiving hole 1134a on the initial epitaxial layer 1135a, and then filling the dielectric receiving hole 1134a with an interconnect dielectric 1134 to form an epitaxial layer 1135, the interconnect dielectric 1134 can replace the insulating dielectric 1131, thereby simplifying the subsequent drilling process, improving the production efficiency of the semiconductor structure 100, and reducing the cost of the semiconductor structure 100.

[0161] In some examples, such as Figure 11 As shown, before filling the interconnecting medium 1134 into the dielectric receiving hole 1134a, the dielectric receiving hole 1134a can be cleaned, and then a third insulating layer 116 is formed on the sidewall of the dielectric receiving hole 1134a.

[0162] For example, the third insulating layer 116 can be formed using any of the following thin film deposition processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). The embodiments of this disclosure do not further limit the process for forming the third insulating layer 116.

[0163] For example, a third insulating layer 116 may be formed on both the sidewall and bottom wall of the dielectric receiving hole 1134a, and then the third insulating layer 116 on the bottom wall of the dielectric receiving hole 1134a may be removed.

[0164] After the third insulating layer 116 is formed, the interconnecting dielectric 1134 is filled into the dielectric receiving hole 1134a, such as... Figure 12 As shown, this allows the third insulating layer 116 to be located between the interconnecting medium 1134 and the insulating medium 1131, serving as an electrical isolation layer and reducing the risk of short circuits between the interconnecting medium 1134 and conductive components such as the metal trace 1132.

[0165] Step S14: Multiple wafers are stacked together, and adjacent wafers are bonded together to form a first stack.

[0166] Figure 13 This is a schematic diagram of the structure of a stack provided in some embodiments of this disclosure. For example... Figure 13As shown, after filling the dielectric receiving holes 1134a of each wafer 113 with interconnect dielectric 1134, multiple wafers 113 can be stacked and adjacent wafers 113 can be bonded to form a first stack body 1101a.

[0167] Step S15: Form the first interconnection section.

[0168] After the stack body 1101 is formed, a first interconnect portion 111 is formed, so that the first stack body 1101a can become a first wafer group 110a.

[0169] Figure 14 A flowchart illustrating the steps of a method for fabricating a semiconductor structure provided in some embodiments of this disclosure.

[0170] In some examples, such as Figure 14 As shown, forming the second wafer set (i.e., step S2) includes:

[0171] Step S21: Provide a plurality of wafers. Each wafer includes an initial epitaxial layer of a substrate, which is stacked on one side of the substrate. The initial epitaxial layer includes an insulating dielectric.

[0172] Step S22: A dielectric receiving hole is formed on the initial epitaxial layer, and the dielectric receiving hole penetrates the initial epitaxial layer along the stacking direction.

[0173] Step S23: Fill the dielectric receiving hole with interconnect dielectric, and the interconnect dielectric and insulating dielectric form an epitaxial layer. The interconnect dielectric and the substrate are made of the same material.

[0174] Step S24: Multiple wafers are stacked together, and adjacent wafers are bonded together to form a second stack.

[0175] Step S25: The first interconnection section and the second interconnection section are formed.

[0176] Understandably, the method for forming the first stack 1101a is roughly the same as the method for forming the second stack 1101b (i.e., steps S11 to S14 and steps S21 to S24 are roughly the same), and will not be described in detail here.

[0177] Furthermore, the step of forming the first interconnect portion 111 on the first stack body 1101a (i.e., step S15) is substantially the same as the step of forming the first interconnect portion 111 on the second stack body 1101b.

[0178] The following example, using the second stack 1101b as an example, illustrates the method for forming the first interconnect portion 111 and the second interconnect portion 112.

[0179] Figure 15This is a flowchart illustrating the steps of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure. In some examples, such as... Figure 15 As shown, forming the first interconnect and the second interconnect (i.e., step S25) includes:

[0180] Step S251: A first interconnect receiving hole is formed, which extends along the stacking direction to expose the metal trace.

[0181] For example, the first interconnect receiving hole 111a can be formed using a photolithography process. Alternatively, other etching processes can also be used to form the first interconnect receiving hole 111a.

[0182] Figure 16 This is a schematic diagram illustrating the structure of a first interconnect portion receiving hole provided in some embodiments of this application. In some examples, such as... Figure 16 As shown, multiple first interconnect receiving holes 111a can be formed in the same process step to simplify the fabrication process of the semiconductor structure 100. Understandably, the multiple first interconnect receiving holes 111a expose the metal traces 1132 of multiple wafers 113 respectively.

[0183] In some examples, such as Figure 16 As shown, the insulating medium 1131 includes a stepped portion 1131a, which is close to the interconnect medium 1134 along a direction parallel to the substrate 1133. Along the stacking direction Z, multiple stepped portions 1131a in the same wafer group 110 are arranged in a stepped shape.

[0184] like Figure 16 As shown, along the stacking direction Z, the interconnect medium 1134 of the second wafer and the step portion 1131a of the first wafer can be partially disposed opposite each other, the interconnect medium 1134 of the third wafer and the step portion 1131a of the second wafer can be partially disposed opposite each other, the interconnect medium 1134 of the fourth wafer and the step portion 1131a of the third wafer can be partially disposed opposite each other, and so on.

[0185] Figure 17 This is a flowchart illustrating the steps of a method for fabricating a semiconductor structure according to some embodiments of the present disclosure. In some examples, such as... Figure 17 As shown, forming the first interconnect portion receiving hole 111a (step S251) includes:

[0186] Step S2511: Form a first type of receiving hole. The first type of receiving hole is opened on the step portion of the nth wafer and exposes the metal traces of the nth wafer.

[0187] Step S2512: A second type of receiving via is formed. This second type of receiving via penetrates the interconnect dielectric and substrate of wafers n to m, extends to the step portion of wafer (m-1), and exposes the metal traces of wafer (m-1). Here, n and m are both positive integers, and both n and m are greater than or equal to 2. n is greater than or equal to m.

[0188] See you again Figure 16 For example, a first type of receiving via 1111a and a second type of receiving via 1112a may be formed on one side of the epitaxial layer 1135 exposed in the first stack 1101a. The epitaxial layer 1135 exposed in the first stack 1101a may be the epitaxial layer 1135 of the nth wafer (e.g., the 4th wafer).

[0189] In this way, the exposed substrate 1133 (e.g., the substrate 1133 of the first wafer) in the first stack 1101a can play a supporting role, reducing the risk of the first stack 1101a breaking during the formation of the first type of receiving hole 1111a and the second type of receiving hole 1112a, and improving the reliability of the semiconductor structure fabrication method.

[0190] In step S2513, a first type of first interconnect portion is formed within the first type of receiving hole. A second type of first interconnect portion is formed within the second type of receiving hole.

[0191] For example, metal can be filled into the first type of receiving hole 1111a to form a first type of first interconnect 1111, such that the first type of first interconnect 1111 can be embedded in the step portion 1131a of the nth wafer and coupled to the metal trace 1132 of the nth wafer.

[0192] Similarly, metal can be filled into the second type of receiving hole 1112a to form a second interconnect portion 112, such that the second type of first interconnect portion 1112 can penetrate the interconnect medium 1134 and substrate 1133 of the nth to mth wafers, extend to the step portion 1131a of the (m-1)th wafer, and be coupled to the metal trace 1132 of the (m-1)th wafer.

[0193] For example, the value of n can be 2, 3, 4, 5, 6, etc., and the value of m can be 2, 3, 4, 5, 6, etc. The embodiments of this disclosure do not further limit the values ​​of n and m.

[0194] For example, the first type of first interconnect 1111 and the second type of first interconnect 1112 can be formed in the same process step to simplify the fabrication process of the semiconductor structure 100 and reduce the cost of the semiconductor structure 100.

[0195] In some examples, forming a second type of receiving hole (i.e., step S2512) includes:

[0196] An initial second type of containment hole is formed, which penetrates the interconnect medium and substrate of the nth to mth wafers and exposes the step portion of the (m-1)th wafer.

[0197] Remove a portion of the step portion of the (m-1)th wafer to expose the metal traces of the (m-1)th wafer, thereby forming a second type of receiving via.

[0198] Figure 18 This is a schematic diagram of the structure of an initial receiving hole provided in some embodiments of this disclosure. For example, when forming the second type of receiving hole 1112a, as... Figure 18 As shown, an initial receiving hole 1113a can be formed first, penetrating the interconnect medium 1134 and the substrate 1133 through the nth to mth wafers. Understandably, the initial receiving hole 1113a can expose the step portion 1131a of the (m-1)th wafer. Then, part of the step portion 1131a of the (m-1)th wafer is removed, so that the metal trace 1132 of the (m-1)th wafer can be exposed, thereby forming a second type of receiving hole 1112a that penetrates the interconnect medium 1134 and the substrate 1133 through the nth to mth wafers and exposes the metal trace 1132 of the (m-1)th wafer.

[0199] For example, during the process of removing a portion of the step portion 1131a, a portion of the step portion 1131a of the nth wafer can be removed simultaneously to form a first type of receiving hole 1111a.

[0200] Understandably, the interconnect medium 1134 and the substrate 1133 are made of the same material. A second type of receiving via 1112a is provided, penetrating the interconnect medium 1134 and the substrate 1133 from the nth wafer to the mth wafer. This eliminates the need to form the second type of receiving via 1112a on the alternately stacked insulating medium 1131 and the substrate 1133; instead, it can be formed on the alternately stacked interconnect medium 1134 and the substrate 1133. This simplifies the process of forming the second type of receiving via 1112a, improves the ease of forming it, increases the production efficiency of the semiconductor structure 100, and reduces the interconnection cost of wafer-to-wafer bonding, thus reducing the production cost of the semiconductor structure 100 and facilitating high integration of the semiconductor structure 100.

[0201] After forming the first interconnect receiving hole (i.e., step S251), see Figure 15 The methods for fabricating semiconductor structures also include:

[0202] Step S252: A second interconnect receiving hole is formed, which penetrates the interconnect medium and substrate of multiple wafers in the second stack along the stacking direction.

[0203] For example, the first interconnect receiving hole 111a and the second interconnect receiving hole 112a can be formed in the same process step to simplify the fabrication process of the semiconductor structure 100.

[0204] Alternatively, when forming the second wafer assembly 110b, one of the first interconnect receiving hole 111a and the second interconnect receiving hole 112a can be formed first, and then the other of the first interconnect receiving hole 111a and the second interconnect receiving hole 112a can be formed, reducing the risk of excessive drilling in the same process step, which could lead to the second stack 1101b breaking.

[0205] In some examples, the initial receiving hole 1113a and the second interconnect receiving hole 112a can be formed in the same process step, and then a portion of the step portion 1131a can be removed to expose the metal trace 1132 in order to form the first interconnect receiving hole 111a.

[0206] Figure 19 This is a schematic diagram of the structure of a first interconnect portion receiving hole and a second interconnect portion receiving hole provided for some embodiments of this disclosure. Figure 20 The diagram shows the structure of the first insulating layer and the second insulating layer provided in some embodiments of this application.

[0207] In some examples, such as Figure 19 and Figure 20 As shown, when forming the second interconnect receiving hole 112a, the second interconnect receiving hole 112a can penetrate the interconnect medium 1134 of a plurality of wafers 113 in the second stack 1101b along the stacking direction Z, and the substrate 1133 of the nth to the second wafer. For example, the second interconnect receiving hole 112a can extend to the substrate 1133 of the first wafer, but does not penetrate the substrate 1133 of the first wafer.

[0208] In some examples, after forming the second interconnect receiving hole, the following is also included:

[0209] The temporary substrate is bonded to the epitaxial layer exposed in the second stack.

[0210] Remove the exposed substrate from the second stack to expose the second interconnect receiving hole.

[0211] Figure 21 Schematic diagrams of the structure of a temporary substrate and a second stack provided for some embodiments of this application. Examples, such as... Figure 21As shown, the temporary substrate 101 can be bonded to the epitaxial layer 1135 of the nth wafer in the second stack 1101b. Then, the temporary substrate 101 and the second stack 1101b are flipped to remove part of the substrate 1133 of the first wafer, thereby exposing the second interconnect receiving hole 112a. At this time, the second interconnect receiving hole 112a can penetrate the interconnect medium 1134 and the substrate 1133 of multiple wafers 113 in the second stack 1101b.

[0212] For example, the temporary substrate 101 can be bonded to the second stack 1101b using temporary bonding adhesive, or the temporary substrate 101 can be bonded to the second stack 1101b using other methods. The embodiments of this disclosure do not further limit the method of bonding the temporary substrate 101 and the second stack 1101b.

[0213] Understandably, by removing part of the substrate 1133 of the first wafer under the support of the temporary substrate 101, thereby exposing the second interconnect receiving hole 112a, the risk of the second stack 1101b breaking can be reduced.

[0214] Step S253: A first interconnect portion is formed in the first interconnect portion receiving hole, and a second interconnect portion is formed in the second interconnect portion receiving hole.

[0215] Understandably, the first interconnect receiving hole 111a can expose the metal trace 1132, and the first interconnect 111 is formed in the first interconnect receiving hole 111a, so that the first interconnect 111 can be coupled to the metal trace 1132.

[0216] For example, the first interconnect portion 111 can be formed within the first interconnect portion receiving hole 111a using a deposition process. Taking the first interconnect portion 111 as a metal material, metal can be deposited within the first interconnect portion receiving hole 111a to form the first interconnect portion 111.

[0217] Alternatively, other processes may be used to form the first interconnect portion 111 within the first interconnect portion receiving hole 111a. The embodiments of this disclosure do not further limit the specific method of forming the first interconnect portion 111 within the first interconnect portion receiving hole 111a.

[0218] A first interconnect receiving hole 111a is formed to expose the metal trace 1132. Then, a first interconnect portion 111 is formed in the first interconnect receiving hole 111a, so that the first interconnect portion 111 can be coupled to the metal trace 1132. The process is simple and the processing convenience of the semiconductor structure 100 is improved.

[0219] For example, after the first interconnect portion 111 is filled into the first interconnect portion receiving hole 111a, a chemical mechanical polishing (CMP) process can be used to smooth it out in order to improve the surface smoothness of the wafer assembly 110.

[0220] In some examples, such as Figure 20 and Figure 21 As shown, before filling the first interconnect portion 111 into the first interconnect portion receiving hole 111a, the first interconnect portion receiving hole 111a can be cleaned, and then a first insulating layer 114 is formed on the sidewall of the first interconnect portion receiving hole 111a.

[0221] For example, the first insulating layer 114 can be formed using any of the following thin film deposition processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). It is understood that the embodiments of this disclosure do not further limit the process for forming the first insulating layer 114.

[0222] For example, a first insulating layer 114 may be formed on both the sidewall and the bottom wall of the first interconnect receiving hole 111a, and then the first insulating layer 114 on the bottom wall of the first interconnect receiving hole 111a may be removed.

[0223] After the first insulating layer 114 is formed, the first interconnect portion 111 is filled into the first interconnect portion receiving hole 111a, so that the first insulating layer 114 can be located between the first interconnect portion 111 and the wafer 113, playing an electrical isolation role and reducing the risk of short circuit between the first interconnect portion 111 and conductive components such as the metal trace 1132.

[0224] For example, after removing a portion of the substrate 1133 of the first wafer to expose the second interconnect receiving hole 112a, the second interconnect 112 can be formed within the second interconnect receiving hole 112a under the support of the temporary substrate 101. The temporary substrate 101 can support the second stack 1101b, reducing the risk of the second stack 1101b breaking during the formation of the second interconnect 112.

[0225] Alternatively, before bonding the temporary substrate 101 and the second stack 1101b, the second interconnect portion 112 can be formed within the second interconnect portion receiving hole 112a, supported by the substrate 1133 of the first wafer. At this time, the first interconnect portion 111 can be formed simultaneously within the first interconnect portion receiving hole 111a. The substrate 1133 of the first wafer can support the second stack 1101b, reducing the risk of the second stack 1101b breaking during the formation of the first interconnect portion 111 and the second interconnect portion 112.

[0226] For example, a deposition process can be used to form the second interconnect portion 112 within the second interconnect portion receiving hole 112a. Taking the second interconnect portion 112 as a metal material, metal can be deposited within the second interconnect portion receiving hole 112a to form the second interconnect portion 112.

[0227] Alternatively, other processes may be used to form the second interconnect portion 112 within the second interconnect portion receiving hole 112a. The embodiments of this disclosure do not further limit the specific method of forming the second interconnect portion 112 within the second interconnect portion receiving hole 112a.

[0228] Understandably, after the second interconnect portion 112 is formed in the second interconnect portion receiving hole 112a, the second stack body 1101b can become the second wafer group 110b.

[0229] The second interconnect receiving hole 112a penetrates the interconnect medium 1134 and substrate 1133 of multiple wafers 113 in the second stack 1101b along the stacking direction Z, and the second interconnect portion 112 is formed in the second interconnect receiving hole 112a, so that the second interconnect portion 112 can penetrate the interconnect medium 1134 and substrate 1133 of multiple wafers 113 in the second stack 1101b along the stacking direction Z. The process is simple and the processing convenience of the semiconductor structure 100 is improved.

[0230] For example, after the second interconnect portion 112 is filled into the second interconnect portion receiving hole 112a, a chemical mechanical polishing (CMP) process can be used to smooth it out in order to improve the surface smoothness of the wafer assembly 110.

[0231] For example, such as Figure 20 and Figure 21 As shown, before forming the second interconnect portion 112, the second interconnect portion receiving hole 112a can be cleaned, and then a second insulating layer 115 is formed on the sidewall of the second interconnect portion receiving hole 112a.

[0232] For example, the second insulating layer 115 can be formed using any of the following thin film deposition processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). It is understood that the embodiments of this disclosure do not further limit the process for forming the second insulating layer 115.

[0233] For example, a second insulating layer 115 may be formed on both the sidewall and the bottom wall of the second interconnection receiving hole 112a, and then the second insulating layer 115 on the bottom wall of the second interconnection receiving hole 112a may be removed.

[0234] After the second insulating layer 115 is formed, metal is filled into the second interconnection receiving hole 112a to form the second interconnection 112, so that the second insulating layer 115 can surround the outer periphery of the second interconnection 112 and play the role of electrical isolation, reducing the risk of short circuit between the second interconnection 112 and conductive components such as the metal trace 1132.

[0235] For example, the second interconnect portion 112 of the second wafer group 110b and the first interconnect portion 111 of the first wafer group 110a can be coupled under the support of the temporary substrate 101 to reduce the risk of the second wafer group 110b breaking during the coupling process. After the coupling is completed and the semiconductor structure 100 is formed, the temporary substrate 101 can be removed by debonding, or the temporary substrate 101 can be retained. The embodiments of this disclosure do not further limit this.

[0236] Figure 22 This is a schematic diagram of the structure of a semiconductor device provided in some embodiments of this disclosure. Figure 23 This is a schematic diagram of the structure of a semiconductor device provided for other embodiments of this disclosure.

[0237] Further embodiments of this disclosure provide a semiconductor device. For example, such as... Figure 22 As shown, the semiconductor device 200 may include a stack structure 210 and a package structure 204, with the package structure 204 encapsulating the stack structure 210.

[0238] For example, the package structure 204 can be a package substrate. Understandably, the package structure 204 can protect the stack structure 210.

[0239] Understandably, the semiconductor structure 100 described above may include multiple stacked structures 210. Cutting the semiconductor structure 100 allows the multiple stacked structures 210 to be separated, such as... Figure 23As shown, a separate stack structure 210 is formed. The stack structure 210 in the semiconductor device 200 can be any one of the multiple stack structures 210 of the semiconductor structure 100.

[0240] like Figure 22 As shown, the stack structure 210 may further include a first solder ball 213, which is located on the side of the logic chip 212 away from the storage chip 211 and is coupled to the logic chip 212. Furthermore, the first solder ball 213 is coupled to a pin 205 of the package structure 204.

[0241] For example, the semiconductor device 200 may also include an adapter layer 203, which may be a silicon bridge. The first solder ball 213 may be coupled to the adapter layer 203 and, through the adapter layer 203, to the pin 205 of the package structure 204.

[0242] In some examples, continue to refer to Figure 22 The semiconductor device 200 may further include a die 201, which may include a graphics processing unit (GPU). Alternatively, the die 201 may be other processing units. The die 201 can be coupled to the stack structure 210 via an adapter layer 203, and the die 201 can also be coupled to the pins 205 of the package structure 204 via the adapter layer 203.

[0243] Understandably, stacking multiple memory chips 211 and one logic chip 212 to form a stack structure 210 allows interconnection between the multiple memory chips 211 and between the memory chips 211 and the logic chip 212 via through silicon vias (TSVs). Compared to packaging the memory chips 211 and the logic chip 212 separately, this can shorten lead lengths, reduce impedance, and reduce signal transmission time.

[0244] In summary, the embodiments of this disclosure have at least the following beneficial effects:

[0245] In the embodiments of this disclosure, multiple wafers 113 are stacked and adjacent wafers 113 are bonded together, which can increase the connection density between the multiple wafers 113, shorten the distance of signal transmission between the multiple wafers 113, increase the signal transmission speed, and increase bandwidth and information transmission rate.

[0246] The first interconnect portion 111 is coupled to the metal traces 1132 of the wafer 113, so that the first interconnect portion 111 can lead out the metal traces 1132 of the wafer 113, thereby enabling the metal traces 1132 of each wafer 113 in the wafer group 110 to be coupled to other conductive components respectively, realizing the interconnection between the wafer 113 and other conductive components.

[0247] Furthermore, the first interconnect portion 111 can penetrate the interconnect medium 1134 and substrate 1133 of at least a portion of the wafer 113 (other wafers 113 located on the same side as the wafer 113 coupled to the first interconnect portion 111), and is embedded in the step portion 1131a and coupled to the metal trace 1132. In other words, the first interconnect portion 111 can avoid the insulating medium 1131 and metal trace 1132 of at least a portion of the wafer 113 (other wafers 113 located on the same side as the wafer 113 coupled to the first interconnect portion 111).

[0248] In this way, it is unnecessary to form the first interconnect receiving hole 111a on the alternately stacked insulating medium 1131 and substrate 1133. Instead, the first interconnect receiving hole 111a can be formed on the alternately stacked interconnect medium 1134 and substrate 1133. The interconnect medium 1134 and substrate 1133 are made of the same material, which simplifies the process of forming the first interconnect receiving hole 111a, improves the convenience of forming the first interconnect receiving hole 111a, improves the production efficiency of semiconductor structure 100, and reduces the interconnection cost of wafer to wafer bonding, that is, reduces the production cost of semiconductor structure 100.

[0249] Furthermore, both the interconnect medium 1134 and the substrate 1133 can be made of silicon. The silicon etching (poly etch) process can achieve deep hole etching, which reduces the limitation on the number of stacked wafers 113 caused by the drilling depth, allowing more wafers 113 to be bonded, which is beneficial to improving the 100-degree integration of the semiconductor structure.

[0250] Similarly, during the formation of the second interconnect portion 112, it is not necessary to form the second interconnect portion receiving hole 112a on the alternately stacked insulating medium 1131 and substrate 1133. Instead, the second interconnect portion receiving hole 112a can be formed on the alternately stacked interconnect medium 1134 and substrate 1133. In this way, multiple processes are not required during etching. The second interconnect portion receiving hole 112a can be formed in one process, which improves the convenience of forming the second interconnect portion receiving hole 112a, improves the production efficiency of the semiconductor structure 100, and reduces the interconnection cost of the wafer-to-wafer bonding method. That is, it reduces the production cost of the semiconductor structure 100 and facilitates the high integration of the semiconductor structure 100.

[0251] Furthermore, by coupling the second interconnect portion 112 to the first interconnect portion 111 of the first wafer group 110a, the metal traces 1132 of the first wafer group 110a can be led out through the first interconnect portion 111 and the second interconnect portion 112. The interconnect portion does not need to penetrate through each wafer 113 in the second wafer group 110b and extend to the first wafer group 110a. Therefore, it is not necessary to form receiving holes that penetrate through each wafer 113 in the second wafer group 110b and extend to the first wafer group 110a. This reduces the requirement for the drilling depth of the operating machine when fabricating the semiconductor structure 100, thereby reducing the limitation imposed by the drilling depth of the operating machine on the number of wafers 113 to be bonded. This facilitates the bonding of a larger number of wafers 113, thereby improving the integration of the semiconductor structure 100.

[0252] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Multiple wafer groups are stacked together, and adjacent wafer groups are bonded together; each wafer group includes a wafer and a first interconnect portion; there are multiple wafers stacked together, and adjacent wafers are bonded together; each wafer includes an insulating dielectric and a metal trace, and the metal trace is embedded in the insulating dielectric; the first interconnect portion is coupled to the metal trace; The plurality of wafer groups include a first wafer group and a second wafer group arranged adjacent to each other; the second wafer group further includes a second interconnect portion; the second interconnect portion penetrates through the plurality of wafers in the second wafer group along the stacking direction and avoids the metal traces of the second wafer group; the second interconnect portion of the second wafer group is coupled to the first interconnect portion of the first wafer group.

2. The semiconductor structure according to claim 1, characterized in that, The wafer includes a substrate and an interconnect dielectric, wherein the interconnect dielectric and the insulating dielectric are disposed in a direction parallel to the substrate to form an epitaxial layer; the epitaxial layer is stacked on one side of the substrate; wherein the interconnect dielectric and the substrate are made of the same material; The second interconnect portion extends through the interconnect medium and substrate of the plurality of wafers in the second wafer group along the stacking direction.

3. The semiconductor structure according to claim 2, characterized in that, The insulating medium includes a stepped portion that is close to the interconnect medium along a direction parallel to the substrate; along the stacking direction, multiple stepped portions in the same wafer group are arranged in a stepped shape; The first interconnect extends along the stacking direction, and one end of the first interconnect is embedded in the stepped portion and coupled to the metal trace.

4. The semiconductor structure according to claim 3, characterized in that, Multiple stepped portions in the same wafer group form a step group, and the step groups of the multiple wafer groups are arranged in a step shape along the stacking direction.

5. The semiconductor structure according to claim 3, characterized in that, The wafer group includes a first wafer to an nth wafer, which are stacked sequentially. The first interconnect portion includes a first type of first interconnect portion and a second type of first interconnect portion; the first type of first interconnect portion is embedded in the step portion of the nth wafer and coupled to the metal traces of the nth wafer; The second type of first interconnect portion penetrates the interconnect medium and substrate of the nth to mth wafers, and one end of the second type of first interconnect portion is embedded in the step portion of the (m-1)th wafer and coupled to the metal trace of the (m-1)th wafer; Where n and m are both positive integers, and both n and m are greater than or equal to 2; n is greater than or equal to m.

6. The semiconductor structure according to claim 2, characterized in that, The substrate is made of monocrystalline silicon, and the interconnect medium is made of polycrystalline silicon.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that, Along the stacking direction, the second interconnect portion and the first interconnect portion coupled to the second interconnect portion are partially staggered.

8. The semiconductor structure according to any one of claims 1 to 6, characterized in that, The wafer assembly further includes a first insulating layer located between the first interconnect portion and the wafer.

9. The semiconductor structure according to any one of claims 1 to 6, characterized in that, The second wafer assembly further includes a second insulating layer located between the second interconnect portion and the wafer.

10. The semiconductor structure according to any one of claims 1 to 6, characterized in that, The first wafer group and the second wafer group are bonded using at least one of hybrid bonding and microbump bonding.

11. The semiconductor structure according to any one of claims 1 to 6, characterized in that, In any of the wafer groups, two adjacent wafers are bonded using at least one of hybrid bonding and microbump bonding.

12. The semiconductor structure according to any one of claims 1 to 6, characterized in that, The number of wafers in the first wafer group is equal to the number of wafers in the second wafer group.

13. A method for fabricating a semiconductor structure, characterized in that, include: A first wafer group is formed; the first wafer group includes a wafer and a first interconnect portion; the number of wafers is multiple, the multiple wafers are stacked, and two adjacent wafers are bonded; the wafer includes an insulating medium and metal traces, the metal traces are embedded in the insulating medium; the first interconnect portion is coupled to the metal traces; A second wafer set is formed; the first wafer set includes a wafer, a first interconnect portion, and a second interconnect portion; the number of wafers is multiple, and the multiple wafers are stacked, with adjacent wafers bonded together; each wafer includes an insulating medium and metal traces, the metal traces being embedded in the insulating medium; the first interconnect portion is coupled to the metal traces; the second interconnect portion penetrates the multiple wafers in the second wafer set along the stacking direction, and avoids the metal traces of the second wafer set; The second interconnect portion of the second wafer group is coupled to the first interconnect portion of the first wafer group.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, Forming the second wafer set includes: providing a plurality of wafers; each wafer includes an initial epitaxial layer of a substrate, the initial epitaxial layer being stacked on one side of the substrate; the initial epitaxial layer includes an insulating dielectric. A dielectric accommodating hole is formed on the initial epitaxial layer, and the dielectric accommodating hole penetrates the initial epitaxial layer along the stacking direction; An interconnecting medium is filled into the dielectric receiving hole, and the interconnecting medium and the insulating medium form an epitaxial layer; wherein the interconnecting medium and the substrate are made of the same material; Multiple wafers are stacked together, and two adjacent wafers are bonded together to form a second stack. The first interconnection section and the second interconnection section are formed.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that, The formation of the first interconnection section and the second interconnection section includes: A first interconnect receiving hole is formed, which extends along the stacking direction to expose the metal trace; A second interconnect receiving hole is formed, which penetrates the interconnect medium and substrate of a plurality of wafers in the second stack along the stacking direction; The first interconnect portion is formed in the first interconnect portion receiving hole, and the second interconnect portion is formed in the second interconnect portion receiving hole.

16. The method for preparing a semiconductor structure according to claim 15, characterized in that, The insulating medium includes a stepped portion, which is close to the interconnect medium along a direction parallel to the substrate; along the stacking direction, multiple stepped portions in the same wafer group are arranged in a stepped shape; the second wafer group includes a first wafer to an nth wafer, which are stacked sequentially; Forming the first interconnect portion receiving hole includes: A first type of receiving hole is formed, which is opened on the step portion of the nth wafer and exposes the metal traces of the nth wafer; A second type of receiving hole is formed, which penetrates the interconnect medium and substrate of the nth to mth wafers, extends to the step portion of the (m-1)th wafer, and exposes the metal trace of the (m-1)th wafer; wherein, n and m are both positive integers, and n and m are both greater than or equal to 2; n is greater than or equal to m; A first type of first interconnect portion is formed within the first type of receiving hole; a second type of first interconnect portion is formed within the second type of receiving hole.

17. The method for preparing a semiconductor structure according to claim 16, characterized in that, Forming the second type of receiving hole includes: An initial second type of receiving hole is formed, the initial second type of receiving hole penetrating the interconnect medium and substrate of the nth wafer to the mth wafer, and exposing the step portion of the (m-1)th wafer; Remove a portion of the step portion of the (m-1)th wafer to expose the metal traces of the (m-1)th wafer, thereby forming the second type of receiving via.

18. The method for preparing a semiconductor structure according to claim 15, characterized in that, After forming the second interconnect receiving hole, it also includes: The temporary substrate is bonded to the exposed epitaxial layer in the second stack. Remove the exposed substrate from the second stack to expose the second interconnect receiving hole.

19. The method for preparing a semiconductor structure according to any one of claims 13 to 18, characterized in that, Forming the first wafer set includes: A plurality of wafers are provided; each wafer includes an initial epitaxial layer of a substrate, the initial epitaxial layer being stacked on one side of the substrate; the initial epitaxial layer includes an insulating dielectric. A dielectric accommodating hole is formed on the initial epitaxial layer, and the dielectric accommodating hole penetrates the initial epitaxial layer along the stacking direction; An interconnecting medium is filled into the dielectric receiving hole, and the interconnecting medium and the insulating medium form an epitaxial layer; wherein the interconnecting medium and the substrate are made of the same material; Multiple wafers are stacked together, and two adjacent wafers are bonded together to form a first stack. The first interconnection department was formed.

20. A semiconductor device, characterized in that, The semiconductor structure according to any one of claims 1 to 12 includes multiple stacked structures; The semiconductor device includes the stack structure and the package structure, wherein the package structure encapsulates the stack structure.

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