Semiconductor device and preparation method thereof
By forming a top sidewall on the gate structure as a mask, etching and thickening the gate metal, the problem of high channel resistance and gate metal resistance in semiconductor devices is solved, achieving a shorter channel length and lower resistivity, and improving signal transmission efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SILERGY SEMICON TECH (HANGZHOU) CO LTD
- Filing Date
- 2025-12-25
- Publication Date
- 2026-04-21
AI Technical Summary
In the prior art, the channel resistance and gate metal resistance of semiconductor devices are relatively large, making it difficult to effectively reduce the gate metal resistance when the gate length is reduced, and it is also difficult to define the window in photolithography.
By forming a top sidewall on the gate structure as a mask, etching the gate structure to form a shorter channel length, and thickening the gate metal in a self-aligned manner, a second metal layer with lower resistivity is deposited to reduce the gate resistance.
It effectively reduces the channel resistance and gate resistance of the device, shortens the signal transmission delay, breaks through the limits of photolithography equipment, and improves the performance of the device.
Smart Images
Figure CN121908569A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor device manufacturing technology, and in particular relates to a semiconductor device and its preparation method. Background Technology
[0002] As market demands for smaller size and higher energy efficiency in power devices increase, wide-bandgap GaN devices, due to their lower power loss and faster switching capabilities, have been widely used in high-frequency power conversion systems. Compared to silicon metal-oxide-semiconductor field-effect transistors (MOSFETs), GaN high electron mobility transistors (HEMTs) offer better quality factors and more promising performance in high-power and high-frequency applications.
[0003] The signal delay time of a device is positively correlated with the resistance of its gate metal. Therefore, reducing the gate metal resistance is crucial to minimizing signal delay. Typically, the gate interconnect metal is formed by photolithography of a window smaller than the gate length, within which a dock or other interconnect metal is deposited. However, as the gate length decreases and the device area increases, the gate metal resistance increases. Furthermore, defining a window smaller than the gate length through photolithography becomes extremely difficult, as it's impossible to directly thicken the metal on top of the gate. Designing devices with short gate lengths and low gate metal resistance is a pressing problem that needs to be solved. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor device and its fabrication method, which solves the problems of large channel resistance and large gate metal resistance in the prior art.
[0005] To achieve the above and other related objectives, the present invention provides a method for fabricating a semiconductor device. The method includes: forming an underlying structure, the underlying structure comprising at least a substrate layer and a channel layer above the substrate layer, and a barrier layer on the upper surface of the channel layer; forming a material layer for a gate structure above the barrier layer; forming a first dielectric layer on the material layer of the gate structure; forming a top sidewall of the gate structure on one or both sides of the first dielectric layer; removing the first dielectric layer; using the top sidewall as a mask, etching the material layer of the gate structure to form a gate structure; forming a first passivation layer above the underlying structure, wherein the first passivation layer covers the top sidewall and the gate structure; planarizing the first passivation layer and exposing the top sidewall; removing the top sidewall covered within the first passivation layer to form a first buried via; forming a second metal layer within the first buried via; and forming a source structure and a drain structure on both sides of the gate structure, respectively.
[0006] In other embodiments, the material layer of the gate structure includes: a P-type doped group III-V compound material layer covering the upper surface of the barrier layer and a metal layer covering the upper surface of the P-type doped group III-V compound material layer.
[0007] In other embodiments, the method of etching the material layer of the gate structure using the top sidewall as a mask to form the gate structure includes: using the top sidewall as a mask to etch the P-type doped III-V compound material layer to form a P-type gate of the gate structure, and etching the metal layer covering the upper surface of the P-type doped III-V compound material layer to form a gate metal layer of the gate structure.
[0008] In other embodiments, the underlying structure further includes a cap layer formed on the upper surface of the barrier layer.
[0009] In other embodiments, the material layer of the gate structure includes: a gate dielectric layer covering the upper surface of the cap layer and a metal layer covering the upper surface of the gate dielectric layer.
[0010] In other embodiments, the method of etching the material layer of the gate structure using the top sidewall as a mask to form the gate structure includes: using the top sidewall as a mask to etch a metal layer covering the upper surface of the gate dielectric layer to form a gate metal layer of the gate structure, wherein the gate metal layer and the gate dielectric layer covering the upper surface of the cap layer together constitute the gate structure.
[0011] In other embodiments, the method for removing the top sidewalls covered within the first passivation layer includes: removing the top sidewalls covered within the first passivation layer using a wet or dry etching method, wherein the selective etching ratio between the top sidewalls and the first passivation layer is greater than 3:1.
[0012] In other embodiments, top sidewalls of a gate structure are formed on both sides of the first dielectric layer. The gate structure includes a first gate structure and a second gate structure. The source structure includes a first source structure and a second source structure. The drain structure includes a first drain structure and a second drain structure. The first source structure and the first drain structure are located on both sides of the first gate structure, and the second source structure and the second drain structure are located on both sides of the second gate structure.
[0013] In other embodiments, the method of forming the source structure and the drain structure includes: etching the first passivation layer to form source contact holes and drain contact holes on both sides of the gate structure, and filling the source contact holes and drain contact holes with metal to form the source structure and the drain structure.
[0014] In other embodiments, the first source structure and the second source structure are combined into a single source structure.
[0015] In other embodiments, the source contact hole and the drain contact hole extend at least to the upper surface of the barrier layer.
[0016] In other embodiments, a second passivation layer is formed on the upper surface of the first passivation layer, the second passivation layer covering the source structure, drain structure, gate structure, and second metal layer; a source metal interconnect structure, a drain metal interconnect structure, and a gate metal interconnect structure are formed, wherein the contact holes of the source metal interconnect structure and the contact holes of the drain metal interconnect structure extend from the upper surface of the second passivation layer to the corresponding source structure and the drain structure, respectively, and the contact holes of the source metal interconnect structure and the contact holes of the drain metal interconnect structure are both located inside the active region; the contact holes of the gate metal interconnect structure extend from the upper surface of the second passivation layer to the gate structure, and the contact holes of the gate metal interconnect structure are located outside the active region.
[0017] In other embodiments, after forming a first passivation layer above the underlying structure, the fabrication method further includes: forming a third gate structure and a top dielectric layer located on the upper surface of the third gate structure, the third gate structure being located on a side other than the first gate structure and the second gate structure; forming a third passivation layer covering the upper surfaces of the first passivation layer and the third gate structure; and planarizing the first passivation layer and the third passivation layer to expose the top sidewall and the top dielectric layer.
[0018] In other embodiments, the preparation method further includes: removing the top sidewall and top dielectric layer covering the first passivation layer and the third passivation layer to form a first buried via and a second buried via, and forming a second metal layer and a third metal layer in the first buried via and the second buried via, respectively.
[0019] In other embodiments, forming a source structure and a drain structure on both sides of the gate structure includes: forming a first source structure and a first drain structure on both sides of the first gate structure, forming a second source structure and a second drain structure on both sides of the second gate structure, and forming a third source structure and a third drain structure on both sides of the third gate structure; wherein the third source structure and the third drain structure are formed synchronously with the first source structure, the first drain structure, the second source structure, and the second drain structure.
[0020] In other embodiments, the method of forming a third gate structure includes: etching the first passivation layer to form a first type of opening; forming a gate dielectric layer of the third gate structure on at least the sidewalls and bottomwalls of the first type of opening; depositing a metal material layer on at least the gate dielectric layer of the third gate structure; forming a top dielectric layer of the third gate structure in a predetermined region of the metal material layer; and etching the metal material layer using the top dielectric layer as a mask to form a gate electrode of the third gate structure.
[0021] In other embodiments, the method further includes: forming an isolation region between the second drain structure and the third source structure after forming a second passivation layer on the upper surface of the first passivation layer and before forming the source metal interconnect structure, the drain metal interconnect structure and the gate metal interconnect structure; wherein the isolation region extends from the upper surface of the barrier layer at least into the interior of the channel.
[0022] Secondly, this application provides a semiconductor device, the device comprising: a bottom layer, the bottom layer comprising at least a substrate layer and a channel layer above the substrate layer, and a barrier layer on the upper surface of the channel layer; a first passivation layer above the bottom layer, a first gate structure and a second gate structure above the bottom layer, and a second metal layer on the upper surfaces of the first gate structure and the second gate structure respectively; a first source structure and a first drain structure on both sides of the first gate structure, and a second source structure and a second drain structure on both sides of the second gate structure; wherein the first passivation layer covers the first source structure, the first drain structure and the first gate structure and the second metal layer on the upper surface of the first gate structure, and the first passivation layer also covers the second source structure, the second drain structure and the second gate structure and the second metal layer on the upper surface of the second gate structure, and the width of the first gate structure and the second gate structure is less than 1 μm.
[0023] In other embodiments, the first gate structure and the second gate structure include: a P-type gate located on the upper surface of the barrier layer and a gate metal layer located on the upper surface of the P-type gate, wherein the resistivity of the second metal layer is less than the resistivity of the gate metal layer.
[0024] In other embodiments, the projection of the second metal layer onto the underlying structure coincides with the projection of the gate metal layer onto the underlying structure.
[0025] In other embodiments, the underlying structure further includes a cap layer located on the upper surface of the barrier layer, wherein the material of the cap layer includes a group III-V compound.
[0026] In other embodiments, the first gate structure and the second gate structure include: a gate dielectric layer located on the upper surface of the cap layer and a gate metal layer located on the upper surface of the gate dielectric layer.
[0027] In other embodiments, the device further includes: a third source structure and a third drain structure located on the same side outside the first gate structure and the second gate structure; and a third gate structure located between the third source structure and the third drain structure and a third metal layer located on the upper surface of the third gate structure.
[0028] In other embodiments, the third gate structure includes: a gate dielectric layer of the third gate structure located at least on the sidewalls and bottomwalls of the first type of opening; and a gate electrode of the third gate structure located at least on the gate dielectric layer of the third gate structure, wherein the first type of opening is located within the first passivation layer and on the upper surface of the barrier layer.
[0029] In other embodiments, the device further includes: a third passivation layer covering the upper surface of the first passivation layer, and together with the first passivation layer, covering the first source structure, the first drain structure, the first gate structure, and the second metal layer located on the upper surface of the first gate structure; further covering the second source structure, the second drain structure, the second gate structure, and the second metal layer located on the upper surface of the second gate structure; and further covering the third source structure, the third drain structure, the third gate structure, and the third metal layer located on the upper surface of the third gate structure.
[0030] In other embodiments, the projection of the third metal layer onto the underlying structure coincides with the projection of the gate electrode of the third gate structure onto the underlying structure.
[0031] In other embodiments, the device further includes: a second passivation layer formed on the upper surface of the first passivation layer, the second passivation layer covering the source structure, the drain structure, the gate structure, and the second metal layer; a source metal interconnect structure electrically connected to the source structure, a drain metal interconnect structure electrically connected to the drain structure, and a gate metal interconnect structure electrically connected to the gate structure, wherein the contact holes of the source metal interconnect structure and the contact holes of the drain metal interconnect structure are both located inside the active region; and the contact holes of the gate metal interconnect structure are located outside the active region.
[0032] In other embodiments, the device further includes an isolation region located between the second drain structure and the third source structure; the isolation region extends from the upper surface of the barrier layer at least into the interior of the channel.
[0033] This invention defines a gate length that breaks through the limitations of photolithography equipment by forming the top sidewall of the gate structure, thereby reducing the channel resistance of the device. Furthermore, this invention reduces the gate resistance of the device by thickening the gate metal of enhancement-mode (E-mode) and / or depletion-mode (D-mode) devices through self-alignment. Simultaneously, the resistivity of the deposited second gate metal layer is lower than that of the first gate metal layer, further reducing the gate resistance and shortening the gate signal transmission delay of the GaN device. Attached Figure Description
[0034] Figure 1A-1N The diagram shows the structural steps of a HEMT device according to one embodiment of the present invention.
[0035] Figure 10 The diagram shown is a schematic diagram of the metal interconnect structure of the present invention;
[0036] Figure 2A-2L The diagram shows the structural steps of a HEMT device according to one embodiment of the present invention.
[0037] Figure 3A-3L The diagram shows the structural steps of a HEMT device according to one embodiment of the present invention.
[0038] Figure 3M The diagram shown is a schematic representation of the metal interconnect structure of the present invention. Detailed Implementation
[0039] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0040] First aspect, Embodiment 1: This application provides a method for fabricating a semiconductor device, the method comprising: forming an underlying structure, the underlying structure including at least a substrate layer and a channel layer above the substrate layer, and a barrier layer on the upper surface of the channel layer; forming a material layer of a gate structure above the barrier layer; forming a first dielectric layer on the material layer of the gate structure; forming a top sidewall of the gate structure on one or both sides of the first dielectric layer; removing the first dielectric layer; using the top sidewall as a mask, etching the material layer of the gate structure to form a gate structure; forming a first passivation layer above the underlying structure, wherein the first passivation layer covers the top sidewall and the gate structure; planarizing the first passivation layer and exposing the top sidewall; removing the top sidewall covered within the first passivation layer to form a first buried via; forming a second metal layer within the first buried via; and forming a source structure and a drain structure on both sides of the gate structure, respectively. In this embodiment, as... Figure 1A As shown, a bottom layer structure 10 is formed, comprising a substrate layer 101, a channel layer 103 on the substrate layer 101, and a barrier layer 104 on the surface of the channel layer 103, with a 2DEG formed at the contact surface between the channel layer 103 and the barrier layer 104. Further, in other embodiments, the bottom layer structure 10 also includes a buffer layer 102 located between the substrate layer 101 and the channel layer 103, and corresponding to the material of the channel layer 103, to release stress caused by lattice mismatch and thermal mismatch between the channel layer 103 and the substrate layer 101 during epitaxial growth. Specifically, the substrate layer 101 can be made of materials such as silicon substrate, sapphire substrate, silicon carbide substrate, diamond substrate, etc. The channel layer 103 can be made of group III nitride materials such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), etc. The barrier layer 104 can be made of a material corresponding to that of the channel layer 103, such as an AlGaN barrier layer, an InGaN barrier layer, or an InAlN barrier layer. When the channel layer 103 is a GaN channel layer, the buffer layer 102 can be made of a material such as Al... x Ga 1-x N-buffer layer, etc. The specific materials and thicknesses of the base layer 101, the buffer layer 102, the channel layer 103, and the barrier layer 104 are not limited here and can be selected as needed.
[0041] The HEMT device can be either a depletion-mode HEMT device or an enhancement-mode HEMT device; when the HEMT device is an enhancement-mode HEMT device, such as Figure 1BAs shown, a material layer for forming a gate structure is formed above the barrier layer 104. The gate structure material layer includes a P-type doped III-V compound material layer 201 covering the upper surface of the barrier layer 104 and a metal layer 202 covering the upper surface of the P-type doped III-V compound material layer 201. The III-V compound material includes one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium nitride (InAlN). The metal layer can be a gate metal suitable for HEMT devices, such as a TiN or Ni / Au stack structure forming a Schottky contact, but is not limited to these.
[0042] In this embodiment, a first dielectric layer 301 is formed on the material layer of the gate structure; a top sidewall 402 of the gate structure is formed on one or both sides of the first dielectric layer 301; as shown Figure 1C-1F As shown, a first dielectric layer 301 is formed on the upper surface of a predetermined region of the gate structure material layer. In this embodiment, as... Figure 1C As shown, a first dielectric layer 301 is formed on the upper surface of a predetermined region of the metal layer 202. The material of the first dielectric layer 301 can be a nitride insulating material, such as silicon nitride (SiN), or other insulating materials, such as silicon dioxide (SiO2), or it can be a stack of nitride insulating materials and oxide insulating materials, etc. Figure 1D As shown, a second dielectric layer 401 is formed on the upper surface of the gate structure material layer and the first dielectric layer. The second dielectric layer 401 covers the upper surface of the metal layer 202 and the first dielectric layer 301. The material of the second dielectric layer 401 can be a nitride insulating material, such as silicon nitride (SiN), or other insulating materials, such as silicon dioxide (SiO2), or a stack of nitride insulating materials and oxide insulating materials, etc. It should be noted that the first dielectric layer 301 and the second dielectric layer 401 are different dielectric layers, and the etching selectivity ratio between the two dielectric layers is greater than 3:1. The second dielectric layer 401 is fully etched to form the top sidewall 402 of the gate structure on one or both sides of the first dielectric layer 301. As an example, such as Figure 1E As shown, top sidewalls 402 of gate structures are formed on both sides of the first dielectric layer 301. In other examples, the second dielectric layer 401 is fully etched to form a top sidewall on one side of the first dielectric layer 301 (an embodiment where only one sidewall is formed is not shown in the figure). Figure 1F As shown, the first dielectric layer 301 is removed. The method of removing the first dielectric layer 301 can be dry etching or wet etching, and the method of removing the first dielectric layer 301 is not limited here.
[0043] In this embodiment, the top sidewall 402 is used as a mask to etch the material layer of the gate structure to form gate structures 20 and 21; as Figure 1G As shown, the etching of the gate structure material layer includes etching a P-type doped III-V compound material layer 201 covering the upper surface of the barrier layer 104 and a metal layer 202 covering the upper surface of the P-type doped III-V compound material layer 201. The etching method for the gate structure material layer can be dry etching or wet etching, which is not limited here. After etching, gate structures 20 and 21 are formed. The gate structures 20 and 21 include a lower P-type gate 203 and an upper gate metal layer 204. Here, we refer to the gate structures 20 and 21 as the first gate structure 21 and the second gate structure 20, respectively. In this embodiment, the gate structure material layer is etched using the top sidewall as a mask, thereby forming the gate structure. Since the width of the top sidewall is very small, the gate structure formed using it as a mask is also very short. That is, this application forms a shorter channel length gate structure by anisotropic dry etching of multilayer dielectrics, thereby reducing the channel resistance of the device. The process of forming the gate structure in this application breaks through the precision limit of photolithography equipment on the production line.
[0044] In this embodiment, as Figure 1H As shown, a first passivation layer 501 is formed above the bottom layer structure 10. Specifically, in this embodiment, the first passivation layer 501 is located on the upper surface of the first barrier layer 104, and it covers the top sidewall 402 and the gate structures 20 and 21. The material of the first passivation layer 501 can be a nitride insulating material, such as silicon nitride (SiN), or other insulating materials, such as silicon dioxide (SiO2), or a stack of nitride and oxide insulating materials. It should be noted that the first passivation layer 501 and the top sidewall 402 are different dielectric layers, and the etching selectivity ratio between the two dielectric layers is greater than 3:1.
[0045] In this embodiment, as Figure 1I As shown, after planarizing the first passivation layer 501, a passivation layer 502 with exposed top sidewall 402 is formed. In this embodiment, chemical mechanical polishing (CPM) is mainly used to planarize the first passivation layer 501. Alternatively, thermal reflow or etching back process can be used to planarize the first passivation layer 501. The method of planarizing the first passivation layer 501 is not limited here.
[0046] In this embodiment, the top sidewall 402 covering the passivation layer 502 is removed to form a first buried hole 403, and a second metal layer 404 is formed within the first buried hole 403. Specifically, as shown... Figure 1J-1K As shown, after removing the top sidewall 402 encased within the passivation layer 502, since the first passivation layer 501 and the top sidewall 402 are different dielectric layers, and the etching selectivity ratio between the two dielectric layers is greater than 3:1, the top sidewall 402 encased within the passivation layer 502 can be removed using wet or dry etching methods to form a first buried via 403. Further, a metal layer is deposited within the first buried via 403 to form a second metal layer 404 for the gate structures 20 and 21, wherein the resistivity of the second metal layer 404 is less than the resistivity of the gate metal layer 204. In this embodiment, the combined superposition of the gate metal layer 204 and the second metal layer 404 of the gate structure effectively reduces the resistance of the gate structure, thereby shortening the gate signal transmission delay time of the GaN device.
[0047] In this embodiment, a source structure and a drain structure are formed on both sides of the gate structures 20 and 21, respectively. The source structure and the drain structure are located on opposite sides of the gate structures 20 and 21, and are spaced apart from them. The source structure is preferably an ohmic contact source structure, and the drain structure is preferably an ohmic contact drain structure, and both the source structure and the drain structure extend at least to the upper surface of the barrier layer 104. For example, as... Figure 1L As shown, both the source structure and the drain structure are located on the surface of the barrier layer 104. In other embodiments, both the source structure and the drain structure extend into the barrier layer 104. In still other embodiments, both the source structure and the drain structure extend into the channel layer. Figure 1LAs shown, the gate structure includes a first gate structure 21 and a second gate structure 20, the source structure includes a first source structure 601 and a second source structure 603, and the drain structure includes a first drain structure 602 and a second drain structure 604. The first source structure 601 and the first drain structure 602 are respectively located on both sides of the first gate structure 21, and the second source structure 603 and the second drain structure 604 are respectively located on both sides of the second gate structure 20. In this embodiment, the method for forming the source structure and the drain structure includes: etching a passivation layer 502 to form source contact holes and drain contact holes on both sides of the gate structure, and filling the source contact holes and drain contact holes with metal to form the source structure and the drain structure. When forming the source structure, the first source contact hole and the second source contact hole share a single contact hole, that is, the first source structure 601 and the second source structure 603 are merged into a single source structure. In other embodiments, the first source contact hole and the second source contact hole may be formed when forming the source structure, that is, the first source structure 601 and the second source structure 603 may be formed respectively.
[0048] Example 2: When the HEMT device is a depletion-mode HEMT device, such as Figure 2A As shown, a bottom layer structure 10 is formed, which includes a base layer 101, a channel layer 103 located on the base layer 101, and a barrier layer 104 located on the surface of the channel layer 103, with a 2DEG formed at the contact surface between the channel layer 103 and the barrier layer 104. This bottom layer structure 10 is similar to the bottom layer structure 10 in Embodiment 1, and will not be described again here.
[0049] In this embodiment, a material layer for a gate structure is formed above the barrier layer 104, such as... Figure 2B As shown, in this embodiment, the underlying structure further includes a cap layer 205 formed on the upper surface of the barrier layer 104, which covers the upper surface of the barrier layer 104. The gate structure material layer includes a gate dielectric layer 206 covering the upper surface of the cap layer 205 and a metal layer 207 covering the upper surface of the gate dielectric layer 206. The cap layer 205 is made of a III-V compound material, such as AlGaN, InGaN, InAlN, etc. The gate dielectric layer 206 can be made of materials such as silicon nitride (SiN), or other insulating materials, such as silicon dioxide (SiO2), or a stack of nitride insulating materials and oxide insulating materials, etc. The metal layer 207 can be a gate metal suitable for HEMT devices, such as a TiN or Ni / Au stack structure that constitutes a Schottky contact, but is not limited to these.
[0050] In this embodiment, a first dielectric layer is formed on the material layer of the gate structure; a top sidewall of the gate structure is formed on one or both sides of the first dielectric layer; the first dielectric layer is removed; as... Figure 2C-2E As shown, a first dielectric layer 301 is formed on the upper surface of a predetermined region of the gate structure material layer, that is, a first dielectric layer 301 is formed on the upper surface of a predetermined region of the metal layer 207. Further, a second dielectric layer 401 is formed on the upper surfaces of the metal layer 207 and the first dielectric layer 301, covering the upper surfaces of the metal layer 207 and the first dielectric layer 301. The second dielectric layer 401 is fully etched to form a top sidewall 402 on one or both sides of the first dielectric layer 301, such as... Figure 2E As shown, top sidewalls 402 are formed on both sides of the first dielectric layer 301. In other examples, the second dielectric layer 401 is fully etched to form a sidewall 402 on one side of the first dielectric layer 301 (examples with only one sidewall are not shown in the figure). It should be noted that the first dielectric layer 301 and the second dielectric layer 401 are different dielectric layers, and the etching selectivity ratio between the two dielectric layers is greater than 3:1. Figure 2F As shown, the first dielectric layer 301 is removed; the method of removing the first dielectric layer 301 can be dry etching or wet etching, and the method of removing the first dielectric layer 301 is not limited here. Then, using the top sidewall 402 as a mask, the material layer of the gate structure is etched to form the gate structure; as shown Figure 2G As shown, the material layer etched here for the gate structure only includes etching the metal layer 207 covering the upper surface of the gate dielectric layer 206. The etching method for the metal layer 207 can be dry etching or wet etching, which is not limited here. After etching, gate structures 20 and 21 are formed. Gate structures 20 and 21 include the gate dielectric layer 206 located on the upper surface of the cap layer 205 and the gate metal layer 208 located on the upper surface of the gate dielectric layer 206. The gate structures 20 and 21 include the lower gate dielectric layer 206 and the upper gate metal layer 208.
[0051] In this embodiment, as Figure 2HAs shown, a first passivation layer 501 is formed above the underlying structure, wherein the first passivation layer 501 covers the top sidewall 402 and the gate structures 20 and 21; that is, the first passivation layer 501 is located on the upper surface of the gate dielectric layer 206, and the first passivation layer 501 covers the top sidewall 402 and the gate structures 20 and 21. Here, we refer to the gate structures 20 and 21 as the first gate structure 21 and the second gate structure 20, respectively. In this embodiment, the gate structure is formed by etching the material layer of the gate structure using the top sidewall as a mask. Since the width of the formed top sidewall is very small, the gate structure formed using it as a mask is also very short. That is, this application forms a gate structure with a shorter channel length by anisotropic dry etching of multilayer dielectrics, thereby reducing the channel resistance of the device. The process of forming the gate structure in this application breaks through the precision limits of photolithography equipment on the production line.
[0052] In this embodiment, the first passivation layer 501 is planarized, and the top sidewall 402 is exposed; as follows Figure 2I As shown, the first passivation layer 501 can also be planarized using chemical mechanical polishing (CPM) to form a passivation layer 502, exposing at least the upper surface of the top sidewall 402. In other embodiments, the first passivation layer 501 can also be planarized using a thermal reflow process or an etching process; the method for planarizing the first passivation layer 501 is not limited here.
[0053] In this embodiment, the top sidewall 402 covering the passivation layer 502 is removed to form a first buried hole 403, and a second metal layer 404 is formed within the first buried hole 403, such as... Figure 2J-2K As shown, similarly, since the etching selectivity ratio of the top sidewall 402 to the passivation layer 502 is greater than 3:1, the top sidewall 402 covering the first passivation layer 502 can be removed by wet or dry etching to form the first buried via 403. Then, a second metal layer 404 is deposited within the first buried via 403 to form the second metal layer 404. The resistivity of the second metal layer 404 is less than that of the gate metal layer 208. With the combined superposition of the gate metal layer 208 and the second metal layer 404, the gate structures 20 and 21 can effectively reduce the resistance of the gate structure, thereby shortening the signal transmission delay time of the GaN device.
[0054] In this embodiment, a source structure and a drain structure are formed on both sides of the gate structure, such as... Figure 2LAs shown, the source structure and the drain structure are located on opposite sides of the gate structure, and are spaced apart from the gate structure. The source structure is preferably an ohmic contact source structure, and the drain structure is preferably an ohmic contact drain structure, and both the source structure and the drain structure extend at least to the upper surface of the barrier layer. For example, as... Figure 2L As shown, both the source structure and the drain structure are located on the surface of the barrier layer. In other embodiments, both the source structure and the drain structure extend into the barrier layer. In still other embodiments, both the source structure and the drain structure extend into the channel layer. Here, we refer to the gate structures 20 and 21 as the first gate structure 21 and the second gate structure 20, respectively. Correspondingly, the source structure includes a first source structure 601 and a second source structure 603, and the drain structure includes a first drain structure 602 and a second drain structure 604. The first source structure 601 and the first drain structure 602 are located on opposite sides of the first gate structure 21, and the second source structure 603 and the second drain structure 604 are located on opposite sides of the second gate structure 20. In this embodiment, when forming the source structure, the first source contact hole and the second source contact hole share a single contact hole, that is, the first source structure 601 and the second source structure 603 share a single source structure. In other embodiments, the first source contact hole and the second source contact hole may be formed when forming the source structure, that is, the first source structure 601 and the second source structure 603 may be formed respectively.
[0055] Example 3: Continue to refer to Figure 1A-1L , adopt as Figure 1A-1L Based on the steps to form a HEMT device, further steps include, for example... Figure 1MAs shown, a second passivation layer 503 is formed on the upper surface of the passivation layer 502. The second passivation layer 503 covers the first source structure 602, the first drain structure 602, the second source structure 603, the second drain structure 604, the second metal layer 404 on the first gate structure 21, and the second metal layer 404 on the second gate structure 20. Then, a source metal interconnect structure, a drain metal interconnect structure, and a gate metal interconnect structure are formed. The contact holes 81 of the source metal interconnect structure and the contact holes 82 of the drain metal interconnect structure extend from the upper surface of the second passivation layer 503 to... The upper surfaces of the source structure and the drain structure are in contact with each other. This contact is an electrical connection contact, and the contact holes of the source metal interconnect structure and the contact holes of the drain metal interconnect structure are located inside the active region. Since the gate metal length of the active region is very short, it is difficult to form a smaller contact hole of the gate metal interconnect structure in the active region. Therefore, the contact hole 83 of the gate metal interconnect structure is disposed outside the active region. The contact hole 83 of the gate metal interconnect structure extends from the upper surface of the second passivation layer 503 to the upper surface of the gate structure. This contact is an electrical connection contact.
[0056] In other embodiments, when the HEMT device is a depletion-type HEMT device, the method for forming the metal interconnect structure is the same as in this embodiment, and will not be described again here.
[0057] Example 4: This example differs from the previous examples in that it is a monolithically integrated HEMT device. Continuing with reference to 1A-1G, the process of forming the first gate structure 21 and the second gate structure 20 is consistent with the steps in Example 1, and will not be repeated here. Furthermore, as... Figure 3A As shown, after forming the first passivation layer 501 above the underlying structure 10 and before planarizing the first passivation layer 501, a third gate structure 22 and a top dielectric layer 405 located on the upper surface of the third gate structure are formed on the side outside the first gate structure 21 and the second gate structure 20. Specifically, as shown... Figure 3B-3EAs shown, the method for forming the third gate structure 22 includes: etching the first passivation layer 501 to form a first type of opening 220; forming a gate dielectric layer (not shown in the figure) of the third gate structure on at least the sidewalls and bottom walls of the first type of opening 220; specifically, the gate dielectric layer can be formed by deposition, and the material of the gate dielectric layer can be silicon nitride (SiN), or other insulating materials, such as silicon dioxide (SiO2), or a stack of nitride insulating materials and oxide insulating materials; depositing a metal material layer 221 on at least the gate dielectric layer of the third gate structure 22, wherein the material of the metal material layer 221 is TiN, A Ni / Au stack or similar structure is formed; a top dielectric layer 405 of the third gate structure 22 is formed in a predetermined region of the metal material layer 221. The top dielectric layer of the third gate structure 22 can be formed by deposition. The predetermined region is at least above the first type of opening 220. The top dielectric layer 405 can be a nitride insulating material, such as silicon nitride (SiN), or other insulating materials, such as silicon dioxide (SiO2), or a stack of nitride insulating materials and oxide insulating materials, etc. Using the top dielectric layer 405 as a mask, the metal material layer 221 is etched to form the gate electrode 222 of the third gate structure 22.
[0058] like Figure 3F As shown, a third passivation layer 505 is formed on the upper surface of the first passivation layer 501. The third passivation layer 505 covers the first passivation layer 501, the third gate structure 22, and the top dielectric layer 405 located on the upper surface of the third gate structure.
[0059] like Figure 3G-3IAs shown, the third passivation layer 505 and the first passivation layer 501 are planarized, exposing the upper surfaces of the top sidewall 402 and the top dielectric layer 405. After planarizing the first passivation layer 501 and the third passivation layer 505, a passivation layer 506 is formed that exposes the upper surfaces of the top sidewall 402 and the top dielectric layer 405. In this embodiment, the third passivation layer 505 and the first passivation layer 501 are mainly planarized by chemical mechanical polishing (CPM). Alternatively, a thermal reflow process or a back etching process can be used for planarization. The method for planarizing the first passivation layer 501 and the third passivation layer 505 is not limited here. Further, the top sidewall 404 and top dielectric layer 405 covering the passivation layer 506 are removed to form the first buried via 406 and the second buried via 407. It should be noted that the passivation layer 506 and the first passivation layer 501 can be the same dielectric layer, and the top sidewall 402 and the top dielectric layer 405 can be the same dielectric layer. However, the passivation layer 506 and the first passivation layer 501 are different dielectric layers from the top sidewall 402 and the top dielectric layer 405, and the etching selectivity ratio between the two dielectric layers is greater than 3:1. The top sidewall 402 and the top dielectric layer 405 covering the passivation layer 506 can be removed using wet or dry etching. Then, a second metal layer 404 and a third metal layer 409 are formed in the first buried via 406 and the second buried via 407, respectively, to form the second metal layer 404 of the first gate structure 21 and the second gate structure 20, and the third metal layer 409 of the third gate structure 22, respectively. The resistivity of the third metal layer 409 and the second metal layer 404 is lower than that of their corresponding gate metal layers. The combined superposition of the first gate structure 21 and the second gate structure 20 with the gate metal layer and the second metal layer 404, and the combined superposition of the third gate structure 22 with the gate metal layer and the third metal layer 409, effectively reduces the resistance of all gate structures, thereby shortening the signal transmission delay time of the GaN device.
[0060] like Figure 3J As shown, a first source structure 601 and a first drain structure 602 are formed on both sides of the first gate structure 21, a second source structure 603 and a second drain structure 604 are formed on both sides of the second gate structure 20, and a third source structure 605 and a third drain structure 606 are formed on both sides of the third gate structure 22; wherein, the third source structure 605 and the third drain structure 606 are formed simultaneously with the first source structure 601, the first drain structure 602, the second source structure 603, and the second drain structure 604. Figure 3JAs shown, in this embodiment, the third source structure 605 and the third drain structure 606 are formed on the right side outside the first gate structure 21 and the second gate structure 20. In other embodiments, the third source structure 605 and the third drain structure 606 can also be formed on the left side outside the first gate structure 21 and the second gate structure 20.
[0061] In this embodiment, as Figure 3K-3M As shown, the method further includes: forming a second passivation layer 507 on the upper surface of the second passivation layer 506; further, forming a source metal interconnect structure, a drain metal interconnect structure, and a gate metal interconnect structure, wherein the contact holes 81 and 82 of the source metal interconnect structure extend from the upper surface of the second passivation layer 507 to the upper surfaces of the first source structure 601, the first drain structure 602, the second source structure 603, the second drain structure 604, the third source structure 605, and the third drain structure 606, respectively, and the contact holes 81 and 82 of the source metal interconnect structure are both located inside the active region; the contact holes 83 of the gate metal interconnect structure extend from the upper surface of the second passivation layer 507 to the upper surfaces of the first gate structure 21, the second gate structure 20, and the third gate structure 22, and the contact holes 83 of the gate metal interconnect structure are located outside the active region. Since the gate metal length of the active region is very small, it is difficult to form a smaller contact hole. Therefore, the contact hole 83 of the gate metal interconnect structure is located outside the active region and extends from the upper surface of the second passivation layer 503 to the upper surfaces of the first gate structure 21, the second gate structure 20, and the third gate structure 22, respectively. The contact here is an electrical connection contact.
[0062] Referring again to 3K, after the second passivation layer 507 is formed on the upper surface of the passivation layer 506, and before the source metal interconnect structure, drain metal interconnect structure and gate metal interconnect structure are formed, an isolation region 909 is formed between the second drain structure 604 and the third source structure 605. The isolation region 909 extends from the upper surface of the barrier layer 104 at least into the channel layer 103 to block the 2DEG at the contact surface between the channel layer 103 and the barrier layer 104.
[0063] Secondly, Example 5: Figure 1LAs shown, this embodiment provides a semiconductor device, which includes a bottom structure 10. The bottom structure includes at least a substrate layer 101 and a channel layer 103 above the substrate layer 101, and a barrier layer 104 on the upper surface of the channel layer 103; it also includes a first passivation layer 502 above the bottom structure 10, a first gate structure 21 and a second gate structure 20 above the bottom structure 10, and metal layers 404 on the upper surfaces of the first gate structure 21 and the second gate structure 20, respectively; and it also includes first source structures 601 on both sides of the first gate structure 21. The system comprises a first drain structure 602 and second source structures 603 and 604 located on either side of the second gate structure 20. The first passivation layer 502 covers the first source structure 601, the first drain structure 602, and the first gate structure 21, and also covers the second source structure 603, the second drain structure 604, and the second gate structure 20. The first passivation layer 502 exposes the first source structure 601, the first drain structure 602, the second source structure 603, the second drain structure 604, and the upper surface of the metal layer 404 located on the upper surface of the first gate structure 21 and the second gate structure 20. The resistivity of the second metal layer 404 is less than the resistivity of the gate metal layer 204. The widths of the first gate structure and the second gate structure are less than 1 μm. In this embodiment, the first gate structure and the second gate structure are formed by first forming the top sidewall of the gate structure, and then using the top sidewall as a mask to form the gate structure. The gate structure formed in this way is very short, breaking through the precision limits of the photolithography equipment on the production line. In this embodiment, the gate resistance is effectively reduced by the superposition of the gate metal layer 204 and the second metal layer 404 of the gate structure, thereby shortening the gate signal transmission delay time of the GaN device.
[0064] Continue to refer to Figure 1L The HEMT device is an enhancement-mode HEMT device. The first gate structure 21 and the second gate structure 20 include a P-type doped P-type gate 203 located on the upper surface of the barrier layer 104 and a gate metal layer 204 located on the upper surface of the P-type gate 203. In this embodiment, the P-type gate 203 is one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium nitride (InAlN). The gate metal layer 204 can use existing gate metals suitable for HEMT devices, such as TiN or Ni / Au stacks that form Schottky contacts, but is not limited to these.
[0065] Continue to refer to Figure 1LIn this embodiment, the first source structure 601, the first drain structure 602, the second source structure 603, and the second drain structure 604 extend at least to the upper surface of the barrier layer 104. In other embodiments, the first source structure 601, the first drain structure 602, the second source structure 603, and the second drain structure 604 all extend into the barrier layer 104. In still other embodiments, the first source structure 601, the first drain structure 602, the second source structure 603, and the second drain structure 604 all extend into the channel layer 103.
[0066] Continue to refer to Figure 1L In this embodiment, the projection of the second metal layer 404 on the underlying structure 10 coincides with the projection of the gate metal layer 204 on the underlying structure 10.
[0067] Example 6: In this example, as Figure 1N and 1O As shown, the HEMT device further includes a source metal interconnect structure, a drain metal interconnect structure, and a gate metal interconnect structure, as well as a second passivation layer 503 located on the upper surface of the first passivation layer 502. The second passivation layer 503 covers the upper surface of the first passivation layer 502 and encapsulates the upper surfaces of the first source structure 601, the first drain structure 602, the second source structure 603, and the second drain structure 604. The contact holes 81 and 82 of the source metal interconnect structure extend from the upper surface of the second passivation layer 503 to the upper surfaces of the first source structure 601, the first drain structure 602, the second source structure 603, and the second drain structure 604, respectively, and these contact holes 81 and 82 contact the first source structure 601, the first drain structure 602, the second source structure 603, and the second drain structure 604, respectively. These contacts are electrical connections. The contact holes 81 of the source metal interconnect structure and 82 of the drain metal interconnect structure are both located inside the active region; the contact holes 83 of the gate metal interconnect structure extend from the upper surface of the second passivation layer 507 to the upper surfaces of the first gate structure 21 and the second gate structure 20, respectively, and the contact holes 83 of the gate metal interconnect structure are located outside the active region.
[0068] Example 7: In this example, as Figure 2L As shown, Figure 2LThe diagram shown is a structural diagram of a HEMT device according to an embodiment of the present invention. Unlike Embodiment 5, the HEMT device in this embodiment is a depletion-type HEMT device. In this embodiment, the underlying structure further includes a cap layer 205 located on the upper surface of the barrier layer 104, wherein the material of the cap layer 205 includes a III-V compound. The P-type gate 203 is one or more of gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), and aluminum indium nitride (InAlN). In this embodiment, the first gate structure 21 and the second gate structure 20 are different from the gate structure in Embodiment 6. Specifically, the gate structure in this embodiment includes a gate dielectric layer 206 located on the upper surface of the cap layer 205 and a gate metal layer 208 located on the upper surface of the gate dielectric layer 206. The gate dielectric layer 206 can be made of materials such as silicon nitride (SiN), other insulating materials such as silicon dioxide (SiO2), or a stack of nitride and oxide insulating materials. The gate metal layer 208 can use existing gate metals suitable for HEMT devices, such as TiN or Ni / Au stacks forming Schottky contacts, but is not limited to these. The resistivity of the second metal layer 404 is less than that of the gate metal layer 208. Similarly, in this embodiment, the widths of the first and second gate structures are less than 1µm. In this embodiment, the first and second gate structures are formed by first forming the top sidewalls of the gate structure, and then using the top sidewalls as a mask to form the gate structure. This method results in a very short gate structure, exceeding the precision limits of photolithography equipment on the production line. The projection of the second metal layer 404 onto the underlying structure 10 coincides with the projection of the gate metal layer 208 onto the underlying structure 10. With the combined superposition of the gate metal layer 208 and the second metal layer 404 of the gate structure, the gate resistance can be effectively reduced, thereby shortening the signal transmission delay time of the GaN device.
[0069] Example 8: In this example, as Figure 3L and 3M As shown, Figure 3LThe diagram shown is of the HEMT device structure according to Embodiment 8 of the present invention. Unlike Embodiment 5, the HEMT device in this embodiment is a monolithically integrated HEMT device. This monolithically integrated HEMT device further includes: a third source structure 605 and a third drain structure 606 located on the same side outside the first gate structure 21 and the second gate structure 20; a second metal layer 404 located on the upper surfaces of the first gate structure 21 and the second gate structure 22; a third gate structure 22 located between the third source structure 605 and the third drain structure 606; and a third metal layer 409 located on the upper surface of the third gate structure 22. The third gate structure 22 includes: a gate dielectric layer (not shown in the figure) of the third gate structure located at least on the sidewalls and bottom walls of the first type of opening; and a gate electrode 222 of the third gate structure located at least on the gate dielectric layer of the third gate structure, wherein the first type of opening is located within the first passivation layer 501 and on the upper surface of the barrier layer 104. The monolithically integrated HEMT device further includes a third passivation layer 507. The third passivation layer 506 covers the upper surface of the first passivation layer 501 and, together with the first passivation layer 501, encapsulates the first source structure, the first drain structure, and the first gate structure, as well as the second metal layer located on the upper surface of the first gate structure. It also encapsulates the second source structure, the second drain structure, and the second gate structure, as well as the second metal layer located on the upper surface of the second gate structure, and further encapsulates the third source structure, the third drain structure, and the third gate structure, as well as the third metal layer located on the upper surface of the third gate structure. In this embodiment, the third source structure 605 and the third drain structure 606 have the same structure as the first source structure 601, the first drain structure 602, the second source structure 603, and the second drain structure 604 in Embodiment Six, and are formed in the same step. In this embodiment, a third gate structure 22 located between the third source structure 605 and the third drain structure 606, and a third metal layer 409 located on the upper surface of the third gate structure are also included. In this embodiment, the third gate structure 22 is a depletion-type gate structure. Furthermore, in this embodiment, the resistivity of the second metal layer 404 is less than the resistivity of the metal layers of the first and second gate structures of the gate structure, and the resistivity of the third metal layer 409 is less than the resistivity of the gate metal layer of the third gate structure. The projection of the second metal layer 404 onto the underlying structure 10 coincides with the projection of the gate metal layer 204 onto the underlying structure 10. The projection of the third metal layer 409 onto the underlying structure 10 coincides with the projection of the gate metal layer 222 onto the underlying structure 10.The monolithically integrated HEMT device further includes a second passivation layer 507 formed on the upper surface of the first passivation layer, the second passivation layer 507 covering the source structure, drain structure, gate structure and second metal layer; it also includes a source metal interconnect structure electrically connected to the source structure, a drain metal interconnect structure electrically connected to the drain structure and a gate metal interconnect structure electrically connected to the gate structure, wherein the contact holes of the source metal interconnect structure and the contact holes of the drain metal interconnect structure are both located inside the active region; the contact holes of the gate metal interconnect structure are located outside the active region.
[0070] like Figure 3K As shown, the monolithically integrated HEMT device further includes an isolation region 909 located between the second drain structure 604 and the third source structure 605; wherein the isolation region 909 extends from the upper surface of the barrier layer 104 to at least the interior of the channel 103, and the isolation region 909 is used to block 2DEG at the contact surface between the channel layer 103 and the barrier layer 104.
[0071] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for fabricating a semiconductor device, characterized in that, The preparation method includes: A substructure is formed, the substructure comprising at least a base layer, a channel layer above the base layer, and a barrier layer on the upper surface of the channel layer. A material layer with a gate structure is formed above the barrier layer; A first dielectric layer is formed on the material layer of the gate structure; A top sidewall of a gate structure is formed on one or both sides of the first dielectric layer; Remove the first dielectric layer; Using the top sidewall as a mask, the material layer of the gate structure is etched to form the gate structure; A first passivation layer is formed above the underlying structure, wherein the first passivation layer covers the top sidewall and the gate structure; The first passivation layer is planarized, and the top sidewall is exposed; Remove the top sidewalls encased within the first passivation layer to form the first buried hole. A second metal layer is formed within the first buried hole. A source structure and a drain structure are formed on both sides of the gate structure, respectively.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The material layer of the gate structure includes: a P-type doped group III-V compound material layer covering the upper surface of the barrier layer and a metal layer covering the upper surface of the P-type doped group III-V compound material layer.
3. The method for fabricating a semiconductor device according to claim 2, characterized in that, A method for etching the material layer of the gate structure using the top sidewall as a mask to form the gate structure includes: Using the top sidewall as a mask, the P-type doped III-V compound material layer is etched to form a P-type gate of the gate structure, and the metal layer covering the upper surface of the P-type doped III-V compound material layer is etched to form a gate metal layer of the gate structure.
4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The underlying structure also includes a cap layer formed on the upper surface of the barrier layer.
5. The method for fabricating a semiconductor device according to claim 3, characterized in that, The material layers of the gate structure include: a gate dielectric layer covering the upper surface of the cap layer and a metal layer covering the upper surface of the gate dielectric layer.
6. The method for fabricating a semiconductor device according to claim 2, characterized in that, A method for etching the material layer of the gate structure using the top sidewall as a mask to form the gate structure includes: Using the top sidewall as a mask, the metal layer covering the upper surface of the gate dielectric layer is etched to form the gate metal layer of the gate structure. The gate metal layer and the gate dielectric layer covering the upper surface of the cap layer together constitute the gate structure.
7. The method for fabricating a semiconductor device according to claim 1, characterized in that, Methods for removing the top sidewalls encased within the first passivation layer include: The top sidewalls encapsulated within the first passivation layer are removed using wet or dry etching methods, wherein the selective etching ratio between the top sidewalls and the first passivation layer is greater than 3:
1.
8. The method for fabricating a semiconductor device according to claim 1, characterized in that, Top sidewalls of a gate structure are formed on both sides of the first dielectric layer. The gate structure includes a first gate structure and a second gate structure. The source structure includes a first source structure and a second source structure. The drain structure includes a first drain structure and a second drain structure. The first source structure and the first drain structure are respectively located on both sides of the first gate structure. The second source structure and the second drain structure are respectively located on both sides of the second gate structure.
9. The method for fabricating a semiconductor device according to claim 1, characterized in that, Methods for forming source and drain structures include: The first passivation layer is etched to form source contact holes and drain contact holes on both sides of the gate structure, and metal is filled into the source contact holes and drain contact holes to form source structure and drain structure.
10. The method for fabricating a semiconductor device according to claim 8, characterized in that, The first source structure and the second source structure are combined into a single source structure.
11. The method for fabricating a semiconductor device according to claim 9, characterized in that, The source contact hole and the drain contact hole extend at least to the upper surface of the barrier layer.
12. The method for fabricating a semiconductor device according to claim 9, characterized in that, The method further includes: A second passivation layer is formed on the upper surface of the first passivation layer, and the second passivation layer covers the source structure, the drain structure, the gate structure, and the second metal layer. A source metal interconnect structure, a drain metal interconnect structure, and a gate metal interconnect structure are formed. The contact holes of the source metal interconnect structure and the contact holes of the drain metal interconnect structure extend from the upper surface of the second passivation layer to the corresponding source structure and the drain structure, respectively, and the contact holes of the source metal interconnect structure and the contact holes of the drain metal interconnect structure are both located inside the active region. The contact holes of the gate metal interconnect structure extend from the upper surface of the second passivation layer to the gate structure, and the contact holes of the gate metal interconnect structure are located outside the active region.
13. The method for fabricating a semiconductor device according to claim 8, characterized in that, After forming a first passivation layer on top of the underlying structure, the preparation method further includes: A third gate structure and a top dielectric layer are formed on the upper surface of the third gate structure, the third gate structure being located on a side other than the first gate structure and the second gate structure. A third passivation layer is formed, which covers the upper surface of the first passivation layer and the third gate structure. The first passivation layer and the third passivation layer are planarized to expose the top sidewall and the top dielectric layer.
14. The method for fabricating a semiconductor device according to claim 13, characterized in that, The preparation method further includes: Remove the top sidewalls and top dielectric layer encapsulated within the first and third passivation layers to form the first and second buried vias, respectively. A second metal layer and a third metal layer are formed in the first and second buried holes, respectively.
15. The method for fabricating a semiconductor device according to claim 13, characterized in that, The formation of a source structure and a drain structure on both sides of the gate structure includes: A first source structure and a first drain structure are formed on both sides of the first gate structure, a second source structure and a second drain structure are formed on both sides of the second gate structure, and a third source structure and a third drain structure are formed on both sides of the third gate structure. The third source structure and the third drain structure are formed synchronously with the first source structure, the first drain structure, the second source structure, and the second drain structure.
16. The method for fabricating a semiconductor device according to claim 13, characterized in that, Methods for forming the third gate structure include: The first passivation layer is etched to form a first type of opening. A gate dielectric layer of a third gate structure is formed on at least the sidewalls and bottomwalls of the first type of opening; At least a metal material layer is deposited on the gate dielectric layer of the third gate structure; A top dielectric layer of a third gate structure is formed in a predetermined region of the metal material layer. Using the top dielectric layer as a mask, the metal material layer is etched to form the gate electrode of the third gate structure.
17. The method for fabricating a semiconductor device according to claim 12, characterized in that, The method further includes: After the second passivation layer is formed on the upper surface of the first passivation layer, and before the source metal interconnect structure, drain metal interconnect structure and gate metal interconnect structure are formed, an isolation region is formed between the second drain structure and the third source structure; wherein the isolation region extends from the upper surface of the barrier layer at least into the interior of the channel.
18. A semiconductor device, characterized in that, The device includes: The underlying structure includes at least a base layer and a channel layer located above the base layer, and a barrier layer located on the upper surface of the channel layer; The first passivation layer is located above the underlying structure. A first gate structure and a second gate structure located above the underlying structure, and a second metal layer located on the upper surface of the first gate structure and the second gate structure, respectively; The first source structure and the first drain structure are located on both sides of the first gate structure, and the second source structure and the second drain structure are located on both sides of the second gate structure. The first passivation layer covers the first source structure, the first drain structure, the first gate structure, and the second metal layer located on the upper surface of the first gate structure. The first passivation layer also covers the second source structure, the second drain structure, the second gate structure, and the second metal layer located on the upper surface of the second gate structure. The widths of the first gate structure and the second gate structure are less than 1 μm.
19. The semiconductor device according to claim 18, characterized in that: The first gate structure and the second gate structure include: A P-type gate is located on the upper surface of the barrier layer, and a gate metal layer is located on the upper surface of the P-type gate, wherein the resistivity of the second metal layer is less than the resistivity of the gate metal layer.
20. The semiconductor device according to claim 19, characterized in that: The projection of the second metal layer onto the underlying structure coincides with the projection of the gate metal layer onto the underlying structure.
21. The semiconductor device according to claim 18, characterized in that: The underlying structure also includes a cap layer located on the upper surface of the barrier layer, wherein the material of the cap layer includes a group III-V compound.
22. The semiconductor device according to claim 21, characterized in that: The first gate structure and the second gate structure include: The gate dielectric layer is located on the upper surface of the cap layer, and the gate metal layer is located on the upper surface of the gate dielectric layer.
23. The semiconductor device according to claim 18, characterized in that: The device also includes: A third source structure and a third drain structure located on the same side outside the first gate structure and the second gate structure; And a third gate structure located between the third source structure and the third drain structure, and a third metal layer located on the upper surface of the third gate structure.
24. The semiconductor device according to claim 23, characterized in that: The third gate structure includes: A gate dielectric layer of a third gate structure located at least on the sidewalls and bottomwalls of the first type of opening; At least the gate electrode of the third gate structure located on the gate dielectric layer of the third gate structure. The first type of opening is located within the first passivation layer and on the upper surface of the barrier layer.
25. The semiconductor device according to claim 23, characterized in that: The device also includes: It also includes a third passivation layer, which covers the upper surface of the first passivation layer and together with the first passivation layer covers the first source structure, the first drain structure, the first gate structure, and the second metal layer located on the upper surface of the first gate structure. It also covers the second source structure, the second drain structure, the second gate structure, and the second metal layer located on the upper surface of the second gate structure. Furthermore, it covers the third source structure, the third drain structure, the third gate structure, and the third metal layer located on the upper surface of the third gate structure.
26. The semiconductor device according to claim 24, characterized in that: The projection of the third metal layer onto the underlying structure coincides with the projection of the gate electrode of the third gate structure onto the underlying structure.
27. The semiconductor device according to claim 18, characterized in that: The device also includes: A second passivation layer is formed on the upper surface of the first passivation layer, and the second passivation layer covers the source structure, the drain structure, the gate structure, and the second metal layer. The source metal interconnect structure electrically connected to the source structure The drain metal interconnect structure electrically connected to the drain structure The gate metal interconnect structure electrically connected to the gate structure, The contact holes of the source metal interconnect structure and the drain metal interconnect structure are both located inside the active region; the contact holes of the gate metal interconnect structure are located outside the active region.
28. The semiconductor device according to claim 24, characterized in that: The device also includes: The isolation region located between the second drain structure and the third source structure; The isolation zone extends from the upper surface of the barrier layer at least into the interior of the channel.