Semiconductor device and manufacturing method thereof

Abstract

The present invention provides a semiconductor device and a manufacturing method thereof, the manufacturing method comprising: forming first and second trench regions in a semiconductor substrate having an active region and a lead-out region, and defining first and second mesa regions; forming a field oxide layer covering the inner wall of the groove and each mesa area, and filling a first polycrystalline silicon layer; forming a mask layer with a first opening (exposing the active region) and a second opening (exposing the second mesa region); synchronously removing the field oxide layers on the table tops of the two areas through one-time wet etching, so that the two table top areas obtain consistent surface height reference; a gate structure is then formed. The step difference between the two intervals is eliminated from the source through synchronous etching, accumulation and amplification of morphology deviation in the follow-up process are avoided, and the uniformity of the dielectric layer, the photoetching precision and the injection consistency are remarkably improved. According to the method, additional masks or planarization modules do not need to be added, the process is simplified, the cost is reduced, and the reliability and the yield of the device are greatly improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Shielded gate trench power devices (MOSFET-SGT) are widely used in power conversion due to their low on-resistance and excellent switching characteristics. In a typical MOSFET-SGT process, a trench extending from the active region to the lead-out region is usually formed on the semiconductor substrate, and a thick field oxide layer is formed on the trench sidewalls and substrate surface using a field oxidation process.

[0003] In existing manufacturing processes, a patterned mask layer is typically used to fully cover the lead-out area and expose the active area. Subsequently, a wet etching process is used to remove the field oxide layer on the mesa region of the active area to allow for the subsequent growth of a thinner gate dielectric layer and the formation of the gate structure.

[0004] However, the aforementioned prior art has the following drawbacks: Because the mesa region of the lead-out area is completely protected by the mask layer during etching, its surface retains the initial thickness of the field oxide layer. However, the mesa region of the active area has its surface height significantly reduced due to the removal of the field oxide layer. This results in a physical step difference between the lead-out and active areas. This step difference persists into subsequent integration processes. For example, it can affect the critical dimensional stability of subsequent interconnect lithography, causing defocusing issues, and hindering the penetration of bulk ion implantation in high-voltage devices, thus impacting semiconductor device performance.

[0005] While there are methods to suppress step differences by planarization through chemical mechanical polishing (CMP) or by using multilayer hard mask structures, these approaches typically require additional process steps and expensive production equipment, significantly increasing the complexity of the manufacturing process and production costs.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] In view of the problems in the prior art, the purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, which overcomes the difficulties of the prior art and can solve the technical problems of complex semiconductor device manufacturing process and high manufacturing cost in related technologies.

[0008] The first aspect of this disclosure provides a method for manufacturing a semiconductor device, comprising: A semiconductor substrate is provided, which has an active region and a lead-out region; Multiple trenches are formed in a semiconductor substrate. The trenches are divided into a first trench region located in an active region and a second trench region located in a lead-out region. The active region has a first mesa region outside the first trench region, and the lead-out region has a second mesa region outside the second trench region. A field oxide layer is formed, which covers the sidewalls and bottom of the trench, and covers the first mesa region and the second mesa region. Then, a first polysilicon layer is filled into the trench. A patterned mask layer is formed, the patterned mask layer having a first opening exposing the active region and one or more second openings exposing the second mesa region; Wet etching is performed using a patterned mask layer as a mask. The field oxide layer above the first mesa region and a portion of the field oxide layer located on the side of the first polysilicon layer in the first trench region are removed through the first opening, so that the first polysilicon layer remaining at the bottom of the first trench region forms a shielding gate. At the same time, the field oxide layer on the second mesa region is removed through the second opening. Remove the graphical mask layer; After removing the patterned photoresist, a gate structure is formed in the first trench region.

[0009] Optionally, the second opening is located above the second platform area between two adjacent second trench areas.

[0010] Optionally, there may be multiple second openings arranged in an array.

[0011] Optionally, the size of the second opening and the spacing between adjacent second openings are configured such that, during wet etching, the field oxide layer on the second mesa region is completely connected and stripped through lateral etching of the field oxide layer.

[0012] Optionally, during the wet etching process, by adjusting the component ratio of the etching solution and / or the etching time, the field oxide layer on the sidewall of the first trench region is etched to a predetermined depth to expose the sidewall of the first trench region, while simultaneously removing the field oxide layer on the second mesa region.

[0013] Optionally, before wet etching using a patterned mask layer as a mask, the semiconductor device fabrication method further includes: Using a patterned mask layer as a mask, the first polysilicon layer at a certain depth within the first trench region is etched back to form a shielding gate.

[0014] Optionally, a gate structure is formed in the first trench region, including: A grid dielectric layer is formed on the exposed sidewall surface, the shielding grid surface, the first mezzanine area, and the second mezzanine area surface in the first trench region; A second polysilicon layer is filled in the first trench region to form a gate structure, and the gate structure covers the gate dielectric layer in the first trench region.

[0015] Optionally, the method for manufacturing a semiconductor device further includes: An interlayer dielectric layer is formed, which covers the active region and the extraction region; A connection hole is formed in the interlayer dielectric layer to connect the first polysilicon layer in the gate structure and the second trench region, respectively, and the connection hole is filled with conductive material.

[0016] Optionally, the method for manufacturing a semiconductor device further includes: A metal layer is formed on the interlayer dielectric layer, and the metal layer is etched to form a metal interconnect layer that connects the conductive material; A passivation layer is formed on the surface of the metal interconnect layer and between adjacent metal interconnect layers.

[0017] A second aspect of this disclosure provides a semiconductor device comprising: A semiconductor substrate having an active region and an extraction region; Multiple trenches are located within a semiconductor substrate. The trenches are divided into a first trench region located in an active region and a second trench region located in a lead-out region. The active region has a first mesa region outside the first trench region, and the lead-out region has a second mesa region outside the second trench region. A first polysilicon layer is filled to a certain depth within the first trench region to form a shielding gate, and is also filled within the second trench region. A field oxide layer covers the sidewalls and bottom of the first trench region and the second trench region, and is located between the semiconductor substrate and the first polysilicon layer, wherein the silicon surfaces of the first mesa region and the second mesa region are not covered by the field oxide layer. The gate structure is located above the shielding gate within the first trench region.

[0018] Optionally, the semiconductor device further includes: An interlayer dielectric layer covering the first and second tabletop areas; The connection hole of the first polysilicon layer located in the interlayer dielectric layer and respectively contacting the gate structure and the second trench region, and the conductive material filling the connection hole.

[0019] The semiconductor device and its manufacturing method proposed in this disclosure have the following advantages: In semiconductor device manufacturing, a patterned mask layer is designed to form a first opening in the active region and one or more second openings in the second mesa region of the lead-out region. When wet etching is performed using this mask layer, the field oxide layer on both the first mesa region of the active region and the second mesa region of the lead-out region can be removed simultaneously. This allows for the synchronous removal of the field oxide layers on both regions in the same process step, ensuring a consistent surface height reference for the active and lead-out mesa regions after the node.

[0020] Compared to traditional processes that treat the active and extraction regions of the field oxide layer separately in different steps, this method avoids the gradual amplification and accumulation of surface morphology deviations caused by differences in process timing in subsequent steps. Since the formation of all subsequent dielectric layers, conductive layers, and interconnect structures is a continuous global process above the substrate, the existence of initial height differences directly leads to uneven interlayer dielectric thickness, inconsistent photolithography depth, increased deviations in critical dimensions of interconnects, and even affects ion implantation uniformity. By eliminating the step difference in the extraction region during the field oxide layer removal stage, this method ensures the uniformity of subsequent process conditions, significantly improving the photolithography accuracy of interconnects, doping uniformity, and overall device reliability.

[0021] Furthermore, this solution only requires modification of the mask layer pattern, without the need to add additional independent process modules such as masks, photolithography, or chemical mechanical polishing. The process flow is simple, the production cost is low, and the compatibility is strong, giving it significant technical and economic advantages.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0023] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0024] Figure 1 Cross-sectional electron microscope images of semiconductor devices with shielding gate structures in related technologies; Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this disclosure; Figure 3 Cross-sectional electron microscope images of a medium-voltage semiconductor device fabricated using the manufacturing method disclosed herein are shown; Figure 4 A cross-sectional electron microscope image of a high-voltage semiconductor device fabricated using the manufacturing method disclosed herein is shown; Figures 5 to 9 ,as well as Figures 11 to 18The present disclosure provides cross-sectional views of the semiconductor device at various stages of the manufacturing process, wherein the cross-sectional views are expressed using discontinuous cutting lines to display the active region and the lead-out region side by side on the same drawing. Figure 10 for Figure 9 The top view corresponding to the sectional view shown is used to illustrate the arrangement of the first opening and the second opening. Detailed Implementation

[0025] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0026] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0027] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, they should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0028] Figure 1 Cross-sectional electron microscope images of semiconductor devices with shielded gate structures in related technologies, such as... Figure 1 As shown, the semiconductor substrate 1 has an active region AA with a first mesa region 11 and an exit region S1 with a second mesa region 12. There is a step difference ΔH between the first mesa region 11 and the second mesa region 12.

[0029] This disclosure proposes an improved method for fabricating a semiconductor device by forming a second opening in a patterned mask layer, which exposes the mesa region of the lead-out area, thereby making the mesa region of the lead-out area available to the etching solution during subsequent wet etching.

[0030] When using a patterned mask layer as a mask for wet etching, the etching solution can not only etch the field oxide layer in the active region mesa area and the corresponding area in the first trench area through the first opening, but also act on the take-up region mesa area through the second opening to remove the field oxide layer on the take-up region mesa area.

[0031] Therefore, in the same wet etching step, the field oxide layer of the active region mesa area and the take-up region mesa area can be simultaneously etched, so that the two maintain a relatively consistent surface morphology in subsequent processes, thereby avoiding the formation of a significant height difference between the active region and the take-up region due to the residual field oxide layer in the take-up region mesa area.

[0032] In the above manufacturing method, the etching of the field oxide layer in the mesa area of ​​the take-up area can be achieved by adjusting the pattern of the patterned mask layer, without introducing new etching or planarization steps into the existing manufacturing process, thereby maintaining the continuity of the manufacturing process.

[0033] Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to one embodiment of this disclosure is provided. Figure 2 As shown, the method for manufacturing this semiconductor device includes, but is not limited to, the following steps: Step 210: Provide a semiconductor substrate having an active region and an extraction region; Step 220: Form a plurality of trenches in a semiconductor substrate, the trenches extending from the active region to the lead-out region, such that the trenches are divided into a first trench region located in the active region and a second trench region located in the lead-out region, the active region having a first mesa region outside the first trench region, and the lead-out region having a second mesa region outside the second trench region. Step 230: Form a field oxide layer that covers the sidewalls and bottom of the trench, and covers the first mesa region and the second mesa region, and then fill the trench with a first polysilicon layer; Step 240: Form a patterned mask layer, the patterned mask layer having a first opening exposing the active region and one or more second openings exposing the second mesa region; Step 250: Perform wet etching using a patterned mask layer as a mask, remove the field oxide layer above the first mesa region and a portion of the field oxide layer at the side of the first polysilicon layer in the first trench region through the first opening, so that the first polysilicon layer remaining at the bottom of the first trench region forms a shielding gate, and at the same time remove the field oxide layer on the second mesa region through the second opening. Step 260: Remove the patterned photoresist; Step 270: After removing the patterned photoresist, a gate structure is formed in the first trench region.

[0034] In this embodiment, by simultaneously applying the active region mesa region and the take-off region mesa region in the same wet etching process, the field oxide layer of both is removed under the same etching conditions, thereby giving the active region mesa region and the take-off region mesa region a consistent surface height reference after this process node.

[0035] Figure 3 Demonstrating a medium-voltage semiconductor device using Figure 2 Electron microscope images of the fabrication process of the semiconductor device shown. Figure 4 Demonstrating a high-voltage semiconductor device using Figure 2 Electron microscope (EM) images of the semiconductor device fabrication process shown. (Example: Electron microscope images of the semiconductor device.) Figure 3 and Figure 4 As shown, the active region AA has a first platform region 11, and the lead-out region S1 has a second platform region 12. The step difference between the first platform region 11 and the second platform region 12 basically disappears, and the surface height is roughly the same.

[0036] Therefore, compared to etching the active region and the extraction region separately in different process steps, completing the above etching process in the same wet etching process helps to avoid the surface morphology differences introduced by different process stages from being continuously amplified in subsequent processes.

[0037] Since subsequent manufacturing processes for semiconductor devices are typically performed continuously on and above the semiconductor substrate, if a mesa height difference exists between the active region and the lead-out region due to residual field oxide layer, this height difference will be retained as an initial morphological difference and superimposed on subsequently formed dielectric layers, conductive layers, or other structural layers. Therefore, eliminating the field oxide layer on the mesa region of the lead-out region at this process node, so that the mesa region of the lead-out region and the mesa region of the active region have a consistent initial surface morphology, is beneficial for maintaining the consistency of the formation conditions of each structural layer in subsequent manufacturing processes.

[0038] The following section provides a detailed explanation of the cross-sectional structures of semiconductor devices at each stage of the manufacturing process. Figure 1 The method for manufacturing the semiconductor device shown is illustrated. The cross-sectional view of this disclosure uses a discontinuous cutting line representation, placing the active region and the lead-out region on the same plane.

[0039] like Figure 5 As shown, a semiconductor substrate 1 is provided. The semiconductor substrate 1 serves as the basic structure of the semiconductor device, used to support the subsequently formed trench structure, gate structure, and related functional layers.

[0040] The semiconductor substrate 1 can be a third-generation wide-bandgap semiconductor material such as silicon carbide or gallium nitride, or other materials such as silicon, germanium, silicon germanide, gallium arsenide, or indium gallium nitride; or it can be a silicon substrate or germanium substrate on an insulator. This disclosure does not limit it in this regard.

[0041] Semiconductor substrate 1 can be a single-crystal silicon substrate or semiconductor substrate 1 having an active region AA and an extraction region S1, such as Figure 2 As shown, the active region AA is shown to the left of the dashed line, and the lead-out region S1 is shown to the right of the dashed line. The active region AA is used to form the trench structure and gate structure later, and is the main area for realizing the current control function of the semiconductor device; the lead-out region S1 is used to form the structure that is electrically connected to the active region later, so as to realize the lead-out of the device electrode.

[0042] In this embodiment, the active region AA and the lead-out region S1 are disposed adjacently on the semiconductor substrate 1 along a planar direction, and undergo different structural formation and material retention states during subsequent manufacturing processes. The division of the active region AA and the lead-out region S1 provides a basis for forming differentiated structures in different regions during subsequent process steps.

[0043] In this embodiment, the semiconductor substrate 1 has a predetermined conductivity type. Specifically, the semiconductor substrate 1 can be an N-type semiconductor substrate or a P-type semiconductor substrate, and its conductivity type can be selected according to the design requirements of the device; this disclosure does not limit this selection.

[0044] like Figure 6 As shown, a plurality of trenches 2 are formed in a semiconductor substrate 1. The trenches 2 are divided into a first trench region 2a located in an active region AA and a second trench region 2b located in an exit region S1. The active region AA has a first mesa region 11 outside the first trench region 2a, and the exit region S1 has a second mesa region 12 outside the second trench region 2b.

[0045] In some embodiments, multiple trenches 2 are arranged side-by-side along a planar direction, each trench 2 extending continuously from the active region AA to the lead-out region S1 in physical space. In this layout, the trench segment located within the active region AA is defined as the first trench region 2a, and the trench segment located within the lead-out region S1 is defined as the second trench region 2b. For example, the second trench region 2b may be located at one end (single-sided lead-out layout), or at both ends (double-sided symmetrical lead-out layout), or surrounding the outer periphery of the first trench region 2a (peripheral annular lead-out layout), to meet different gate resistance and layout area requirements.

[0046] In other embodiments, the trench 2 presents a non-linear topology. For example, the second trench region 2b can be configured as a bus trench, extending at a predetermined angle (e.g., perpendicularly) to the extending directions of the plurality of first trench regions 2a. In this configuration, the plurality of parallel first trench regions 2a are physically connected to the second trench region 2b. This non-linear topology helps optimize gate resistance distribution and layout utilization, and is particularly suitable for large-area power chips.

[0047] Regardless of the arrangement, the first trench region 2a and the second trench region 2b are physically integrated and connected, thereby ensuring uniform potential distribution and low resistance of the gate polysilicon.

[0048] In some embodiments, the trench 2 can be formed by photolithography and anisotropic etching (e.g., dry etching, reactive ion etching (RIE), or deep reactive ion etching (DRIE)). The etching depth can be adjusted according to the semiconductor device design requirements, for example, etching to a predetermined depth inside the semiconductor substrate 1 or to a specific doped layer location to ensure channel continuity and electrical connectivity.

[0049] In this process, by adjusting the etching time, etching gas composition and etching power, the trench 2 extends downward in a direction perpendicular to the surface of the semiconductor substrate 1, and extends from the active region AA to the lead-out region S1 in a planar direction.

[0050] Each trench 2 thus formed spans the active region AA and the extraction region S1 in the planar direction, such that trench 2 forms a first trench region 2a in the active region AA and a second trench region 2b in the extraction region S1. The first trench region 2a and the second trench region 2b are structurally part of a continuous trench, but they correspond to different regions in terms of functional area division.

[0051] In the active region AA, unetched semiconductor material regions are retained between multiple first trench regions 2a, forming a first mesa region 11. In the lead-out region S1, unetched semiconductor material regions are also retained between multiple second trench regions 2b, forming a second mesa region 12. The first mesa region 11 and the second mesa region 12 are integrally continuous on the same semiconductor substrate 1, but correspond to the active region AA and the lead-out region S1 respectively in planar positions.

[0052] In some implementations, the depth of the trench 2 can be set according to the design requirements of the semiconductor device, such as etching to a predetermined depth inside the semiconductor substrate 1, or etching to a specific doped layer location in the semiconductor substrate 1, to meet the requirements of subsequent process steps for structural continuity or electrical connection.

[0053] like Figure 7 As shown, after forming trench 2, the semiconductor substrate 1 undergoes field oxidation treatment to form a field oxide layer 3 on the surface of the semiconductor substrate 1. The field oxidation treatment can be achieved by a thermal oxidation process, such as introducing oxygen or water vapor into a high-temperature oxidation environment to cause an oxidation reaction on the surface of the semiconductor substrate 1, thereby forming a silicon oxide layer as the field oxide layer 3 on its surface.

[0054] Through field oxidation, the field oxide layer 3 grows continuously along the sidewalls and bottom of the trench 2, so that the sidewalls and bottom of the trench 2 are covered by the field oxide layer 3. At the same time, the field oxide layer 3 also covers the first mesa region 11 located in the active region AA and the second mesa region 12 located in the lead-out region S1, so that the field oxide layer 3 forms a continuously distributed insulating layer structure on the surface of the semiconductor substrate 1.

[0055] In some embodiments, the thickness of the field oxide layer 3 can be controlled according to the semiconductor device design requirements. For example, by adjusting the oxidation temperature, oxidation time or oxidation atmosphere, the field oxide layer 3 can be formed on the sidewalls of the trench 2, the bottom of the trench, and the first mesa region 11 and the second mesa region 12 with an oxide layer of a predetermined thickness range.

[0056] like Figure 8 As shown, after the formation of the field oxide layer 3, in the trench 2 (such as...) Figure 7 The first polysilicon layer 4 is filled in the trench 2 (as shown). Specifically, a chemical vapor deposition process can be used to deposit polysilicon material on the surface of the semiconductor substrate 1, so that the polysilicon material gradually fills the trench 2 and covers the field oxide layer 3. During the deposition of the first polysilicon layer 4, the polysilicon material can be deposited simultaneously in the trench 2 and on the surface area covered by the field oxide layer 3.

[0057] In some embodiments, after the first polysilicon layer 4 is deposited, the polysilicon material located on the outer surface of the trench 2 can be removed or adjusted by a back etching or planarization process, so that the first polysilicon layer 4 is retained in the trench 2, forming a structural layer filling the trench 2, providing a basic structure for subsequent process steps.

[0058] Optionally, the first polysilicon layer 4 in the trench 2 is approximately flush with the surface of the field oxide layer 3.

[0059] like Figure 9 As shown, in one specific embodiment, after the first polysilicon layer 4 is formed, a patterned mask layer 5 is formed on the surface of the semiconductor substrate 1; At least one first opening 5a and one or more second openings 5b are formed on the surface of the semiconductor substrate 1 through a patterned mask layer 5.

[0060] The patterned mask layer 5 can be selected from photoresist or other hard mask materials. Taking photoresist as an example, the patterned mask layer 5 is formed by photolithography. For example, a photoresist layer is first coated on the surface of the semiconductor substrate 1, and the photoresist layer is exposed and developed to form a mask structure with a predetermined pattern in the photoresist layer.

[0061] The first opening 5a is configured to expose the entire active region AA, including the first mezzanine region 11 and the first trench region 2a. The second opening 5b is configured to expose the second mezzanine region 12 in the lead-out region S1, such that the area located in the first mezzanine region 11 and the first trench region 2a (e.g., Figure 7 The field oxide layer 3 in the second mesa region 12 (as shown) can be selectively treated in subsequent processes.

[0062] Figure 10 for Figure 9 The top view corresponding to the cross-sectional view shown is as follows: Figure 10 As shown, in an optional embodiment, the second opening 5b is disposed above the second platform region 12 between two adjacent second trench regions 2b in the lead-out region S1. By arranging the second opening 5b at the platform position between the second trench regions 2b, the second opening 5b and the second trench regions 2b are offset from each other in planar position, thereby ensuring that the structure inside the second trench region 2b is not directly exposed when forming the patterned mask layer 5.

[0063] In a further embodiment, there are multiple second openings 5b, and the multiple second openings 5b are arranged in an array on the second platform area 12. The array arrangement can be a one-dimensional array arranged along the extension direction of the lead-out area S1, or a two-dimensional array arranged simultaneously along the length and width directions of the lead-out area S1. The specific arrangement can be set according to the area size of the lead-out area S1 and the distribution of the second trench area 2b.

[0064] In another embodiment, the size of the second opening 5b and the spacing between adjacent second openings 5b are preset. Specifically, the opening size of the second opening 5b and the spacing between the second openings 5b are configured such that, during the subsequent wet etching process of the field oxide layer 3, the etching solution can not only etch the exposed field oxide layer 3 in the vertical direction, but also gradually expand the etching range between adjacent second openings 5b through the lateral etching effect of the field oxide layer 3, thereby forming a connected etching region of the field oxide layer 3 located on the second mesa region 12 during the etching process.

[0065] By setting the size and spacing of the second opening 5b in the above manner, the field oxide layer 3 on the second mesa region 12 can be completely etched away during the wet etching process, providing the required surface structure conditions for subsequent process steps.

[0066] like Figure 11As shown, in one specific embodiment, the semiconductor device manufacturing method after forming the patterned mask layer 5 further includes: using the patterned mask layer 5 as a mask to perform a back etching process on the first polysilicon layer 4 in the first trench region 2a. The patterned mask layer 5 covers the second trench region 2b of the lead-out region S1, thereby protecting the first polysilicon layer 4 in the second trench region 2b from thinning during the back etching of the first polysilicon layer 4 in the active region AA.

[0067] Specifically, since the patterned mask layer 5 forms a first opening 5a in the active region AA for exposing the entire active region AA, the first polysilicon layer 4 located in the active region AA, especially in the first trench region 2a, is exposed during the etch-back process.

[0068] In this embodiment, the first polysilicon layer 4 in the first trench region 2a is partially etched back using an anisotropic etching process (e.g., dry etching), so that the first polysilicon layer 4 forms a residual structure of a predetermined height in the first trench region 2a. This residual structure of the first polysilicon layer 4 at the bottom of the first trench region 2a serves as the basic form of the shielding gate structure in subsequent processes.

[0069] At this time, the height of the first polysilicon layer 4 in the active region AA is lower than the height of the first polysilicon layer 4 in the lead-out region S1, but the two remain continuously connected so as to form a complete conductive path in subsequent processes.

[0070] like Figure 12 As shown, after completing the above-mentioned back etching step, a wet etching process is further performed using the patterned mask layer 5 as a mask. The wet etching process can use a fluorine-containing etchant or other chemical solutions suitable for silicon oxide etching to etch the field oxide layer 3 in the exposed area.

[0071] During wet etching, the field oxide layer 3 located in the active region AA is etched away through the first opening 1a. Specifically, the field oxide layer 3 covering the first mesa region 11 is directly removed by the etching solution; simultaneously, the etching solution penetrates along the side of the first polysilicon layer 4 in the first trench region 2a, etching the field oxide layer 3 located on the sidewall of the first trench region 2a to a predetermined depth, thereby gradually exposing the sidewall of the first trench region 2a. Utilizing the isotropic characteristics of wet etching, the field oxide layer 3 on the first mesa region 11 is removed, and a portion of the field oxide layer on the sidewall of the first trench region 2a is simultaneously etched laterally to reserve sidewall space for the subsequent formation of the gate structure.

[0072] In one optional embodiment, during the wet etching process, the etching depth of the field oxide layer 3 on the sidewall of the first trench region 2a can be controlled by adjusting the component ratio of the etching solution and / or the etching time. In this way, the field oxide layer located on the sidewall of the first trench region 2a is etched to a predetermined depth to meet the process requirements of the sidewall interface when forming the gate structure in the first trench region 2a.

[0073] Simultaneously, during the wet etching process, the etching solution also etches the field oxide layer 3 located on the second mesa region 12 of the lead-out area S1 through one or more second openings 5b formed in the patterned mask layer 5. Since the second openings 5b directly expose the second mesa region 12, the etching solution can act on the field oxide layer 3 in this region, causing it to be removed during the wet etching process.

[0074] Through the above wet etching steps, selective removal of the field oxide layer 3 on the sidewall of the first mesa region 11 and the first trench region 2a is achieved in the active region. At the same time, the field oxide layer 3 on the second mesa region 12 is removed in the lead-out region S1, and the first polysilicon layer 4 remaining at the bottom of the first trench region 2a is kept in a predetermined shape for subsequent formation of the gate structure.

[0075] During the aforementioned wet etching process, the etching solution acts on the second mesa region 12 through the second opening 5b. Because the second opening 5b is planarly positioned relative to the second trench region 2b (e.g., ... Figure 7 As shown, the wet etching solution is staggered with each other, and its flow on the mesa of the second mesa region 12 is directional (i.e., it etches laterally from the second opening 5b to both sides). Therefore, when the etching solution removes the field oxide layer 3 that protrudes above the surface of the second mesa region 12, it will not penetrate into or corrode the field oxide layer on the sidewall of the second trench region 2b. This characteristic ensures the integrity of the internal structure of the second trench region 2b in the lead-out region S1 and avoids device reliability risks caused by excessive etching.

[0076] Furthermore, regarding the physical stability of the process, although the field oxide layer 3 above the second mesa region 12 may be completely removed during the lateral interconnect etching process described in this disclosure, causing the patterned mask layer 5 (such as a photoresist layer) to temporarily separate from its underlying solid support, the patterned mask layer 5 is supported by the buoyancy of the etching solution due to the wet etching process. Furthermore, due to the viscosity of the liquid and its physical connection with the surrounding unetched mask layers, the patterned mask layer 5 maintains its positional stability during etching and will not detach or collapse. This ensures that even after the field oxide layer 3 is completely interconnected and stripped, the patterned mask layer 5 can still provide the expected shielding protection until the etching process is completed and the subsequent cleaning and photoresist removal steps are performed.

[0077] like Figure 13 As shown, after wet etching is completed to etch the active region AA and remove the field oxide layer 3 of the lead-out region S1, the patterned mask layer 5 (as shown) is then processed. Figure 12 (As shown) is removed. Taking the patterned mask layer 5 using photoresist as an example, the specific method may include: Plasma Asher: The semiconductor substrate 1 is placed in a plasma asher equipment, utilizing oxygen plasma ( The photoresist is oxidized and vaporized using plasma. By adjusting the power, temperature, and processing time, the photoresist is completely removed while minimizing damage to the first polysilicon layer 4, the inner field oxide layer 3 of the first trench region 2a, and the trench sidewalls.

[0078] Wet Strip: An optional method is to immerse the semiconductor substrate 1 in a resist remover solution (e.g., containing hydrogen peroxide or a sulfuric acid / hydrogen peroxide mixture) to dissolve the photoresist. After treatment, the semiconductor substrate 1 is rinsed with deionized water and dried to ensure that the first trench region 2a, the first mesa region 11, and the second mesa region 12 are clean.

[0079] After removing the patterned mask layer 5, the first polysilicon layer 4 at the bottom of the first trench region 2a forms a shielding gate 41, the sidewalls of the first trench region 2a are exposed, and the field oxide layer 3 above the second mesa region 12 has been removed, providing a clean surface for subsequent gate structure and interlayer interconnect fabrication.

[0080] like Figure 14 As shown, a gate dielectric layer 6 is formed on the exposed sidewall surface of the first trench region 2a region, the surface of the shielding gate 41, the surface of the first mezzanine region 11 and the surface of the second mezzanine region 12. A second polysilicon layer (Poly-Si) 7 is filled in the first trench region 2a to form a gate structure 8, and the gate structure 8 covers the gate dielectric layer 6 in the first trench region 2a.

[0081] In this embodiment, the gate dielectric layer 6 can be formed by thermal oxidation or chemical vapor deposition (CVD). The thickness of the gate dielectric layer 6 can be designed according to the electrical parameters of the semiconductor device, and it serves as a gate insulating layer to ensure the first trench region 2a (e.g., Figure 13 (As shown) Insulation performance between the sidewall and shielding grid 41 and the second polysilicon layer 7.

[0082] like Figure 14As shown, the gate dielectric layer 6 covers the exposed sidewalls of the first trench region 2a and the surface of the shielding gate 41, and also covers the surfaces of the first mesa region 11 and the second mesa region 12, as well as the surface of the first polysilicon layer 4 in the lead-out region S1. The shielding gate 41 is insulated from the subsequently deposited second polysilicon layer 7 by the gate dielectric layer 6, and there is no electrical connection between them.

[0083] The second polysilicon layer 7 fills the first trench region 2a and covers the shielding gate 41. Specifically, polysilicon material is first deposited using a deposition process, such as low-pressure chemical vapor deposition (LPCVD). The deposited polysilicon material covers the surface of the gate dielectric layer 6 and fills the first trench region 2a. Next, the deposited polysilicon material can be planarized using a chemical mechanical polishing process until the gate dielectric layer 6 of the first trench region 2a and the first mesa region 11 and the second mesa region 12 is exposed. The remaining second polysilicon layer 7 in the first trench region 2a serves as the gate structure 8, used to control the conductive channel of the active region AA, and simultaneously achieves electric field shielding through the gate dielectric layer 6 isolated from the shielding gate 41.

[0084] like Figure 15 As shown, after forming the gate structure 8, the source region 91 and the drain region 92 are formed to realize the conductive channel and current input / output function of the semiconductor device.

[0085] In some implementations, a P-type body region is first fabricated. Specifically, a source mask is used to cover the lead-out region S1, exposing the active region AA, for example, exposing the source region regions on both sides of the gate structure 8. Using the formed gate structure 8 as a self-aligned hard mask, P-type doped ions (such as boron B or borofluoride BF2) are implanted directly on both sides of the gate structure 8. The ions penetrate the thin gate dielectric layer 6 on the surface of the first mesa region 11 and enter the semiconductor substrate 1, ensuring uniform body depth and precise self-alignment with the edge of the gate structure 8, thereby avoiding channel length deviation. During this process, due to the aforementioned step difference elimination process, the surface of the lead-out region S1 remains flat, allowing the source mask to cover the second mesa region 12 with a uniform thickness, effectively preventing the penetration of doped ions at the edge of the lead-out region S1, ensuring the consistency of the entire body region implantation and the electrical purity of the lead-out region. After implantation, high-temperature driven diffusion and activation annealing are performed to repair lattice damage, diffuse dopant ions, and form the required bulk concentration gradient to improve breakdown voltage and threshold voltage stability.

[0086] After the P-type body region is formed, N+ source region 91 implantation continues to achieve precise control of the body-source junction. Specifically, the implantation region is defined using a source mask, exposing the first mesa region 11 of the active region AA. Using the gate structure 8 as a self-aligned hard mask, N-type doped ions (such as arsenic (As) or phosphorus (P)) are directly implanted into the active region AA. Ions penetrate the thin gate dielectric layer 6 of the first mesa region 11 and enter the semiconductor substrate 1, forming high-concentration N+ source regions 91 on the top of the first mesa regions 11 on both sides of the gate structure 8. This self-alignment method ensures that the edges of the source regions 91 are precisely aligned with the sidewalls of the gate structure 8, avoiding additional photolithographic alignment errors, while precisely controlling the channel length and ensuring that the electrical integrity and reliability of the gate dielectric layer 6 are not compromised. At the same time, the implantation mask protects the lead-out region S1 and the surface of the gate structure 8, preventing ions from bombarding the shallow top layer of the gate poly layer, which could lead to additional doping or reliability issues. After ion implantation, high-temperature annealing is performed to activate doping and repair lattice damage.

[0087] After the formation of the front source region 91 is completed, the back side of the semiconductor substrate 1 is processed to form the electrical contact of the drain region 92. Next, after surface cleaning and passivation of the back side of the semiconductor substrate 1, N+ enhancement doping (such as phosphorus ion implantation) can be performed on the back side and then annealed to activate it, thereby forming a high-concentration doped layer on the back surface of the semiconductor substrate 1. This back-side enhanced doped layer serves as the drain region 92.

[0088] After forming the drain region 92, a back metal layer is deposited on the back side of the semiconductor substrate 1 using sputtering, evaporation, or chemical vapor deposition (CVD) processes. The material can be a titanium / nickel / silver (Ti / Ni / Ag) multilayer structure or an aluminum / tungsten composite layer. To ensure good ohmic contact between the back metal and the semiconductor substrate 1, rapid thermal annealing can be performed before deposition, or the substrate can be heated during deposition to enhance interfacial adhesion and ohmic properties.

[0089] After the source region 91 and drain region 92 are formed, the source region 91 and the first trench region 2a (as shown in the figure) Figure 7 The channels formed (as shown) are connected to achieve front-side control current conduction, while the drain region 92 is connected to the external circuit through the back side of the semiconductor substrate 1 and the back metal electrode, achieving vertical current flow. This layout not only ensures the low on-resistance of the vertical power MOSFET, but also maintains the effectiveness of gate control and the stability of device breakdown voltage. Furthermore, it benefits from the aforementioned step difference elimination process, ensuring uniform injection in the body and source regions, thereby improving the device breakdown voltage stability and overall reliability.

[0090] like Figure 16As shown, after the source region 91 and drain region 92 are formed, in order to achieve a reliable electrical interconnection between the gate structure 8 and the first polysilicon layer 4 in the lead-out region S1, an inter-layer dielectric (ILD) is first formed on the surface of the semiconductor device. Specifically, silicon oxide (SiO2) can be used. ), silicon nitride (S An interlayer dielectric layer 10 is formed by uniformly covering the active region AA, the lead-out region S1, and the gate structure 8 with either a low-k dielectric material or a chemical vapor deposition (CVD) or spin coating process. This interlayer dielectric layer 10 isolates different conductive layers, prevents short circuits, and provides a smooth surface for subsequent interconnects. Since the thick field oxide layer of the lead-out region S1 has been removed in the previous process, the interlayer dielectric layer 10 exhibits surface smoothness between the active region and the lead-out region S1.

[0091] Since the patterned mask layer 5 and its second opening 5b have been utilized in the previous process (e.g. Figure 9 (As shown) Removing the thick field oxide layer on the second mesa region 12 of the lead-out region S1 significantly reduces the overall surface roughness of the semiconductor substrate 1. The subsequently formed interlayer dielectric layer 10 exhibits good surface flatness between the active region and the lead-out region S1. Benefiting from this, in the subsequent photolithography process defining the connection hole 10a, the photolithography machine has a consistent depth of focus (DOF) window throughout the entire region, effectively avoiding defocusing at the edge of the lead-out region S1 and ensuring the consistency of the morphology and size of the connection hole 10a.

[0092] Subsequently, contact holes 10a are defined on the interlayer dielectric layer 10 using photolithography. Benefiting from the flat surface of the interlayer dielectric layer 10, the photolithography process achieves a consistent depth of focus throughout the entire area, ensuring the consistency of the contact hole 10a's morphology. Photoresist is applied to the surface of the interlayer dielectric layer 10, forming openings at desired locations, allowing the contact holes 10a to connect to the first trench region 2a (e.g., ...). Figure 7 The gate structure 8 and the second trench region 2b (as shown) are located within the gate structure 8 and the second trench region 2b. Figure 7 The first polysilicon layer 4 is shown. Next, the interlayer dielectric layer 10 is etched by wet or dry etching (e.g., reactive ion etching, RIE) to form a connection hole 10a with the required depth and sidewall profile.

[0093] like Figure 17As shown, after forming the connecting hole 10a, a conductive material 101 is filled into the connecting hole 10a to achieve electrical interconnection. The conductive material can be aluminum (Al), copper (Cu), tungsten (W), or their alloys, and the conductive material 101 is filled into the connecting hole 10a by a deposition process (such as physical vapor deposition PVD, chemical vapor deposition CVD, or electroplating). Subsequently, a chemical mechanical planarization (CMP) process can be used to remove excess conductive material from the surface of the interlayer dielectric layer 10, leaving the conductive material only in the connecting hole 10a, forming a stable through-hole interconnect structure. This embodiment reduces the initial undulation of the subsequent interlayer dielectric layer 10 by eliminating the field oxygen step in the lead-out region S1, thereby reducing the grinding load of the CMP process and improving the uniformity of grinding throughout the region.

[0094] After this step is completed, the gate structure 8 and the first polysilicon layer 4 in the second trench region 2b are electrically interconnected through a conductive material, while the interlayer dielectric layer 10 maintains the insulation isolation between each conductive layer.

[0095] like Figure 18 As shown, after the connection hole 10a is formed, a metal interconnect layer 102 is formed on the interlayer dielectric layer 10 to realize the interconnection between the top electrode of the semiconductor device and the external circuit.

[0096] First, a metal layer is deposited on the surface of the interlayer dielectric layer 10. Aluminum (Al), copper (Cu), or an aluminum / copper composite metal can be used. Deposition methods include sputtering, evaporation, or electroplating. The metal layer covers the entire surface of the semiconductor device to form a reliable electrical contact with the conductive material 101.

[0097] Subsequently, the metal layer is patterned using photolithography and etching processes to remove unwanted metal layers and divide it into multiple electrically insulated metal interconnect layers 102 (e.g., source metal interconnect layers, gate lead-out metal interconnect layers, etc.). After etching, gaps are formed between adjacent metal interconnect layers 102, exposing the underlying interlayer dielectric layer 10.

[0098] Finally, a passivation layer 103 is formed on the surface of the metal interconnect layers 102 and in the gaps between them. Specifically, the passivation layer 103 is deposited onto the top and sidewalls of the metal interconnect layers 102 and fills the gaps between adjacent metal interconnect layers 102 to contact the underlying interlayer dielectric layer 10. In this way, the passivation layer 103 tightly surrounds the top and sidewalls of each metal interconnect layer 102, achieving physical isolation and electrical insulation protection between the electrodes and the external environment.

[0099] Optionally, holes can be made at specific locations in the passivation layer 103 by photolithography and etching to expose a portion of the metal interconnect layer 102 as a bonding pad for subsequent wire bonding.

[0100] Through the above steps, the semiconductor device of this embodiment completes the entire manufacturing process from the formation of the gate structure 8, the formation of the source region 91 / drain region 92 to interlayer interconnection, metal interconnection and passivation. This method ensures reliable connection between the gate structure 8, the first polysilicon layer 4 in the lead-out region S1 and the external circuit, while maintaining electrical isolation between the top electrode of the device and the gate, source and drain, meeting the requirements of high voltage and high current applications.

[0101] Figure 18 This illustration shows a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure. The semiconductor device is a shielded gate trench MOSFET power device formed using the aforementioned manufacturing method. The structural features of this semiconductor device can be formed by the manufacturing method or obtained by other semiconductor manufacturing processes capable of achieving the same structure.

[0102] like Figure 18 As shown, the semiconductor device includes a semiconductor substrate 1, which has an active region AA and a lead-out region S1. The active region AA is used to form a trench structure and a gate structure to realize current control function. The lead-out region S1 is used to form a structure electrically connected to the active region AA to realize the electrical connection lead-out of the gate structure.

[0103] The semiconductor substrate 1 may be made of materials such as silicon (Si), silicon carbide (SiC) or gallium nitride (GaN), for example, a silicon substrate of the first conductivity type (such as an N-type silicon substrate) to support vertical current flow and high voltage withstand.

[0104] Multiple trenches 2 located within the semiconductor substrate 1 are divided into a first trench region 2a located in the active region AA and a second trench region 2b located in the lead-out region S1. The first trench region 2a is used to accommodate the shielding gate 41 and the gate structure 8 to realize the function of the active transistor, and the second trench region 2b is used for the lead-out of the gate structure 8 to ensure uniform potential distribution.

[0105] The active region AA has a first mesa region 11 outside the first trench region 2a, and the lead-out region S1 has a second mesa region 12 outside the second trench region 2b. The first mesa region 11 is used for subsequent source region and body region doping to cooperate with the trench sidewalls to form a channel region, and the second mesa region 12 is used for the lead-out connection of the gate structure 8, providing a flat surface to support interconnection.

[0106] A first polysilicon layer 4 fills a portion of the depth within the first trench region 2a to form a shielding gate 41, and also fills the second trench region 2b. The first polysilicon layer 4 within the second trench region 2b serves as the gate runner polysilicon, and its top height is flush with the top of the trench 2 to provide a gate electrical connection path. The first polysilicon layer 4 is formed through chemical vapor deposition and etch-back during the manufacturing process, and maintains a continuous connection between the active region AA and the runner region S1 to achieve potential transfer.

[0107] A field oxide layer 3 covers the trench sidewalls and bottom of the first trench region 2a and the second trench region 2b, and is located between the semiconductor substrate 1 and the first polysilicon layer 4 to form an electrically isolated structure. The field oxide layer 3 is used to insulate the trench sidewalls to reduce the risk of leakage at the trench sidewalls. The silicon surfaces of the first mesa region 11 and the second mesa region 12 are not covered by the field oxide layer 3.

[0108] The gate structure 8 is located above the shielding gate 41 within the first trench region 2a. A gate dielectric layer 6 is formed between the gate structure 8 and the semiconductor substrate 1. The gate dielectric layer 6 covers the sidewall surfaces of the first trench region 2a, the surface of the shielding gate 41, the first mesa region 11, and the surfaces of the second mesa region 12. The gate dielectric layer 6 can be formed by thermal oxidation or chemical vapor deposition processes and is used to provide electrical isolation between the gate structure and the semiconductor substrate and the shielding gate.

[0109] The gate structure 8 is filled in the first trench region 2a and covers the gate dielectric layer 6. It can be deposited by low-pressure chemical vapor deposition (LPCVD) and planarized by chemical mechanical polishing.

[0110] like Figure 18 As shown, in some embodiments, the semiconductor device further includes an interlayer dielectric layer 10 covering the first mesa region 11 and the second mesa region 12. This interlayer dielectric layer 10 is made of silicon oxide (SiO2). Or borosilicate glass (BPSG), deposited via plasma-enhanced chemical vapor deposition (PECVD), is used to insulate the underlying structure and achieve surface planarization. Since the mesa field oxide layer has been removed, the interlayer dielectric layer 10 exhibits uniform thickness and a flat surface between the active region AA and the extraction region S1, improving photolithography accuracy.

[0111] The connection hole 10a located within the interlayer dielectric layer 10 and respectively contacting the gate structure 8 and the second trench region 2b is the first polysilicon layer 4. Figure 16As shown, the interconnect 10a is formed through photolithography and RIE etching, with a depth adapted to the thickness of the interlayer dielectric layer 10, and slightly tilted sidewalls to improve fillability. The interconnect 10a is filled with a conductive material 101, such as tungsten (W), achieved through CVD deposition and CMP planarization. This structure ensures reliable electrical interconnection between the gate structure 8 and the polysilicon layer of the gate lead-out region (the first polysilicon layer 4 within the second trench region 2b), providing a low-resistance signal transmission path, while the interlayer dielectric layer 10 maintains insulation between the conductive layers, avoiding parasitic capacitance and short circuits. This interconnection benefits from surface planarization, improving the critical dimensional stability of the interconnect and ensuring overall device reliability and high-voltage withstand capability.

[0112] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate having an active region and an extraction region; A plurality of trenches are formed in the semiconductor substrate, the trenches being divided into a first trench region located in the active region and a second trench region located in the lead-out region, the active region having a first mesa region outside the first trench region, and the lead-out region having a second mesa region outside the second trench region; A field oxide layer is formed, which covers the sidewalls and bottom of the trench, and covers the first mesa region and the second mesa region, and then a first polysilicon layer is filled in the trench; A patterned mask layer is formed, the patterned mask layer having a first opening exposing the active region and one or more second openings exposing the second mesa region; Wet etching is performed using the patterned mask layer as a mask to remove the field oxide layer above the first mesa region and a portion of the field oxide layer located on the side of the first polysilicon layer in the first trench region through the first opening, so that the first polysilicon layer remaining at the bottom of the first trench region forms a shielding gate, and at the same time, the field oxide layer on the second mesa region is removed through the second opening. Remove the patterned mask layer; After removing the patterned photoresist, a gate structure is formed in the first trench region.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The second opening is located above the second platform area between two adjacent second trench areas.

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The second opening is multiple and arranged in an array.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The size of the second opening and the spacing between adjacent second openings are configured such that, during the wet etching process, the field oxide layer on the second mesa region is completely connected and stripped through the lateral etching of the field oxide layer.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that, During the wet etching process, by adjusting the component ratio of the etching solution and / or the etching time, the field oxide layer on the sidewall of the first trench area is etched to a predetermined depth to expose the sidewall of the first trench area, while simultaneously removing the field oxide layer on the second mesa area.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Before wet etching is performed using the patterned mask layer as a mask, the method for manufacturing the semiconductor device further includes: Using the patterned mask layer as a mask, the first polysilicon layer at a certain depth within the first trench region is etched back to form the shielding gate.

7. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Forming a gate structure in the first trench region includes: A gate dielectric layer is formed on the exposed sidewall surface of the first trench area, the shielding gate surface, the first mezzanine area, and the second mezzanine area surface; A second polysilicon layer is filled in the first trench region to form the gate structure, and the gate structure covers the gate dielectric layer in the first trench region.

8. The method for manufacturing a semiconductor device according to claim 1, characterized in that, The method for manufacturing the semiconductor device further includes: An interlayer dielectric layer is formed, which covers the active region and the extraction region; A connection hole is formed in the interlayer dielectric layer, which connects the gate structure and the first polysilicon layer in the second trench region, and the connection hole is filled with conductive material.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The method for manufacturing the semiconductor device further includes: A metal layer is formed on the interlayer dielectric layer, and the metal layer is etched to form a metal interconnect layer connecting the conductive material; A passivation layer is formed on the surface of the metal interconnect layer and between adjacent metal interconnect layers.

10. A semiconductor device, characterized in that, include: A semiconductor substrate having an active region and an extraction region; A plurality of trenches are located within the semiconductor substrate, the trenches being divided into a first trench region located in the active region and a second trench region located in the lead-out region, the active region having a first mesa region outside the first trench region, and the lead-out region having a second mesa region outside the second trench region; A first polysilicon layer is filled to a certain depth within the first trench region to form a shielding gate, and is also filled within the second trench region. A field oxide layer covers the sidewalls and bottom of the first trench region and the second trench region, and is located between the semiconductor substrate and the first polysilicon layer, wherein the silicon surfaces of the first mesa region and the second mesa region are not covered by the field oxide layer; A gate structure is located above the shielding gate within the first trench region.

11. The semiconductor device according to claim 10, characterized in that, The semiconductor device further includes: An interlayer dielectric layer covering the first and second platform areas; A connection hole located within the interlayer dielectric layer and contacting the gate structure and the second trench region respectively, and a conductive material filling the connection hole.

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