High-power wide-bandgap semiconductor device based on multi-conduction and preparation method of high-power wide-bandgap semiconductor device

Abstract

The invention discloses a high-power wide bandgap semiconductor device based on multiconduction and a preparation method thereof, the device comprises a substrate, a buffer layer, a channel layer and a barrier layer which are sequentially arranged from bottom to top, and the buffer layer comprises a first part and a second part which are sequentially stacked; in the second part, the center of an annular laminated structure formed by the channel layer and the barrier layer is filled with an electrostatic shielding layer, and a gate metal layer is arranged in the central region of the electrostatic shielding layer; the upper surfaces of the electrostatic shielding layer and the gate metal layer are covered with a channel layer material; a conductive medium layer is arranged in the central region of the gate metal layer; the outer side of the upper surface of the annular laminated structure comprises a plurality of cylindrical gate structures, and each cylindrical gate structure comprises a gate dielectric layer and a cylindrical gate; the upper surface of the conductive dielectric layer is provided with a source electrode, and the outer side of the annular laminated structure is provided with a drain electrode. According to the invention, a transverse high-mobility channel and a longitudinal high-voltage drift region are introduced into the same device, and multi-path composite conduction is realized through structural coupling.

Description

Technical Field

[0001] This invention belongs to the field of wide bandgap semiconductor technology, specifically relating to a high-power wide bandgap semiconductor device based on multi-conduction and its fabrication method. Background Technology

[0002] Wide-bandgap semiconductors (such as GaN and SiC) are widely used in RF power amplifiers, power electronics, and high-voltage converters due to their advantages such as high breakdown field, high thermal conductivity, and high electron mobility. A typical GaN HEMT (High Electron Mobility Transistor) achieves high lateral conductivity by forming a two-dimensional electron gas through an AlGaN / GaN heterojunction. However, its breakdown voltage is limited by the lateral electric field distribution, making it difficult to balance high voltage and high current.

[0003] To improve breakdown performance, existing research has introduced vertical structures, such as CAVET (Current Aperture Vertical Electron Transistor) and BAVET (Barrier Aligned Vertical Field-Effect Transistor). BAVET significantly improves the on-state performance by combining a lateral InGaAs channel, a vertical aperture drift region, and an electrostatic shielding layer, and reduces the drain voltage drop by utilizing trap modulation.

[0004] However, current mainstream wide-bandgap power semiconductor devices (such as lateral AlGaN / GaN HEMTs, vertical GaN MOSFETs, and CAVET / BAVET structures) still have several limitations under high-voltage and high-current operating conditions, mainly in the following aspects: 1) The conduction path is singular, making it difficult to simultaneously achieve low on-resistance and high breakdown voltage. Traditional lateral HEMT devices rely on a two-dimensional electron gas (2DEG) formed by a heterojunction for lateral conduction. Due to the limited length of the lateral current channel, increasing the gate-drain spacing is necessary to suppress drain field concentration, but the short-channel effect significantly increases the device's on-resistance. While vertical conduction structures can effectively improve breakdown voltage, the conduction current is limited by the area of ​​the local vertical drift region, and the process is complex with low chip area utilization. Therefore, existing structures cannot simultaneously achieve low on-resistance and high breakdown voltage.

[0005] 2) The electric field concentration effect is significant, limiting the reliability of the device. In lateral HEMT structures, electric field concentration mainly occurs at the gate-drain edge and barrier interface region. Local high fields can easily induce interface traps, charge trapping, and thermal breakdown. Furthermore, as the device channel length decreases, the short-channel effect becomes more significant, leading to weakened potential control and longitudinal electric field expansion, affecting the device's breakdown voltage and stability. While vertical devices partially alleviate electric field concentration, their gate control and electric field modulation dimensions are limited. Currently common field plates or shielding structures can only adjust the electric field in a single direction, lacking overall optimization methods for the three-dimensional potential distribution.

[0006] 3) Lack of effective potential regulation limits dynamic performance. Traditional HEMTs mostly employ a single-gate structure, which cannot independently control the potential at different depths within the channel. During high-voltage dynamic switching, the electric field distribution changes drastically with the bias, leading to increased dynamic on-resistance, threshold drift, and charge hysteresis. The lack of an effective three-dimensional potential control mechanism makes it difficult for the device to maintain stable electrical performance during high-voltage switching.

[0007] In addition, there are problems such as complex processes, difficulty in compatibility with mainstream CMOS / large-size silicon-based technologies, and limited thermal management. Summary of the Invention

[0008] To address the aforementioned problems in the prior art, this invention provides a high-power wide-bandgap semiconductor device based on multi-conduction and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a high-power wide-bandgap semiconductor device based on multi-conduction, comprising a substrate, a buffer layer, a channel layer, and a barrier layer arranged sequentially from bottom to top, wherein... The buffer layer includes a first part and a second part that are sequentially stacked on the substrate, wherein the second part is located at the center of the upper surface of the first part and has a surface size smaller than that of the first part; The second part of the buffer layer, the channel layer and the barrier layer are all in a ring structure. A ring-shaped electrostatic shielding layer is filled in the central groove of the ring stack structure formed by the second part, the channel layer and the barrier layer. A gate metal layer is disposed in the central region of the electrostatic shielding layer. The upper surfaces of the electrostatic shielding layer and the gate metal layer are covered with a channel layer material; a conductive dielectric layer extending from the upper surface of the channel layer material into the interior of the buffer layer is disposed in the central region of the gate metal layer. The outer side of the upper surface of the annular stacked structure includes a plurality of cylindrical gate structures surrounding the electrostatic shielding layer. Each cylindrical gate structure includes an annular gate dielectric layer extending from the upper surface of the barrier layer to the interior of the buffer layer and a cylindrical gate disposed inside the central groove of the gate dielectric layer. The upper surface of the conductive dielectric layer is provided with a source electrode, and the upper surface of the buffer layer outside the annular stacked structure is provided with a drain electrode.

[0009] In one embodiment of the present invention, both the electrostatic shielding layer and the gate metal layer are ring-shaped structures, which are circular or square rings. The outer surface of the electrostatic shielding layer is in contact with the inner surface of the ring-shaped stacked structure, the inner surface of the electrostatic shielding layer is in contact with the outer surface of the gate metal layer, and the inner surface of the gate metal layer is in contact with the outer surface of the conductive dielectric layer.

[0010] In one embodiment of the present invention, the lower surfaces of the electrostatic shielding layer, the gate metal layer, and the conductive dielectric layer are all in contact with the upper surface of the first portion of the buffer layer; The upper surfaces of the electrostatic shielding layer and the gate metal layer are flush with the upper surface of the channel layer, and the upper surface of the conductive dielectric layer is flush with the upper surface of the channel layer material.

[0011] In one embodiment of the present invention, the gate metal layer includes a first annular side gate, a second annular side gate, and a third annular side gate spaced apart along the axial direction by the electrostatic shielding layer, wherein the inner surfaces of the first annular side gate, the second annular side gate, and the third annular side gate are all in contact with the conductive dielectric layer.

[0012] In one embodiment of the present invention, the plurality of cylindrical grid structures are uniformly surrounded around the outer periphery of the electrostatic shielding layer and spaced apart from the electrostatic shielding layer; In each cylindrical gate structure, a gate dielectric layer surrounds the outside of the cylindrical gate, and both the gate dielectric layer and the cylindrical gate extend from the upper surface of the barrier layer to the upper surface of the first portion of the buffer layer.

[0013] In one embodiment of the present invention, both the conductive dielectric layer and the source electrode are cylindrical and have the same diameter.

[0014] In one embodiment of the present invention, the drain electrode is in the form of a ring structure, located on the upper surface of the first portion of the buffer layer and spaced apart from the ring stack structure.

[0015] In one embodiment of the present invention, a heterojunction structure is formed between the barrier layer and the channel layer to generate a two-dimensional electron gas.

[0016] Another aspect of the present invention provides a method for fabricating a high-power wide-bandgap semiconductor device based on multi-conduction, the method comprising: S1: Epitaxial growth of buffer layer and channel layer on substrate; S2: A first columnar opening is formed inside the channel layer and the buffer layer, an electrostatic shielding layer is filled inside the first columnar opening, a second columnar opening is formed inside the electrostatic shielding layer, a gate metal layer is filled inside the second columnar opening, and a channel layer material is deposited on the upper surface of the electrostatic shielding layer, the gate metal layer and the remaining channel layer. S3: Deposit a barrier layer on the upper surface of the channel layer material; S4: A plurality of third columnar openings are made from the barrier layer, penetrating the barrier layer, the channel layer and part of the buffer layer, and the gate dielectric layer and the columnar gate are sequentially filled in the third columnar openings. S5: A fourth columnar opening extending to the upper surface of the channel layer is formed on the barrier layer above the electrostatic shielding layer and the gate metal layer. A fifth columnar opening extending into the buffer layer is formed at the bottom center of the fourth columnar opening. A conductive dielectric layer is filled inside the fifth columnar opening. S6: A source electrode is generated above the conductive dielectric layer, and a drain electrode is generated on the upper surface of the first part of the buffer layer.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention proposes a high-power wide-bandgap semiconductor device based on multi-path conduction. It employs an integrated multi-path conduction and electric field modulation design approach, unifying and optimizing the conductive path design, potential distribution modulation, and device electrode layout to achieve a dynamic balance between conduction and turn-off performance. A lateral-vertical composite channel structure is constructed, introducing a lateral high-mobility channel and a vertical high-voltage drift region within the same device, achieving multi-path composite conduction through structural coupling. The electric field distribution is optimized through the collaborative design of a three-dimensional gate and an electrostatic shielding layer. Simultaneously, it possesses silicon-based compatibility and high manufacturability.

[0018] 1. Construct a horizontal and vertical composite conductive structure to achieve both high current and high withstand voltage. This invention introduces a lateral high-mobility channel and a longitudinal high-voltage drift region within the same device. The lateral channel provides low-resistance, high-mobility electron transport, while the longitudinal conduction path provides high current carrying capacity and high breakdown voltage. The two are coupled through structural coupling to achieve multi-path composite conduction. This design achieves synergistic optimization of on-resistance, breakdown voltage, and power density.

[0019] 2. Three-dimensional potential modulation to improve electric field distribution By setting a uniformly surrounding cylindrical gate structure, an electrostatic shielding layer, and side gates (or segmented gates), three-dimensional electric field shaping of the channel and drift region is achieved. The potential is distributed synergistically in both the horizontal and vertical directions, which reduces the peak electric field and alleviates the edge field strength, thereby significantly improving the breakdown voltage and reliability.

[0020] 3. Balancing process feasibility and system scalability The structure of this invention is based on a GaN epitaxial platform and can be realized through epitaxial design, etching, and metallization processes without the need for complex bonding or multi-substrate processing, thus possessing silicon-based compatibility and high manufacturability. This structure also has the potential for array-based design and can serve as the foundation for high-power modules, 3D integration, or chiplet interconnect units.

[0021] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0022] Figure 1 This is a cross-sectional schematic diagram of a high-power wide-bandgap semiconductor device based on multi-conduction provided in an embodiment of the present invention; Figure 2 This is a top view schematic diagram of a high-power wide-bandgap semiconductor device based on multi-conduction provided in an embodiment of the present invention; Figure 3 This is a top view schematic diagram of another high-power wide-bandgap semiconductor device based on multi-conduction provided in an embodiment of the present invention; Figure 4 This is a cross-sectional schematic diagram of another high-power wide-bandgap semiconductor device based on multi-conduction provided in an embodiment of the present invention; Figure 5 This is a flowchart of a method for fabricating a high-power wide-bandgap semiconductor device based on multi-conduction, provided by an embodiment of the present invention; Figures 6a to 6l This is a schematic diagram of a method for fabricating a high-power wide-bandgap semiconductor device based on multi-conduction, provided in an embodiment of the present invention.

[0023] Explanation of reference numerals in the attached figures: 1-Substrate; 2-Buffer layer; 21-First part; 22-Second part; 3-Channel layer; 4-First columnar opening; 5-Electrostatic shielding layer; 6-Second columnar opening; 7-Gate metal layer; 8-Barrier layer; 9-Third columnar opening; 10-Gate dielectric layer; 11-Columnar gate; 12-Fourth columnar opening; 13-Fifth columnar opening; 14-Conductive dielectric layer; 15-Source; 16-Drain. Detailed Implementation

[0024] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a high-power wide-bandgap semiconductor device based on multi-conduction and its fabrication method according to the present invention.

[0025] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0026] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element.

[0027] Example 1 Please see Figure 1 , Figure 1 This is a cross-sectional schematic diagram of a high-power wide-bandgap semiconductor device based on multi-conduction according to an embodiment of the present invention. The high-power wide-bandgap semiconductor device includes a substrate 1, a buffer layer 2, a channel layer 3, and a barrier layer 8, arranged sequentially from bottom to top. In this embodiment, the substrate 1 is selected as a SiC, Si, or sapphire substrate. The buffer layer 2 includes a first portion 21 and a second portion 22 sequentially stacked on the substrate 1. The first portion 21 has the same surface dimensions as the substrate 1, and the second portion 22 is located at the center of the upper surface of the first portion 21 and has a smaller surface dimension than the first portion 21. In this embodiment, the buffer layer 2 is made of GaN material. The total thickness of the buffer layer 2 is 1-3 μm.

[0028] The second part 22 of the buffer layer 2, the channel layer 3 and the barrier layer 8 are all ring-shaped and have the same inner and outer diameters, so that the second part 22 of the buffer layer 2, the channel layer 3 and the barrier layer 8 form a ring-shaped stacked structure.

[0029] A heterojunction structure is formed between the barrier layer 8 and the channel layer 3 to generate a two-dimensional electron gas. In a specific example, the channel layer 3 is made of GaN, and the barrier layer 8 is made of AlGaN, InAlGaN, or InGaAs. An AlGaN / GaN, InAlGaN / GaN, or InGaAs / GaN heterojunction structure is formed between the barrier layer 8 and the channel layer 3.

[0030] Furthermore, an annular electrostatic shielding layer 5 is filled in the central groove of the annular stacked structure, and a gate metal layer 7 is disposed in the central region of the electrostatic shielding layer 5; a channel layer material of 10-20 nm is covered on the upper surface of the electrostatic shielding layer 5 and the gate metal layer 7; a conductive dielectric layer 14 extending from the upper surface of the channel layer material to the interior of the buffer layer 2 is disposed in the central region of the gate metal layer 7.

[0031] In one specific embodiment, both the electrostatic shielding layer 5 and the gate metal layer 7 are annular structures, which can be circular or square rings. The outer surface of the electrostatic shielding layer 5 contacts the inner surface of the annular stacked structure, the inner surface of the electrostatic shielding layer 5 contacts the outer surface of the gate metal layer 7, and the inner surface of the gate metal layer 7 contacts the outer surface of the conductive dielectric layer 14. Alternatively, the conductive dielectric layer 14 can be cylindrical or square. The lower surfaces of the electrostatic shielding layer 5, the gate metal layer 7, and the conductive dielectric layer 14 are all in contact with the upper surface of the first portion 21. The upper surfaces of the electrostatic shielding layer 5 and the gate metal layer 7 are flush with the upper surface of the channel layer 3, and the upper surface of the conductive dielectric layer 14 is flush with the upper surface of the channel layer material.

[0032] In another embodiment of the invention, such as Figure 4 As shown, the gate metal layer 7 includes a first annular side gate 71, a second annular side gate 72, and a third annular side gate 73 spaced apart along the axial direction by the electrostatic shielding layer 5. The inner surfaces of the first annular side gate 71, the second annular side gate 72, and the third annular side gate 73 are all in contact with the conductive dielectric layer 14. That is, the inner surface of the electrostatic shielding layer 5 forms two protrusions extending inward to the outer surface of the conductive dielectric layer 14, dividing the gate metal layer 7 into annular first annular side gate 71, second annular side gate 72, and third annular side gate 73 arranged sequentially along the axial direction of the conductive dielectric layer 14, forming a multi-side gate structure.

[0033] Furthermore, the outer surface of the annular stacked structure includes multiple cylindrical gate structures surrounding the electrostatic shielding layer 5. Each cylindrical gate structure includes an annular gate dielectric layer 10 extending from the upper surface of the barrier layer 8 into the interior of the buffer layer 2, and a cylindrical gate 11 disposed within the central groove of the gate dielectric layer 10. Figure 1 As shown, each cylindrical gate structure has the same shape and size, uniformly surrounding the outer periphery of the electrostatic shielding layer 5 and spaced apart from it. In one embodiment, the gate dielectric layer 10 is a ring structure, and adaptively, the cylindrical gate 11 is a cylindrical structure, such as... Figure 2 As shown. In another embodiment, the gate dielectric layers 10 are all square ring structures, and adaptively, the pillar gate 11 is a square pillar structure, as shown. Figure 3 As shown. The lower surfaces of both the gate dielectric layer 10 and the pillar gate 11 extend to contact the upper surface of the first portion 21.

[0034] In this embodiment, the gate dielectric layer 10 can be, for example, made of silicon nitride. This gate dielectric layer 10 has excellent insulation properties, effectively isolating the cylindrical gate 11 from the source / drain region, preventing current leakage and electron leakage, and improving the device's insulation performance. Furthermore, the gate dielectric layer 10 has a low dielectric constant, which helps reduce capacitance and losses, and improves the device's high-frequency performance. It also exhibits excellent heat resistance and reliability, making it adaptable to various operating environments. In this ring structure, applying a bias voltage between two adjacent cylindrical gates 1111 allows control of the conduction and pinch-off of the device's lateral channel, thereby achieving effective switching control of the lateral current.

[0035] Furthermore, a source electrode 15 is disposed on the upper surface of the conductive dielectric layer 14. The conductive dielectric layer 14 and the source electrode 15 have the same surface shape and size, and their vertical projections completely overlap.

[0036] In this embodiment, a drain electrode 16 is provided on the upper surface of the channel layer 3 on the outer side of the annular stacked structure. The drain electrode 16 is in the form of an annular structure, located on the upper surface of the first part 21 of the buffer layer 2 and spaced apart from the stacked structure.

[0037] The gate metal layer 7 and the conductive dielectric layer 14 together form a vertical current path. This annular side gate structure can achieve vertical electric field adjustment, and works in conjunction with the lateral channel switching control formed by the cylindrical gate structure to form a three-dimensional potential regulation system. That is, in this embodiment, the lateral conductive channel formed by the channel layer 3 and the barrier layer 8, together with the gate metal layer 7 and the conductive dielectric layer 14 below, form a vertical current path (vertical conductive channel), enabling electrons to enter the vertical conductive channel from the source through the lateral conductive channel. This structure achieves combined lateral and vertical conduction. By precisely controlling the etching depth and opening size of the first cylindrical opening 4 and the second cylindrical opening 6, a vertical conductive channel connected to the lateral conductive channel can be established below the lateral conductive channel, allowing electrons to enter the vertical conductive channel from the source through the lateral channel.

[0038] This invention proposes a high-power wide-bandgap semiconductor device based on multi-path conduction. It employs an integrated multi-path conduction and electric field modulation design approach, unifying and optimizing the conductive path design, potential distribution modulation, and device electrode layout to achieve a dynamic balance between conduction and turn-off performance. A lateral-vertical composite channel structure is constructed, introducing a lateral high-mobility channel and a vertical high-voltage drift region within the same device, achieving multi-path composite conduction through structural coupling. The electric field distribution is optimized through the collaborative design of a three-dimensional gate and an electrostatic shielding layer. Simultaneously, it possesses silicon-based compatibility and high manufacturability.

[0039] This invention introduces a lateral high-mobility channel and a longitudinal high-voltage drift region within the same device. The lateral channel provides low-resistance, high-mobility electron transport, while the longitudinal conduction path provides high current carrying capacity and high breakdown voltage. These two components are structurally coupled to achieve multi-path composite conduction, thus achieving synergistic optimization of on-resistance, breakdown voltage, and power density. By setting a cylindrical gate structure, an electrostatic shielding layer, and a side gate (or a segmented gate), three-dimensional electric field shaping of the channel and drift region is achieved. The potential is synergistically distributed in both the lateral and longitudinal directions, reducing the peak electric field and mitigating the edge field strength, thereby significantly improving breakdown voltage and reliability. The structure of this invention is based on a GaN epitaxial platform and can be realized through epitaxial design, etching, and metallization processes, without the need for complex bonding or multi-substrate processing, exhibiting silicon-based compatibility and high manufacturability. This structure also has the potential for array design and can serve as the basic architecture for high-power modules, 3D integration, or chiplet interconnect units.

[0040] Example 2 Based on Example 1, this example provides a method for fabricating a high-power wide-bandgap semiconductor device based on multi-conduction. Please refer to [link to example]. Figure 5 , Figure 5 This is a flowchart illustrating a method for fabricating a high-power wide-bandgap semiconductor device based on multi-conduction, according to an embodiment of the present invention. The method includes: S1: Buffer layer 2 and channel layer 3 are epitaxially grown on substrate 1, such as... Figure 6a As shown.

[0041] A SiC, Si, or sapphire substrate is selected as the substrate 1 in this embodiment. A buffer layer 2 is epitaxially grown on the substrate 1 to reduce dislocation density and improve thermal conductivity. In this embodiment, the buffer layer 2 is made of GaN material. The buffer layer 2 includes a first portion 21 and a second portion 22 sequentially stacked on the substrate 1. The first portion 21 has the same surface dimensions as the substrate 1, and the second portion 22 is located in the middle of the first portion 21 and has a smaller surface dimension than the first portion 21. The total thickness of the buffer layer 2 is 1~3 μm.

[0042] Subsequently, a channel layer 3 is epitaxially grown on the upper surface of the second portion 22 of the buffer layer 2. The material of the channel layer 3 is GaN, InGaAs, etc. This channel layer 3 can form a heterojunction with the subsequent barrier layer material, providing a basis for lateral channel conduction. The thickness of the channel layer 3 is 20-80 nm.

[0043] S2: Define the longitudinal conduction region: A first columnar opening 4 is opened inside the channel layer 3 and the buffer layer 2, an electrostatic shielding layer 5 is filled inside the first columnar opening 4, a second columnar opening 6 is opened inside the electrostatic shielding layer 5, and a gate metal 7 is filled inside the second columnar opening 6.

[0044] First, a first columnar opening 4 of a predetermined size is etched downwards from the center region of the upper surface of the channel layer 3 using photolithography and dry etching processes (such as inductively coupled plasma etching, ICP). This first columnar opening 4 extends downwards from the upper surface of the channel layer 3, penetrating the channel layer 3 and part of the buffer layer 2. In this embodiment, the first columnar opening 4 penetrates the second portion 22 of the channel layer 3 and the buffer layer 2. Figure 6b As shown, the area where the first columnar opening 4 is located will subsequently form a longitudinal conductive channel.

[0045] Subsequently, an electrostatic shielding layer 5 is filled inside the first columnar opening 4, such as... Figure 6c As shown, the electrostatic shielding layer 5 is prepared using a material suitable for electrostatic shielding. Next, a second columnar opening 6 of a predetermined size is etched downwards from the center region of the electrostatic shielding layer 5 using photolithography and dry etching processes. This second columnar opening 6 extends downwards from the upper surface of the electrostatic shielding layer 5 and has the same depth as the first columnar opening 4, as shown. Figure 6d As shown, next, the gate metal 7 is filled inside the second columnar opening 6, as... Figure 6e As shown, the channel layer 3, the second part 22 of the buffer layer 2, the electrostatic shielding layer 5 and the gate metal 7 are all coaxial.

[0046] Subsequently, a 10-20 nm thick channel layer material is deposited on the upper surface of the electrostatic shielding layer 5, the gate metal 7, and the remaining channel layer 3 to cover the electrostatic shielding layer 5 and the gate metal 7, as shown below. Figure 6f As shown.

[0047] S3: Define the lateral conduction region: deposit a barrier layer 8 on the upper surface of the channel layer material.

[0048] Specifically, a barrier layer 8 is deposited on the upper surface of the channel layer 3. The material of the barrier layer 8 is AlGaN, InAlGaN, or InGaAs. A heterojunction layer such as AlGaN / GaN, InAlGaN / GaN, or InGaAs / GaN is formed between the barrier layer 8 and the channel layer 3, thereby forming a lateral conductive channel with a high-mobility two-dimensional electron gas. In this embodiment, the thickness of the barrier layer 8 is approximately 10-25 nm to obtain a sufficient two-dimensional electron gas density.

[0049] S4: Define a cylindrical gate structure and form a lateral channel switch: Multiple third cylindrical openings 9 are made from the barrier layer 8, penetrating the barrier layer 8, the channel layer 3, and part of the buffer layer 2, and the gate dielectric layer 10 and the cylindrical gate 11 are sequentially filled into the third cylindrical openings 9 to form a cylindrical gate structure. The multiple cylindrical gate structures together form a lateral channel switch.

[0050] Specifically, multiple third columnar openings 9 are formed in the outer ring region of the upper surface of the barrier layer 8 prepared above using photolithography and dry etching, penetrating the barrier layer, channel layer, and part of the buffer layer. These multiple third columnar openings 9 are spaced apart from each other and form a ring structure around the center of the upper surface of the barrier layer 8, and are spaced apart from the electrostatic shielding layer 5 in the central region. Figure 6h As shown.

[0051] Subsequently, a gate dielectric layer 10 is filled into the third columnar opening 9, and a groove is etched in the central region of the gate dielectric layer 10. The depth of the groove is equal to the depth of the gate dielectric layer 10, and a columnar gate 11 is grown in the groove. Figure 6i As shown.

[0052] S5: Prepare a longitudinal conductive channel and form a three-dimensional potential control system: A fourth columnar opening 12 extending to the upper surface of the channel layer is opened on the barrier layer 8 above the electrostatic shielding layer 5 and the gate metal layer 7. A fifth columnar opening 13 extending into the buffer layer 2 is opened at the bottom center of the fourth columnar opening 12. A conductive dielectric layer 14 is filled inside the fifth columnar opening 13.

[0053] First, using photolithography and dry etching processes, a fourth columnar opening 12 extending to the upper surface of the channel layer is formed in the central region of the barrier layer 8, such as... Figure 6j As shown. In this embodiment, the diameter of the fourth columnar opening 12 is equal to the outer diameter of the electrostatic shielding layer 5. Then, a fifth columnar opening 13 with a diameter smaller than that of the gate metal layer 7 is formed in the central region of the fourth columnar opening 12. The fifth columnar opening 13 extends from the bottom center of the fourth columnar opening 12 to the upper surface of the first portion 21 of the buffer layer 2, as shown. Figure 6k As shown. Next, a conductive dielectric layer 14 is grown inside the fifth columnar opening 13, such that the gate metal layer 7 forms an annular side gate structure surrounding the conductive dielectric layer 14, as shown. Figure 6l As shown.

[0054] S6: A source electrode 15 is generated above the conductive dielectric layer 14, and a drain electrode is generated on the upper surface of the first part of the buffer layer 2.

[0055] Specifically, a multilayer metal Ti / Al / Ni / Au system is deposited in the source region defined above the conductive dielectric layer 14 and the drain region defined on the upper surface of the first part of the channel layer 3, and annealed to form a stable ohmic contact; the source and drain are respectively connected to the transverse conductive channel and the longitudinal conductive channel, thereby realizing the transmission of current in two directions.

[0056] Furthermore, the preparation method of this embodiment also includes: S7: Perform surface passivation and interconnection.

[0057] Specifically, a passivation dielectric layer is deposited on the device surface to stabilize the surface potential, and structural integration can be achieved through metal interconnects or air bridges.

[0058] This invention provides a high-power wide-bandgap semiconductor device based on multi-conduction. By reducing the on-resistance and increasing the breakdown voltage through three-dimensional potential modulation, it achieves high-voltage and high-current output and improves power density while ensuring device stability and process compatibility. It can solve the problems of single conduction path, electric field concentration and limited breakdown capability in the prior art.

[0059] This invention constructs a composite conduction path in both the transverse and longitudinal directions within the same heterojunction structure. This allows current to be transmitted between a high-mobility transverse channel and a high-voltage drift longitudinal path, effectively expanding the conductive cross-section, reducing the equivalent on-resistance, and improving the device's current carrying capacity and energy transfer efficiency. Simultaneously, the multi-dimensional shunt current transmission disperses localized heat accumulation, improving the device's thermal stability and reliability. Regarding electric field control, this invention employs multiple cylindrical gate structures, combined with an electrostatic shielding layer, a gate metal layer, and a conductive dielectric layer to form a three-dimensional potential control system. This achieves a uniform distribution of the transverse and longitudinal electric fields, effectively suppressing electric field concentration, short-channel effects, and trapping behavior, significantly improving the device's withstand voltage performance and stability.

[0060] This invention achieves a balance between low on-resistance, high breakdown voltage, and high reliability, while also possessing high mobility and excellent switching characteristics. Furthermore, the structure exhibits good process compatibility and scalability, making it suitable for various wide bandgap material platforms and high-power integrated applications.

[0061] In the several embodiments provided by this invention, it should be understood that the apparatus and methods disclosed in this invention can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of modules is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0062] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated module can be implemented in hardware or in the form of hardware plus software functional modules.

[0063] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high-power wide-bandgap semiconductor device based on multi-conduction, characterized in that, It includes, from bottom to top, a substrate (1), a buffer layer (2), a channel layer (3), and a barrier layer (8), wherein, The buffer layer (2) includes a first part (21) and a second part (22) stacked sequentially on the substrate (1). The second part (22) is located at the center of the upper surface of the first part (21) and its surface size is smaller than that of the first part (21). The second part (22) of the buffer layer (2), the channel layer (3) and the barrier layer (8) are all in a ring structure. The central groove of the ring stack structure formed by the second part (22), the channel layer (3) and the barrier layer (8) is filled with a ring-shaped electrostatic shielding layer (5). A gate metal layer (7) is provided in the central region of the electrostatic shielding layer (5). The upper surfaces of the electrostatic shielding layer (5) and the gate metal layer (7) are covered with a channel layer material; a conductive dielectric layer (14) extending from the upper surface of the channel layer material to the interior of the buffer layer (2) is provided in the central region of the gate metal layer (7); The outer side of the upper surface of the annular stacked structure includes a plurality of cylindrical gate structures surrounding the electrostatic shielding layer (5). Each cylindrical gate structure includes an annular gate dielectric layer (10) extending from the upper surface of the barrier layer (8) to the interior of the buffer layer (2) and a cylindrical gate (11) disposed inside the central groove of the gate dielectric layer (10). The upper surface of the conductive dielectric layer (14) is provided with a source electrode (15), and the upper surface of the buffer layer (2) on the outer side of the annular stacked structure is provided with a drain electrode (16).

2. The high-power wide-bandgap semiconductor device based on multi-conduction as described in claim 1, characterized in that, Both the electrostatic shielding layer (5) and the gate metal layer (7) are ring-shaped structures, either circular or square. The outer surface of the electrostatic shielding layer (5) is in contact with the inner surface of the ring-shaped stacked structure, the inner surface of the electrostatic shielding layer (5) is in contact with the outer surface of the gate metal layer (7), and the inner surface of the gate metal layer (7) is in contact with the outer surface of the conductive dielectric layer (14).

3. The high-power wide-bandgap semiconductor device based on multi-conduction as described in claim 2, characterized in that, The lower surfaces of the electrostatic shielding layer (5), the gate metal layer (7), and the conductive dielectric layer (14) are all in contact with the upper surface of the first part (21) of the buffer layer (2); The upper surfaces of the electrostatic shielding layer (5) and the gate metal layer (7) are flush with the upper surface of the channel layer (3), and the upper surface of the conductive dielectric layer (14) is flush with the upper surface of the channel layer material.

4. The high-power wide-bandgap semiconductor device based on multi-conduction as described in claim 1, characterized in that, The gate metal layer (7) includes a first annular side gate (71), a second annular side gate (72) and a third annular side gate (73) spaced apart along the axial direction by the electrostatic shielding layer (5), and the inner surfaces of the first annular side gate (71), the second annular side gate (72) and the third annular side gate (73) are in contact with the conductive dielectric layer (14).

5. The high-power wide-bandgap semiconductor device based on multi-conduction as described in claim 1, characterized in that, The plurality of cylindrical grid structures are uniformly surrounded around the outer periphery of the electrostatic shielding layer (5) and spaced apart from the electrostatic shielding layer (5); In each cylindrical gate structure, the gate dielectric layer (10) surrounds the outside of the cylindrical gate (11), and both the gate dielectric layer (10) and the cylindrical gate (11) extend from the upper surface of the barrier layer (8) to the upper surface of the first portion (21) of the buffer layer (2).

6. The high-power wide-bandgap semiconductor device based on multi-conduction as described in claim 1, characterized in that, Both the conductive dielectric layer (14) and the source electrode (15) are cylindrical and have the same diameter.

7. The high-power wide-bandgap semiconductor device based on multi-conduction as described in claim 1, characterized in that, The drain (16) has a ring structure, is located on the upper surface of the first part (21) of the buffer layer (2) and is spaced apart from the ring stack structure.

8. The high-power wide-bandgap semiconductor device based on multi-conduction as described in claim 1, characterized in that, A heterojunction structure is formed between the barrier layer (8) and the channel layer (3) to generate a two-dimensional electron gas.

9. A method for fabricating a high-power wide-bandgap semiconductor device based on multi-conduction, characterized in that, The method for fabricating the high-power wide-bandgap semiconductor device according to any one of claims 1 to 8 comprises: S1: Epitaxial growth of buffer layer and channel layer on substrate; S2: A first columnar opening is formed inside the channel layer and the buffer layer, an electrostatic shielding layer is filled inside the first columnar opening, a second columnar opening is formed inside the electrostatic shielding layer, a gate metal layer is filled inside the second columnar opening, and a channel layer material is deposited on the upper surface of the electrostatic shielding layer, the gate metal layer and the remaining channel layer. S3: Deposit a barrier layer on the upper surface of the channel layer material; S4: A plurality of third columnar openings are made from the barrier layer, penetrating the barrier layer, the channel layer and part of the buffer layer, and the gate dielectric layer and the columnar gate are sequentially filled in the third columnar openings. S5: A fourth columnar opening extending to the upper surface of the channel layer is formed on the barrier layer above the electrostatic shielding layer and the gate metal layer. A fifth columnar opening extending into the buffer layer is formed at the bottom center of the fourth columnar opening. A conductive dielectric layer is filled inside the fifth columnar opening. S6: A source electrode is generated above the conductive dielectric layer, and a drain electrode is generated on the upper surface of the first part of the buffer layer.

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