Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, at least one electronic adjustment layer is formed between a gate structure and a drain structure based on a patterned sacrificial layer, the electronic adjustment layer is configured to be a III-V compound, and the electronic adjustment layer close to the drain structure and the gate structure is arranged in a non-contact manner with the gate structure and the drain structure. The electron adjusting layer can generate relatively high donor state interface density so as to form more positive charges at the interface of the electron adjusting layer and the barrier layer, so that the effect of increasing the 2DEG concentration below the electron adjusting layer is achieved; the two-dimensional electron gas density at the contact surface of the channel layer and the barrier layer, which is substantially close to the lower part of the drain electrode structure, is higher than the 2DEG density at the contact surface of the channel layer and the barrier layer, which is close to the gate electrode structure, so that the on resistance of the device and the parasitic capacitance of the device are reduced; and meanwhile, the electronic adjusting layer close to the gate structure and the electronic adjusting layer close to the drain structure are correspondingly arranged in a non-contact mode, so that the breakdown risk at the drain structure and the gate structure can be effectively reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device manufacturing technology, and in particular relates to a semiconductor device and its preparation method. Background Technology

[0002] Compared to first- and second-generation semiconductor materials, third-generation semiconductor material gallium nitride (GaN) has a wide bandgap (3.4 eV), high breakdown field strength (3.0 MV / cm), and high electron saturation velocity (2.5 × 10⁻⁶). 7 The AlGaN / GaN heterostructure, formed by the ternary compound AlGaN and the binary compound GaN, can generate a high concentration of two-dimensional electron gas (2DEG) under the action of polarization effect. This makes the high electron mobility transistor (HEMT) based on the AlGaN / GaN heterojunction have a series of advantages such as high current density, high power density, high breakdown voltage, low on-resistance, high operating frequency, and small size. It has promising applications in high current, low power consumption, high voltage switching devices and radio frequency devices, and is currently a hot research topic in the field of semiconductor power electronic devices.

[0003] Currently, the on-resistance of III-V compound HEMT devices, represented by AlGaN / GaN heterojunctions, is relatively high, which severely restricts the device's lifespan and common application scenarios. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor device and its fabrication method, which at least solves the problem of high on-resistance in HEMT devices in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a semiconductor device, the device comprising:

[0006] The underlying structure includes at least a semiconductor substrate layer, a channel layer located above the semiconductor substrate layer, and a barrier layer located on the upper surface of the channel layer; wherein, a 2DEG is formed at the contact surface between the channel layer and the barrier layer.

[0007] A gate structure located on the upper surface of the preset region of the barrier layer;

[0008] The drain structure and the source structure extend at least into the interior of the underlying structure. The drain structure and the source structure are located on opposite sides of the gate structure and are not in contact with the gate structure.

[0009] At least one electronic conditioning layer is located on the upper surface of a portion of the barrier layer outside the gate structure; wherein the electronic conditioning layer is configured as a III-V compound, and at least one electronic conditioning layer is formed between the gate structure and the drain structure, and the electronic conditioning layer closest to the drain structure is disposed in a non-contact manner with the drain structure, and the electronic conditioning layer closest to the gate structure is disposed in a non-contact manner with the gate structure.

[0010] Optionally, the source structure and the drain structure are ohmic contact source and drain structures, and the source structure and the drain structure extend into the channel layer or the barrier layer.

[0011] Optionally, at least one of the electronic conditioning layers is further formed between the gate structure and the source structure.

[0012] Furthermore, the electron conditioning layer closest to the source structure is disposed in a non-contact manner with the source structure.

[0013] Optionally, it further includes an insulating layer located on the barrier layer between the source structure and the drain structure and covering the gate structure and all the electronic conditioning layers.

[0014] Optionally, the insulating layer covering the gate structure and the electronic modulation layer is the same insulating structure.

[0015] Optionally, the barrier layer covering the gate structure and the electronic control layer and the insulating layer covering the electronic control layer are the same insulating structure.

[0016] Optionally, the insulating layer covering the gate structure and the electronic conditioning layer, as well as the insulating layer covering the barrier layer between the gate structure and the drain structure, is the same insulating structure.

[0017] Optionally, the insulating layer is configured as a continuous, integral structure.

[0018] Optionally, in the direction from the gate structure to the drain structure, the insulating layer has no interlayer interface.

[0019] Furthermore, the material of the insulating layer includes silicon oxide and / or silicon nitride.

[0020] Optionally, it further includes an interface repair layer, which is located on the surface of the barrier layer between the source structure and the drain structure and covers the exposed outer surfaces of the gate structure and all the electronic conditioning layers, and the insulating layer is formed on the surface of the interface repair layer.

[0021] Furthermore, the material of the interface repair layer includes at least one of aluminum nitride, aluminum oxide, hafnium dioxide, yttrium oxide, lanthanum oxide, and silicon nitride.

[0022] Optionally, the underlying structure further includes a buffer layer located between the semiconductor substrate layer and the channel layer.

[0023] Optionally, all of the said electronic conditioning layers are spaced apart.

[0024] Furthermore, the material of the electronic conditioning layer includes at least one of AlN, AlGaN, GaN, InGaN, InAlGaN, and InAlGaAs.

[0025] Optionally, the semiconductor device is a depletion-type HEMT device or an enhancement-type HEMT device; when the semiconductor device is a depletion-type HEMT device, the gate structure includes at least a gate metal layer; when the semiconductor device is an enhancement-type HEMT device, the gate structure includes a p-type doped III-V compound and a gate metal layer.

[0026] Secondly, this application also provides a method for fabricating a semiconductor device, the method comprising the following steps:

[0027] A bottom layer structure is provided, the bottom layer structure including a semiconductor substrate layer, a channel layer located above the semiconductor substrate, and a barrier layer located on the upper surface of the channel layer; wherein, a 2DEG is formed at the contact surface between the channel layer and the barrier layer;

[0028] A gate structure is formed above the upper surface of a predetermined region of the barrier layer;

[0029] A patterned sacrificial layer is formed; wherein the patterned sacrificial layer covers a portion of the upper surface of the barrier layer and the surface of the gate structure, so as to expose at least a portion of the upper surface of the barrier layer outside the gate structure;

[0030] A source structure and a drain structure are formed, wherein the source structure and the drain structure extend at least into the interior of the underlying structure, and the source structure and the drain structure are located on opposite sides of the gate structure, and neither of them is in contact with the gate structure;

[0031] Based on the patterned sacrificial layer, at least one electronic conditioning layer is formed on the exposed surface of the barrier layer between the gate structure and the drain structure; wherein the conditioning electronic layer is configured as a group III-V compound, and the electronic conditioning layer closest to the drain structure is disposed in a non-contact manner with the drain structure, and the electronic conditioning layer closest to the gate structure is disposed in a non-contact manner with the gate structure.

[0032] Optionally, the method for forming the patterned sacrificial layer includes:

[0033] A sacrificial layer is formed above the barrier layer and the gate structure;

[0034] The sacrificial layer in the predetermined area is etched to form the patterned sacrificial layer.

[0035] Optionally, after forming the electronic conditioning layer, the process further includes a step of removing the patterned sacrificial layer.

[0036] Furthermore, after removing the patterned sacrificial layer and before forming the source structure and the drain structure, an insulating layer is also formed; wherein the insulating layer is located on a portion of the upper surface of the barrier layer and the upper surface of the electronic conditioning layer, and covers the gate structure.

[0037] Optionally, the insulating layer covering the gate structure and the electronic control layer is formed using the same process under the same process conditions.

[0038] Optionally, the insulating layer is formed using the same process under the same process conditions.

[0039] Optionally, after removing the patterned sacrificial layer, an interface repair layer is further formed; wherein the interface repair layer is located on the upper surface of a portion of the barrier layer and covers the exposed outer surfaces of the gate structure and all of the electronic conditioning layers.

[0040] Furthermore, the interface repair layer is formed using an atomic layer deposition process.

[0041] Furthermore, the material of the interface repair layer includes at least one of aluminum nitride, aluminum oxide, hafnium dioxide, yttrium oxide, lanthanum oxide, and silicon nitride.

[0042] Optionally, the process temperature for forming the electronic conditioning layer is higher than the process temperature for forming the insulating layer.

[0043] Optionally, the source structure and the drain structure are ohmic contact source structures and ohmic contact drain structures.

[0044] Furthermore, the method for forming the source structure and the drain structure includes:

[0045] Contact holes are formed on both sides of the gate structure, and the contact holes extend at least to the barrier layer;

[0046] The contact hole is filled with metal and annealed to form an ohmic contact.

[0047] Optionally, the method of forming the gate structure includes:

[0048] A p-type doped group III-V compound is formed on the upper surface of the preset region;

[0049] A gate metal layer is formed on the upper surface of the p-type doped group III-V compound.

[0050] Optionally, the method of forming the gate structure includes forming a gate metal layer on the upper surface of the preset region.

[0051] Optionally, the method of forming the gate structure includes:

[0052] A gate dielectric layer is formed on the upper surface of the preset region;

[0053] The gate metal layer is formed on the gate dielectric layer.

[0054] Optionally, at least one of the electronic conditioning layers is further formed between the gate structure and the source structure.

[0055] Furthermore, the electron conditioning layer closest to the source structure is disposed in a non-contact manner with the source structure.

[0056] Furthermore, the material of the electronic conditioning layer includes at least one of AlN, AlGaN, GaN, InGaN, InAlGaN, and InAlGaAs.

[0057] As described above, the semiconductor device and its fabrication method of the present invention form at least one electronic conditioning layer between the gate structure and the drain structure based on a patterned sacrificial layer. The electronic conditioning layer is configured as a III-V compound, and the electronic conditioning layer closest to the drain structure is disposed in a non-contact manner with the drain structure, and the electronic conditioning layer closest to the gate structure is disposed in a non-contact manner with the gate structure. This electronic conditioning layer can generate a higher donor state interface density to form more positive charges at the interface between the electronic conditioning layer and the barrier layer, thereby increasing the two-dimensional electron gas concentration below the electronic conditioning layer. This results in a higher two-dimensional electron gas density at the interface between the channel layer and the barrier layer near the drain structure than at the interface between the channel layer and the barrier layer near the gate structure, thereby reducing the on-resistance and parasitic capacitance of the device. At the same time, the electronic conditioning layers near the gate structure and the electronic conditioning layers near the drain structure are respectively configured in a non-contact manner, which can effectively reduce the breakdown risk at the drain structure and the gate structure. Attached Figure Description

[0058] Figure 1 and Figure 2 The diagram shows two examples of cross-sectional structures of a semiconductor device according to Embodiment 1 of the present invention.

[0059] Figures 3 to 13The diagram shows a cross-sectional view of each step in the fabrication method of the semiconductor device according to Embodiment 2 of the present invention.

[0060] Figures 14 to 17 The diagram shows a cross-sectional view of each step in the fabrication method of the semiconductor device according to Embodiment 3 of the present invention.

[0061] Component designation explanation

[0062] 10 Underlying structure 100 Semiconductor substrate 101 Buffer layer 102 Channel layer 103 Barrier layer 104 Two-dimensional electronic gas 11 Source structure 12 Drain structure 13 gate structure 130 Gate dielectric layer 131 Gate metal layer 132 P-type doped group III-V compounds 14 Electronic regulation layer 15 Insulation layer 16 Interface Repair Layer 17 Sacrificial layer 170 Patterned sacrificial layers 171 window Detailed Implementation

[0063] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0064] Please see Figures 1 to 17 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0065] This application provides a method for fabricating a semiconductor device, the method comprising the following steps:

[0066] A bottom layer structure is provided, the bottom layer structure including a semiconductor substrate layer, a channel layer located above the semiconductor substrate, and a barrier layer located on the upper surface of the channel layer; wherein, a 2DEG is formed at the contact surface between the channel layer and the barrier layer;

[0067] A gate structure is formed above the upper surface of a predetermined region of the barrier layer;

[0068] A patterned sacrificial layer is formed; wherein the patterned sacrificial layer covers a portion of the upper surface of the barrier layer and the surface of the gate structure, so as to expose at least a portion of the upper surface of the barrier layer outside the gate structure;

[0069] A source structure and a drain structure are formed, wherein the source structure and the drain structure extend at least into the interior of the underlying structure, and the source structure and the drain structure are located on opposite sides of the gate structure, and neither of them is in contact with the gate structure;

[0070] Based on the patterned sacrificial layer, at least one electronic conditioning layer is formed on the exposed surface of the barrier layer between the gate structure and the drain structure; wherein the conditioning electronic layer is configured as a group III-V compound, and the electronic conditioning layer closest to the drain structure is disposed in a non-contact manner with the drain structure, and the electronic conditioning layer closest to the gate structure is disposed in a non-contact manner with the gate structure.

[0071] The semiconductor device fabrication method of this application involves forming at least one electronic conditioning layer between a gate structure and a drain structure using a patterned sacrificial layer. The electronic conditioning layer is configured as a III-V compound, with the electronic conditioning layer closest to the drain structure and the electronic conditioning layer closest to the gate structure being non-contact. This electronic conditioning layer can generate a higher donor-state interface density to form more positive charges at the interface between the electronic conditioning layer and the barrier layer, thereby increasing the two-dimensional electron gas concentration below the electronic conditioning layer. This results in a higher two-dimensional electron gas density at the interface between the channel layer and the barrier layer near the drain structure compared to the interface near the gate structure, thus reducing the device's on-resistance and parasitic capacitance. Simultaneously, the non-contact configuration of the electronic conditioning layers near the gate structure and the drain structure effectively reduces the breakdown risk at both the drain and gate structures.

[0072] This application also provides a semiconductor device, which can be prepared using the preparation method described in this application, but is not limited to the preparation method described in this application; any preparation method capable of forming the semiconductor device is acceptable. The beneficial effects achievable by this semiconductor device can be found in the above preparation method description, and will not be repeated here. The semiconductor device includes:

[0073] The underlying structure includes at least a semiconductor substrate layer, a channel layer located above the semiconductor substrate layer, and a barrier layer located on the upper surface of the channel layer; wherein, a 2DEG is formed at the contact surface between the channel layer and the barrier layer.

[0074] A gate structure located on the upper surface of the preset region of the barrier layer;

[0075] The drain structure and the source structure extend at least into the interior of the underlying structure. The drain structure and the source structure are located on opposite sides of the gate structure and are not in contact with the gate structure.

[0076] At least one electronic conditioning layer is located on the upper surface of a portion of the barrier layer outside the gate structure; wherein the electronic conditioning layer is configured as a III-V compound, and at least one electronic conditioning layer is formed between the gate structure and the drain structure, and the electronic conditioning layer closest to the drain structure is disposed in a non-contact manner with the drain structure, and the electronic conditioning layer closest to the gate structure is disposed in a non-contact manner with the gate structure.

[0077] The semiconductor device and its fabrication method of this application will be described in detail below with reference to the specific accompanying drawings and corresponding embodiments.

[0078] Example 1

[0079] This embodiment provides a semiconductor device, such as Figure 1 and Figure 2 As shown, and refer to Figure 3 and Figure 5 The semiconductor device includes:

[0080] The underlying structure 10 includes at least a semiconductor substrate 100, a channel layer 102 located above the semiconductor substrate 100, and a barrier layer 103 located on the upper surface of the channel layer 102; wherein a two-dimensional electron gas 104 (2DEG) is formed at the contact surface between the channel layer 102 and the barrier layer 103.

[0081] Gate structure 13 located on the upper surface of the preset region of the barrier layer 103;

[0082] The drain structure 12 and the source structure 11 extend at least into the interior of the underlying structure 10. The drain structure 12 and the source structure 11 are located on opposite sides of the gate structure 13, and neither of them is in contact with the gate structure 13.

[0083] At least one electronic conditioning layer 14 is located on the upper surface of a portion of the barrier layer 103 outside the gate structure 13; wherein the electronic conditioning layer 14 is configured as a III-V compound, and at least one electronic conditioning layer 14 is formed between the gate structure 13 and the drain structure 12, with the electronic conditioning layer 14 closest to the drain structure 12 being non-contact with the drain structure 12, and the electronic conditioning layer 14 closest to the gate structure 13 being non-contact with the gate structure 13. This non-contact arrangement of the electronic conditioning layer with the drain structure optimizes device performance while completely avoiding interference with the original drain process flow caused by the introduction of the electronic conditioning layer.

[0084] It should be noted that the electron conditioning layer 14 generates a higher donor state interface density to form more positive charges at the interface between the electron conditioning layer 13 and the barrier layer 103, thereby increasing the two-dimensional electron gas concentration below the electron conditioning layer 14 and reducing the on-resistance of the device.

[0085] HEMT devices are typically based on heterojunction structures of group III-V materials, such as AlGaAs / GaAs heterojunctions or AlGaN / GaN heterojunctions. 2DEGs are usually formed at the interface of the heterojunction, where electrons are confined to an extremely narrow space (usually a few nanometers) and can only move freely in a two-dimensional plane. Therefore, the carrier mobility and conductivity are extremely high.

[0086] As an example, the underlying structure 10 further includes a buffer layer 101 located between the semiconductor substrate layer 100 and the channel layer 102. The buffer layer 101 is used to release stress caused by lattice mismatch and thermal mismatch between the epitaxially grown heterostructure and the semiconductor substrate layer 100. For example, when the underlying structure 10 is a GaN-based HEMT device thin film structure, the buffer layer 101 can be selected as an AlGaN buffer layer. Further, it can be a composite material layer with gradually decreasing Al content along the growth direction of the AlGaN buffer layer. This is only an example, and the specific configuration of the buffer layer 101 can be selected according to actual needs.

[0087] As an example, the underlying structure 10 is a GaN-based HEMT device thin film structure, formed into a GaN-based HEMT device. Therefore, the channel layer 102 is a GaN channel layer, and the barrier layer 103 is an AlGaN barrier layer.

[0088] As an example, the semiconductor substrate 100 can be any suitable semiconductor substrate, such as a Si substrate, a SiC substrate, an aluminum nitride substrate, an aluminum oxide substrate, or a sapphire substrate, etc. In this embodiment, the semiconductor substrate 100 is preferably selected as a Si substrate. In addition, the semiconductor substrate 100 can also be doped, such as N-type or P-type doping. In this embodiment, the Si substrate is selected as P-type doped.

[0089] As a preferred example, the bandgap of the electron control layer 14 is greater than or equal to the bandgap of the barrier layer 103. For example, the material of the electron control layer 14 can be at least one of AlN, AlGaN, InGaN, InAlGaN, and InAlGaAs. Specifically, when the underlying structure 10 is a GaN-based HEMT device thin film structure, the electron control layer 13 is selected as an aluminum nitride electron control layer of semiconductor material. The electron control layer 13 can be doped or undoped as needed.

[0090] As an example, such as Figure 2 As shown, the semiconductor device of this embodiment further includes an insulating layer 15, which is located on the barrier layer 103 between the source structure 11 and the drain structure 12 and covers the gate structure 13 and all the electron conditioning layers 14. In an optional embodiment, the insulating layer covering the gate structure and the electron conditioning layers is the same insulating structure; further, the insulating layer covering the gate structure and the electron conditioning layer and the insulating layer covering the barrier layer between the gate structure and the drain structure is the same insulating structure. In another optional embodiment, the barrier layer covering the gate structure and the electron conditioning layer and the insulating layer covering the electron conditioning layer are the same insulating structure. In another optional embodiment, the insulating layer 15 is configured as a continuous integral structure, that is, in this embodiment, the drain structure 12, the electron conditioning layer 14 and the gate structure 13 are all in contact with the same insulating structure, and the insulating layer has no interlayer interface in the direction from the gate structure to the drain structure. The material of the insulating layer 15 can be silicon oxide or silicon nitride, or a mixture of silicon oxide and silicon nitride. When the same insulating structure is made of a single material, it is a homogeneous continuous body without internal interlayer interfaces or material decomposition. When the same insulating structure is made of multiple mixed materials, it has no interlayer interfaces in the lateral direction. The continuous, integral structure of the insulating layer avoids the problem of uneven electric field distribution caused by interface defects, thereby improving the breakdown electric field of the device, as well as the device's operational stability and reliability.

[0091] As an example, such as Figure 1 As shown, the semiconductor device in this embodiment further includes an interface repair layer 16. The interface repair layer 16 is located on the surface of the barrier layer 103 between the source structure 11 and the drain structure 12, and covers the exposed outer surfaces of the gate structure 13 and all the electronic conditioning layers 14, to repair defects on the exposed structural surfaces and protect them. The material of the interface repair layer 16 can be at least one from the group consisting of aluminum nitride, aluminum oxide, hafnium dioxide, yttrium oxide, lanthanum trioxide, and silicon nitride. For example, it can be aluminum nitride or aluminum oxide, or a mixture of aluminum nitride and aluminum oxide, and its thickness is generally thin. Further, as... Figure 1 As shown, if the insulating layer 15 is also included, then the insulating layer 15 is formed on the surface of the interface repair layer 16.

[0092] As an example, such as Figure 2As shown, the electron conditioning layer 14 can also be formed between the gate structure 13 and the source structure 11, that is, the electron conditioning layer 14 is formed between the gate structure 13 and the drain structure 12, and also between the gate structure 13 and the source structure 11. Furthermore, the electron conditioning layer 14 closest to the source structure 11 is non-contact with the source structure 11, so that when forming the ohmic contact holes of the source structure 11 and the drain structure 12, it is not necessary to etch the electron conditioning layer 14, thus allowing it to be implemented using the same etching process, facilitating process control and reducing process complexity.

[0093] Furthermore, the number of electron conditioning layers 14 between the gate structure 13 and the drain structure 12 can be one (e.g., Figure 1 (As shown) can also be multiple; additionally, when the electron conditioning layer 14 is also disposed between the gate structure 13 and the source structure 11, the number can be one (e.g. Figure 2 (As shown) There can also be multiple layers. The number of the electronic conditioning layers 14 is set according to actual needs. More preferably, all the electronic conditioning layers 14 are spaced apart. When two or more (including the number of these) electronic conditioning layers 14 are provided between the gate structure 13 and the source structure 11 and / or the drain structure 12, the density of the 2DEG below can be controlled segmentally. While reducing the on-resistance, the electric field between the gate source and / or the gate drain can also be controlled, making the channel electric field distribution more uniform and improving the breakdown voltage of the device.

[0094] As an example, the source structure 11 and the drain structure 12 are ohmic contact source structures 11 and 12. Furthermore, the source structure 11 and the drain structure 12 extend at least into the barrier layer 103, and may also extend into the channel layer 102, depending on actual needs.

[0095] As an example, the semiconductor device in this embodiment can be a depletion-mode HEMT device (D-mode) or an enhancement-mode HEMT device (E-mode). When it is a depletion-mode HEMT device, such as Figure 5 As shown, the gate structure 13 includes a gate dielectric layer 130 and a gate metal layer 131, or it may only include the gate metal layer 131 without the gate dielectric layer 130; when it is an enhancement-mode HEMT device, such as Figure 5As shown, the gate material layer includes a P-type doped group III-V compound layer 132 and a gate metal layer 131. Preferably, the P-type doped group III-V compound layer 132 is P-type GaN, and the gate metal layer 131 can be made of existing materials suitable for use as gate metal layers in HEMT devices, such as a Ni / Au stacked structure, the thickness of each metal layer in which can be set according to specific needs.

[0096] Example 2

[0097] This embodiment provides a method for fabricating a semiconductor device. This method can be used to fabricate the semiconductor device described in Embodiment 1. However, the semiconductor device in Embodiment 1 is not limited to the fabrication method of this embodiment, but the fabrication method of this embodiment is superior.

[0098] like Figure 3 As shown, step S1 is performed first to provide a bottom layer structure 10, which includes a semiconductor substrate layer 100, a channel layer 102 located above the semiconductor substrate layer 100, and a barrier layer 103 located on the upper surface of the channel layer 102; wherein, a two-dimensional electron gas 104 (2DEG) is formed at the contact surface between the channel layer 102 and the barrier layer 103.

[0099] It should be noted that the underlying structure 10 can be grown by epitaxial technology or purchased externally, as long as the structure can realize the HEMT semiconductor device in this embodiment.

[0100] HEMT devices are typically based on heterojunction structures of group III-V materials, such as AlGaAs / GaAs heterojunctions or AlGaN / GaN heterojunctions. 2DEGs are usually formed at the interface of the heterojunction, where electrons are confined to an extremely narrow space (usually a few nanometers) and can only move freely in a two-dimensional plane. Therefore, the carrier mobility and conductivity are extremely high.

[0101] As an example, the underlying structure 10 further includes a buffer layer 101 located between the semiconductor substrate layer 100 and the channel layer 102. The buffer layer 101 is used to release stress caused by lattice mismatch and thermal mismatch between the epitaxially grown heterostructure and the semiconductor substrate layer 100. For example, when the underlying structure 10 is a GaN-based HEMT device thin film structure, the buffer layer 101 can be selected as an AlGaN buffer layer. Further, it can be a composite material layer with gradually decreasing Al content along the growth direction of the AlGaN buffer layer. This is only an example, and the specific configuration of the buffer layer 101 can be selected according to actual needs.

[0102] As an example, the underlying structure 10 is a GaN-based HEMT device thin film structure, which is subsequently formed into a GaN-based HEMT device. Therefore, the channel layer 102 is a GaN channel layer, and the barrier layer 103 is an AlGaN barrier layer.

[0103] As an example, the semiconductor substrate 100 can be any suitable semiconductor substrate, such as a Si substrate, a SiC substrate, an aluminum nitride substrate, an aluminum oxide substrate, or a sapphire substrate, etc. In this embodiment, the semiconductor substrate 100 is preferably selected as a Si substrate. In addition, the semiconductor substrate 100 can also be doped, such as N-type or P-type doping. In this embodiment, the Si substrate is selected as P-type doped.

[0104] like Figure 5 As shown, step S2 is then performed to form a gate structure 13 above the upper surface of the preset region of the barrier layer 103.

[0105] This embodiment employs a gate-first process, meaning that the gate structure 13 is fabricated first, followed by the source and drain structures. Therefore, the gate structure 13 is fabricated first after the underlying structure 10 is formed.

[0106] As a specific example, the method for forming the gate structure 13 includes: firstly, depositing the material layer required for the gate structure 13 on the barrier layer 103. It should be noted that the HEMT device fabricated in this embodiment can be a depletion-mode HEMT device (D-mode) or an enhancement-mode HEMT device (E-mode). When it is a depletion-mode HEMT device, such as... Figure 4 As shown, the material layers required for the gate structure 13 include a gate dielectric layer 130 and a gate metal layer 131, or it may only include the gate metal layer 131 without the gate dielectric layer 130; when it is an enhancement-mode HEMT device, such as Figure 4 As shown, the material layer required for the gate structure 13 includes a p-type doped III-V compound 132 and a gate metal layer 131; preferably, the p-type doped III-V compound 132 is p-type gallium nitride. Figure 5 As shown, the material layer required for the deposited gate structure 13 is then etched using a photolithography etching process to form the gate structure 13 of a predetermined shape and size in a predetermined region.

[0107] The gate metal layer 131 can be made of existing materials suitable for use as gate metal layers in HEMT devices, such as a Ni / Au stack structure, the thickness of each metal layer in which can be set according to specific needs.

[0108] like Figure 7As shown, step S3 is then performed to form a patterned sacrificial layer 170; wherein the patterned sacrificial layer 170 covers a portion of the upper surface of the barrier layer 103 and the surface of the gate structure 13, so as to expose a portion of the upper surface of the barrier layer 103 on one side of the gate structure 13, where one side of the gate structure 13 refers to the side near the subsequently formed drain structure; wherein the patterned sacrificial layer 170 has a window 171, the window 171 is formed on the side of the gate structure 11 near the subsequently formed drain structure, and is not in the region of the subsequently formed drain structure nor extends to the region where the gate structure 13 is located.

[0109] Subsequent processes will form an electronic conditioning layer 14 in the window 171, thus the window 171 determines the position of the subsequent electronic conditioning layer 14. In this embodiment, the patterned sacrificial layer 170 has one of the windows 171, so an electronic conditioning layer 14 will be formed on the side of the gate structure 11 near the drain structure, and this electronic conditioning layer 14 will not contact the gate structure 13 and the drain structure.

[0110] Of course, the number of windows 171 on the patterned sacrificial layer 170 is not excessively limited here; it can be one or more. When there are multiple windows 171, multiple electronic conditioning layers 14 will be formed between the gate structure 13 and the drain structure, which can segmentally control the density of the 2DEG below it. While reducing the on-resistance, it can also control the electric field between the gate and drain, making the channel electric field distribution more uniform, thereby improving the breakdown voltage of the device.

[0111] As a specific example, the method for forming the patterned sacrificial layer 170 includes: Figure 6 As shown, a sacrificial layer 17 is first deposited on the surface of the barrier layer 103 and the gate structure 13. The sacrificial layer 17 is formed, for example, using a conventional and suitable CVD, PVD, or ALD deposition process. The material of the sacrificial layer 17 can be silicon oxide and / or silicon nitride. Figure 7 As shown, a portion of the sacrificial layer 17 is then etched away using an etching process to obtain the patterned sacrificial layer 170. Of course, the patterned sacrificial layer 170 with the desired pattern can be implemented using a corresponding photomask.

[0112] like Figure 9As shown, step S4 is then performed, whereby an electron conditioning layer 14 is formed in the window 171 based on the patterned sacrificial layer 170; wherein, the electron conditioning layer 14 is configured as a III-V compound, and the electron conditioning layer 14 causes the 2DEG density at the interface between the channel layer 102 and the barrier layer 103 in the corresponding region below it to be higher than the 2DEG density at the interface between the channel layer 102 and the barrier layer 103 in other regions. Preferably, the electron conditioning layer 14 is configured as one or more of AlN, AlGaN, InGaN, InAlGaN, and InAlGaAs.

[0113] It should be noted that the electron conditioning layer 14 generates a higher donor state interface density to form more positive charges at the interface between the electron conditioning layer 14 and the barrier layer 103, thereby increasing the concentration of the two-dimensional electron gas below the electron conditioning layer 14 and reducing the on-resistance of the device. In addition, in the accompanying drawings of this embodiment, a thicker red dashed line is used to distinguish the enhancement effect of the electron conditioning layer 14 on the density of the 2DEG below it.

[0114] As an example, such as Figure 8 As shown, the electron conditioning layer 14 can be formed using existing conventional and suitable full-area deposition processes, such as CVD, PVD, or ALD deposition processes. The formed electron conditioning layer 14 not only fills the window 171, but is also deposited on the patterned sacrificial layer 170. Alternatively, a selective deposition process can be used to form the electron conditioning layer 14 only in the window 171.

[0115] As a preferred example, the bandgap of the electron control layer 14 is greater than or equal to the bandgap of the barrier layer 103. For example, the material of the electron control layer 14 can be at least one of AlN, AlGaN, InGaN, InAlGaN, and InAlGaAs. Specifically, when the underlying structure 10 is a GaN-based HEMT device thin film structure, the electron control layer 14 is selected as an aluminum nitride electron control layer of semiconductor material. The electron control layer 14 can be doped or undoped as needed.

[0116] As an example, such as Figure 9As shown, after forming the electron conditioning layer 14, the process further includes removing the patterned sacrificial layer 170. It should be noted that when the electron conditioning layer 14 is formed using a full-area deposition process, the formed electron conditioning layer 14 not only fills the window 171 but also deposits on the patterned sacrificial layer 170. In this case, a lift-off process can be used to remove the patterned sacrificial layer 170, and the electron conditioning layer 14 on the patterned sacrificial layer 170 will also be removed simultaneously, thus retaining only the electron conditioning layer 14 in the window 171. When the electron conditioning layer 14 is formed using a selective deposition process, the electron conditioning layer 14 will not form on the patterned sacrificial layer 170. In this case, a suitable wet and / or dry process can be used to remove the patterned sacrificial layer 170.

[0117] As a better example, such as Figure 11 As shown, after removing the patterned sacrificial layer 170, the process further includes forming an insulating layer 15 on the barrier layer 103. The insulating layer 15 is located on a portion of the upper surface of the barrier layer 103 and the upper surface of the electronic conditioning layer 14, and covers the gate structure 13. Generally, the process temperature for preparing the electronic conditioning layer 14 is higher than that for the insulating layer 15. Therefore, in this embodiment, when the electronic conditioning layer 14 is formed first and then the insulating layer 15 is formed, the insulating layer 15 will not be affected by the high-temperature process, thereby avoiding the deterioration effect of the process temperature of the electronic conditioning layer 14 on the contact interface of the insulating layer 15, especially the portion of the insulating layer 15 covering the gate structure 13. Deterioration of the contact quality between the two can easily lead to an increase in gate leakage. However, if the electronic conditioning layer 14 is formed first and then the insulating layer 15 is formed, the high-temperature process conditions of the electronic conditioning layer 14 will not affect the formation process of the insulating layer 15, thereby effectively ensuring the contact quality between the insulating layer 15 and its contact layer. This reduces the device's on-resistance and parasitic capacitance while also reducing the device's gate leakage.

[0118] The insulating layer 15 can be formed using existing suitable deposition processes, such as CVD, PVD, and ALD processes. The material of the insulating layer 15 can be the same as that of the sacrificial layer 17, and the same fabrication process can be used. For example, the insulating layer 15 can be a silicon oxide layer, a silicon nitride layer, or a stack of silicon oxide and silicon nitride layers. The insulating layer covering the gate structure and the electronic control layer is formed using the same process under the same process conditions. In other embodiments, the insulating layer 15 is formed using the same process under the same process conditions. Specifically, the same process here refers to the continuous deposition of insulating material in the same reaction chamber under the same process conditions, thereby forming a complete insulating layer covering the desired area in one step. Forming the insulating layer using a single process not only simplifies the process and reduces costs but also improves the uniformity of the insulating layer.

[0119] As another better example, such as Figure 10 As shown, after removing the patterned sacrificial layer 170, an interface repair layer 16 is formed. The interface repair layer 16 is located on the upper surface of a portion of the barrier layer 103 and covers the exposed outer surfaces of the gate structure 13 and the electronic conditioning layer 14. The interface repair layer 16 can repair defects on the exposed structural surface and protect the exposed structural surface. The interface repair layer 16 can be formed using an atomic layer deposition process with good film deposition uniformity. The material of the interface repair layer 16 can be at least one from the group consisting of aluminum nitride, aluminum oxide, hafnium dioxide, yttrium oxide, lanthanum oxide, and silicon nitride. For example, it can be aluminum nitride or aluminum oxide, or a mixture of aluminum nitride and aluminum oxide, and its thickness is generally thin. Further, as... Figure 12 As shown, if the step of forming the insulating layer 15 is also included at this time, the insulating layer 15 is formed on the surface of the interface repair layer 16.

[0120] As another preferred example, after removing the patterned sacrificial layer 170, the exposed surfaces of the resulting structure can be cleaned to further remove any residue of the patterned sacrificial layer 170, i.e., the exposed surfaces of the barrier layer 103, the gate structure 13, and the electronic control layer 14 can be cleaned.

[0121] Physical cleaning is generally not the preferred method for this cleaning process because it can cause significant damage to the structural surface. Chemical cleaning, or a combination of chemical and physical cleaning, can be used to minimize damage to the structural surface while ensuring cleaning effectiveness. Chemical cleaning is a wet cleaning process that uses chemical agents and their reactions to remove residues from the structural surface. Chemical cleaning combined with physical cleaning refers to the simultaneous use of both chemical and physical cleaning methods. Compared to using physical cleaning alone, the physical cleaning in this combination causes significantly less damage to the structural surface.

[0122] like Figure 13 As shown, step S5 is performed to form a source structure 11 and a drain structure 12. The source structure 11 and the drain structure 12 extend at least into the interior of the bottom layer structure 10. The source structure 11 and the drain structure 12 are located on opposite sides of the gate structure 13 and do not contact the gate structure 13. Furthermore, the electron conditioning layer 14 does not contact the drain structure 12 and the source structure 11, nor does it contact the gate structure 13. Therefore, the process of forming the drain structure 12 and the source structure 11 is not affected by the introduction of the electron conditioning layer 14, which improves the ohmic contact characteristics of the source structure 11 and the drain structure 12.

[0123] As an example, the source structure 11 and the drain structure 12 are ohmic contact source structure 11 and ohmic contact drain structure 12. Specifically, the method for forming the source structure 11 and the drain structure 12 includes: first, forming contact holes on both sides of the gate structure 13, the contact holes extending at least to the barrier layer 103; then, filling the contact holes with metal and annealing to form ohmic contacts for the source structure 11 and the drain structure 12. The annealing process parameters are set according to actual conditions, and the filling metal includes, but is not limited to, TiAlTi / TiAlTiTiN / NiAu, specifically selected according to actual needs. As an example, the source structure 11 and the drain structure 12 extend into the channel layer 102. In other examples, the source structure 11 and the drain structure 12 extend into the upper surface of the barrier layer 103. In some examples, the source structure 11 and the drain structure 12 extend into the barrier layer 103. Here, the extension depth of the source structure 11 and the drain structure 12 is not limited. The extension depth of the source structure 11 and the drain structure 12 into the underlying structure 10 can be set according to actual needs.

[0124] Example 3

[0125] like Figures 14 to 17 As shown, this embodiment provides a method for fabricating a semiconductor device. The fabrication method of this embodiment is basically the same as that of Embodiment 2, except that the pattern of the patterned sacrificial layer 170 formed in step S3 is different. In this embodiment, the patterned sacrificial layer 170 covers part of the upper surface of the barrier layer 103 and the surface of the gate structure 13, so as to expose the upper surface of the barrier layer 103 in a portion of both sides of the gate structure 13. Here, the two sides of the gate structure 11 refer to the side closer to the subsequently formed drain structure 12 and the side closer to the subsequently formed source structure 11; as Figure 15 As shown, when the electronic adjustment layer 14 is formed in step S4, the electronic adjustment layer 14 is formed on both sides of the gate structure 13.

[0126] like Figure 14 As shown, the patterned sacrificial layer 170 has two windows 171, one window 171 is disposed on the side of the gate structure 13 near the drain structure, and the other window 171 is disposed on the side of the gate structure 13 near the source structure, thereby... Figure 15 As shown, when forming the electronic adjustment layer 14 in step S4, an electronic adjustment layer 14 is formed on both sides of the gate structure 13.

[0127] Of course, the number of windows 171 in the patterned sacrificial layer 170 can also be three or more, so that two or more electronic conditioning layers 14 can be formed on the side of the gate structure 13 near the drain structure and / or on the side of the gate structure 13 near the source structure, so as to achieve segmented control of the density of 2DEG below the electronic conditioning layer 14. While reducing the on-resistance, the electric field between the gate drain and / or the gate source can also be controlled, making the channel electric field distribution more uniform, thereby improving the breakdown voltage of the device.

[0128] As a better example, such as Figure 17 As shown, the electron conditioning layer 14 closest to the source structure 11 is not in contact with the source structure 11. That is, neither the source structure 11 nor the drain structure 12 is in contact with the corresponding electron conditioning layer 14. In this case, the etching of the contact holes between the source structure 11 and the drain structure 12 can be achieved using the same etching process, which facilitates process control and reduces process complexity.

[0129] It should also be noted that, except for the differences between this embodiment and Embodiment 2 as described above, all other preparation processes can be referred to Embodiment 2, and will not be repeated here.

[0130] In summary, this invention provides a semiconductor device and its fabrication method. Based on a patterned sacrificial layer, at least one electronic conditioning layer is formed between the gate and drain structures. This electronic conditioning layer is configured as a III-V compound, with the electronic conditioning layer closest to the drain structure and the electronic conditioning layer closest to the gate structure being non-contact. This electronic conditioning layer can generate a higher donor-state interface density, forming more positive charges at the interface between the electronic conditioning layer and the barrier layer. This increases the two-dimensional electron gas concentration below the electronic conditioning layer, resulting in a higher two-dimensional electron gas density at the interface between the channel layer and the barrier layer near the drain structure compared to the interface near the gate structure. This reduces the device's on-resistance and parasitic capacitance. Furthermore, the non-contact configuration of the electronic conditioning layers near the gate and drain structures effectively reduces the breakdown risk at both the drain and gate structures. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0131] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: The underlying structure includes at least a semiconductor substrate layer, a channel layer located above the semiconductor substrate layer, and a barrier layer located on the upper surface of the channel layer; wherein a 2DEG is formed at the contact surface between the channel layer and the barrier layer. A gate structure located on the upper surface of the preset region of the barrier layer; The drain structure and the source structure extend at least into the interior of the underlying structure. The drain structure and the source structure are located on opposite sides of the gate structure and are not in contact with the gate structure. At least one electronic conditioning layer is located on the upper surface of a portion of the barrier layer outside the gate structure; wherein the electronic conditioning layer is configured as a III-V compound, and at least one electronic conditioning layer is formed between the gate structure and the drain structure, and the electronic conditioning layer closest to the drain structure is disposed in a non-contact manner with the drain structure, and the electronic conditioning layer closest to the gate structure is disposed in a non-contact manner with the gate structure.

2. The semiconductor device according to claim 1, characterized in that: The source structure and the drain structure are ohmic contact source and drain structures, and the source structure and the drain structure extend into the channel layer or the barrier layer.

3. The semiconductor device according to claim 1, characterized in that: At least one electronic conditioning layer is also formed between the gate structure and the source structure.

4. The semiconductor device according to claim 3, characterized in that: The electron conditioning layer closest to the source structure is disposed in a non-contact manner with the source structure.

5. The semiconductor device according to claim 1, characterized in that: It also includes an insulating layer located on the barrier layer between the source structure and the drain structure and covering the gate structure and all the electronic conditioning layers.

6. The semiconductor device according to claim 5, characterized in that: The insulating layer covering the gate structure and the electronic modulation layer is the same insulating structure.

7. The semiconductor device according to claim 5, characterized in that: The barrier layer covering the gate structure and the electron control layer and the insulating layer covering the electron control layer are the same insulating structure.

8. The semiconductor device according to claim 5, characterized in that: The insulating layer covering the gate structure and the electronic conditioning layer, as well as the insulating layer covering the barrier layer between the gate structure and the drain structure, is the same insulating structure.

9. The semiconductor device according to claim 5, characterized in that: The insulating layer is configured as a continuous, integral structure.

10. The semiconductor device according to claim 5, characterized in that: In the direction from the gate structure to the drain structure, the insulating layer has no interlayer interface.

11. The semiconductor device according to claim 5, characterized in that: The insulating layer is made of silicon oxide and / or silicon nitride.

12. The semiconductor device according to claim 1 or 5, characterized in that: It also includes an interface repair layer, which is located on the surface of the barrier layer between the source structure and the drain structure and covers the exposed outer surfaces of the gate structure and all the electronic conditioning layers, and the insulating layer is formed on the surface of the interface repair layer.

13. The semiconductor device according to claim 12, characterized in that: The material of the interface repair layer includes at least one of aluminum nitride, aluminum oxide, hafnium dioxide, yttrium oxide, lanthanum oxide, and silicon nitride.

14. The semiconductor device according to claim 1, characterized in that: The underlying structure also includes a buffer layer located between the semiconductor substrate layer and the channel layer.

15. The semiconductor device according to claim 1, characterized in that: All of the aforementioned electronic conditioning layers are spaced apart.

16. The semiconductor device according to claim 1, characterized in that: The material of the electronic conditioning layer includes at least one of AlN, AlGaN, GaN, InGaN, InAlGaN, and InAlGaAs.

17. The semiconductor device according to claim 1, characterized in that: The semiconductor device is a depletion-type HEMT device or an enhancement-type HEMT device; when the semiconductor device is a depletion-type HEMT device, the gate structure includes at least a gate metal layer; when the semiconductor device is an enhancement-type HEMT device, the gate structure includes a p-type doped group III-V compound and a gate metal layer.

18. A method for fabricating a semiconductor device, characterized in that, The preparation method includes the following steps: A bottom layer structure is provided, the bottom layer structure including a semiconductor substrate layer, a channel layer located above the semiconductor substrate, and a barrier layer located on the upper surface of the channel layer; wherein, a 2DEG is formed at the contact surface between the channel layer and the barrier layer; A gate structure is formed above the upper surface of a predetermined region of the barrier layer; A patterned sacrificial layer is formed; wherein the patterned sacrificial layer covers a portion of the upper surface of the barrier layer and the surface of the gate structure, so as to expose at least a portion of the upper surface of the barrier layer outside the gate structure; A source structure and a drain structure are formed, wherein the source structure and the drain structure extend at least into the interior of the underlying structure, and the source structure and the drain structure are located on opposite sides of the gate structure, and neither of them is in contact with the gate structure; Based on the patterned sacrificial layer, at least one electronic conditioning layer is formed on the exposed surface of the barrier layer between the gate structure and the drain structure; wherein the conditioning electronic layer is configured as a group III-V compound, and the electronic conditioning layer closest to the drain structure is disposed in a non-contact manner with the drain structure, and the electronic conditioning layer closest to the gate structure is disposed in a non-contact manner with the gate structure.

19. The method for fabricating a semiconductor device according to claim 18, characterized in that, The method for forming the patterned sacrificial layer includes: A sacrificial layer is formed above the barrier layer and the gate structure; The sacrificial layer in the predetermined area is etched to form the patterned sacrificial layer.

20. The method for fabricating a semiconductor device according to claim 18, characterized in that: The process of forming the electronic conditioning layer also includes the step of removing the patterned sacrificial layer.

21. The method for fabricating a semiconductor device according to claim 20, characterized in that: After removing the patterned sacrificial layer and before forming the source structure and the drain structure, an insulating layer is also formed; wherein the insulating layer is located on a portion of the upper surface of the barrier layer and the upper surface of the electronic conditioning layer, and covers the gate structure.

22. The method for fabricating a semiconductor device according to claim 21, characterized in that: The insulating layer covering the gate structure and the electronic modulation layer is formed using the same process under the same process conditions.

23. The method for fabricating a semiconductor device according to claim 21, characterized in that: The insulating layer is formed using the same process under the same technological conditions.

24. The method for fabricating a semiconductor device according to claim 20, characterized in that: After removing the patterned sacrificial layer, an interface repair layer is formed; wherein the interface repair layer is located on the upper surface of a portion of the barrier layer and covers the exposed outer surfaces of the gate structure and all of the electronic conditioning layers.

25. The method for fabricating a semiconductor device according to claim 24, characterized in that: The interface repair layer is formed using atomic layer deposition (ALD) technology.

26. The method for fabricating a semiconductor device according to claim 24, characterized in that: The material of the interface repair layer includes at least one of aluminum nitride, aluminum oxide, hafnium dioxide, yttrium oxide, lanthanum oxide, and silicon nitride.

27. The method for fabricating a semiconductor device according to claim 21, characterized in that: The process temperature for forming the electronic conditioning layer is higher than the process temperature for forming the insulating layer.

28. The method for fabricating a semiconductor device according to claim 18, characterized in that: The source structure and the drain structure are ohmic contact source structures and ohmic contact drain structures.

29. The method for fabricating a semiconductor device according to claim 28, characterized in that, The method of forming the source structure and the drain structure includes: Contact holes are formed on both sides of the gate structure, and the contact holes extend at least to the barrier layer; The contact hole is filled with metal and annealed to form an ohmic contact.

30. The method for fabricating a semiconductor device according to claim 18, characterized in that, The method of forming the gate structure includes: A p-type doped group III-V compound is formed on the upper surface of the preset region; A gate metal layer is formed on the upper surface of the p-type doped group III-V compound.

31. The preparation method according to claim 18, characterized in that, The method of forming the gate structure includes: A gate metal layer is formed on the upper surface of the preset area.

32. The preparation method according to claim 18, characterized in that, The method of forming the gate structure includes: A gate dielectric layer is formed on the upper surface of the preset region; The gate metal layer is formed on the gate dielectric layer.

33. The method for fabricating a semiconductor device according to claim 18, characterized in that: At least one electronic conditioning layer is also formed between the gate structure and the source structure.

34. The method for fabricating a semiconductor device according to claim 33, characterized in that: The electron conditioning layer closest to the source structure is disposed in a non-contact manner with the source structure.

35. The method for fabricating a semiconductor device according to claim 18, characterized in that: The material of the electronic conditioning layer includes at least one of AlN, AlGaN, GaN, InGaN, InAlGaN, and InAlGaAs.

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