Semiconductor element and manufacturing method thereof
By setting a heavily doped region with a depth greater than that of the gate structure in the trench gate MOSFET and forming wells and heavily doped regions with different conductivity types, the problem of electric field accumulation in the gate structure is solved, thereby improving the reliability and switching characteristics of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HON YOUNG SEMICON CORP
- Filing Date
- 2024-10-18
- Publication Date
- 2026-04-21
AI Technical Summary
The gate structure of a trench gate MOSFET can accumulate a large electric field, which can reduce the device's breakdown voltage and affect its reliability.
A heavily doped region is set on one side of the gate structure, and the bottom depth of the heavily doped region is greater than the bottom depth of the gate structure. During the manufacturing process, wells and heavily doped regions of different conductivity types are formed through an implantation process to reduce the accumulation of electric field at the edge of the gate oxide layer.
It improves the breakdown voltage and body diode voltage, reduces the gate-drain capacitance, improves switching characteristics and short-circuit withstand time, and reduces the gate-source capacitance.
Smart Images
Figure CN121908583A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor element and a method for manufacturing the same. Background Technology
[0002] Metal oxide semiconductor field effect transistors (MOSFETs) are widely used in electronic devices due to their advantages such as fast switching speed, good high-frequency characteristics, high input impedance, and low drive power.
[0003] Generally, the on-state resistance of a MOSFET is a crucial parameter affecting its power consumption. MOSFETs with trench gate structures can help reduce on-resistance, shrink device size, and increase chip density to reduce costs.
[0004] However, the gate structure of trench gate MOSFETs has a large electric field accumulation effect, which reduces the device's breakdown voltage and thus causes reliability issues.
[0005] Therefore, how to propose a semiconductor device and its manufacturing method that can solve the above problems is one of the issues that the industry is currently eager to invest research and development resources to address. Summary of the Invention
[0006] In view of this, one object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can solve the above problems.
[0007] One aspect of the present invention relates to a semiconductor device comprising an epitaxial layer, a current diffusion layer, a gate structure, a well, a heavily doped region, and a source electrode. The epitaxial layer has a first conductivity type. The current diffusion layer is located in the epitaxial layer and has the first conductivity type. The gate structure is located in the epitaxial layer and above the current diffusion layer. The well is located in the epitaxial layer and above the current diffusion layer, and contacts a sidewall of the gate structure. The well has a second conductivity type different from the first conductivity type. The heavily doped region is located in the epitaxial layer and has the second conductivity type. The heavily doped region contacts another sidewall of the gate structure. The bottom depth of the heavily doped region is greater than the bottom depth of the gate structure. The source electrode is located above the epitaxial layer.
[0008] Another aspect of the present invention relates to a method for manufacturing a semiconductor device, comprising: forming a current diffusion layer in an epitaxial layer, wherein the current diffusion layer and the epitaxial layer have a first conductivity type; performing a first implantation process to form a first portion of a well located in the epitaxial layer and above the current diffusion layer, wherein the first portion of the well has a second conductivity type different from the first conductivity type; performing a second implantation process to form a first heavily doped region having the second conductivity type in the epitaxial layer; removing a portion of the epitaxial layer to form a trench exposing the first portion of the well and the first heavily doped region; and forming a gate structure in the trench and contacting the first portion of the well and the first heavily doped region.
[0009] These and other aspects of the invention will become apparent from the following description of preferred embodiments taken in conjunction with the accompanying drawings, but variations and modifications may be made therein without departing from the spirit and scope of the novel concept of the invention. Attached Figure Description
[0010] The accompanying drawings illustrate one or more embodiments of the invention and, together with the written description, serve to explain the principles of the invention. Throughout the drawings, the same reference numerals are used wherever possible to refer to similar or identical elements of the embodiments, wherein:
[0011] Figures 1 to 4 This is a cross-sectional schematic diagram of an intermediate stage in a method for manufacturing a semiconductor device according to some embodiments of the present invention.
[0012] Figures 5 to 7 This is a cross-sectional schematic diagram of an intermediate stage in a method for manufacturing a semiconductor element according to other embodiments of the present invention. Detailed Implementation
[0013] The following disclosure will be described more fully with reference to the accompanying drawings and references, some of which illustrate exemplary embodiments. The invention may be embodied in different forms and should not be limited to the embodiments mentioned below. However, these embodiments are provided to aid in a more complete understanding of the invention and to fully convey the scope of the invention to those skilled in the art.
[0014] The present invention aims to reduce critical electric-field breakdown caused by the accumulation of electric field at the edge of the gate oxide layer of the gate structure by setting a heavily doped region (such as a p-type heavily doped region) with a conductivity type different from that of the epitaxial layer on one side of the gate structure and in contact with the gate structure, while making the bottom depth of the heavily doped region greater than the bottom depth of the gate structure.
[0015] Figures 1 to 4 These are cross-sectional schematic diagrams of intermediate stages in the manufacturing method of a semiconductor element 10 according to some embodiments of the present invention.
[0016] First, please refer to Figure 1 A substrate structure 100 is provided. The substrate structure 100 includes a substrate 101 and an epitaxial layer 110. The epitaxial layer 110 is located above the substrate 101. In some embodiments, the substrate 101 and the epitaxial layer 110 have a first conductivity type. For example, the substrate 101 and the epitaxial layer 110 are n-type semiconductor layers. The epitaxial layer 110 may be formed as a drift region of the semiconductor device 10.
[0017] Next, a current spreading layer 120 is formed in the epitaxial layer 110. The current spreading layer 120 has a first conductivity type (n-type). In some embodiments, the dopant concentration of the current spreading layer 120 is lower than the dopant concentration of the epitaxial layer 110. For example, the dopant concentration of the epitaxial layer 110 is 10. 15 # / cm 3 With 5×10 16 # / cm 3 Between, while the doping concentration of the current diffusion layer 120 is between 10 11 # / cm 3 With 10 13 # / cm 3 between.
[0018] Next, an implantation process is performed to form multiple spaced wells 130 at locations 132 in the epitaxial layer 110 and above the current diffusion layer 120, as shown below. Figure 1 As shown in the image. It is worth noting that in... Figures 1 to 4 In the corresponding implementation, the trap 130 only includes part 132, so in the following paragraphs, the trap 130 will be used directly for feature description.
[0019] Well 130 has a second conductivity type different from the first conductivity type. For example, well 130 is a p-type semiconductor layer. In some embodiments, the doping concentration of well 130 is 10. 11 # / cm 3 With 10 14 # / cm 3 between.
[0020] Next, please refer to Figure 2An implantation process is performed to form a lightly doped region 140 with a first conductivity type (n-type) in the epitaxial layer 110 and adjacent to the well 130. In some embodiments, the bottom depth of the lightly doped region 140 is less than the bottom depth of the well 130. In some embodiments, the dopant concentration of the lightly doped region 140 is less than the dopant concentration of the epitaxial layer 110. For example, the dopant concentration of the lightly doped region 140 is less than 10. 15 # / cm 3 .
[0021] Next, the implantation process is performed again to form a heavily doped region 150 with a first conductivity type (n-type) in the epitaxial layer 110 and adjacent to the lightly doped region 140. For example... Figure 2 As shown, the heavily doped region 150 is located on the side of the lightly doped region 140 away from the epitaxial layer 110. In some embodiments, the bottom depth of the heavily doped region 150 is substantially equal to the bottom depth of the lightly doped region 140. In some embodiments, the dopant concentration of the heavily doped region 150 is greater than the dopant concentration of the lightly doped region 140. For example, the dopant concentration of the heavily doped region 150 is 10. 19 # / cm 3 With 10 21 # / cm 3 between.
[0022] Next, please refer to Figure 3 An implantation process is performed to form a heavily doped region 160 with a second conductivity type (p-type) in the epitaxial layer 110. For example... Figure 3 As shown, the heavily doped region 160 is adjacent to the heavily doped region 150 and located on the side of the heavily doped region 150 away from the lightly doped region 140. In some embodiments, the bottom depth of the heavily doped region 160 is greater than the bottom depth of the well 130. In some embodiments, the heavily doped region 160 extends into the current diffusion layer 120. In other words, the heavily doped region 160 extends downward from the well 130 through the epitaxial layer 110 into the current diffusion layer 120. In some embodiments, the distance D1 between the bottom and top surfaces of the heavily doped region 160 (i.e., the bottom depth of the heavily doped region 160 relative to the top surface of the epitaxial layer 110) is greater than 1 micrometer. In some embodiments, the dopant concentration of the heavily doped region 160 is greater than the dopant concentration of the well 130. For example, the dopant concentration of the heavily doped region 160 is 10. 19 # / cm 3 With 10 21 # / cm 3 between.
[0023] Next, a portion of the epitaxial layer 110 is removed using a hard mask 200 to form trenches T between the wells 130. Specifically, to be located in Figure 3 Taking the trench T in the middle as an example, the trench T is located between portion 132-1 and portion 132-2 of the well 130. One side of the trench T exposes the side of portion 132-1 and the side of the lightly doped region 140 located in portion 132-1, while the other side exposes the side of the heavily doped region 160 located in portion 132-2. In some embodiments, the bottom depth of the trench T is substantially equal to the bottom depth of the well 130. In some embodiments, the hard mask 200 comprises silicon dioxide.
[0024] Next, please refer to Figure 4 A gate structure 170 is formed in the trench T. For example... Figure 4 As shown, the gate structure 170 includes a gate oxide layer 172, a gate electrode 174, and a dielectric layer 176. In some embodiments, forming the gate structure 170 includes the following steps: First, conformally depositing an oxide material in the trench T and on the top surfaces of the lightly doped region 140, the heavily doped region 150, and the heavily doped region 160. Next, depositing an electrode material to further fill the trench T and completely cover the oxide material. Then, performing a planarization process, such as chemical mechanical polishing / planarization (CMP), to remove multiple portions of the oxide material and electrode material to re-expose the top surfaces of the lightly doped region 140, the heavily doped region 150, and the heavily doped region 160, and forming... Figure 4 The gate oxide layer 172 and gate electrode 174 are shown. Next, a dielectric material is deposited covering the lightly doped region 140, heavily doped region 150, heavily doped region 160, gate oxide layer 172, and gate electrode 174. Then, multiple portions of the dielectric material are removed to at least partially expose the top surfaces of the heavily doped regions 150 and 160, forming... Figure 4 The dielectric layer 176 is shown. In some embodiments, the gate oxide layer 172 and the dielectric layer 176 may include, for example, silicon dioxide. The gate electrode 174 may include a polysilicon gate or a conductive metal.
[0025] Next, a source electrode 180 is formed to contact the exposed heavily doped regions 150 and 160 and is electrically connected to the well 130. Simultaneously, a drain electrode 190 is formed beneath the substrate 101, as shown below. Figure 4 As shown in the diagram, the source electrode 180 and drain electrode 190 comprise conductive metal.
[0026] In this way, a plurality of periodically arranged and interconnected semiconductor elements 10 can be formed by the aforementioned manufacturing method. The structure of a single semiconductor element 10, as shown in the box, is a vertical MOSFET with a trench gate structure. It is worth noting that the box divides the heavily doped region 160 into portions 162 and 164. Furthermore, each semiconductor element 10 is located between two adjacent heavily doped regions 160 and includes portion 162 of one heavily doped region 160 and portion 164 of the other heavily doped region 160.
[0027] In detail, the semiconductor device 10 includes a substrate 101, an epitaxial layer 110, a current diffusion layer 120, a well 130, lightly doped regions 140, heavily doped regions 150, portions 162 and 164 of heavily doped regions 160, a gate structure 170, a source electrode 180, and a drain electrode 190. As previously described, the substrate 101, epitaxial layer 110, current diffusion layer 120, lightly doped regions 140, and heavily doped regions 150 have a first conductivity type (n-type), while the well 130, portions 162, and 164 have a second conductivity type (p-type).
[0028] Epitaxial layer 110 is located above substrate 101. Current diffusion layer 120 is located within epitaxial layer 110. Well 130, lightly doped region 140, and heavily doped region 150 are located within epitaxial layer 110 and above current diffusion layer 120. Locations 162 and 164 of heavily doped region 160 are located within epitaxial layer 110. Heavily doped region 150 is located between location 164 of lightly doped region 140 and heavily doped region 160.
[0029] The gate structure 170 is located in the epitaxial layer 110 and above the current diffusion layer 120. For example... Figure 4 As shown in the box, the gate structure 170 is located between portions 132-1 and 132-2 of the well 130. Specifically, the gate structure 170 is disposed between the heavily doped region 150 in portion 132-1 of the well 130 and portion 162 of the heavily doped region 160 in portion 132-2 of the well 130. The lightly doped region 140 is located between the heavily doped region 150 and the gate structure 170. The lightly doped region 140 and portion 132-1 of the well 130 contact one sidewall of the gate structure 170, and portion 162 of the heavily doped region 160 contacts the other sidewall of the gate structure 170. The source electrode 180 is located above the epitaxial layer 110, on one side of the dielectric layer 176 of the gate structure 170, and contacts portion 164 of the heavily doped regions 150 and 160. It is worth noting that the source electrode 180 does not contact the lightly doped region 140. The drain electrode 190 is located below the substrate 101.
[0030] It is worth noting that the heavily doped region 150 with the first conductivity type (n-type) and the source electrode 180 of the semiconductor element 10 are only disposed on one side of the gate structure 170, thus reducing the cell pitch and helping to reduce the gate-drain capacitance. gd This reduces heat dissipation and improves switching characteristics.
[0031] Furthermore, the bottom depths of portions 162 and 164 of the heavily doped region 160 are greater than the bottom depths of the well 130 and the gate structure 170. Specifically, the distance D1 between the bottom and top surfaces of portions 162 and 164 is greater than 1 micrometer. By providing portions 162 and 164 with a depth greater than 1 micrometer and having a second conductivity type (p-type), and by having portion 162 contact the sidewall of the gate structure 170, the electric field accumulation at the edge of the gate oxide layer 172 can be reduced, thereby improving the breakdown voltage and the body diode voltage (V). sd In some embodiments, portions 162 and 164 may also extend into the current diffusion layer 120. It is worth noting that portion 162 does not extend below the gate structure 170, nor does it contact the bottom surface of the gate structure 170.
[0032] Simultaneously, placing a lightly doped region 140 with a first conductivity type (n-type) between the heavily doped region 150 and the gate structure 170 helps reduce charge accumulation in the channel region, thus reducing the probability of short circuits by increasing the short circuit withstand time (SCWT). Furthermore, the lightly doped region 140 also helps reduce the gate-source capacitance (C). gs ).
[0033] Figures 5 to 7 These are schematic cross-sectional views of intermediate stages in the manufacturing method of a semiconductor element 20 according to other embodiments of the present invention.
[0034] In these implementations, upon completion Figure 1 After the intermediate structure is formed, an implantation process is performed to form a portion 134 of a well 130 with a second conductivity type (p-type) in the epitaxial layer 110, above the current diffusion layer 120 and adjacent to portion 132, such as... Figure 5 As shown in the image. It is worth noting that in... Figures 5 to 7 In the corresponding implementation, the trap 130 includes part 132 and part 134, and therefore, in the following paragraphs, part 132 and part 134 will be used to describe its features respectively.
[0035] Location 134 has the same conductivity type and dopant concentration as location 132. In some embodiments, the bottom depth of location 134 may be greater than, substantially equal to or less than the bottom depth of location 132, but the invention is not limited thereto.
[0036] Next, the implantation process is performed again to form a heavily doped region 150 with a first conductivity type (n-type) in the epitaxial layer 110 and adjacent to the well 130. In some embodiments, the bottom depth of the heavily doped region 150 is less than the bottom depth of the portion 132 and less than the top depth of the portion 134. In some embodiments, the dopant concentration of the heavily doped region 150 is greater than the dopant concentration of the epitaxial layer 110. For example, the dopant concentration of the heavily doped region 150 is 10. 19 # / cm 3 With 10 21 # / cm 3 between.
[0037] Next, please refer to Figure 6 An implantation process is performed to form a heavily doped region 160 with a second conductivity type (p-type) in the epitaxial layer 110 and adjacent to the heavily doped region 150. In some embodiments, the bottom depth of the heavily doped region 160 is substantially equal to the bottom depth of the well 130. In some embodiments, the distance D2 between the bottom and top surfaces of the heavily doped region 160 (i.e., the bottom depth of the heavily doped region 160 relative to the top surface of the epitaxial layer 110) is greater than 1 micrometer. In some embodiments, the dopant concentration of the heavily doped region 160 is greater than the dopant concentration of the well 130. For example, the dopant concentration of the heavily doped region 160 is 10... 19 # / cm 3 With 10 21 # / cm 3 between.
[0038] Next, a portion of the epitaxial layer 110 is removed using a hard mask 200 to form trenches T between the wells 130. Specifically, to be located in Figure 6 Taking the trench T in the middle as an example, the trench T is located between portion 132-1 and portion 132-2 of the well 130. One side of the trench T exposes the side of portion 132-1 and the side of the heavily doped region 150 located in portion 132-1, and the other side exposes the side of the heavily doped region 160 located in portion 132-2. The bottom surface of the trench T exposes the top surface of portion 134. In some embodiments, the depth of the bottom surface of the trench T is substantially equal to the depth of the top surface of portion 134 and less than the depth of the bottom surfaces of portions 132, 134, and the heavily doped region 160.
[0039] Next, please refer to Figure 7Similar to the manufacturing method of semiconductor element 10, a gate structure 170 is formed in trench T. The gate structure 170 includes a gate oxide layer 172, a gate electrode 174, and a dielectric layer 176. Next, a source electrode 180 is formed, contacting heavily doped regions 150 and 160 through the dielectric layer 176, and electrically connected to the well 130. Simultaneously, a drain electrode 190 is formed beneath the substrate 101, as shown below... Figure 7 As shown in the image.
[0040] In this way, multiple semiconductor elements 20 arranged periodically and connected can be formed by the aforementioned manufacturing method. The structure of a single semiconductor element 20 is shown in the box. In detail, the semiconductor element 20 includes a substrate 101, an epitaxial layer 110, a current diffusion layer 120, portions 132 and 134 of a well 130, a heavily doped region 150, portions 162 and 164 of a heavily doped region 160, a gate structure 170, a source electrode 180, and a drain electrode 190.
[0041] An epitaxial layer 110 is located above the substrate 101. A current diffusion layer 120 is located within the epitaxial layer 110. Locations 132 and 134 of the well 130, the heavily doped region 150, and locations 162 and 164 of the heavily doped region 160 are located within the epitaxial layer 110 and above the current diffusion layer 120. A gate structure 170 is located within the epitaxial layer 110 and above the current diffusion layer 120. The heavily doped region 150 and location 132 of the well 130 are in contact with one sidewall of the gate structure 170, location 162 of the heavily doped region 160 is in contact with the other sidewall of the gate structure 170, and location 134 of the well 130 is located below the gate structure 170 with its top surface in contact with the bottom surface of the gate structure 170. It is worth noting that the portion 134 of the well 130 is separated from the portion 162 of the heavily doped region 160, so the epitaxial layer 110 can extend between portions 134 and 162 and contact the bottom surface of the gate structure 170. The source electrode 180 is located above the epitaxial layer 110, on one side of the dielectric layer 176 of the gate structure 170, and contacts the heavily doped region 150 and portion 164. The drain electrode 190 is located below the substrate 101.
[0042] Similarly, the semiconductor element 20 has a first conductivity type (n-type) heavily doped region 150 and a source electrode 180 disposed only on one side of the gate structure 170, which can reduce the cell spacing, which is beneficial to reduce the gate-drain capacitance, reduce heat dissipation, and improve switching characteristics.
[0043] Furthermore, the bottom depths of portions 162 and 164 of the heavily doped region 160 are substantially equal to the bottom depth of the well 130 and greater than the bottom depth of the gate structure 170. In some embodiments, the distance D2 between the bottom and top surfaces of portions 162 and 164 of the heavily doped region 160 is greater than 1 micrometer. By providing portions 162 and 164 with a depth greater than 1 micrometer and having a second conductivity type (p-type), and by having portion 162 contact the sidewall of the gate structure 170, the electric field accumulation at the edge of the gate oxide layer 172 can be reduced, thereby improving the breakdown voltage and the body diode voltage. Simultaneously, by providing portion 134 of the well 130 in contact with the bottom surface of the gate structure 170, such that portions 132 and 134 of the well 130 together cover the corner point of the gate structure 170 away from portion 162, it helps to further reduce electric field accumulation and lower the gate-drain capacitance.
[0044] [Symbol Explanation]
[0045] 10,20: Semiconductor components
[0046] 100: Substrate Structure
[0047] 101: Substrate
[0048] 110: Epitaxial layer
[0049] 120: Current diffusion layer
[0050] 130: Trap
[0051] 132, 132-1, 132-2, 134, 162, 164: Location
[0052] 140: Lightly doped region
[0053] 150, 160: Heavily doped regions
[0054] 170: Gate structure
[0055] 172: Gate oxide layer
[0056] 174: Gate electrode
[0057] 176: Dielectric layer
[0058] 180: Source electrode
[0059] 190: Drain electrode
[0060] 200: Hard mask
[0061] D1, D2: Distance
[0062] T: Groove.
Claims
1. A semiconductor element, characterized in that, Include: The epitaxial layer has a first conductivity type; A current diffusion layer is located in the epitaxial layer and has the first conductivity type; A gate structure is located in the epitaxial layer and above the current diffusion layer; A well, located in the epitaxial layer and above the current diffusion layer, and in contact with a sidewall of the gate structure, wherein the well has a second conductivity type different from the first conductivity type; A heavily doped region, located in the epitaxial layer and having the second conductivity type, wherein the heavily doped region contacts another sidewall of the gate structure, and the bottom depth of the heavily doped region is greater than the bottom depth of the gate structure; and The source electrode is located above the epitaxial layer.
2. The semiconductor device according to claim 1, characterized in that, The bottom depth of the heavily doped region is greater than the bottom depth of the well, and the heavily doped region extends into the current diffusion layer.
3. The semiconductor device according to claim 1, characterized in that, The bottom depth of the heavily doped region is substantially equal to the bottom depth of the well.
4. The semiconductor device according to claim 1, characterized in that, The well has a first portion and a second portion, wherein the first portion contacts the sidewall of the gate structure, and the second portion is located below the gate structure and contacts the bottom surface of the gate structure.
5. The semiconductor device according to claim 1, characterized in that, It also includes a lightly doped region located in the epitaxial layer, adjacent to the well, and in contact with the sidewall of the gate structure.
6. A method for manufacturing a semiconductor device, characterized in that, Include: A current diffusion layer is formed in the epitaxial layer, wherein the current diffusion layer and the epitaxial layer have a first conductivity type; A first implantation process is performed to form a first portion of a well located in the epitaxial layer and above the current diffusion layer, wherein the first portion of the well has a second conductivity type different from the first conductivity type; A second implantation process is performed to form a first heavily doped region having the second conductivity type in the epitaxial layer; A portion of the epitaxial layer is removed to form a trench that exposes the first portion of the well and the first heavily doped region; as well as A gate structure is formed in the trench and contacts the first portion of the well and the first heavily doped region.
7. The manufacturing method according to claim 6, characterized in that, Also includes: A third implantation process is performed to form a second heavily doped region having the first conductivity type in the epitaxial layer and adjacent to the well. The gate structure is formed such that it is located between the first heavily doped region and the second heavily doped region.
8. The manufacturing method according to claim 7, characterized in that, Also includes: A fourth implantation process is performed to form a lightly doped region with the first conductivity type in the epitaxial layer and adjacent to the second heavily doped region. The trench is formed such that it also exposes the lightly doped region, and the gate structure is formed such that the gate structure contacts the lightly doped region.
9. The manufacturing method according to claim 6 or 7, characterized in that, It also includes performing a fifth implantation process to form a second portion of the well located in the epitaxial layer, above the current diffusion layer, and adjacent to the first portion of the well, wherein the second portion of the well has the second conductivity type.
10. The manufacturing method according to claim 9, characterized in that, The trench is formed such that the trench also exposes the top surface of the second portion of the well, and the gate structure is formed such that the gate structure contacts the top surface of the second portion of the well.