Silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device for reducing short channel effect and preparation method thereof

Abstract

The invention relates to a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device for reducing a short channel effect and a preparation method thereof. The device comprises an N-type substrate serving as an N-type drain electrode; the N-type epitaxial layer is located on the upper surface of the N-type substrate; the current guide layer is located on the upper surface of the N-type epitaxial layer; the P-type well regions are arranged on the upper surface of the current guiding layer at intervals; the N + source region is positioned in regions on two sides of the center of the surface of the P-type well region; the P + source region is arranged in the middle of the P-type well region and is used for being in metal contact with a source electrode; the P-type buried layer is located at the bottom of the P-type well region; the P-type shielding regions are located on the two sides of the bottom of the P-type well region; a gate oxide layer; the polycrystalline silicon gate is positioned on the upper surface of the gate oxide layer; the source electrode metal is in ohmic contact with the N + source region and the P + source region respectively; and the drain electrode metal is located on the lower surface of the N-type substrate, and the drain electrode metal and the N-type substrate form ohmic contact. According to the invention, the short-channel effect can be weakened, the device size is reduced, the channel density is improved, and the manufacturing cost of the device is reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a silicon carbide MOSFET device with reduced short-channel effect and its fabrication method. Background Technology

[0002] Silicon carbide (SiC), as a third-generation semiconductor material, has advantages over existing silicon materials, such as a wider bandgap, higher critical breakdown electric field, and higher saturation drift velocity. MOSFET devices made of SiC material have advantages over silicon-based MOSFETs of the same voltage rating, such as lower on-resistance, smaller size, and faster switching speed.

[0003] As power electronic systems evolve towards miniaturization and higher frequencies, higher demands are placed on the integration density and switching speed of silicon carbide MOSFETs, leading to a continuous reduction in device feature size. However, when the device channel length shrinks to the submicron level, the short-channel effect (SCE) intensifies significantly, becoming a key bottleneck restricting the performance improvement of silicon carbide MOSFETs. The short-channel effect mainly manifests as threshold voltage roll-off, drain-induced barrier reduction (DIBL), subthreshold swing degradation, and increased output conductance. These problems lead to deterioration of device switching characteristics, increased static power consumption, and severely affect the device's operational stability and reliability.

[0004] In existing technologies, methods to reduce short-channel effects mainly include using heavily doped P-type well regions, introducing buried layer structures, or optimizing the gate structure. However, heavily doped P-type well regions lead to decreased channel mobility, increased threshold voltage, and sacrifice of device conduction performance; traditional buried layer structure fabrication processes are complex, increasing device manufacturing costs; and simple optimization of the gate structure has limited effect on suppressing short-channel effects, making it difficult to meet the application requirements of high-performance silicon carbide devices.

[0005] Therefore, developing a silicon carbide device structure that has good process compatibility, can effectively suppress short-channel effects, and does not significantly sacrifice other device performance is of great significance for promoting the miniaturization and high performance of silicon carbide power devices. Summary of the Invention

[0006] Therefore, the present invention provides a silicon carbide MOSFET device and its fabrication method for reducing short-channel effect, which can weaken short-channel effect, reduce device size, increase channel density and reduce device manufacturing cost.

[0007] To address the aforementioned technical problems, this invention provides a silicon carbide MOSFET device for reducing short-channel effects, comprising: An N-type substrate is used as the N-type drain. An N-type epitaxial layer is located on the upper surface of the N-type substrate, and the N-type epitaxial layer and the substrate form a longitudinal conductive channel; A current guiding layer is located on the upper surface of the N-type epitaxial layer; P-type well regions are spaced apart on the upper surface of the current guiding layer; The N+ source region is located on both sides of the center of the surface of the P-type well region, and the N+ source region and the P-type well region form a PN junction; A P+ source region is disposed in the middle of the P-type well region and is used to contact the source metal, so that the potential of the P-type well region is consistent with that of the source metal. The P-type buried layer is located at the bottom of the P-type trap area; The P-type shielding region is located on both sides of the bottom of the P-type well region, and the P-type shielding region is formed by oblique doping implantation. A gate oxide layer covering the upper surface of the N-type epitaxial layer and the upper boundary of the P-type well region; A polysilicon gate is located on the upper surface of the gate oxide layer, and the polysilicon gate and the gate oxide layer together form a MOS capacitor structure. The source metal is in ohmic contact with the N+ source region and the P+ source region, respectively. The drain metal is located on the lower surface of the N-type substrate, and the drain metal forms an ohmic contact with the N-type substrate.

[0008] This invention also provides a method for fabricating a silicon carbide MOSFET device to reduce short-channel effects, comprising: Step 1: Provide a high-concentration N-type substrate as an N-type drain, and epitaxially grow a low-concentration N-type epitaxial layer; Step 2: Phosphorus or nitrogen is implanted into the surface of the N-type epitaxial layer to form an N+ source region, and aluminum is implanted into the surface of the N-type epitaxial layer to form a P-type buried layer. Step 3: On the surface of the N-type epitaxial layer, aluminum ions are implanted by sidewall oblique ion implantation or without sidewall oblique ion implantation to form a P-type well region. At the same time, aluminum ions are implanted by sidewall oblique ion implantation on both sides of the bottom of the P-type well region to form a highly doped P-type shielding region. Step 4: Aluminum ions are injected into the center of the P-type well region to form a P+ source region; Step 5: A gate oxide layer is grown on the surface of the P-type well region and the N-type epitaxial layer, and a polysilicon gate is deposited on top of the gate oxide layer; Step 6: Deposit an insulating dielectric layer on the polysilicon gate, etch to form contact holes, deposit and selectively etch metal to form source metal, the source metal makes ohmic contact with the N+ source region and P+ source region respectively, and deposit drain metal on the back side of the wafer, the drain metal makes ohmic contact with the N-type substrate.

[0009] In one embodiment of the present invention, the N-type substrate is 4H-SiC, and the doping concentration of the N-type substrate is 1×10⁻⁶. 18 ~5×10 19 cm -3 ; The N-type epitaxial layer was fabricated using 4H-SiC epitaxial growth, with a thickness of 8 μm to 12 μm and a doping concentration of 5 × 10⁻⁶. 15 ~2×10 16 cm -3 .

[0010] In one embodiment of the present invention, the ion doping concentration of the N+ source region is 1×10⁻⁶. 19 ~1×10 20 cm -3 The depth is 0.2μm~0.4μm.

[0011] In one embodiment of the present invention, the gate oxide layer is a thermally grown silicon dioxide layer with a thickness of 30nm~70nm.

[0012] In one embodiment of the present invention, in step one, the surface of the N-type epitaxial layer is N-type doped, and a current guiding layer is formed by ion implantation.

[0013] In one embodiment of the present invention, in step three, a pattern is formed using a photomask or a hard mask, and then an N+ source region and a P-type buried layer are formed by ion implantation.

[0014] In one embodiment of the present invention, in step three, a pattern is formed using a photolithographic mask or a hard mask, then a sidewall structure is formed by etching, and then an N+ source region and a P-type buried layer are formed by ion implantation.

[0015] In one embodiment of the present invention, a P-type well region and a P-type shield region are formed by oblique ion implantation on the sidewalls, with the oblique angle ranging from 10° to 45° of the reference normal.

[0016] In one embodiment of the present invention, in step four, a pattern is formed using a photomask or a hard mask, and then a P+ source region is formed by ion implantation. After completion, impurity annealing is performed to activate the doped impurities.

[0017] The technical solution of the present invention has the following advantages compared with the prior art: (1) The present invention forms a P-type well region by oblique injection, which can make the two ends of the P-type well region deeply doped P-region, i.e. P-type shielding region. A P-type buried layer can also be formed by high-energy doping. The electric field at the channel can be reduced and the short-channel effect can be weakened by the designed P-type shielding region and P-type buried layer.

[0018] (2) Existing devices control the spacing between P-type well regions by the size of the photomask, so they are affected by the process technology and the spacing between P-type well regions cannot be further reduced. The present invention forms P-type well regions by directly injecting at an angle after the N+ source region is formed, which can further reduce the device size, increase the channel density, reduce the on-resistance of the device, and optimize the on-loss.

[0019] (3) The present invention can also reduce the number of photomasks for injection to form the P-type well region, thereby reducing the manufacturing cost of the device. Attached Figure Description

[0020] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0021] Figure 1 This is a schematic diagram of the silicon carbide MOSFET device for reducing short-channel effect according to Embodiment 1 of the present invention.

[0022] Figure 2 This is a schematic diagram of growing an N-type epitaxial layer on an N-type substrate according to Embodiment 2 of the present invention.

[0023] Figure 3 This is a schematic diagram of the injection-formed current guiding layer in Embodiment 2 of the present invention.

[0024] Figure 4(a) is a schematic diagram of the formation of the N+ source region and the P-type buried layer in Embodiment 2 of the present invention. Figure 1 .

[0025] Figure 4(b) is a schematic diagram of the formation of the N+ source region and the P-type buried layer in Embodiment 2 of the present invention. Figure 2 .

[0026] Figure 5(a) is a schematic diagram of the formation of an N+ source region and a P-type buried layer by oblique angle ion implantation in Embodiment 2 of the present invention. Figure 1 .

[0027] Figure 5(b) is a schematic diagram of the formation of an N+ source region and a P-type buried layer by oblique angle ion implantation in Embodiment 2 of the present invention. Figure 2 .

[0028] Figure 6 This is a schematic diagram of the P+ source region formation by injection in Embodiment 2 of the present invention.

[0029] Figure 7 This is a schematic diagram of the growth of the gate oxide layer and the deposition of gate polysilicon on the gate oxide layer in Embodiment 2 of the present invention.

[0030] Figure 8 This is a schematic diagram of the formation of contact holes in the etching medium layer in Embodiment 2 of the present invention.

[0031] Figure 9 This is a schematic diagram of the formation of a silicon carbide MOSFET device according to Embodiment 2 of the present invention.

[0032] Explanation of reference numerals on the accompanying drawings: 01. N-type substrate; 02. N-type epitaxial layer; 03. Current guiding layer; 04. P-type well region; 05. N+ source region; 06. P+ source region; 07. Polysilicon gate; 08. Dielectric layer; 09. Source Metal; 10. P-type burial layer; 11. P-type shielding area; 12. Side wall structure; 14. Drain metal. Detailed Implementation

[0033] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0034] In this invention, when directions (up, down, left, right, front, and back) are described, it is only for the convenience of describing the technical solution of this invention, and does not indicate or imply that the technical features referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this invention.

[0035] In this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," "exceeding," etc., are understood to exclude the stated number; "above," "below," "within," etc., are understood to include the stated number. In the description of this invention, the terms "first" and "second" are used only to distinguish technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0036] In this invention, unless otherwise explicitly defined, the terms "setting," "installing," and "connecting" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium; a fixed connection, a detachable connection, or an integrally formed connection; a mechanical connection, an electrical connection, or a connection capable of mutual communication; or the internal connection of two components or the interaction between two components. Those skilled in the art can reasonably determine the specific meaning of the above terms in this invention based on the specific content of the technical solution.

[0037] Example 1 Reference Figure 1 As shown, a silicon carbide MOSFET device for reducing short-channel effect according to this embodiment includes: N-type substrate 01 serves as the N-type drain. The N-type epitaxial layer 02 is located on the upper surface of the N-type substrate 01, and the N-type epitaxial layer 02 and the substrate form a longitudinal conductive channel; The current guiding layer 03 is located on the upper surface of the N-type epitaxial layer 02; P-type well regions 04 are spaced apart on the upper surface of the current guiding layer 03; N+ source region 05 is located in the region on both sides of the center of the surface of the P-type well region 04, and the N+ source region 05 and the P-type well region 04 form a PN junction; P+ source region 06 is disposed in the middle of the P-type well region 04 and is used to contact the source metal 09, so that the potential of the P-type well region 04 and the source metal 09 are consistent. P-type buried layer 10 is located at the bottom of the P-type trap area 04; P-type shielding region 11 is located on both sides of the bottom of the P-type well region 04. The P-type shielding region 11 is formed by oblique doping implantation. A gate oxide layer covering the upper surface of the N-type epitaxial layer 02 and the upper boundary of the P-type well region 04; A polysilicon gate 07 is located on the upper surface of the gate oxide layer, and the polysilicon gate 07 and the gate oxide layer constitute a MOS capacitor structure. Source metal 09 is in ohmic contact with the N+ source region 05 and the P+ source region 06, respectively. Drain metal 14 is located on the lower surface of the N-type substrate 01, and the drain metal 14 forms an ohmic contact with the N-type substrate 01.

[0038] Example 2 Reference Figures 2 to 9 As shown, this embodiment provides a method for fabricating the silicon carbide MOSFET device with reduced short-channel effect, including: Step 1: Provide a high-concentration N-type substrate 01 as the N-type drain, and epitaxially grow a low-concentration N-type epitaxial layer 02; (Refer to...) Figure 2 As shown; Step 2: Phosphorus or nitrogen is implanted into the surface of the N-type epitaxial layer 02 to form an N+ source region 05, and aluminum is implanted into the surface of the N-type epitaxial layer 02 to form a P-type buried layer 10. Step 3: On the surface of the N-type epitaxial layer 02, aluminum ions are implanted by sidewall oblique ion implantation or without sidewall oblique ion implantation to form a P-type well region 04. At the same time, aluminum ions are implanted by sidewall oblique ion implantation on both sides of the bottom of the P-type well region 04 to form a highly doped P-type shielding region 11; see Figure 4(a). Step 4: Aluminum ions are injected into the middle of the P-type well region 04 to form the P+ source region 06; Step 5: A gate oxide layer is grown on the surface of the P-type well region 04 and the N-type epitaxial layer 02, and a polysilicon gate 07 is deposited on top of the gate oxide layer; as shown Figure 7 As shown; Step six: Deposit an insulating dielectric layer 08 on the polysilicon gate 07, and etch to form contact holes; deposit and selectively etch metal to form source metal 09, which makes ohmic contacts with the N+ source region 05 and P+ source region 06 respectively; and deposit drain metal 14 on the back side of the wafer, which makes ohmic contacts with the N-type substrate 01. Figure 9 As shown.

[0039] In one embodiment, the N-type substrate 01 is made of 4H-SiC, and the doping concentration of the N-type substrate 01 is 1×10⁻⁶. 18 ~5×10 19 cm -3 ; The N-type epitaxial layer O2 is fabricated using 4H-SiC epitaxial growth, with a thickness of 8μm~12μm and a doping concentration of 5×10⁻⁶. 15 ~2×10 16 cm -3 .

[0040] In one embodiment, the ion doping concentration of the N+ source region 05 is 1 × 10⁵. 19 ~1×10 20 cm -3 The depth is 0.2μm~0.4μm.

[0041] In one embodiment, the gate oxide layer is a thermally grown silicon dioxide layer with a thickness of 30nm~70nm.

[0042] In one embodiment, in step one, N-type doping is performed on the surface of the N-type epitaxial layer O2, and a current guiding layer O3 is formed by ion implantation. This can be achieved through nitrogen doping to enhance the device's conductivity. (Refer to...) Figure 3 As shown.

[0043] In one embodiment, as shown in FIG4(a), in step three, a pattern is formed using a photolithographic mask or a hard mask, and then an N+ source region 05 and a P-type buried layer 10 are formed by ion implantation.

[0044] In one embodiment, as shown in FIG4(b), in step three, a pattern is formed using a photomask or a hard mask, then the sidewall structure 12 is etched, and then the N+ source region 05 and the P-type buried layer 10 are formed by ion implantation.

[0045] In one embodiment, as shown in FIG5(a), based on the implementation of FIG4(a), a P-type trap region 04(4) and a P-type shield region 11(11) are formed by oblique angle ion implantation, with the oblique angle ranging from 10° to 45° of the reference normal.

[0046] As shown in Figure 5(b), based on the implementation in Figure 4(b), a P-type trap region 04(4) and a P-type shield region 11(11) are formed by oblique angle ion implantation, with the oblique angle ranging from 10° to 45° of the reference normal.

[0047] In one embodiment, such as Figure 6 As shown, in step four, a pattern is formed using a photolithography mask or a hard mask, and then a P+ source region 06 is formed by ion implantation. After completion, impurity annealing is performed to activate the doped impurities.

[0048] By forming a P-type well region 04 through oblique injection, the two ends of the P-type well region 04 can be deeply doped P-regions, namely P-type shielding regions 1111. High-energy doping can also form a P-type buried layer 10. The designed P-type shielding region 11 and P-type buried layer 10 can reduce the electric field at the channel and weaken the short-channel effect.

[0049] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A silicon carbide MOSFET device for reducing short-channel effects, characterized in that, include: N-type substrate (01) serves as N-type drain; An N-type epitaxial layer (02) is located on the upper surface of the N-type substrate (01), and the N-type epitaxial layer (02) and the substrate form a longitudinal conductive channel; A current guiding layer (03) is located on the upper surface of the N-type epitaxial layer (02); P-type well regions (04) are spaced apart on the upper surface of the current guiding layer (03); The N+ source region (05) is located in the region on both sides of the center of the surface of the P-type well region (04), and the N+ source region (05) and the P-type well region (04) form a PN junction; The P+ source region (06) is disposed in the middle of the P-type well region (04) and is used to contact the source metal (09) so that the potential of the P-type well region (04) and the source metal (09) are consistent; The P-type buried layer (10) is located at the bottom of the P-type trap area (04); The P-type shielding region (11) is located on both sides of the bottom of the P-type well region (04), and the P-type shielding region (11) is formed by oblique doping implantation; A gate oxide layer covering the upper surface of the N-type epitaxial layer (02) and the upper boundary of the P-type well region (04); A polysilicon gate (07) is located on the upper surface of the gate oxide layer, and the polysilicon gate (07) and the gate oxide layer constitute a MOS capacitor structure; The source metal (09) is in ohmic contact with the N+ source region (05) and the P+ source region (06), respectively; Drain metal (14) is located on the lower surface of the N-type substrate (01), and the drain metal (14) forms an ohmic contact with the N-type substrate (01).

2. A method for fabricating a silicon carbide MOSFET device with reduced short-channel effect, characterized in that, include: Step 1: Provide a high-concentration N-type substrate (01) as an N-type drain, and epitaxially grow a low-concentration N-type epitaxial layer (02). Step 2: Phosphorus or nitrogen is implanted into the surface of the N-type epitaxial layer (02) to form an N+ source region (05), and aluminum is implanted into the surface of the N-type epitaxial layer (02) to form a P-type buried layer (10). Step 3: Aluminum ions are implanted on the surface of the N-type epitaxial layer (02) by sidewall oblique ion implantation or non-sidewall oblique ion implantation to form a P-type well region (04). At the same time, aluminum ions are implanted on both sides of the bottom of the P-type well region (04) by sidewall oblique ion implantation to form a highly doped P-type shielding region (11). Step 4: Aluminum ions are injected into the middle of the P-type well region (04) to form a P+ source region (06). Step 5: A gate oxide layer is grown on the surface of the P-type well region (04) and the N-type epitaxial layer (02), and a polysilicon gate (07) is deposited on top of the gate oxide layer. Step 6: Deposit an insulating dielectric layer (08) on the polysilicon gate (07), etch to form a contact hole, deposit and selectively etch a metal to form a source metal (09), the source metal (09) makes ohmic contact with the N+ source region (05) and the P+ source region (06) respectively, and deposit a drain metal (14) on the back side of the wafer, the drain metal (14) makes ohmic contact with the N-type substrate (01).

3. The method for fabricating a silicon carbide MOSFET device with reduced short-channel effect according to claim 2, characterized in that, The N-type substrate (01) is made of 4H-SiC, and the doping concentration of the N-type substrate (01) is 1×10⁻⁶. 18 ~5×10 19 cm -3 ; The N-type epitaxial layer (02) is fabricated using 4H-SiC epitaxial growth, with a thickness of 8μm~12μm and a doping concentration of 5×10⁻⁶. 15 ~2×10 16 cm -3 .

4. The method for fabricating a silicon carbide MOSFET device with reduced short-channel effect according to claim 2, characterized in that, The ion doping concentration of the N+ source region (05) is 1×10⁻⁶. 19 ~1×10 20 cm -3 The depth is 0.2μm~0.4μm.

5. The method for fabricating a silicon carbide MOSFET device with reduced short-channel effect according to claim 2, characterized in that, The gate oxide layer is a thermally grown silicon dioxide layer with a thickness of 30nm~70nm.

6. The method for fabricating a silicon carbide MOSFET device with reduced short-channel effect according to claim 2, characterized in that, In step one, the surface of the N-type epitaxial layer (02) is N-type doped, and a current guiding layer (03) is formed by ion implantation.

7. The method for fabricating a silicon carbide MOSFET device with reduced short-channel effect according to claim 2, characterized in that, In step three, a pattern is formed using a photolithography mask or a hard mask, and then an N+ source region (05) and a P-type buried layer (10) are formed by ion implantation.

8. The method for fabricating a silicon carbide MOSFET device with reduced short-channel effect according to claim 2, characterized in that, In step three, a pattern is formed using a photolithography mask or a hard mask, and then the sidewall structure (12) is etched. Then, an N+ source region (05) and a P-type buried layer (10) are formed by ion implantation.

9. A method for fabricating a silicon carbide MOSFET device with reduced short-channel effect according to claim 7 or 8, characterized in that, P-type trap region (04) and P-type shield region (11) are formed by oblique ion implantation on the sidewalls, with the oblique angle ranging from 10° to 45° of the reference normal.

10. The method for fabricating a silicon carbide MOSFET device with reduced short-channel effect according to claim 2, characterized in that, In step four, a pattern is formed using a photomask or a hard mask, and then a P+ source region is formed by ion implantation (06). After completion, impurity annealing is performed to activate the doped impurities.

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