Silicon-on-insulator substrate, preparation method thereof and radio frequency silicon-on-insulator wafer

Abstract

The invention provides a silicon-on-insulator substrate and a preparation method thereof, and a radio frequency silicon-on-insulator wafer. The silicon-on-insulator substrate comprises a substrate; the insulating layer is arranged on the substrate; and a polysilicon stack disposed on the insulating layer, the polysilicon stack comprising a plurality of polysilicon trap sub-layers separated by conductive intermediate layers, where the conductive intermediate layers are configured to cooperatively generate a potential gradient with adjacent polysilicon trap sub-layers, and free charge carriers are driven to directionally migrate to the adjacent polycrystalline silicon trap sub-layers. According to the silicon-on-insulator substrate, the conductive intermediate layer is adopted to synergistically generate the potential gradient, and active driving and directional migration of free charge carriers are realized, so that the charge capture efficiency is greatly improved, and the total parasitic capacitance is remarkably reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor materials technology, and in particular to silicon-on-insulator substrates and their preparation methods, and radio frequency silicon-on-insulator wafers. Background Technology

[0002] In radio frequency integrated circuits, such as radio frequency silicon-on-insulator (RF-SOI) devices, substrate-induced parasitic capacitance significantly impacts device performance, including signal delay, dynamic power consumption, and switching speed. As semiconductor processes advance to the nanoscale, one of the core requirements for improving integrated circuit performance is effectively reducing device parasitic capacitance.

[0003] Furthermore, in some radio frequency circuits based on silicon-on-insulator wafers, when a bias voltage is applied to the back gate, there is a large back gate leakage current in the trap enrichment layer on the active region side and the back gate region, which will seriously affect the back gate control capability.

[0004] In related technologies, several solutions exist to reduce the parasitic capacitance of RF-SOI devices. However, conventional solutions are limited in their ability to reduce parasitic capacitance, leading to a bottleneck in device performance improvement, and the problem of parasitic capacitance still exists.

[0005] Therefore, how to provide a structure and its fabrication method that can more effectively reduce parasitic capacitance and improve back-gate control capability is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0006] This application provides a silicon-on-insulator substrate and its fabrication method, as well as a radio frequency silicon-on-insulator wafer. This silicon-on-insulator substrate, by employing a conductive intermediate layer to collaboratively generate a potential gradient, achieves active driving and directional migration of free charge carriers, thereby significantly improving charge capture efficiency and substantially reducing total parasitic capacitance.

[0007] The technical solution of this application is implemented as follows: In a first aspect, some embodiments of this application provide a silicon-on-insulator substrate, comprising: Base; An insulating layer disposed on the substrate; and A polysilicon stack disposed on the insulating layer, the polysilicon stack comprising a plurality of polysilicon trap sublayers separated by conductive intermediate layers, The conductive intermediate layer is configured to work with the adjacent polysilicon trap sublayer to generate a potential gradient, thereby driving free charge carriers to migrate directionally to the adjacent polysilicon trap sublayer.

[0008] In some examples, the conductive intermediate layer comprises a two-dimensional transition metal dichalcogenide.

[0009] In some examples, the thickness of two-dimensional transition metal dichalcogenides is atomically thin.

[0010] In some examples, the potential gradient is formed through a Z-shaped heterojunction.

[0011] In some examples, the polysilicon stack comprises: N-type semiconductor layer; and P-type semiconductor layer, The N-type semiconductor layer and the P-type semiconductor layer together form a Z-type heterojunction.

[0012] In some examples, at least one of the N-type semiconductor layer and the P-type semiconductor layer comprises a two-dimensional transition metal dichalcogenide.

[0013] In some examples, the polysilicon stack comprises: N-type semiconductor layer; A first polysilicon trap sublayer disposed on an N-type semiconductor layer; A P-type semiconductor layer disposed on the first polysilicon trap sublayer; and A second polysilicon trap sublayer is disposed on the P-type semiconductor layer.

[0014] In some examples, the first polysilicon trap sublayer is doped polysilicon, and the second polysilicon trap sublayer is intrinsic polysilicon.

[0015] In some examples, the substrate is a high-resistivity silicon substrate, and the insulating layer is an oxide layer.

[0016] Secondly, some embodiments of this application provide a method for fabricating a silicon-on-insulator substrate, the method comprising: An insulating layer is formed on the substrate; and A polysilicon stack is deposited on an insulating layer. The deposition steps include depositing multiple polysilicon trap sublayers and a conductive intermediate layer, wherein the multiple polysilicon trap sublayers are separated by the conductive intermediate layer. The deposition step is performed such that the conductive intermediate layer is configured to generate a potential gradient in conjunction with the adjacent polysilicon trap sublayer to drive free charge carriers to migrate directionally to the adjacent polysilicon trap sublayer.

[0017] In some examples, the conductive intermediate layer comprises a two-dimensional transition metal dichalcogenide.

[0018] In some examples, the preparation method further includes performing an activation treatment on the surface of the two-dimensional transition metal dichalcogenide before depositing the two-dimensional transition metal dichalcogenide sublayer in multiple polycrystalline silicon trap sublayers.

[0019] In some examples, the activation process includes plasma treatment or chemical treatment.

[0020] In some examples, the step of depositing a conductive intermediate layer includes: Depositing an N-type semiconductor layer; and A P-type semiconductor layer is deposited to form a Z-type heterojunction.

[0021] Thirdly, some embodiments of this application provide a radio frequency insulator-on-silicon wafer, including: High-resistivity silicon substrate; An oxide layer disposed on a high-resistivity silicon substrate; An N-type two-dimensional material layer disposed on an oxide layer; A first polycrystalline silicon layer disposed on an N-type two-dimensional material layer; A P-type two-dimensional material layer disposed on the first polycrystalline silicon layer; and A second polycrystalline silicon layer disposed on a P-type two-dimensional material layer. The N-type two-dimensional material layer and the P-type two-dimensional material layer are configured to work together with the adjacent first polysilicon layer and the second polysilicon layer to generate a potential gradient, thereby driving the parasitic charge to migrate directionally to the first polysilicon layer and the second polysilicon layer.

[0022] This application provides a silicon-on-insulator (SiI) substrate and its fabrication method, as well as a radio frequency SiI wafer. The SiI substrate comprises a polysilicon stack. This stack divides the polysilicon trap layer into multiple sublayers by introducing one or more conductive intermediate layers. The design of this conductive intermediate layer plays a dual crucial role: firstly, its conductivity fundamentally avoids the secondary parasitic capacitance problem caused by traditional insulating layers and ensures efficient charge migration between sublayers; secondly, the conductive intermediate layer, in synergy with adjacent polysilicon trap sublayers, constructs an active potential gradient within the stack. This potential gradient actively drives and accelerates the directional migration of parasitic charges to the trap sublayers for efficient capture. This mechanism, transforming passive charge diffusion into active electric field-driven migration, significantly improves the efficiency and speed of charge capture, thereby significantly reducing the total parasitic capacitance of the device. Furthermore, the built-in electric field formed by the potential gradient effectively confines free charge carriers within the polysilicon stack, preventing leakage to the substrate, thus significantly reducing the back-gate leakage current and enhancing back-gate control capability. Attached Figure Description

[0023] Figure 1 A schematic cross-sectional view of a silicon-on-insulator substrate provided for some embodiments of this application.

[0024] Figure 2 This is a schematic diagram of the surface morphology of polycrystalline silicon grains when two-dimensional transition metal dichalcogenides are not introduced in the relevant technology.

[0025] Figure 3A schematic diagram of the surface morphology of polycrystalline silicon grains after introducing two-dimensional transition metal dichalcogenides into a silicon-on-insulator substrate, provided for some embodiments of this application.

[0026] Figure 4 This is a schematic diagram illustrating the accelerated parasitic charge transfer in a built-in electric field composed of two-dimensional materials of different conductivity types in a silicon-on-insulator substrate provided for some embodiments of this application.

[0027] Figure 5 A schematic diagram showing the relationship between the depth and resistivity of a silicon-on-insulator substrate provided for some embodiments of this application.

[0028] Figure 6 A flowchart illustrating a method for fabricating a silicon-on-insulator substrate provided for some embodiments of this application.

[0029] Figure 7 for Figure 6 A flowchart of one step in the preparation method of [the substance].

[0030] Figure 8 A schematic cross-sectional view of a silicon-on-insulator wafer provided for some embodiments of this application. Detailed Implementation

[0031] To make the objectives, technical solutions, and beneficial effects of this application clearer and more explicit, the following detailed description of this application will be provided in conjunction with the accompanying drawings.

[0032] As mentioned in the background section, reducing the parasitic capacitance of radio frequency silicon-on-insulator (RF-SOI) devices is crucial for improving integrated circuit performance.

[0033] Research has shown that, in order to reduce the parasitic capacitance of RF-SOI devices, one approach is to introduce a polycrystalline silicon layer 23 between the buried oxide layer and the substrate silicon layer. The grain boundaries of the polycrystalline silicon are used as trap enrichment layers to capture free charge carriers, thereby reducing parasitic effects.

[0034] However, this approach is not ideal. In conventional single-stage polysilicon deposition methods, the grain size of polysilicon gradually increases in an inverted conical shape as the growth thickness increases. This grain enlargement reduces the grain boundary density, weakens the polysilicon layer's ability to capture free carriers, and results in the continued existence of parasitic capacitance.

[0035] To address the grain size issue, attempts were made to introduce isolation layers, such as silicon oxide (SiO2) or silicon nitride (SiN) layers, into the polycrystalline silicon layer. By growing polycrystalline silicon in a multilayer structure, the trapping ability was improved.

[0036] In-depth analysis and experiments revealed that while this approach of introducing an insulating layer reduces the size of polycrystalline silicon grains to some extent, it introduces new and more hidden technical problems.

[0037] First, there is the issue of thickness. These silicon oxide or silicon nitride isolation layers themselves have a significant thickness, for example, on the order of 1 μm to 10 μm, which increases the total thickness of the substrate, hindering the current trend of semiconductor manufacturing processes towards structural miniaturization.

[0038] Another, and even more serious, problem is secondary parasitic capacitance. The inventors discovered that these insulating layers are insulators. For example, silicon oxide can have a resistivity as high as 1 × 10⁻⁶. 14 ohm·cm to 1×10 16 The insulating property, measured in ohm·cm, hinders the migration of free charge carriers between different polycrystalline silicon sublayers, reducing the trapping efficiency of the trap-enriched layer as a whole. Furthermore, the insulating layer and the conductive polycrystalline silicon layer form a new capacitive structure at the interface, creating localized secondary parasitic capacitance. The generation of this secondary parasitic capacitance contradicts the initial goal of reducing the total parasitic capacitance and may even exacerbate the problem in some cases.

[0039] Based on this, it is recognized that the real technical challenge lies in how to achieve polycrystalline silicon grain refinement while maintaining an ultra-thin structure to adapt to process miniaturization, and avoiding charge obstruction and secondary parasitic capacitance caused by the insulation of the isolation layer.

[0040] Therefore, this application provides a novel silicon-on-insulator substrate structure and its fabrication method.

[0041] See Figure 1 The illustration shows a schematic cross-sectional view of a silicon-on-insulator substrate 100 provided in an embodiment of this application. The silicon-on-insulator substrate 100 can be applied to radio frequency silicon-on-insulator (RF-SOI) devices, such as RF switches, low-noise amplifiers, etc., as well as electronic devices containing such devices, such as mobile phones, communication base stations, Internet of Things devices, etc.

[0042] The silicon-on-insulator substrate 100 includes a substrate 10, an insulating layer 20 disposed on the substrate 10, and a polysilicon stack 30 disposed on the insulating layer 20.

[0043] In some examples, substrate 10 is a high-resistivity silicon substrate. Using a high-resistivity silicon substrate helps reduce substrate coupling effects and RF losses in RF applications. In specific embodiments, the resistivity of substrate 10 can be greater than 2000 ohm·cm. This high-resistivity silicon substrate can achieve a lower oxygen and carbon impurity content and the desired high resistivity through, for example, the Czochralski (CZ) method.

[0044] In some examples, insulating layer 20 is an oxide layer. For example, insulating layer 20 may be a silicon oxide (SiO2) layer, which serves as a buried oxide layer (BOX) in, for example, a radio frequency insulator-on-silicon (RF-SOI) structure. The thickness of insulating layer 20 may be between about 1 nm and about 10 nm.

[0045] The insulating layer 20 can be formed by various methods. For example, the insulating layer 20 can be grown on the surface of the substrate 10 by a wet chemical oxidation process. In one example, a thin chemical oxide layer is grown on the substrate 10 as the insulating layer 20 using an SC1 washing solution, i.e., a mixture of ammonia and hydrogen peroxide. In other examples, the insulating layer 20 can also be formed by a thermal oxidation process or by treatment with an SC2 washing solution, i.e., a mixture of hydrochloric acid and hydrogen peroxide.

[0046] In other examples, the insulating layer 20 can be formed using a low-pressure chemical vapor deposition (LPCVD) process. The temperature of this LPCVD process can range from approximately 900°C to approximately 1100°C. The silicon source gas can be silane (SiH4), silane (Si2H6), or propane (Si3H8), and can be combined with methane (CH4) or methylsilane (SiH3CH3). The oxygen atmosphere can be an argon (Ar) atmosphere with a concentration of approximately 0.1% to approximately 10% oxygen (O2). The reaction time can range from approximately 2 hours to approximately 5 hours.

[0047] A polysilicon stack 30 is disposed on the insulating layer 20. The polysilicon stack 30 includes multiple polysilicon trap sublayers, which are separated by one or more conductive intermediate layers. These polysilicon trap sublayers serve as trap enrichment layers to trap free charge carriers.

[0048] exist Figure 1 In the example shown, the polysilicon stack 30 includes an N-type two-dimensional material layer 302, a first polysilicon trap sublayer 304 disposed on the N-type two-dimensional material layer 302, a P-type two-dimensional material layer 306 disposed on the first polysilicon trap sublayer 304, and a second polysilicon trap sublayer 308 disposed on the P-type two-dimensional material layer 306.

[0049] In this structure, the N-type two-dimensional material layer 302 and the P-type two-dimensional material layer 306 are conductive, and together they form a conductive intermediate layer that separates the first polysilicon trap sublayer 304 and the second polysilicon trap sublayer 308.

[0050] According to some embodiments of this application, synergistic technical effects are achieved by using a conductive intermediate layer, such as a two-dimensional transition metal dichalcogenide (TMDC) material layer, to separate the polycrystalline silicon trap sublayer.

[0051] First, due to the excellent electrical and thermal conductivity of the conductive intermediate layer, the additional capacitance interface formed by the contact between the insulating layer and the polysilicon layer can be fundamentally avoided, eliminating the problem of secondary parasitic capacitance. Furthermore, this conductive intermediate layer allows free charge carriers to migrate effectively between the first polysilicon trap sublayer 304 and the second polysilicon trap sublayer 308, enabling the entire polysilicon stack 30 to function as a unified, thicker trap-rich region, rather than being divided into two isolated thin layers by the insulating layer, thereby significantly improving the overall charge trapping capacity.

[0052] In addition, using two-dimensional transition metal dichalcogenides (TMDC) as a conductive intermediate layer can bring further technical benefits.

[0053] On the one hand, two-dimensional transition metal dichalcogenide materials can have atomic-level thickness. For example, the thickness of a single layer of molybdenum disulfide (MoS2) is approximately 0.65 nm. This atomic-level thickness directly solves the fundamental problem in related technologies where excessively thick isolation layers hinder process miniaturization, greatly facilitating the continuous miniaturization of semiconductor process structures.

[0054] On the other hand, the N-type two-dimensional material layer 302 and the P-type two-dimensional material layer 306, including two-dimensional transition metal dichalcogenide materials, play a role in physical isolation and nucleation control during polycrystalline silicon growth. As analyzed above, conventional one-time thick film deposition leads to inverted conical growth of polycrystalline silicon grains, that is, the grains become larger with increasing thickness, resulting in a decrease in the grain boundary density, i.e., the trap density, of the upper layer. By introducing the N-type two-dimensional material layer 302 and the P-type two-dimensional material layer 306 during the growth process, which act as growth barrier layers or new nucleation surfaces, the continuous growth of the grains in the first polycrystalline silicon trap sublayer 304 is effectively interrupted, and a new, uniform nucleation surface is provided for the growth of the second polycrystalline silicon trap sublayer 308. This structure allows both the first polycrystalline silicon trap sublayer 304 and the second polycrystalline silicon trap sublayer 308 to maintain a small grain size. Since the trap effect of polycrystalline silicon mainly originates from grain boundaries, a smaller grain size means a higher total number of grain boundaries and a higher trap state density within the same volume. Therefore, this structural design achieves grain refinement through a two-dimensional material intermediate layer, thereby significantly enhancing the overall charge trapping capability.

[0055] See Figure 2 and Figure 3 . Figure 2 This is a schematic diagram of the surface morphology of polycrystalline silicon grains when two-dimensional transition metal dichalcogenides are not introduced in the relevant technology. Figure 3 This is a schematic diagram of the surface morphology of polycrystalline silicon grains after introducing a two-dimensional transition metal dichalcogenide as an intermediate layer in an embodiment of this application. (Comparison) Figure 2 and Figure 3 It can be seen that without the introduction of an intermediate layer (such as...) Figure 2 As shown), polycrystalline silicon grains are large and uneven; however, after introducing a two-dimensional transition metal dichalcogenide interlayer (as shown), the grain size of polycrystalline silicon is large and uneven; Figure 3 As shown, the polycrystalline silicon grain size is effectively refined, becoming smaller, denser, and more uniform. This intuitively demonstrates that the solution in this application embodiment can effectively suppress grain growth, thereby improving grain boundary density and charge trapping capability.

[0056] Furthermore, according to embodiments of this application, an active charge-driven mechanism can be constructed using the semiconductor properties of two-dimensional materials.

[0057] In some embodiments of this application, an N-type two-dimensional material layer 302, such as molybdenum disulfide (MoS2) or tungsten disulfide (WS2), and a P-type two-dimensional material layer 306, such as tungsten diselenide (WSe2) or molybdenum distelluride (MoTe2), are spatially separated by a first polycrystalline silicon trap sublayer 304.

[0058] According to the definition of a Z-type heterojunction in materials physical chemistry, a Z-type heterojunction can be formed by two semiconductor materials, typically one with a high conduction band (CB) potential (such as an N-type material) and the other with a low valence band (VB) potential (such as a P-type material), through interfacial contact or the introduction of an electronic medium (such as a redox couple or a conductive bridge). In the structure of this application embodiment, the conductive first polycrystalline silicon trap sublayer 304 assumes the role of the electronic medium or conductive bridge in this definition, connecting the N-type two-dimensional material layer 302 and the P-type two-dimensional material layer 306, thereby constructing the Z-type heterojunction system.

[0059] Due to the difference in work function between the N-type and P-type materials, this Z-shaped heterostructure generates a strong built-in electric field within the polysilicon stack 30. This built-in electric field physically corresponds to a significant potential gradient.

[0060] The generation of this potential gradient transforms the charge trapping mechanism from passive diffusion to active driving. In related technologies, parasitic charges need to drift to the trapping layer through random thermal motion, i.e., passive diffusion. However, in this embodiment, the potential gradient generated by the built-in electric field constitutes an accelerator for parasitic capacitance elimination, actively and rapidly driving and accelerating the directional migration of parasitic charges (e.g., electrons and holes) in the first polysilicon trapping sublayer 304 and the second polysilicon trapping sublayer 308. This active driving mechanism significantly improves the speed and efficiency of charge trapping, rapidly eliminating parasitic charges before they form a significant parasitic capacitance effect, thus more thoroughly solving the parasitic capacitance problem. See also Figure 4This schematically demonstrates how a built-in electric field acts as an accelerator, actively driving parasitic charges (such as electrons e-) to the trap layer. Furthermore, the built-in electric field acts as a charge barrier, firmly fixing or confining free charge carriers, such as electrons and holes, within the trap sublayer of the polysilicon stack 30, effectively preventing these charges from leaking through the insulating layer 20 to the substrate 10 under back-gate bias. This charge confinement effect significantly reduces back-gate leakage current, ensuring the device's back-gate controllability.

[0061] See Figure 5 This illustrates a schematic diagram showing the relationship between the depth and resistivity of the silicon substrate on the insulator in an embodiment of this application. For example... Figure 5 As shown, the curve illustrates the process from the surface of the silicon-on-insulator substrate (SOS) Figure 5 (Middle left) inward to the base ( Figure 5 The resistivity change is shown on the right side of the diagram. In the polysilicon stack 30, the resistivity of the N-type two-dimensional material layer 302 and the P-type two-dimensional material layer 306, i.e., the conductive intermediate layer, decreases significantly, forming two distinct troughs. This confirms the excellent conductivity of the two-dimensional transition metal dichalcogenide. In contrast, the resistivity of the insulating layer 20, i.e., the oxide layer, exhibits an extremely high peak, demonstrating its high insulation properties. The first polysilicon trap sublayer 304 and the second polysilicon trap sublayer 308, as well as the substrate 10, all maintain relatively low resistivity levels. This depth-resistivity curve clearly confirms the structure of the embodiment of this application, namely the stark contrast in electrical properties between the conductive intermediate layer, the conductive polysilicon trap sublayer, and the highly insulating oxide layer.

[0062] The first polycrystalline silicon trap sublayer 304 and the second polycrystalline silicon trap sublayer 308 are polycrystalline silicon thin films with high-density grain boundaries to serve as trap enrichment layers to capture free charge carriers.

[0063] In some specific examples, the first polysilicon trap sublayer 304 is doped polysilicon, while the second polysilicon trap sublayer 308 is intrinsic polysilicon.

[0064] The first polysilicon trap sublayer 304 can be doped with P-type polysilicon, for example, by doping with boron (B). Alternatively, the first polysilicon trap sublayer 304 can also be doped with N-type polysilicon, for example, by doping with phosphorus (P) or arsenic (As).

[0065] The doped first polysilicon trap sublayer 304 can have a relatively low resistivity and functions as a guiding channel or transport layer for charge migration. The intrinsic second polysilicon trap sublayer 308 has a high density of grain boundary defect states and a relatively high resistivity, and functions as an endpoint or storage layer for charge trapping.

[0066] Once parasitic charges are generated, they are first driven and accelerated by the built-in electric field of the Z-type heterojunction, and then rapidly transported through the low-resistivity transport layer, namely the first polysilicon trap sublayer 304. Finally, they are efficiently captured and stored by the high-trap-density storage layer, namely the second polysilicon trap sublayer 308, forming an efficient synergistic trapping mechanism of acceleration-transportation-storage.

[0067] In some examples, the thickness of the first polysilicon trap sublayer 304 can be between about 1 μm and about 3 μm. The thickness of the second polysilicon trap sublayer 308 can also be between about 1 μm and about 3 μm. The total thickness of the polysilicon stack 30 can be designed, for example, between about 2.5 μm and about 3.5 μm.

[0068] This application also provides a method for preparing a silicon-on-insulator substrate 100.

[0069] See Figure 6 The diagram shows a flowchart of the preparation method. The method includes approximately steps S10 to S20.

[0070] In step S10, an insulating layer 20 is formed on the substrate 10.

[0071] In step S20, a polycrystalline silicon stack 30 is deposited on the insulating layer 20.

[0072] Step S10 forms an insulating layer 20 on the substrate 10. As described above, various methods can be used. For example, by wet chemical oxidation, the surface of the substrate 10 is treated with SC1 or SC2 cleaning solution to form a silicon oxide layer with a thickness of about 1 nm to about 10 nm. Alternatively, by low-pressure chemical vapor deposition (LPCVD), at a temperature of about 900 °C to about 1100 °C, silane (SiH4), disilane (Si2H6), or propane (Si3H8), and (CH4) or methylsilane (SiH3CH3) as silicon source gases are reacted in an oxygen (O2) atmosphere with an argon (Ar) concentration of about 0.1% to about 10% for about 2 hours to about 5 hours to deposit the insulating layer 20.

[0073] Step S20 may include depositing multiple polysilicon trap sublayers and a conductive intermediate layer, wherein the multiple polysilicon trap sublayers are separated by the conductive intermediate layer. Step S20, i.e. the deposition step, is performed such that the conductive intermediate layer is configured to cooperate with the adjacent polysilicon trap sublayers to generate a potential gradient, thereby driving the directional migration of free charge carriers to the adjacent polysilicon trap sublayers.

[0074] Specifically, in step S20, depositing a polycrystalline silicon stack 30 on the insulating layer 20 is a multi-step composite process. See also... Figure 7 Step S20 may include steps S21 to S26.

[0075] In step S21, an N-type two-dimensional material layer 302 is deposited. That is, an N-type two-dimensional material layer 302 is deposited on the insulating layer 20.

[0076] The N-type two-dimensional material layer 302 may contain a two-dimensional transition metal dichalcogenide. It can be deposited using CVD, atomic layer deposition (ALD), or metal-organic chemical vapor deposition (MOCVD) processes. Taking CVD as an example, it is used to deposit N-type materials such as molybdenum disulfide (MoS2) or tungsten disulfide (WS2). Process parameters can be: a reaction temperature set at approximately 600°C to approximately 800°C; and a reaction time set at approximately 10 minutes to approximately 30 minutes. By controlling the supply and reaction conditions of precursors, such as molybdenum and sulfur sources, an atomically thick N-type two-dimensional material layer 302 is grown on the insulating layer 20.

[0077] In step S22, an activation treatment is performed on the surface of the N-type two-dimensional material layer 302 to solve the nucleation problem of subsequent polycrystalline silicon deposition.

[0078] Two-dimensional TMDC materials, such as molybdenum disulfide (MoS2), have chemically relatively inert surfaces and lack dangling bonds for chemical bonding. This makes it difficult for subsequent polycrystalline silicon films to nucleate and adhere to their surfaces. Therefore, before depositing the first polycrystalline silicon trap sublayer 304, the preparation method also includes performing an activation treatment on the surface of the N-type two-dimensional material layer 302 to introduce nucleation centers to the inert TMDC surface.

[0079] Activation treatment may include plasma treatment or chemical treatment.

[0080] In some examples of this application, the activation process is plasma treatment. For example, oxygen (O2) plasma treatment is used. Specific process parameters may include a plasma power of approximately 100 watts (W) and a treatment time of approximately 30 seconds (s). High-energy particles or free radicals in the plasma, such as oxygen ions, bombard the TMDC surface, creating defect sites, such as sulfur vacancies, or forming localized oxide bonding sites. These sites disrupt the surface inertia, providing nucleation centers for subsequent polysilicon growth. In other examples, plasma treatment may also employ hydrogen plasma or nitrogen plasma, etc.

[0081] In other examples of this application, the activation treatment is a chemical treatment method. For example, the TMDC surface is chemically modified by introducing an alkaline solution or an acidic solution. An example of an alkaline solution could be ammonium hydroxide (NH4OH) solution. An example of an acidic solution could be formic acid (HCOOH) solution.

[0082] Step S23: Deposit the first polycrystalline silicon trap sublayer 304. That is, deposit the first polycrystalline silicon trap sublayer 304 on the surface of the activated N-type two-dimensional material layer 302.

[0083] The polysilicon deposition can be performed using an APCVD process. The growth temperature can be set, for example, to approximately 1100°C. The growth carrier gas can be argon (Ar). In this step, a dopant gas is introduced simultaneously with the polysilicon deposition, such that the first polysilicon trap sublayer 304 formed is doped polysilicon. For example, a P-type dopant gas, such as diborane, can be introduced to form P-type polysilicon. Alternatively, an N-type dopant gas, such as phosphine, can be introduced to form N-type polysilicon. The deposition thickness is controlled to be from approximately 1 μm to approximately 3 μm.

[0084] Step S24: Deposit a P-type two-dimensional material layer 306. That is, deposit a P-type two-dimensional material layer 306 on the first polysilicon trap sublayer 304.

[0085] The P-type two-dimensional material layer 306 may contain a two-dimensional transition metal dichalcogenide. The deposition process can be similar to step S21, such as CVD, ALD, or MOCVD. Taking CVD as an example, it is used to deposit P-type materials, such as tungsten diselenide (WSe2) or molybdenum distelluride (MoTe2). The process parameters can be: the reaction temperature is set at about 600°C to about 800°C, and the reaction time can be set at 10 minutes to 30 minutes. By controlling the supply of precursors (e.g., tungsten and selenium sources, or molybdenum and tellurium sources), an atomically thick P-type two-dimensional material layer 306 is grown on the first polycrystalline silicon trap sublayer 304.

[0086] Step S25: Perform an activation treatment on the surface of the P-type two-dimensional material layer 306.

[0087] Similar to step S22, the surface of the P-type two-dimensional material layer 306 is reactivated before depositing the second polycrystalline silicon trap sublayer 308. This is because the P-type two-dimensional material layer 306 also has surface inertness and lacks dangling bonds. Nucleation centers are introduced to ensure that the second polycrystalline silicon trap sublayer 308 can grow with high quality. This activation process can be a plasma treatment (e.g., oxygen (O2) plasma, power about 100W, treatment for about 30s; or hydrogen plasma; or nitrogen plasma), or a chemical treatment, for example, using ammonium hydroxide (NH4OH) solution or formic acid (HCOOH) solution.

[0088] Step S26: Deposit a second polycrystalline silicon trap sublayer 308. That is, deposit a second polycrystalline silicon trap sublayer 308 on the surface of the activated P-type two-dimensional material layer 306.

[0089] The polysilicon deposition process is similar to step S23, and can, for example, use an APCVD process at a growth temperature of approximately 1100°C and an argon (Ar) carrier gas. However, the difference is that no doping gas is introduced in this step. This allows the deposited second polysilicon trap sublayer 308 to remain intrinsic polysilicon, utilizing its high density of grain boundary trap states as a charge trapping layer. The deposition thickness is controlled from approximately 1 μm to approximately 3 μm to achieve a target total thickness of the polysilicon stack 30, for example, from approximately 2.5 μm to approximately 3.5 μm.

[0090] Through the above steps S10 to S26, the fabrication of silicon-on-insulator substrate 100 is completed.

[0091] It should be understood that the above-described structures and methods can have various variations and combinations. Where there is no conflict, the features of the technical solutions described in this application can be combined arbitrarily.

[0092] For example, the material of the N-type two-dimensional material layer 302 can be selected from molybdenum disulfide (MoS2) or tungsten disulfide (WS2). The material of the P-type two-dimensional material layer 306 can be selected from tungsten diselenide (WSe2) or molybdenum distelluride (MoTe2). The doping type of the first polycrystalline silicon trap sublayer 304 can be P-type, such as boron (B), or N-type, such as phosphorus (P) or arsenic (As). The activation treatment in steps S22 and S25 can include oxygen (O2) plasma treatment, hydrogen (H2) plasma treatment, nitrogen (N2) plasma treatment, or chemical treatment, such as using ammonium hydroxide (NH4OH) solution or formic acid (HCOOH) solution. The scope of protection of this application is not limited to these specific combinations of materials or parameters.

[0093] In addition, although Figure 1 The illustration shows two polysilicon trap sublayers and two two-dimensional material layers, but the embodiments of this application are not limited to this. The polysilicon stack 30 may contain more polysilicon trap sublayers, which are separated by conductive intermediate layers. For example, it may be a structure of "N-type-TMDC / first polysilicon layer / P-type-TMDC / second polysilicon layer / N-type-TMDC / third polysilicon layer / P-type-TMDC / fourth polysilicon layer..." to further increase the trap density and optimize the potential gradient distribution.

[0094] See Figure 8 Some embodiments of this application also provide a radio frequency insulator-on-silicon wafer 100', comprising: 10' of high-resistivity silicon substrate; An oxide layer 20' is disposed on a high-resistivity silicon substrate 10'; An N-type two-dimensional material layer 302' is disposed on the oxide layer 20'; A first polycrystalline silicon layer 304' is disposed on an N-type two-dimensional material layer 302'; A P-type two-dimensional material layer 306' disposed on the first polysilicon layer 304'; and A second polycrystalline silicon layer 308' is disposed on the P-type two-dimensional material layer 306'. The N-type two-dimensional material layer 302' and the P-type two-dimensional material layer 306' are configured to generate a potential gradient in cooperation with the adjacent first polysilicon layer 304' and second polysilicon layer 308', so as to drive the parasitic charge to migrate directionally to the first polysilicon layer 304' and the second polysilicon layer 308'.

[0095] Examples and Comparative Examples To further verify the beneficial effects of the technical solutions provided in the embodiments of this application, the following comparative description is provided through specific embodiments and comparative examples.

[0096] Example 1: This embodiment adopts Figure 1 The structure shown.

[0097] Step 1: Prepare substrate 10, which is a high-resistivity silicon substrate with a resistivity greater than 2000 ohm·cm.

[0098] Step 2: An insulating layer 20 (silicon oxide layer) approximately 5 nanometers thick is formed on the substrate 10 using a wet chemical oxidation method and SC1 washing solution.

[0099] Step 3: Deposit an N-type two-dimensional material layer 302 on the insulating layer 20 using a CVD process. The material is molybdenum disulfide (MoS2), and the thickness is atomic (approximately 0.65 nanometers).

[0100] Step 4: Perform oxygen (O2) plasma activation treatment on the surface of the N-type two-dimensional material layer 302 (power 100W, treatment 30s).

[0101] Step 5: Deposit a first polycrystalline silicon trap sublayer 304 with a thickness of 1.5 micrometers on the activated surface using APCVD process, and introduce diborane for P-type doping.

[0102] Step 6: Deposit a P-type two-dimensional material layer 306 on the first polycrystalline silicon trap sublayer 304 using a CVD process. The material is tungsten diselenide (WSe2), and the thickness is atomic level.

[0103] Step 7: Perform oxygen (O2) plasma activation treatment on the surface of the P-type two-dimensional material layer 306 (power 100W, treatment 30s).

[0104] Step 8: Deposit a second polycrystalline silicon trap sublayer 308 with a thickness of 1.5 μm on the activated surface using APCVD process. The layer is undoped and remains intrinsic polycrystalline silicon.

[0105] A silicon-on-insulator substrate was prepared.

[0106] Comparative Example 1: Steps 1-2: Same as in Example 1.

[0107] Step 3: Deposit the first polycrystalline silicon sublayer on the insulating layer using the APCVD process, with a thickness of 1.5 μm.

[0108] Step 4: Deposit an insulating layer of silicon oxide (SiO2) with a thickness of 1 μm.

[0109] Step 5: Deposit a second polycrystalline silicon sublayer with a thickness of 1.5 μm on the insulating isolation layer.

[0110] A substrate is obtained.

[0111] Comparative Example 2: This comparative example uses a conventional single trap layer structure.

[0112] Steps 1-2: Same as in Example 1.

[0113] Step 3: A single-layer polycrystalline silicon trap layer with a total thickness of 3μm is deposited on the insulating layer in one step using the APCVD process.

[0114] Result comparison: The substrates prepared in Example 1, Comparative Example 1, and Comparative Example 2 were subjected to TCAD simulation and CV (capacitance-voltage) tests under the same conditions to evaluate their total parasitic capacitance, average grain size, parasitic charge trapping time, and the generation of secondary parasitic capacitance. The key performance indicators are summarized in the table below: Table 1: Performance Comparison of Examples and Comparative Examples

[0115] As can be seen from the results in the table above, the silicon-on-insulator substrate provided in Example 1 of this application has the following advantages compared to Comparative Example 1 and Comparative Example 2: First, the parasitic capacitance is the lowest; the total parasitic capacitance of Example 1 is much lower than that of the two comparative examples. This is attributed to two synergistic effects: on the one hand, compared to Comparative Example 1, the conductive intermediate layer (TMDC) of Example 1 eliminates the secondary parasitic capacitance introduced by the insulating isolation layer (SiO2); on the other hand, compared to Comparative Example 2, Example 1 suppresses the inverted conical growth of grains through the intermediate layer.

[0116] Furthermore, charge capture was the fastest; the charge capture time in Example 1 (<1 ns) was much faster than that in the comparative example. This confirms that the potential gradient formed by the Z-type heterojunction, i.e., the built-in electric field, acts as an accelerator, realizing active, directional charge-driven charge, rather than the passive diffusion in the comparative example.

[0117] In addition, the structure is the thinnest; the thickness of the isolation layer in Example 1 (atomic level) is much smaller than that in Comparative Example 1 (micrometer level), which has a significant advantage for the continuous miniaturization of semiconductor processes.

[0118] In summary, the solution of this application embodiment, through a conductive, atomically thin, two-dimensional material intermediate layer capable of constructing a Z-shaped heterojunction, successfully solves multiple technical problems existing in related technologies, such as high parasitic capacitance, large back gate leakage current, large grain size, secondary parasitic capacitance, and excessively thick isolation layer.

[0119] It should be noted that the technical solutions described in this application can be combined arbitrarily without conflict.

[0120] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A silicon-on-insulator substrate, characterized in that, include: Base; An insulating layer disposed on the substrate; as well as A polysilicon stack disposed on the insulating layer, the polysilicon stack comprising a plurality of polysilicon trap sublayers separated by conductive intermediate layers, The conductive intermediate layer is configured to work with the adjacent polysilicon trap sublayer to generate a potential gradient, thereby driving free charge carriers to migrate directionally to the adjacent polysilicon trap sublayer.

2. The silicon-on-insulator substrate according to claim 1, characterized in that, The conductive intermediate layer comprises a two-dimensional transition metal dichalcogenide.

3. The silicon-on-insulator substrate according to claim 2, characterized in that, The thickness of the two-dimensional transition metal dichalcogenide is atomic level.

4. The silicon-on-insulator substrate according to claim 1, characterized in that, The potential gradient is formed through a Z-type heterojunction.

5. The silicon-on-insulator substrate according to claim 4, characterized in that, The polycrystalline silicon stack comprises: N-type semiconductor layer; and P-type semiconductor layer, The N-type semiconductor layer and the P-type semiconductor layer together form the Z-type heterojunction.

6. The silicon-on-insulator substrate according to claim 5, characterized in that, At least one of the N-type semiconductor layer and the P-type semiconductor layer comprises a two-dimensional transition metal dichalcogenide.

7. The silicon-on-insulator substrate according to claim 5, characterized in that, The polycrystalline silicon stack comprises: The N-type semiconductor layer; A first polysilicon trap sublayer is disposed on the N-type semiconductor layer; The P-type semiconductor layer disposed on the first polysilicon trap sublayer; and A second polysilicon trap sublayer is disposed on the P-type semiconductor layer.

8. The silicon-on-insulator substrate according to claim 7, characterized in that, The first polysilicon trap sublayer is doped polysilicon, and the second polysilicon trap sublayer is intrinsic polysilicon.

9. The silicon-on-insulator substrate according to claim 1, characterized in that, The substrate is a high-resistivity silicon substrate, and the insulating layer is an oxide layer.

10. A method for fabricating a silicon-on-insulator substrate, characterized in that, The preparation method includes: An insulating layer is formed on the substrate; and A polysilicon stack is deposited on the insulating layer. The deposition step includes depositing a plurality of polysilicon trap sublayers and a conductive intermediate layer, wherein the plurality of polysilicon trap sublayers are separated by the conductive intermediate layer. The deposition step is performed such that the conductive intermediate layer is configured to cooperate with the adjacent polysilicon trap sublayer to generate a potential gradient, thereby driving free charge carriers to migrate directionally to the adjacent polysilicon trap sublayer.

11. The method for preparing a silicon-on-insulator substrate according to claim 10, characterized in that, The conductive intermediate layer comprises a two-dimensional transition metal dichalcogenide.

12. The method for preparing a silicon-on-insulator substrate according to claim 11, characterized in that, Prior to depositing the two-dimensional transition metal dichalcogenide sublayers in the plurality of polycrystalline silicon trap sublayers, the preparation method further includes performing an activation treatment on the surface of the two-dimensional transition metal dichalcogenide.

13. The method for preparing a silicon-on-insulator substrate according to claim 12, characterized in that, The activation process includes plasma treatment or chemical treatment.

14. The method for fabricating a silicon-on-insulator substrate according to claim 10, characterized in that, The step of depositing the conductive intermediate layer includes: Depositing an N-type semiconductor layer; and A P-type semiconductor layer is deposited to form a Z-type heterojunction.

15. A silicon-on-a-radio frequency insulator wafer, characterized in that, include: High-resistivity silicon substrate; An oxide layer disposed on the high-resistivity silicon substrate; An N-type two-dimensional material layer disposed on the oxide layer; A first polycrystalline silicon layer disposed on the N-type two-dimensional material layer; A P-type two-dimensional material layer disposed on the first polycrystalline silicon layer; as well as A second polycrystalline silicon layer is disposed on the P-type two-dimensional material layer. The N-type two-dimensional material layer and the P-type two-dimensional material layer are configured to cooperate with the adjacent first polysilicon layer and second polysilicon layer to generate a potential gradient, thereby driving parasitic charges to migrate directionally to the first polysilicon layer and the second polysilicon layer.

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