Gallium arsenide gate etching and metallization process based on interface strengthening layer

Abstract

The invention relates to a gallium arsenide gate etching and metallization process based on an interface strengthening layer, which comprises the following steps of: coating first photoresist layers on source metal and drain metal, defining the etching width of a cap layer by adopting an overlay process, and etching a channel on a substrate by adopting wet etching; s2, removing the first photoresist layer, and coating a polyimide (PI) layer; s3, coating a second photoresist layer, developing the photoresist, and then baking; s4, etching the polyimide PI layer by adopting dry etching oxygen plasma until the GaAs etched layer is formed; s5, the second photoresist layer is removed, a third photoresist layer is coated and development is carried out, the third photoresist layer is negative photoresist, and S6, metal evaporation is carried out, the total thickness of the metal evaporation is not larger than the thickness of the third photoresist layer, and the third photoresist layer and redundant metal are removed. According to the invention, cracks after metal evaporation caused by upwarp of the photoresist after etching can be avoided, and the yield of the grid electrode is greatly improved.

Description

Technical Field

[0001] This invention relates to the field of gate metal technology, and in particular to a gallium arsenide gate etching and metallization process based on an interface reinforcement layer. Background Technology

[0002] In current gallium arsenide (GaAs) device manufacturing processes, gate patterning typically employs i-line or electron beam lithography. However, during subsequent GaAs substrate etching, photoresist is prone to localized lifting or peeling. As the etching mask, the lifting of the photoresist alters the intended pattern morphology, resulting in a significant discrepancy between the etched gate line width and the design value. The lifted photoresist microscopically forms a discontinuous, stepped, and fragile substrate. During metal evaporation on this substrate, stress concentration causes cracks at the lifted edges of the photoresist. These cracks block the gate current path, leading to open circuits or performance degradation, severely reducing product yield and reliability.

[0003] This problem not only directly affects the control accuracy of the critical gate dimension, usually leading to an abnormal increase in gate CD, but also causes instability in the photoresist structure during subsequent gate metal evaporation processes, resulting in defects such as metal layer cracks, which seriously affect device performance and process yield. Summary of the Invention

[0004] The purpose of this invention is to provide a gallium arsenide gate etching and metallization process based on an interface reinforcement layer, which can avoid the cracks in the metal evaporation caused by the photoresist lifting after etching, and greatly improve the gate yield.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a gallium arsenide gate etching and metallization process based on an interface reinforcement layer, the process comprising the following steps: Step S1: Coat the first photoresist layer on both the source and drain metals, define the cap layer etching width using an overlay process, and etch the channel into the substrate using a wet etching process. Step S2: Remove the first photoresist layer, coat the polyimide (PI) layer, and bake. Step S3: Coating the second photoresist layer, developing the photoresist, and then baking it; Step S4: Use dry etching oxygen plasma to etch the polyimide (PI) layer down to the GaAs layer to be etched. Step S5: Remove the second photoresist layer, coat the third photoresist layer, and develop. The third photoresist layer is a negative photoresist. Step S6: Perform metal vapor deposition. The total thickness of the vapor-deposited metal should not exceed the thickness of the third photoresist layer. Remove the third photoresist layer and excess metal.

[0006] Furthermore, the coating thickness of the first photoresist layer is no greater than 10,000 Å.

[0007] Furthermore, the coating thickness of the polyimide (PI) is 500~3000 Å.

[0008] Furthermore, when coating the second photoresist layer, the thickness should not exceed 3000 Å if the gate linewidth is not greater than 0.5 μm; if the gate linewidth is greater than 0.3 μm, the photoresist thickness should be greater than 3000 Å.

[0009] Furthermore, the thickness of the third photoresist layer is 10000 Å.

[0010] Furthermore, the metal used in the vapor deposition process is Ti, PT, or Au.

[0011] Furthermore, after defining the cap layer etching width using the overlay process in step S1, the process also includes a baking step.

[0012] Furthermore, the baking temperature is 100°C to 125°C, and the baking time is 20 minutes to 40 minutes.

[0013] Furthermore, the baking in step S2 is carried out in a stepped manner: baking at 90°C to 120°C for 10 to 15 minutes; baking at 150°C for 10 minutes; baking at 200°C for 10 to 20 minutes; baking at 250°C for 10 to 20 minutes; and baking at 300°C for 30 to 60 minutes.

[0014] Furthermore, the baking temperature in step S3 is 145–155°C, and the baking time is 25–35 minutes. The beneficial effects of this invention are: 1. The cap layer of GaAs is etched off in advance to avoid cracks in the metal vapor deposition caused by the photoresist lifting after etching. 2. By using photoresist topography overlay process, the photoresist topography defining the photoresist linewidth is overlaid onto the PI using dry etching, which optimizes the loss of control and deviation of gate critical dimension (Gate CD); 3. Using PI as the gate metal filler eliminates the need for removal; the metal lies on the PI, which is especially beneficial for small linewidths, such as 0.1um, preventing the gate from being broken due to the small linewidth during NMP photoresist removal, greatly improving gate yield. In the original technology, the CD was a Y-shaped gate with a 0.1um linewidth and a 0.6um gate cap width; in this invention, the PI is placed under the entire cap width, effectively changing the CD from 0.1um to 0.6um. During the photoresist removal process, the reason for breakage is the position of the 0.1um linewidth. In this invention, the 0.1um linewidth portion is not exposed, thus making the entire gate stronger. 4. Using PI filling greatly improves the process window, allowing for an increase in gate metal thickness while keeping other conditions unchanged, thereby reducing gate resistance. 5. The breakdown voltage of the device is proportional to the etching; the width of the cap layer etching is defined in the first photoresist layer, which means that the definition of the breakdown voltage is extracted from the original gate etching process, simplifying the process; and it avoids the possibility of increasing the etching time in order to meet the required value of the gate breakdown voltage during the original etching process, which would exacerbate the photoresist warping and increase the possibility of metal cracks, and also increase the possibility of linewidth defocusing. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the photoresist patterning in this invention; Figure 2 This is a schematic diagram of wet etching after photoresist patterning in this invention; Figure 3 This is a schematic diagram illustrating the direct baking process after photoresist patterning; Figure 4 This is a schematic diagram of wet etching performed on a pre-baked image. Figure 5 This is a schematic diagram of the polyimide (PI) layer being coated. Figure 6 This is a schematic diagram of the second photoresist layer being coated. Figure 7 This is a schematic diagram of the etching of a polyimide (PI) layer; Figure 8 This is a schematic diagram of the process of applying the third photoresist layer; Figure 9 This is a schematic diagram of vapor-deposited metal; Figure 10 A schematic diagram showing the removal of the third photoresist layer and excess metal.

[0016] Wherein: 1. GaAs substrate, 2. First photoresist layer, 3. Channel, 4. Polyimide (PI) layer, 5. Second photoresist layer, 6. Third photoresist layer, 7. Metal. Detailed Implementation

[0017] The invention will now be further described with reference to the accompanying drawings.

[0018] Please see Figures 1 to 10 The present invention provides an embodiment: a gallium arsenide gate etching and metallization process based on an interface reinforcement layer: the process includes the following steps: Step S1: Coat the first photoresist layer 2 on both the source and drain metals. Use an overlay process to define the etch width of the cap layer. Use wet etching to etch the channel 3 into the substrate. Different patterning linewidths determine different etch widths of GaAs material. When the CD requirement is large, the CD is larger after the photoresist is patterned, and the linewidth of GaAs substrate 1 is also larger after wet etching. Step S2: Remove the first photoresist layer 2, coat the polyimide PI layer 4, and bake it; polyimide PI is used as the gate metal filler, so it does not need to be removed; let the metal 7 lie on the polyimide PI layer 4, especially for small linewidths, such as 0.1um, to avoid the gate being broken due to the small linewidth during NMP removal of photoresist, which greatly improves the gate yield. Step S3: Coating the second photoresist layer 5 and baking the photoresist after development; the purpose of baking is to make the photoresist contour oblique so that the contour can be overlaid on the polyimide PI layer 4, so that the gate metal 7 can be smoothly laid on the polyimide PI layer 4 and avoid cracks in the metal 7. Step S4: Use dry etching oxygen plasma to etch PI down to the etched layer of GaAs substrate 1. Step S5: Remove the second photoresist layer 5, coat the third photoresist layer 6, and develop. The third photoresist layer 6 is a negative photoresist. Step S6: Deposit metal 7 by evaporation. The total thickness of the deposited metal 7 should not exceed the thickness of the third photoresist layer 6. Remove the third photoresist layer 6 and excess metal 7. In the background art, the thickness of metal 7 (generally, the thickness of gate metal 7 is 5000~6500 Å) is limited by the gate linewidth. With a small linewidth, but with a thick metal 7, the gate metal 7 is prone to breakage (light at the top, middle, and bottom). This invention uses PI filling to greatly improve the process window, which allows the thickness of the gate metal 7 to be increased while keeping other conditions unchanged, thereby reducing the gate resistance. Please continue reading. Figures 1 to 4 As shown, in one embodiment of the present invention, the coating thickness of the first photoresist layer 2 is no greater than 10,000 Å. This layer thickness plays a role in determining the shape of the gate metal 7 in the invention; it should not be too thick to avoid cracks in the gate metal 7 after evaporation. Please continue reading. Figure 5 As shown, in one embodiment of the present invention, the coating thickness of the polyimide (PI) is 500~3000 Å.

[0019] Please continue reading. Figure 6 As shown, in one embodiment of the present invention, when the second photoresist layer 5 is coated, the thickness does not exceed 3000 Å when the gate linewidth is not greater than 0.5 μm; if the gate linewidth is greater than 0.3 μm, the photoresist thickness is greater than 3000 Å.

[0020] Please continue reading. Figure 8As shown, in one embodiment of the present invention, the coating thickness of the third photoresist layer 6 is 10000 Å.

[0021] Please continue reading. Figure 9 As shown, in one embodiment of the present invention, the metal 7 in the operation vapor deposition is Ti, PT or Au.

[0022] Please continue reading. Figures 3 to 4 As shown, in one embodiment of the present invention, after defining the etch width of the cap layer using the overlay process in step S1, the step further includes a baking step.

[0023] Please continue reading. Figures 3 to 4 As shown, in one embodiment of the present invention, the baking temperature is 100°C to 125°C, and the baking time is 20 min to 40 min. When the CD requirement is small, the baking process can reduce the CD.

[0024] Please continue reading. Figures 3 to 4 As shown, in one embodiment of the present invention, the baking in step S2 is carried out in a stepped manner: baking at 90°C to 120°C for 10 to 15 minutes; baking at 150°C for 10 minutes; baking at 200°C for 10 to 20 minutes; baking at 250°C for 10 to 20 minutes; and baking at 300°C for 30 to 60 minutes. This stepped approach avoids film defects caused by vigorous evaporation. Pre-bake primarily removes solvents and stabilizes the film; then curing occurs, triggering the main imidization reaction to form a stable polyimide film.

[0025] Please continue reading. Figures 3 to 4 As shown, in one embodiment of the present invention, the baking temperature in step S3 is 145-155°C and the baking time is 25-35 min. Specific Implementation Example 1:

[0026] 1. A first photoresist layer 2 with a thickness of no more than 10,000 Å is coated on the source and drain metals 7; Then it is divided into two cases, mainly because different patterning line widths determine different GaAs material etching widths; like Figure 1 As shown, after patterning the photoresist, the CD is relatively large, and after wet etching, the linewidth of the GaAs substrate 1 is also relatively large, such as... Figure 2 As shown; exist Figure 1 Based on the baking process, the CD can be reduced as follows: Figure 3 As shown, the etch width is smaller within the same etch time, such as Figure 4 As shown; 2. Remove the first photoresist layer 2 and coat it with polyimide (PI) to a thickness of 500~3000 Å, such as... Figure 5 The thickness of this layer in this embodiment plays a role in determining the shape of the gate metal 7. It should not be too thick to avoid cracks in the gate metal 7 after evaporation. 3. Coat the second photoresist layer 5. When the gate linewidth is no greater than 0.5 μm, the thickness should not exceed 3000 Å; if the gate linewidth is greater than 0.3 μm, the photoresist thickness should be greater than 3000 Å. Develop the photoresist and bake it as follows: Figure 6 The purpose of baking is to make the photoresist profile angled so that the profile can be overlaid onto the PI, so that the gate metal 7 can be smoothly laid on the PI (avoiding cracks in the metal 7). 3. Use dry etching oxygen plasma to etch PI down to the etched layer on the GaAs substrate; such as Figure 7 As shown; 4. Remove the second photoresist layer 5 and coat the third photoresist layer 6; the third photoresist layer is a negative photoresist with a thickness of 10000 Å, and after development, it appears as follows. Figure 8 As shown; 5. For the vapor deposition process, metal 7 is typically Ti / PT / Au, and the total thickness should not exceed the thickness of the third photoresist layer 6. Figure 9 As shown; in this embodiment, the use of PI filling greatly improves the process window, which can increase the thickness of the gate metal 7 while keeping other conditions unchanged, thereby reducing the gate resistance; 6. After removing the photoresist, as shown Figure 10 As shown; the gate fabrication process is complete; This invention operates on the following principle: By pre-etching away the GaAs cap layer, it avoids the cracking of the metal 7 after evaporation caused by the photoresist warping after etching; by using a photoresist topography overlay process, the photoresist topography defining the photoresist linewidth is overlaid onto the PI using dry etching, thus optimizing the gate critical dimension (Gate). CD) Out of control and deviation; using PI as the gate metal 7 filler eliminates the need for removal; allowing the metal 7 to lie on the PI, especially for small linewidths such as 0.1um, avoids the gate being broken due to the small linewidth during NMP photoresist removal, greatly improving gate yield; using PI filler greatly improves the process window, allowing the gate metal 7 thickness to be increased while other conditions remain unchanged, thus reducing gate resistance; the device breakdown voltage is proportional to the etching width; the cap layer etching width is defined in the first photoresist layer 2, thus removing the definition of breakdown voltage from the original gate etching process, simplifying the process; and avoiding the original practice of increasing etching time to meet the required gate breakdown voltage value, which exacerbates the possibility of photoresist warping and increasing the possibility of metal 7 cracks, and also increases the possibility of linewidth defocusing.

[0027] The above description is only a preferred embodiment of the present invention and should not be construed as a limitation of this application. All equivalent changes and modifications made in accordance with the scope of the patent application of the present invention should be included in the scope of the present invention.

Claims

1. A gallium arsenide gate etching and metallization process based on an interface reinforcement layer, characterized in that: The process includes the following steps: Step S1: Coat the first photoresist layer on both the source and drain metals, define the cap layer etching width using an overlay process, and etch the channel into the substrate using a wet etching process. Step S2: Remove the first photoresist layer, coat the polyimide (PI) layer, and bake. Step S3: Coating the second photoresist layer, developing the photoresist, and then baking it; Step S4: Use dry etching oxygen plasma to etch the polyimide (PI) layer down to the GaAs layer to be etched. Step S5: Remove the second photoresist layer, coat the third photoresist layer, and develop. The third photoresist layer is a negative photoresist. Step S6: Perform metal vapor deposition. The total thickness of the vapor-deposited metal should not exceed the thickness of the third photoresist layer. Remove the third photoresist layer and excess metal.

2. The gallium arsenide gate etching and metallization process based on an interface reinforcement layer according to claim 1, characterized in that: The coating thickness of the first photoresist layer is no greater than 10000. .

3. The gallium arsenide gate etching and metallization process based on an interface reinforcement layer according to claim 1, characterized in that: The coating thickness of the polyimide (PI) is 500~3000 mm. .

4. The gallium arsenide gate etching and metallization process based on an interface reinforcement layer according to claim 1, characterized in that: When coating the second photoresist layer, the thickness should not exceed 3000 μm when the gate linewidth is no greater than 0.5 μm. ; If the gate linewidth is greater than 0.3µm and the photoresist thickness is greater than 3000µm... .

5. The gallium arsenide gate etching and metallization process based on an interface reinforcement layer according to claim 1, characterized in that: The thickness of the third photoresist layer is 10000. .

6. The gallium arsenide gate etching and metallization process based on an interface reinforcement layer according to claim 1, characterized in that: The metal used in the vapor deposition process is Ti, PT, or Au.

7. The gallium arsenide gate etching and metallization process based on an interface reinforcement layer according to claim 1, characterized in that: After defining the cap layer etching width using the overlay process in step S1, the process also includes a baking step.

8. The gallium arsenide gate etching and metallization process based on an interface reinforcement layer according to claim 7, characterized in that: The baking temperature is 100°C to 125°C, and the baking time is 20 minutes to 40 minutes.

9. The gallium arsenide gate etching and metallization process based on an interface reinforcement layer according to claim 1, characterized in that: The baking in step S2 is carried out in a stepped manner: baking at 90°C to 120°C for 10 to 15 minutes; baking at 150°C for 10 minutes; baking at 200°C for 10 to 20 minutes; baking at 250°C for 10 to 20 minutes; and baking at 300°C for 30 to 60 minutes.

10. The gallium arsenide gate etching and metallization process based on an interface reinforcement layer according to claim 1, characterized in that: The baking temperature in step S3 is 145–155°C, and the baking time is 25–35 minutes.

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