Semiconductor device and method of manufacturing the same

Abstract

A method of manufacturing a semiconductor device may include: providing a substrate; forming a source fin region, a source / drain pattern, a gate structure and an inter-gate insulating layer on the substrate; forming a full-height contact part; forming a full-height gate contact part; recessing the first subset of full height contacts and the second subset of full height gate contacts to form reduced height contacts and reduced height gate contacts, respectively; forming an upper insulating pattern; and forming an interconnection pattern on the full height contact, the full height gate contact, and the upper insulating pattern.

Description

Cross-references to related applications

[0001] This patent application claims priority to Korean Patent Application No. 10-2024-0144278, filed on October 21, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly, to a semiconductor device including a field-effect transistor. Background Technology

[0003] Semiconductor devices include integrated circuits composed of metal-oxide-semiconductor field-effect transistors (MOS-FETs). To meet the growing demand for semiconductor devices with smaller pattern sizes and reduced design rules, the size of MOS-FETs is shrinking. This shrinking of MOS-FETs can lead to a degradation in the operating characteristics of semiconductor devices. Accordingly, various studies are underway to overcome the technological limitations associated with the miniaturization of semiconductor devices and to provide high-performance semiconductor devices. Summary of the Invention

[0004] Embodiments of the present invention provide a semiconductor device with improved reliability.

[0005] An embodiment of the present invention provides a semiconductor device with improved electrical characteristics.

[0006] According to embodiments of the present invention, a method of manufacturing a semiconductor device may include: forming an active fin region, a source / drain pattern, a gate structure, and an inter-gate insulating layer on a substrate; forming full-height contacts that penetrate the inter-gate insulating layer and are respectively connected to the source / drain pattern; forming full-height gate contacts that are respectively connected to the gate structure; recessing a first subset of the full-height contacts and a second subset of the full-height gate contacts to form a reduced-height contact and a reduced-height gate contact, respectively; forming an upper insulating pattern on the reduced-height contacts and the reduced-height gate contacts; and forming interconnect patterns on the full-height contacts, the full-height gate contacts, and the upper insulating pattern.

[0007] According to embodiments of the present invention, a method of manufacturing a semiconductor device may include: providing a substrate; forming a source fin region, a source / drain pattern, a gate structure, and an inter-gate insulating layer on the substrate; forming full-height contacts penetrating the inter-gate insulating layer and respectively connected to the source / drain pattern, each full-height contact including a corresponding full-height blocking pattern; forming full-height gate contacts respectively connected to the gate structure, each full-height gate contact including a full-height gate blocking pattern; simultaneously recessing a first subset of the full-height contacts and a second subset of the full-height gate contacts to form a reduced-height contact and a reduced-height gate contact; and forming an upper insulating pattern on the reduced-height contacts and the reduced-height gate contacts. Forming the reduced-height contacts and the reduced-height gate contacts may include: simultaneously removing a portion of the full-height blocking pattern of the first subset of the full-height contacts and a portion of the full-height gate blocking pattern of the second subset of the full-height gate contacts.

[0008] According to embodiments of the present invention, a method of manufacturing a semiconductor device may include: providing a substrate; forming an active fin region on the substrate; forming a gate structure on the active fin region; forming a first source / drain pattern and a second source / drain pattern on a first active fin region and a second active fin region of the substrate, respectively; forming an inter-gate insulating layer to cover the first source / drain pattern and the second source / drain pattern; forming full-height contacts that are respectively connected to the first source / drain pattern and penetrate the inter-gate insulating layer; forming full-height gate contacts that are respectively connected to the gate structure; recessing a first subset of the full-height contacts to form a reduced-height contact; recessing a second subset of the full-height gate contacts to form a reduced-height gate contact; forming an upper insulating pattern on the reduced-height contacts and the reduced-height gate contacts; and forming interconnect patterns on the full-height contacts, the full-height gate contacts, and the upper insulating pattern. The first subset of the full-height contact portion and the second subset of the full-height gate contact portion can be recessed simultaneously, and the formation of the interconnect pattern can include interconnect patterns spaced apart from each other in a first direction parallel to the substrate, and the interconnect pattern has a line shape extending along a second direction intersecting the first direction. Attached Figure Description

[0009] Figures 1 to 3 This is a conceptual diagram illustrating the logic unit of a semiconductor device according to an embodiment of the present invention.

[0010] Figure 4 This is a plan view illustrating a semiconductor device according to an embodiment of the present invention.

[0011] Figures 5A to 5D They are respectively along Figure 4 The cross-sectional views taken from lines A-A', B-B', C-C' and D-D'.

[0012] Figure 5EThis is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention, and corresponding to... Figure 4 The line C-C'.

[0013] Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A and Figure 11A It is along Figure 4 A cross-sectional view taken along line B-B' is used to illustrate a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0014] Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B and Figure 11B It is along Figure 4 A cross-sectional view taken along line D-D' is used to illustrate a method for manufacturing a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0015] Exemplary embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, which illustrate exemplary embodiments. However, the inventive concept can be embodied in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein. It should also be emphasized that this disclosure provides details of alternative examples, but such enumeration of alternatives is not exhaustive. Furthermore, any consistency in detail among the various examples should not be construed as requiring such detail. Refer to the language of the claims when determining the claims of the invention.

[0016] Throughout this specification, when a component is described as "comprising" a particular element or group of elements, it should be understood that the component is formed solely by that element or group of elements, or that the element or group of elements may be combined with additional elements to form the component, unless the context otherwise indicates. On the other hand, the term "composed of" indicates that the component is formed solely by the listed elements.

[0017] It will be understood that when an element is referred to as being “connected” or “coupled” to another element or “on top of” another element, the element may be directly connected or coupled to the other element or directly on top of the other element, or there may be an intermediate element. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or “in contact” or “on” another element (or in any form that uses the word “in contact”), there is no intermediate element at the point of contact.

[0018] As used herein, components described as "electrically connected" are configured such that electrical signals can be transmitted from one component to another (although such electrical signals may attenuate in strength during transmission and can be transmitted selectively). Furthermore, components with "direct electrical connections" form a common electrical node through electrical connections of one or more conductors (e.g., wires, pads, internal wiring, vias, etc.). Therefore, directly electrically connected components do not include components electrically connected via active elements such as transistors or diodes.

[0019] The terms used in this document (such as "identical," "equal," etc.) when referring to features such as orientation, layout, location, shape, size, composition, quantity, or other measurements do not necessarily mean exactly the same feature, but are intended to cover nearly identical features, including typical variations that may result from conventional manufacturing processes. The term "substantially" may be used in this document to emphasize this meaning.

[0020] The term “substrate” can refer to a base substrate (e.g., the initial semiconductor substrate that forms the wafer substrate in the final wafer product, such as a bulk semiconductor substrate (e.g., formed of crystalline silicon), a silicon-on-insulator (SOI) substrate, etc.), or include such base substrates and stacked structures of layers formed on the base substrate.

[0021] Ordinal numbers such as "first," "second," and "third" can simply be used as labels to distinguish certain elements, steps, etc., from one another. Terms not described using "first," "second," etc., in the specification may still be referred to as "first" or "second" in the claims. Furthermore, a term referenced with a specific ordinal number in a particular claim (e.g., "first") may be described elsewhere with a different ordinal number (e.g., "second") in the specification or another claim.

[0022] Figures 1 to 3 This is a conceptual diagram illustrating a logic unit of a semiconductor device according to an embodiment of the present invention. Like all semiconductor devices disclosed herein, a semiconductor memory device can be a semiconductor chip. Such a semiconductor chip can be a monolithically (e.g., diced) semiconductor device formed from a wafer (which may be formed from a substrate (e.g., a bulk silicon substrate, a bulk germanium substrate, silicon-on-insulator (SOI) etc.) or from a combination of several component wafers (each component wafer having a corresponding substrate).

[0023] Reference Figure 1A single-height cell (SHC) can be configured. For example, a first power line M1_R1 and a second power line M1_R2 can be provided on the substrate 100. The first power line M1_R1 can be a conductive path supplied with a source voltage VSS (e.g., ground voltage). The second power line M1_R2 can be a conductive path supplied with a drain voltage VDD (e.g., power supply voltage).

[0024] A single-height cell SHC can be defined between a first power line M1_R1 and a second power line M1_R2. The single-height cell SHC may include a first active region AR1 and a second active region AR2. One of the first active region AR1 and the second active region AR2 may be a PMOSFET region, and the other of the first active region AR1 and the second active region AR2 may be an NMOSFET region. For example, the single-height cell SHC may have a CMOS structure disposed between the first power line M1_R1 and the second power line M1_R2.

[0025] Each of the first active region AR1 and the second active region AR2 may have a first width W1 in the first direction D1. The length of the single-height cell SHC in the first direction D1 may be defined as the first height HE1. The first height HE1 may be equal to or substantially equal to the distance (e.g., spacing) between the first power line M1_R1 and the second power line M1_R2.

[0026] A single-height cell (SHC) can constitute a single logic cell. In this disclosure, a logic cell can be a logic device configured to perform a specific function (e.g., AND, OR, XOR, XNOR, inverter, etc.). For example, a logic cell may include transistors constituting a logic device and interconnects connecting the transistors to each other.

[0027] Reference Figure 2 A dual-height cell (DHC) can be configured. For example, a first power line M1_R1, a second power line M1_R2, and a third power line M1_R3 can be provided on the substrate 100. The first power line M1_R1 can be located between the second power line M1_R2 and the third power line M1_R3. The third power line M1_R3 can be a conductive path to which a source voltage VSS is supplied.

[0028] The dual-height unit (DHC) can be defined between the second power line M1_R2 and the third power line M1_R3. The dual-height unit (DHC) may include a pair of first active regions AR1 and a pair of second active regions AR2.

[0029] One of the pair of second active regions AR2 may be adjacent to the second power line M1_R2. The other of the pair of second active regions AR2 may be adjacent to the third power line M1_R3. The pair of first active regions AR1 may be adjacent to the first power line M1_R1. When viewed in a plan view, the first power line M1_R1 may be positioned between the pair of first active regions AR1.

[0030] The length of the dual-height unit DHC in the first direction D1 can be defined as the second height HE2. The second height HE2 can be... Figure 1 The first height HE1 is twice or approximately twice the height of the first active region AR1 in the dual-height unit DHC. The pair of first active regions AR1 of the dual-height unit DHC can be combined to be used as a single active region.

[0031] In an embodiment, Figure 2 The dual-height unit (DHC) in the diagram can be defined as a multi-height unit. Although not shown, a multi-height unit may include a triple-height unit, the height of which is approximately three times the height of the single-height unit (SHC).

[0032] Reference Figure 3 The first single-height cell SHC1, the second single-height cell SHC2, and the double-height cell DHC can be arranged two-dimensionally on the substrate 100. The first single-height cell SHC1 can be disposed between the first power line M1_R1 and the second power line M1_R2. The second single-height cell SHC2 can be disposed between the first power line M1_R1 and the third power line M1_R3. The second single-height cell SHC2 can be adjacent to the first single-height cell SHC1 in the first direction D1.

[0033] The dual-height unit DHC can be located between the second power line M1_R2 and the third power line M1_R3. The dual-height unit DHC can be adjacent to the first single-height unit SHC1 and the second single-height unit SHC2 in the second direction D2.

[0034] The partition structure DB can be disposed between the first single-height unit SHC1 and the dual-height unit DHC, and between the second single-height unit SHC2 and the dual-height unit DHC. The active region of the dual-height unit DHC can be electrically separated from the active regions of each of the first single-height unit SHC1 and the second single-height unit SHC2 through the partition structure DB.

[0035] Figure 4 This is a plan view illustrating a semiconductor device according to an embodiment of the present invention. Figures 5A to 5D It is along Figure 4 The cross-sectional views taken from lines A-A', B-B', C-C' and D-D'. Figure 4 and Figures 5A to 5DThe semiconductor devices in can be Figure 1 An example of a single-height unit (SHC) in [the context of the text].

[0036] Reference Figure 4 and Figures 5A to 5D A single-height cell (SHC) can be disposed on the substrate 100. Logic transistors constituting logic circuits can be disposed on the single-height cell (SHC). The substrate 100 can be a semiconductor substrate formed of and / or comprising silicon, germanium, silicon-germanium, or compound semiconductor materials. In an embodiment, the substrate 100 can be a silicon substrate.

[0037] A single-height element SHC may have a first boundary BD1 and a second boundary BD2, which are opposite to each other in a second direction D2. The first boundary BD1 and the second boundary BD2 may extend along the first direction D1. The single-height element SHC may have a third boundary BD3 and a fourth boundary BD4, which are opposite to each other in the first direction D1. The third boundary BD3 and the fourth boundary BD4 may extend along the second direction D2.

[0038] A pair of partition structures DB can be provided on opposite sides of a single-height cell SHC, with the pair of partition structures DB facing each other in the second direction D2. For example, a pair of partition structures DB can be provided on the first boundary BD1 and the second boundary BD2 of the single-height cell SHC, respectively. The partition structures DB can extend longitudinally along the first direction D1, parallel to the gate electrode GE. The spacing between the partition structure DB and its adjacent gate electrode GE can be equal to a first spacing.

[0039] The substrate 100 may include a first active region AR1 and a second active region AR2. Each of the first active region AR1 and the second active region AR2 may extend along a second direction D2.

[0040] The first active pattern AP1 and the second active pattern AP2 may be defined by trenches formed in the upper portion of the substrate 100 (e.g., the first active pattern AP1 and the second active pattern AP2 may each be surrounded by trenches formed in the upper portion of the substrate). The first active pattern AP1 may be disposed on a first active region AR1, and the second active pattern AP2 may be disposed on a second active region AR2. The first active pattern AP1 and the second active pattern AP2 may extend along a second direction D2. The first active pattern AP1 and the second active pattern AP2 may be vertically projecting portions of the substrate 100.

[0041] The first active pattern AP1 and the second active pattern AP2, protruding above the device isolation layer ST, can form a first active fin region FN1 and a second active fin region FN2. The first active fin region FN1 and the second active fin region FN2 can be active fin regions FS. The first active fin region FN1 can be disposed on the first active pattern AP1. The second active fin region FN2 can be disposed on the second active pattern AP2.

[0042] The first active pattern AP1 and the second active pattern AP2 may be disposed adjacent to each other in a first direction D1 parallel to the bottom surface of the substrate 100. Each of the first active pattern AP1 and the second active pattern AP2 may extend along a second direction D2, which is parallel to the bottom surface of the substrate 100 and not parallel to the first direction D1 (e.g., orthogonal). Each of the first active pattern AP1 and the second active pattern AP2 may protrude upward from the substrate 100 in a third direction D3 perpendicular to the first direction D1 and the second direction D2.

[0043] A device isolation layer ST can be disposed on the substrate 100. The device isolation layer ST can be configured to fill the region between the first active pattern AP1 and the second active pattern AP2, which are spaced apart from each other. The device isolation layer ST may not cover the active fin region FS (e.g., the upper surface of the device isolation layer ST may be lower than the upper surface of the active fin region FS).

[0044] Multiple first source / drain patterns SD1 can be disposed on a first active pattern AP1. The first source / drain patterns SD1 can each be disposed within a first recess RS1 formed in a first active fin region FN1. The first source / drain patterns SD1 can be impurity regions of a first conductivity type (e.g., p-type). A channel pattern can be located between a pair of first source / drain patterns SD1. The first active fin region FN1 located between the pair of first source / drain patterns SD1 can be used as a channel region.

[0045] Multiple second source / drain patterns SD2 can be disposed on the second active pattern AP2. The second source / drain patterns SD2 can each be disposed within a second recess RS2 formed in the second active fin region FN2. The second source / drain patterns SD2 can be impurity regions of a second conductivity type (e.g., n-type), which may be different from the first conductivity type. A channel pattern can be located between a pair of second source / drain patterns SD2. The second active fin region FN2 located between the pair of second source / drain patterns SD2 can be used as a channel region.

[0046] The first source / slot pattern SD1 and the second source / slot pattern SD2 can be spaced apart from each other in the first direction D1 and the second direction D2.

[0047] The active fin region FS can be located between the source / drain patterns SD1 and SD2. The source / drain patterns SD1 and SD2 can cover the side surface of the active fin region FS, and the height of the bottom surface of the source / drain patterns SD1 and SD2 can be lower than the top surface of the active fin region FS.

[0048] The source / drain patterns SD1 and SD2 can be epitaxial patterns formed by a selective epitaxial growth (SEG) process. The source / drain patterns SD1 and SD2 can be epitaxial growth patterns formed from at least one of silicon germanium (SiGe), silicon (Si), or silicon carbide (SiC).

[0049] In an embodiment, the first source / drain pattern SD1 may be formed of a semiconductor material (e.g., SiGe) with a lattice constant greater than that of the semiconductor material of the substrate 100, and / or may include a semiconductor material with a lattice constant greater than that of the semiconductor material of the substrate 100. Therefore, a pair of first source / drain patterns SD1 may apply compressive strain to the channel pattern (i.e., the first active fin region FN1) therebetween.

[0050] The second source / drain pattern SD2 may be formed of and / or include the same semiconductor element as the substrate 100 (e.g., Si). Therefore, a pair of second source / drain patterns SD2 may apply tensile strain to the channel pattern (i.e., the second active fin region FN2) between them.

[0051] In an embodiment, the second source / drain pattern SD2 may have an uneven or embossed side surface. For example, the side surface of the second source / drain pattern SD2 may have a wavy or serrated profile. The side surface of the second source / drain pattern SD2 may be a portion protruding toward the second active fin region FN2.

[0052] The gate structure GST can be disposed on the first active fin region FN1 and the second active fin region FN2. The gate structure GST may include a gate insulating pattern GI, a gate electrode GE on the gate insulating pattern GI, a gate capping pattern GP on the gate electrode GE, and a gate spacer GS in contact with the gate insulating pattern GI and the gate capping pattern GP.

[0053] The gate insulating pattern GI can conformally cover the exposed top surface of the device isolation layer ST, as well as the exposed top and side surfaces of the first active fin region FN1 and the second active fin region FN2. The gate insulating pattern GI can be formed from at least one of silicon oxide or a high-k dielectric material (e.g., HfO2, HfSiO, HfSiON, HfON, HfAlO, HfLaO, and TaO2) and / or include at least one of silicon oxide or a high-k dielectric material.

[0054] The gate electrode GE can be disposed on the gate insulating pattern GI. In an embodiment, multiple gate electrodes GE can be disposed. The gate insulating pattern GI can be located between the gate electrode GE and the first active fin region FN1 and the second active fin region FN2. The gate electrode GE can be formed and / or comprise a conductive material, and can be formed and / or comprise at least one of a conductive metal nitride material (e.g., titanium nitride or tantalum nitride) or a metallic material (e.g., aluminum or tungsten).

[0055] Each gate electrode GE may extend longitudinally along a first direction D1. Each gate electrode GE may vertically overlap with a first active fin region FN1 and a second active fin region FN2. The gate electrodes GE may be arranged to be spaced apart from each other at a first pitch in a second direction D2. The gate electrodes GE may extend longitudinally along the first direction D1 and may be arranged to be spaced apart from each other in a second direction D2 that is not parallel to the first direction D1.

[0056] A gate capping pattern GP may be disposed on the gate electrode GE. The gate capping pattern GP may cover the top surface of the gate electrode GE and may extend along a first direction D1. The gate capping pattern GP may include a material having etch selectivity relative to the first interlayer insulating layer 120 described below. The gate capping pattern GP may be formed of and / or include at least one of SiON, SiCN, SiCON, or SiN.

[0057] A gate spacer GS can be disposed on the opposite side surface of the gate electrode GE and the opposite side surface of the gate cap pattern GP. The gate spacer GS can extend along the extension direction of the gate electrode GE on the opposite side surface of the gate electrode GE. A gate insulating pattern GI can be located between the gate electrode GE and the gate spacer GS. In an embodiment, the gate spacer GS can be formed and / or include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or combinations thereof.

[0058] An inter-gate insulating layer 132 may be disposed between adjacent gate structures GST to cover the first source / drain pattern SD1 and the second source / drain pattern SD2. The inter-gate insulating layer 132 may be formed of at least one of silicon nitride, silicon oxide, or silicon oxynitride and / or include at least one of silicon nitride, silicon oxide, or silicon oxynitride.

[0059] In embodiments, the gate insulating pattern GI may include a silicon oxide layer, a silicon oxynitride layer, and / or a high-k dielectric layer. For example, the gate insulating pattern GI may have a structure of stacked silicon oxide layers and high-k dielectric layers. The high-k dielectric layer may be formed of and / or include a high-k dielectric material with a dielectric constant higher than that of silicon oxide. For example, the high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0060] In embodiments, the semiconductor device may include a negative capacitance (NC) FET that uses a negative capacitor. For example, the gate insulating pattern GI may include a ferroelectric layer exhibiting ferroelectric properties and a paraelectric layer exhibiting paraelectric properties.

[0061] The ferroelectric layer can have negative capacitance, and the paraelectric layer can have positive capacitance. When two or more capacitors are connected in series and each capacitor has positive capacitance, the total capacitance can be reduced to less than the value of each individual capacitor's capacitance. Conversely, when at least one capacitor in series has negative capacitance, the total capacitance of the series capacitors can have a positive value and can be greater than the absolute value of each individual capacitor's capacitance.

[0062] When a ferroelectric layer with negative capacitance and a paraelectric layer with positive capacitance are connected in series, the total capacitance of the series-connected ferroelectric and paraelectric layers can be increased. Due to this increase in total capacitance, a transistor including the ferroelectric layer can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0063] The ferroelectric layer can possess ferroelectric properties. The ferroelectric layer can be formed from, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and / or lead zirconium titanium oxide, and / or include at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and / or lead zirconium titanium oxide. Hafnium zirconium oxide can be hafnium oxide doped with zirconium (Zr). Alternatively, hafnium zirconium oxide can be a compound composed of hafnium (Hf), zirconium (Zr), and / or oxygen (O).

[0064] The ferroelectric layer may also include dopants. Dopants may include at least one of the following: aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), or tin (Sn). The type of dopant in the ferroelectric layer may vary depending on the ferroelectric material included in the ferroelectric layer.

[0065] When the ferroelectric layer includes hafnium oxide, the dopant in the ferroelectric layer may include at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al) and / or yttrium (Y).

[0066] When the dopant is aluminum (Al), the aluminum content in the ferroelectric layer can range from 3 at% to 8 at% (atomic percentage). Here, the dopant content (e.g., aluminum atoms) can be the ratio of the number of aluminum atoms to the total number of hafnium and aluminum atoms.

[0067] When the dopant is silicon (Si), the silicon content in the ferroelectric layer can range from 2 at% to 10 at%. When the dopant is yttrium (Y), the yttrium content in the ferroelectric layer can range from 2 at% to 10 at%. When the dopant is gadolinium (Gd), the gadolinium content in the ferroelectric layer can range from 1 at% to 7 at%. When the dopant is zirconium (Zr), the zirconium content in the ferroelectric layer can range from 50 at% to 80 at%.

[0068] The paraelectric layer may have paraelectric properties. The paraelectric layer may be formed from, for example, at least one of silicon oxide and / or a high-k metal oxide material, and / or include at least one of silicon oxide and / or a high-k metal oxide material. Metal oxide materials that can be used as the paraelectric layer may include, for example, at least one of hafnium oxide, zirconium oxide, and / or aluminum oxide, but the inventive concept is not limited to these examples.

[0069] The ferroelectric layer and the paraelectric layer can be formed from and / or comprise the same material. The ferroelectric layer may have ferroelectric properties, but the paraelectric layer may not. For example, in the case where both the ferroelectric and paraelectric layers contain hafnium oxide, the crystal structure of the hafnium oxide in the ferroelectric layer may differ from the crystal structure of the hafnium oxide in the paraelectric layer.

[0070] A ferroelectric layer exhibits ferroelectric properties only when its thickness is within a specific range. In embodiments, the thickness of the ferroelectric layer can range from 0.5 nm to 10 nm, but the inventive concept is not limited to this example. Since the critical thickness associated with the occurrence of ferroelectric properties varies depending on the type of ferroelectric material, the thickness of the ferroelectric layer can also vary depending on the type of ferroelectric material.

[0071] For example, the gate insulating pattern GI may include a single ferroelectric layer. As another example, the gate insulating pattern GI may include multiple ferroelectric layers spaced apart from each other. The gate insulating pattern GI may have a multilayer structure in which multiple ferroelectric layers and multiple paraelectric layers are stacked alternately.

[0072] The first interlayer insulating layer 120 may be disposed on the gate structure GST. The first interlayer insulating layer 120 may be disposed on the gate structure GST and the gate interlayer insulating layer 132. The first interlayer insulating layer 120 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or tetraethyl orthosilicate (TEOS).

[0073] First active contact AC1 and second active contact AC2 can be respectively disposed on first source / drain pattern SD1 and second source / drain pattern SD2. In the following description, an active contact is a contact that is connected to the source / drain pattern of the active fin region. Gate contact GC can be disposed on gate structure GST. In the following description, a gate contact is a contact that is connected to gate structure GST. Contacts such as active contacts or gate contacts can be referred to as long contacts or short contacts depending on their relative height. Long contacts can be full-height contacts, and short contacts can be reduced-height contacts. A reduced-height contact refers to a contact that was initially a full-height contact but whose height was subsequently reduced in another process.

[0074] Interconnect layer M1 may be disposed on the first interlayer insulating layer 120. Interconnect layer M1 may include interconnect insulating layer 130 and interconnect pattern M1_I. Interconnect pattern M1_I may include a first power line M1_R1, a second power line M1_R2, and interconnect pattern M1_I. The interconnect lines M1_R1, M1_R2, and M1_I of interconnect layer M1 may extend along the second direction D2 and be parallel to each other.

[0075] For example, the first power line M1_R1 and the second power line M1_R2 can be respectively located at the third boundary BD3 and the fourth boundary BD4 of the single-height unit SHC. The first power line M1_R1 can extend along the third boundary BD3 in the second direction D2. The second power line M1_R2 can extend along the fourth boundary BD4 in the second direction D2.

[0076] The interconnect pattern M1_I of the interconnect layer M1 can be disposed between the first power line M1_R1 and the second power line M1_R2. The interconnect pattern M1_I of the interconnect layer M1 can be arranged to be spaced apart from each other in a first direction D1 parallel to the substrate 100. The interconnect pattern M1_I can be a line pattern extending along a second direction D2 intersecting the first direction D1. The linewidth of each interconnect pattern M1_I can be smaller than the linewidth of each of the first power line M1_R1 and the second power line M1_R2.

[0077] Return to reference Figure 4 and Figures 5A to 5DThe first active contact AC1 and the second active contact AC2 can be configured to penetrate the gate inter-insulating layer 132 and the first inter-layer insulating layer 120, and can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. A pair of active contacts AC1 and AC2 can be respectively disposed on opposite sides of the gate electrode GE. When viewed in a plan view, each of the first active contact AC1 and the second active contact AC2 can be a strip pattern extending along the first direction D1.

[0078] A first active contact AC1 may be connected to a first source / drain pattern SD1. The first active contact AC1 may be a self-aligned contact. For example, the first active contact AC1 may be formed using a gate cap pattern GP and a gate spacer GS via a self-aligned process. For example, the first active contact AC1 may cover at least a portion of the side surface of the gate spacer GS. Although not shown, each of the first active contact AC1 and the second active contact AC2 may cover a portion of the top surface of the gate cap pattern GP.

[0079] A metal-semiconductor compound layer SC (e.g., a silicide layer) may be located between a first active contact AC1 and a first source / drain pattern SD1, and between a second active contact AC2 and a second source / drain pattern SD2. The first active contact AC1 and the second active contact AC2 may be electrically connected to the source / drain patterns SD1 and SD2 via the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound layer SC may be formed of and / or include at least one of titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, or cobalt silicide.

[0080] The gate contact GC can be configured to penetrate the inter-gate insulating layer 132 and the first inter-layer insulating layer 120, and can be electrically connected to the gate electrode GE, respectively. When viewed in a plan view, the gate contact GC can overlap with the first active region AR1 and the second active region AR2, respectively.

[0081] The first active contact AC1 may include a first long active contact tAC1 and a first short active contact sAC1. Compared to the position of the first short active contact sAC1, the first long active contact tAC1 may be located closer to the gate contact GC. The length of the first long active contact tAC1 on the third direction D3 may be greater than the length of the first short active contact sAC1 on the third direction D3.

[0082] The first long active contact tAC1 may include a first long active conductive pattern tAFM1 and a first long active blocking pattern tABM1 surrounding the first long active conductive pattern tAFM1.

[0083] The first long active barrier pattern tABM1 may cover the side and bottom surfaces of the first long active conductive pattern tAFM1. The height of the top surface tABM1TS of the first long active barrier pattern tABM1 may be equal to or the same as the height of the top surface tAFM1TS of the first long active conductive pattern tAFM1. Here, height may refer to the distance from the substrate 100 measured along the third direction D3. For example, the expression "heights are equal" may mean that the distances from the substrate 100 measured along the third direction D3 are equal to each other.

[0084] The first long active contact tAC1 can be connected to the interconnect pattern M1_I. The top surface of the first long active contact tAC1 can contact the interconnect pattern M1_I. The top surface tAFM1TS of the first long active conductive pattern tAFM1 can contact the interconnect pattern M1_I. The top surface tABM1TS of the first long active blocking pattern tABM1 can contact the interconnect pattern M1_I. Since the first long active contact tAC1 is connected to the interconnect pattern M1_I, the first source / drain pattern SD1 and the interconnect pattern M1_I can be electrically connected to each other through the first long active contact tAC1.

[0085] The first short active contact sAC1 may include a first short active conductive pattern sAFM1 and a first short active barrier pattern sABM1 surrounding the first short active conductive pattern sAFM1. The first short active barrier pattern sABM1 may cover a portion of the side surface and the bottom surface of the first short active conductive pattern sAFM1. The first short active barrier pattern sABM1 may contact the upper insulating pattern UIP.

[0086] The height of the top surface sABM1TS of the first short active barrier pattern sABM1 can be lower than the height of the top surface tABM1TS of the first long active barrier pattern tABM1. The height of the top surface sABM1TS of the first short active barrier pattern sABM1 can be lower than the height of the top surface sAFM1TS of the first short active conductive pattern sAFM1. The height of the top surface sAFM1TS of the first short active conductive pattern sAFM1 can be lower than the height of the top surface tABM1TS of the first long active barrier pattern tABM1. Here, height can refer to the distance from the substrate 100 measured along the third direction D3. For example, stating "the height of element A is lower than the height of element B" can mean that the distance of element A from the substrate 100 along the third direction D3 is less than the distance of element B from the substrate 100.

[0087] The upper insulating pattern UIP can be disposed on the first short active contact sAC1. The top surface sABM1TS of the first short active blocking pattern sABM1 and the top surface sAFM1TS of the first short active conductive pattern sAFM1 can contact the upper insulating pattern UIP. The first short active contact sAC1 and the interconnecting pattern M1_I can be spaced apart from each other by the upper insulating pattern UIP. The first short active contact sAC1 and the interconnecting pattern M1_I can be electrically separated from each other by the upper insulating pattern UIP.

[0088] Each of the first long active conductive pattern tAFM1 and the first short active conductive pattern sAFM1 may be formed by and / or include at least one metallic material (e.g., aluminum, copper, tungsten, molybdenum, and cobalt).

[0089] Each of the first long active blocking pattern tABM1 and the first short active blocking pattern sABM1 may include a metal layer or a metal nitride layer. The metal layer may be formed of at least one of titanium, tantalum, tungsten, nickel, cobalt, or platinum and / or include at least one of titanium, tantalum, tungsten, nickel, cobalt, or platinum. The metal nitride layer may be formed of at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN) and / or include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN).

[0090] The gate contact GC may include a long gate contact tGC and a short gate contact sGC. The bottom surface of the long gate contact tGC may be connected to the gate electrode GE, and the top surface of the long gate contact tGC may be in contact with the interconnect pattern M1_I. The bottom surface of the short gate contact sGC may be connected to the gate electrode GE, and the top surface of the short gate contact sGC may be spaced apart from the interconnect pattern M1_I and in contact with the upper insulating pattern UIP.

[0091] The long gate contact tGC may include a long gate conductive pattern tGFM and a long gate blocking pattern tGBM surrounding the long gate conductive pattern tGFM. The short gate contact sGC may include a short gate conductive pattern sGFM and a short gate blocking pattern sGBM surrounding the short gate conductive pattern sGFM. The area on the short gate contact sGC may be filled with an upper insulating pattern UIP.

[0092] The top surface of the long gate contact tGC can contact the interconnect pattern M1_I. The top surface tGFMTS of the long gate conductive pattern tGFM can contact the interconnect pattern M1_I. The top surface tGBMTS of the long gate blocking pattern tGBM can contact the interconnect pattern M1_I.

[0093] The top surface of the short gate contact sGC and the interconnect pattern M1_I can be spaced apart from each other. The top surface of the short gate conductive pattern sGFM sGFMTS and the interconnect pattern M1_I can be spaced apart from each other. The top surface of the short gate blocking pattern sGBM sGBMTS and the interconnect pattern M1_I can be spaced apart from each other.

[0094] The height of the top surface of the short gate conductive pattern sGFM can be equal to or the same as the height of the top surface of the short active conductive pattern sAFM.

[0095] The height of the top surface of the short gate contact sGC can be lower than the height of the top surface of the long gate contact tGC. The height of the top surface sGFMTS of the short gate conductive pattern sGFM can be lower than the height of the top surface tGFMTS of the long gate conductive pattern tGFM. The height of the top surface sGBMTS of the short gate blocking pattern sGBM can be lower than the height of the top surface tGBMTS of the long gate blocking pattern tGBM. The height of the top surface sGBMTS of the short gate blocking pattern sGBM can be lower than the height of the top surface sGFMTS of the short gate conductive pattern sGFM.

[0096] The upper portion of the first short active contact sAC1 adjacent to the long gate contact tGC can be filled with an upper insulating pattern UIP. For example, the upper portion of the first short active contact sAC1 adjacent to the long gate contact tGC can be prevented from horizontally overlapping the long gate contact tGC (i.e., in the first direction D1 and the second direction D2) by the upper insulating pattern UIP. Therefore, it is possible to prevent the adjacent long gate contact tGC and the first short active contact sAC1 from contacting each other and to prevent short circuits between them.

[0097] The second active contact AC2 can be connected to the second source / drain pattern SD2. The second active contact AC2 can be configured to have the same or substantially the same characteristics as the first active contact AC1.

[0098] Figure 5E This is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention, and corresponding to... Figure 4 The line C-C'. For the sake of brevity, previously described elements may be identified by the same reference numerals without repeating their description.

[0099] Reference Figure 5E The gate contact GC may include a long gate contact tGC and a short gate contact sGC. The short gate contact sGC may include a short gate conductive pattern sGFMa and a short gate blocking pattern sGBMa.

[0100] The short gate conductive pattern sGFMa can have a partially recessed shape. For example, the short gate conductive pattern sGFMa can be configured as a stepped shape with a partially recessed region. In this case, the height of the uppermost surface sGFMaT1 of the short gate conductive pattern sGFMa can be greater than the height of the lowermost surface sGFMaT2 of the short gate conductive pattern sGFMa. In this case, the uppermost surface sGFMaT1 of the short gate conductive pattern sGFMa can be defined as the highest part of the top surface of the short gate conductive pattern sGFMa. The lowermost surface sGFMaT2 of the short gate conductive pattern sGFMa can be defined as the lowest part of the top surface of the short gate conductive pattern sGFMa.

[0101] The portion of the short gate conductive pattern sGFMa that vertically overlaps with the interconnect pattern M1_I (e.g., on the third-direction D3) may be recessed. The portion of the short gate conductive pattern sGFMa that does not vertically overlap with the interconnect pattern M1_I (e.g., on the third-direction D3) may not be recessed.

[0102] The recessed portion of the short gate conductive pattern sGFMa can be filled by the upper insulating pattern UIP. The lowermost surface sGFMaT2 of the short gate conductive pattern sGFMa can contact the upper insulating pattern UIP. The uppermost surface sGFMaT1 of the short gate conductive pattern sGFMa can contact the interconnect insulating layer 130.

[0103] The short gate blocking pattern sGBMa can contact the side surface of the short gate conductive pattern sGFMa. The surface of the short gate blocking pattern sGBMa that contacts the recessed portion of the short gate conductive pattern sGFMa can be positioned at a lower height than the surface of the short gate blocking pattern sGBMa that contacts the non-recessed portion of the short gate conductive pattern sGFMa. The side surface of the short gate blocking pattern sGBMa can be located at different heights.

[0104] In an embodiment, the surface of the short gate blocking pattern sGBMa that contacts the recessed portion of the short gate conductive pattern sGFMa can be positioned at the same height as the lowest surface sGFMaT2 of the short gate conductive pattern sGFMa.

[0105] In an embodiment, although not shown, the surface of the short gate blocking pattern sGBMa that contacts the recessed portion of the short gate conductive pattern sGFMa can be set to be lower than the height of the lowest surface sGFMaT2 of the short gate conductive pattern sGFMa.

[0106] Figures 6A to 11A It is along Figure 4 A cross-sectional view taken along line B-B' is used to illustrate a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 6B to 11B It is along Figure 4The cross-sectional view taken along line D-D' is used to illustrate a method of manufacturing a semiconductor device according to an embodiment of the present invention. To avoid repetition, previously described elements may be identified by the same reference numerals, and the previous description applies to these elements, thus requiring no repetition.

[0107] Reference Figure 6A and Figure 6B A substrate 100 may be provided, comprising a first active pattern AP1 and a second active pattern AP2. The first active pattern AP1 and the second active pattern AP2 may be formed on the substrate 100. For example, the substrate 100 may be etched to form trenches, with active patterns formed in the regions between the trenches; active patterns may be epitaxially grown from the substrate 100; or a combination of material removal from the substrate 100 and active pattern growth from the substrate may be performed. A device isolation layer ST may be formed on the substrate 100 to define active fin regions. For example, the device isolation layer ST may be formed as part of a deposition process. Gate structures GST may be formed on the substrate 100 and on the active fin regions, each gate structure GST comprising a gate insulating pattern GI, a gate electrode GE, a gate cap pattern GP, ​​and a gate spacer GS. For example, a gate structure GST may be formed by depositing a material layer of the gate insulating pattern GI, the gate electrode GE, and the gate cap pattern GP, ​​patterning it (e.g., using a selective etching process), and forming a gate spacer on either side of the patterned structure (e.g., by depositing a material layer of the gate spacer and etching it).

[0108] A first source / drain pattern SD1 can be formed on a first active region AR1 of the substrate 100. A second source / drain pattern SD2 can be formed on a second active region AR2 of the substrate 100. For example, the source / drain patterns can be formed by implanting impurities into the active region between the gate structures.

[0109] An inter-gate insulating layer 132 may be formed between spaced-apart gate structures GST to cover the first source / drain pattern SD1 and the second source / drain pattern SD2. For example, the inter-gate insulating layer 132 may be formed as part of a deposition process. A first inter-layer insulating layer 120 may be formed on the inter-gate insulating layer 132 and on the gate cap pattern GP of the gate structure GST. For example, the first inter-layer insulating layer 120 may be formed as part of a deposition process.

[0110] Reference Figure 7A and Figure 7BThe first long active contact tAC1 can be formed to penetrate the first interlayer insulating layer 120, the gate cap pattern GP, ​​and the interlayer insulating layer 132, and can be connected to the first source / drain pattern SD1. The second long active contact tAC2 connected to the second source / drain pattern SD2 can be formed to have a structure similar to the first long active contact tAC1.

[0111] Forming the first long active contact tAC1 may include: forming a first long active blocking pattern tABM1; and forming a first long active conductive pattern tAFM1 on the first long active blocking pattern tABM1.

[0112] For example, a long active contact mask (not shown) can be formed on the first interlayer insulating layer 120, and then this long active contact mask (not shown) can be used as a mask to form a long active contact hole (not shown) to penetrate the first interlayer insulating layer 120, the gate cap pattern GP, ​​the interlayer insulating layer 132, and a portion of the first source / drain pattern SD1. The long active contact hole (not shown) can be formed to expose the first source / drain pattern SD1. For example, an etching process can remove a portion of the first interlayer insulating layer 120, the gate cap pattern GP, ​​the interlayer insulating layer 132, and the first source / drain pattern SD1. A metal semiconductor compound layer SC can be formed on the exposed first source / drain pattern SD1 and along the long active contact hole (not shown). For example, a deposition process can form the metal semiconductor compound layer SC. A first long active barrier pattern tABM1 can be formed on the metal semiconductor compound layer SC and in a long active contact hole (not shown), and a first long active conductive pattern tAFM1 can be formed on the first long active barrier pattern tABM1 to fill the remaining portion of the long active contact hole. For example, the first long active barrier pattern tABM1 and the first long active conductive pattern tAFM1 can be formed in separate deposition processes.

[0113] The first long active contact tAC1 can be connected to the first source / drain pattern SD1. The upper part of the first long active contact tAC1 and the long active contact mask (not shown) can be removed. A planarization process can be performed to expose the top surface of the first interlayer insulating layer 120 and the top surface of the first long active contact tAC1, and to place the top surface of the first interlayer insulating layer 120 and the top surface of the first long active contact tAC1 at the same or substantially the same height. In this specification, the term "substantially the same" can mean that the difference falls within approximately 5% of the tolerance range.

[0114] Reference Figure 8A and Figure 8BA gate mask pattern MS1 ​​can be formed on the top surface of the first interlayer insulating layer 120 and the first long active contact tAC1. The gate mask pattern MS1 ​​can be formed to cover the top surface of the first long active contact tAC1 and pattern the area where the gate contact GC will be formed. The first trench TR1 can be formed by patterning the area where the gate contact GC will be formed using the gate mask pattern MS1. The first trench TR1 can be formed to penetrate the first interlayer insulating layer 120 and the gate cap pattern GP. The first trench TR1 can be formed to expose the inter-gate insulating layer 132. The first trench TR1 can be formed to penetrate a portion of the gate structure GST. Parts of the top surface of the gate electrode GE, the top surface of the gate insulating pattern GI, and the top surface of the gate spacer GS can be exposed through the first trench TR1. For example, an etching process can remove material to form the first trench TR1.

[0115] Reference Figure 9A and Figure 9B A long gate contact tGC can be formed in the first trench TR1. The long gate contact tGC can be connected to the gate structure GST. A long gate blocking pattern tGBM can be formed in and along the first trench TR1, and a long gate conductive pattern tGFM can be formed on the long gate blocking pattern tGBM. For example, the long gate blocking pattern tGBM and the long gate conductive pattern tGFM can be formed in separate deposition processes. The gate mask pattern MS1 ​​can be removed. The top surface of the long gate contact tGC, the top surface of the first interlayer insulating layer 120, and the top surface of the first long active contact tAC1 can be simultaneously planarized and exposed (e.g., they can be planarized in the same process).

[0116] Reference Figure 10A and Figure 10B Some of the first long active contact tAC1 can be recessed to form a first short active contact sAC1 (e.g., a subset of the first long active contact tAC1). Some of the long gate contacts tGC can be recessed by an etching process to form short gate contacts sGC (e.g., a subset of the long gate contacts tGC). Recessing the first long active contact tAC1 and recessing the long gate contacts tGC can be performed simultaneously in the same etching process (e.g., in situ within the same reaction chamber without disrupting the vacuum of the reaction chamber). For example, the first short active contact sAC1 and the short gate contact sGC can be formed simultaneously and are part of the same process.

[0117] Forming the first short active contact sAC1 and the short gate contact sGC may include simultaneously removing a portion of the first long active conductive pattern tAFM1 and a portion of the long gate conductive pattern tGFM to form the first short active conductive pattern sAFM1 and the short gate conductive pattern sGFM, respectively. For example, an etching process may remove both a portion of the first long active conductive pattern tAFM1 and a portion of the long gate conductive pattern tGFM.

[0118] Forming the first short active contact sAC1 and the short gate contact sGC may include simultaneously removing a portion of the first long active blocking pattern tABM1 and a portion of the long gate blocking pattern tGBM to form the first short active blocking pattern sABM1 and the short gate blocking pattern sGBM, respectively.

[0119] The removal depth of the first long active blocking pattern tABM1 can be greater than the removal depth of the first long active conductive pattern tAFM1. Therefore, the height of the top surface sABM1TS of the first short active blocking pattern sABM1 can be lower than the height of the top surface sAFM1TS of the first short active conductive pattern sAFM1.

[0120] The uppermost surface of the first short active contact sAC1 can be the top surface sAFM1TS of the first short active conductive pattern sAFM1. In this case, the height of the uppermost surface of the first short active contact sAC1 can be higher than the height of the uppermost surface of the first short active blocking pattern sABM1.

[0121] The removal depth of the long gate blocking pattern tGBM can be greater than the removal depth of the long gate conductive pattern tGFM. Therefore, the height of the top surface sGBMTS of the short gate blocking pattern sGBM can be lower than the height of the top surface sGFMTS of the short gate conductive pattern sGFM.

[0122] For example, a mask pattern (not shown) may be formed on the planarized top surface of the first interlayer insulating layer 120, the first long active contact tAC1, and the long gate contact tGC. The mask pattern (not shown) may be patterned to expose the regions where the first short active contact sAC1 and the short gate contact sGC are formed.

[0123] Some recesses in the first long active contact tAC1 exposed by the mask pattern (not shown) can be formed to create a first short active contact sAC1 (e.g., a subset of the first long active contact tAC1 recessed in an etching process). The upper portion of the exposed first short active contact sAC1 can be defined as a first hole H1. The first hole H1 can be defined by the first short active contact sAC1 and the first interlayer insulating layer 120.

[0124] When some of the first long active contact tAC1 exposed by the mask pattern (not shown) is recessed, some of the long gate contact tGC exposed by the mask pattern (not shown) can also be recessed. That is, recessing the first long active contact tAC1 and recessing the long gate contact tGC can be performed by a single process (such as an etching process).

[0125] Some recesses in the long gate contact tGC exposed by the mask pattern (not shown) can be formed to create short gate contacts sGC (e.g., a subset of the long gate contacts tGC). The upper portion of the exposed short gate contacts sGC can be defined as a second hole H2. The second hole H2 can be defined by the short gate contacts sGC and the first interlayer insulating layer 120.

[0126] Reference Figure 11A and Figure 11B An upper insulating pattern UIP can be formed to fill the first hole H1 and the second hole H2. The upper insulating pattern UIP can be formed on the first short active contact sAC1 and the short gate contact sGC. For example, the upper insulating pattern UIP can be formed by a deposition process.

[0127] The upper insulating pattern UIP, the top surface of the first long active contact tAC1, the top surface of the first interlayer insulating layer 120, and the long gate contact tGC can be planarized simultaneously (e.g., as part of the same planarization process).

[0128] Return to reference Figure 4 and Figures 5A to 5D The interconnect layer M1 can be formed on the first long active contact tAC1, the long gate contact tGC, the first interlayer insulating layer 120 and the upper insulating pattern UIP.

[0129] Forming the interconnect layer M1 may include forming an interconnect insulating layer 130 on the first long active contact tAC1, the long gate contact tGC, the first interlayer insulating layer 120, and the upper insulating pattern UIP. The interconnect layer M1 can be formed by a deposition process. Alternatively, the interconnect layer M1 can be directly formed on the first long active contact tAC1 and the long gate contact tGC.

[0130] Forming the interconnect layer M1 may include forming an interconnect pattern M1_I using a mask patterning process after forming the interconnect insulating layer 130. The interconnect pattern M1_I may be formed to contact a first long active contact tAC1 and a long gate contact tGC. A first power line M1_R1 and a second power line M1_R2 may be formed. For example, the interconnect pattern M1_I may be formed using a deposition process.

[0131] Semiconductor devices can be manufactured to have the same characteristics as... Figure 4 and Figures 5A to 5DThe same structure as the one in the text.

[0132] In a three-dimensional field-effect transistor according to an embodiment of the present invention, long active contacts, short active contacts, long gate contacts, and short gate contacts can be formed simultaneously (e.g., as part of the same process). The long active contacts and long gate contacts can be connected to interconnect patterns without the use of via plugs. Accordingly, short-circuit faults between the active contacts and the gate contacts can be improved, and the manufacturing process can be simplified by omitting the via layer. The electrical characteristics and reliability of the semiconductor device can be improved.

[0133] While exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: Provide substrate; An active fin region, a source / drain pattern, a gate structure, and an inter-gate insulating layer are formed on the substrate. Form full-height contacts that penetrate the inter-gate insulating layer and are respectively connected to the source / drain patterns; Form full-height gate contacts that are respectively connected to the gate structure; Simultaneously, the first subset of the full-height contact portion and the second subset of the full-height gate contact portion are recessed to form a reduced-height contact portion and a reduced-height gate contact portion, respectively. An upper insulating pattern is formed on the height reduction contact portion and the height reduction gate contact portion; as well as Interconnect patterns are formed on the full-height contact portion, the full-height gate contact portion, and the upper insulating pattern.

2. The method according to claim 1, wherein, Each of the full-height contact portions includes a full-height blocking pattern. Each of the full-height gate contacts includes a full-height gate blocking pattern. Each of the height-reducing contact portions includes a height-reducing blocking pattern. Each of the height reduction gate contacts includes a height reduction gate blocking pattern, and Forming the height reduction blocking pattern and the height reduction gate blocking pattern includes simultaneously removing a portion of the full-height blocking pattern and a portion of the full-height gate blocking pattern.

3. The method according to claim 1, wherein, Each of the reduced-height gate contacts includes a reduced-height gate conductive pattern and a reduced-height gate blocking pattern. Each of the height-reducing contact portions includes a height-reducing conductive pattern and a height-reducing blocking pattern, and The height of the top surface of the reduced-height gate conductive pattern is the same as the height of the top surface of the reduced-height conductive pattern.

4. The method according to claim 1, wherein, Each of the height reduction gate contacts includes a height reduction gate conductive pattern and a height reduction gate blocking pattern, and The height of the top surface of the reduced gate blocking pattern is lower than the height of the top surface of the reduced gate conductive pattern.

5. The method according to claim 1, wherein, Each of the full-height contact portion and the full-height gate contact portion contacts the corresponding interconnect pattern, and The height reduction contact portion and the height reduction gate contact portion are spaced apart from the interconnect pattern.

6. The method according to claim 1, wherein, Each of the full-height contact portions includes a full-height conductive pattern and a full-height blocking pattern. Each of the height-reducing contact portions includes a height-reducing conductive pattern and a height-reducing blocking pattern. The height of the top surface of the full-height conductive pattern is the same as the height of the top surface of the full-height blocking pattern, and The height of the top surface of the height-reducing blocking pattern is lower than the height of the top surface of the height-reducing conductive pattern.

7. The method according to claim 1, further comprising: Before forming the full-height contact portion, a metal-semiconductor compound layer is formed on the source / drain pattern. The metal-semiconductor compound layer is located between the source / drain pattern and the full-height contact portion and the reduced-height contact portion.

8. The method according to claim 1, wherein, Forming the interconnect pattern includes: forming interconnect patterns spaced apart from each other in a first direction parallel to the substrate, and the interconnect patterns having a line extending along a second direction intersecting the first direction.

9. A method for manufacturing a semiconductor device, comprising: Provide substrate; An active fin region, a source / drain pattern, a gate structure, and an inter-gate insulating layer are formed on the substrate. A full-height contact portion is formed that penetrates the inter-gate insulating layer and is respectively connected to the source / drain pattern, and each full-height contact portion includes a corresponding full-height blocking pattern; Form full-height gate contacts that are respectively connected to the gate structure, each of the full-height gate contacts including a full-height gate blocking pattern; Simultaneously, the first subset of the full-height contact portion and the second subset of the full-height gate contact portion are recessed to form a reduced-height contact portion and a reduced-height gate contact portion, respectively. as well as An upper insulating pattern is formed on the height reduction contact portion and the height reduction gate contact portion. The process of forming the height reduction contact portion and the height reduction gate contact portion includes: simultaneously removing a portion of the full-height blocking pattern of a first subset of the full-height contact portion and a portion of the full-height gate blocking pattern of a second subset of the full-height gate contact portion.

10. The method of claim 9, further comprising forming an interconnect pattern on the full-height contact portion, the full-height gate contact portion, and the upper insulating pattern.

11. The method according to claim 10, wherein, Forming the interconnect pattern includes: forming interconnect patterns spaced apart from each other in a first direction parallel to the substrate, and the interconnect patterns having a line extending along a second direction intersecting the first direction.

12. The method according to claim 10, wherein, The upper insulating pattern is located between the height reduction contact and the interconnect pattern, and between the height reduction gate contact and the interconnect pattern.

13. The method according to claim 9, wherein, The process involves removing portions of the full-height blocking pattern and the full-height gate blocking pattern to form a reduced-height blocking pattern and a reduced-height gate blocking pattern, respectively. The height of the uppermost surface of the height-reducing contact portion is higher than the height of the uppermost surface of the height-reducing blocking pattern.

14. The method according to claim 9, wherein, Each of the full-height contact portions includes a full-height conductive pattern. Each of the full-height gate contacts includes a full-height gate conductive pattern, and Forming the reduced height contact portion and the reduced height gate contact portion includes: simultaneously removing a portion of the full height conductive pattern and a portion of the full height gate conductive pattern to form the reduced height conductive pattern and the reduced height gate conductive pattern, respectively.

15. The method of claim 9, further comprising: Before forming the full-height contact portion, a metal-semiconductor compound layer is formed on the source / drain pattern. The metal-semiconductor compound layer is located between the source / drain pattern and the full-height contact portion and the reduced-height contact portion.

16. The method of claim 9, further comprising: A planarization process is performed to expose the top surface of the full-height contact, the top surface of the full-height gate contact, and the top surface of the upper insulating pattern; as well as Interconnect patterns are formed on the exposed top surfaces of the full-height contact portion, the full-height gate contact portion, and the upper insulating pattern.

17. The method of claim 9, further comprising forming an interconnect pattern on the upper insulating pattern, in, Each interconnect pattern in the interconnect pattern is electrically connected to a corresponding full-height contact and a corresponding full-height gate contact, and The interconnect pattern is spaced apart from the height reduction contact and the height reduction gate contact.

18. A method for manufacturing a semiconductor device, comprising: Provide substrate; An active fin region is formed on the substrate, the active fin region including a first active fin region and a second active fin region; A gate structure is formed on the active fin region; A first source / drain pattern and a second source / drain pattern are formed on the first active fin region and the second active fin region of the substrate, respectively; An inter-gate insulating layer is formed to cover the first source / drain pattern and the second source / drain pattern; Form full-height contact portions that are respectively connected to the first source / drain pattern and penetrate the intergate insulating layer; Form full-height gate contacts that are respectively connected to the gate structure; The first subset of the full-height contact portion is recessed to form a reduced-height contact portion; The second subset of the full-height gate contact portion is recessed to form a reduced-height gate contact portion; An upper insulating pattern is formed on the height reduction contact portion and the height reduction gate contact portion; as well as Interconnect patterns are formed on the full-height contact portion, the full-height gate contact portion, and the upper insulating pattern. Simultaneously, the process of recessing the full-height contact portion and the full-height gate contact portion are performed, and... Forming the interconnect pattern includes: forming interconnect patterns spaced apart from each other in a first direction parallel to the substrate, and the interconnect patterns having a line extending along a second direction intersecting the first direction.

19. The method of claim 18, further comprising: Before forming the full-height contact portion, a metal-semiconductor compound layer is formed on the source / drain pattern. The metal-semiconductor compound layer is located between the source / drain pattern and the full-height contact portion and the reduced-height contact portion.

20. The method of claim 19, further comprising: Before forming the interconnect pattern, a planarization process is performed to expose the top surface of the full-height contact, the top surface of the full-height gate contact, and the top surface of the upper insulating pattern.

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