Gallium nitride HEMTs and silicon terminal diamond MOSFETs integrated structure and preparation method thereof

Abstract

The invention discloses a gallium nitride HEMTs (Metal Oxide Semiconductor Transistor) and silicon terminal diamond MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) integrated structure and a preparation method thereof. According to the preparation method, after a polycrystalline diamond layer is grown on the other side of a silicon substrate, the silicon substrate in a region corresponding to diamond MOSFETs is oxidized to form silicon oxide, a silicon terminal diamond is formed in a position corresponding to a grid region in the region corresponding to the diamond MOSFETs, and the silicon terminal diamond has no natural conducting channel under zero grid voltage, so that the silicon terminal diamond can be used as a silicon terminal. Therefore, the normally-off characteristic is easy to realize, and the PMOS transistor is more suitable for being used as an enhanced PMOS transistor. The integrated structure provided by the invention comprises the silicon terminal diamond enhanced device and the gallium nitride enhanced device, so that the technical problem that the enhanced device is difficult to realize due to the'normally open 'characteristic of the hydrogen terminal diamond is effectively avoided.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to an integrated structure of gallium nitride HEMTs and silicon-terminated diamond MOSFETs and its fabrication method. Background Technology

[0002] Gallium nitride (GaN) materials, as the core representative of third-generation wide-bandgap semiconductors, have shown great application potential in the fields of high-efficiency power conversion and radio frequency power amplification due to their high breakdown field strength, high electron saturation drift velocity and excellent electron mobility. They have become a key enabling technology for modern electronic systems such as 5G / 6G communication base stations, radar systems, fast chargers and new energy vehicles.

[0003] However, as devices evolve towards higher power densities and smaller sizes, their inherent performance bottleneck, the "self-heating effect," becomes increasingly prominent. Because high-power devices made of gallium nitride (GaN) are typically fabricated on heterogeneous substrates with low thermal conductivity (such as silicon, silicon carbide, and sapphire), the enormous heat generated during operation cannot be dissipated in time, leading to a sharp rise in channel temperature. This high temperature triggers a series of problems, including decreased carrier mobility, threshold voltage drift, and reliability degradation, severely restricting the full performance and lifespan of GaN devices. Therefore, efficient thermal management has become a core challenge for unlocking the full potential of GaN devices and driving their development towards higher power levels.

[0004] To address the heat dissipation challenges of GaN devices, industry and academia have been seeking substrates or heat sinks with higher thermal conductivity. Among numerous materials, diamond, with its extremely high thermal conductivity and excellent insulation properties, is hailed as the "ultimate heat dissipation material." Tightly integrating gallium nitride (GaN) with diamond to construct an ultra-low thermal resistance path from the "heat source" to the "cold end" can solve the self-heating problem of GaN devices, potentially increasing power density several times over. Simultaneously, diamond is no longer merely a passive heat dissipation material but is being used as an ultra-wide bandgap semiconductor material to manufacture high-performance diamond devices. Diamond devices exhibit extremely high breakdown field strength, extremely high carrier saturation velocity, and theoretically, can operate at temperatures above 500°C, making them particularly suitable for power switches operating in ultra-high voltage and extreme environments. Against this backdrop, methods for integrating diamond and GaN devices have emerged. This is not simply a physical joining of the two devices but aims for a deep integration of complementary functions at the chip level. The strategic value and technological implications of this method are profoundly reflected in the following aspects: Gallium nitride (GaN) devices excel at achieving high-frequency, high-efficiency power conversion in medium- and high-voltage scenarios, while diamond devices possess unparalleled potential in ultra-high-voltage, extreme power density, or high-temperature environments. Through monolithic or heterogeneous integration, mixed-signal or intelligent power systems can be constructed, where GaN devices handle the high-frequency switching main circuit, while diamond devices can be used for ultra-high-voltage interfaces, surge protection, or control circuits in extreme environments, thereby achieving a leapfrog improvement in the overall system performance.

[0005] When depletion-type MOSFETs are used in CMOS logic circuits, one MOSFET is always conducting in the path, forming a continuous static current path, resulting in huge static power consumption, causing the chip to overheat or even burn out, and malfunctioning. The "normally closed" characteristic of enhancement-type MOSFETs (being off at zero gate voltage) is key to realizing "complementary" logic and ultra-low static power consumption in CMOS circuits, making them the mainstream choice. However, hydrogen-terminated diamond has a natural two-dimensional hole gas channel at zero gate voltage, making it essentially "normally open," which is a fundamental obstacle to the fabrication of enhancement-type devices using diamond-based MOSFETs.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] To address the aforementioned problems in the prior art, this invention provides an integrated structure of gallium nitride HEMTs and silicon-terminated diamond MOSFETs, and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a method for fabricating an integrated structure of gallium nitride HEMTs and silicon-terminated diamond MOSFETs, comprising the following steps: S1. Obtain a single-crystal silicon substrate, and form a polycrystalline diamond layer on one side of the single-crystal silicon substrate to obtain a first structure; S2. In the first structure, the side of the monocrystalline silicon substrate away from the polycrystalline diamond layer is thinned to a preset thickness to obtain the second structure. S3. In the second structure, a gallium nitride layer and an aluminum gallium nitride layer are sequentially grown on the side of the thinned single-crystal silicon substrate away from the polycrystalline diamond layer to obtain the third structure. S4. In the third structure, the aluminum gallium nitride layer and the gallium nitride layer are etched in the region corresponding to the diamond MOSFETs to expose the single crystal silicon substrate and obtain the fourth structure. S5. In the fourth structure, the single-crystal silicon substrate exposed in the corresponding region of the diamond MOSFETs is oxidized to form a first silicon dioxide layer, thus obtaining the fifth structure. S6. In the fifth structure, an aluminum gallium nitride layer is etched in the region corresponding to gallium nitride HEMTs to form a first groove, and the first groove exposes the gallium nitride layer to obtain the sixth structure. S7. In the sixth structure, a second silicon dioxide layer is grown on the surface of the region corresponding to gallium nitride HEMTs to obtain the seventh structure. S8. In the seventh structure, the first silicon dioxide layer is etched in the region corresponding to the diamond MOSFETs to form two second grooves, the second grooves exposing the polycrystalline diamond layer; and the structure is placed in a hydrogen atmosphere and annealed at a temperature range of 300-500°C to obtain the eighth structure. S9. Grow P in the two second grooves + Diamond, forming P + Diamond layer, obtaining the ninth structure; S10. In the ninth structure, a first source, a first drain, and a first gate are formed in the corresponding region of gallium nitride HEMTs; a second source, a second drain, and a second gate are formed in the corresponding region of diamond MOSFETs. S11. The first gate and the second gate are connected by a first lead, and the first drain and the second drain are connected by a second lead to obtain an integrated structure of gallium nitride HEMTs and silicon-terminated diamond MOSFETs.

[0008] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The preparation method provided by the present invention involves growing a polycrystalline diamond layer on the other side of a silicon substrate, oxidizing the silicon substrate in the region corresponding to the diamond MOSFETs to form silicon oxide, and forming silicon-terminated diamond at the corresponding position of the gate region in the region corresponding to the diamond MOSFETs. Since the silicon-terminated diamond does not have a natural conductive channel under zero gate voltage, it is easy to achieve "normally off" characteristics and is more suitable for making enhancement-mode PMOS transistors.

[0009] 2. This invention utilizes silicon as a bridge between diamond and gallium nitride (GaN), two different materials, to simultaneously fabricate silicon-terminated diamond-enhanced devices and GaN-enhanced devices, achieving complementary use. This effectively avoids the technical challenge of realizing enhancement devices due to the "normally on" characteristic of hydrogen-terminated diamond, and solves the fatal flaw of huge static power consumption in circuits. Furthermore, the extremely high thermal conductivity of diamond allows for rapid heat dissipation from GaN devices, improving the overall heat dissipation capacity of the devices.

[0010] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the fabrication process of an integrated structure of gallium nitride HEMTs and silicon-terminated diamond MOSFETs provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the first structure obtained in an embodiment of the present invention; Figure 3 This is a schematic diagram of the second structure obtained in an embodiment of the present invention; Figure 4 This is a schematic diagram of the third structure obtained in the embodiments of the present invention; Figure 5 This is a schematic diagram of the generation of two-dimensional electron gas at the interface between the gallium nitride layer and the aluminum gallium nitride layer in the third structure of the present invention. Figure 6 This is a schematic diagram of the fourth structure obtained in the embodiments of the present invention; Figure 7 This is a schematic diagram of the fifth structure obtained in the embodiments of the present invention; Figure 8 This is a schematic diagram of the sixth structure obtained in the embodiments of the present invention; Figure 9 This is a schematic diagram of the seventh structure obtained in the embodiments of the present invention; Figure 10 This is a schematic diagram of the eighth structure obtained in the embodiments of the present invention; Figure 11 This is a schematic diagram of the ninth structure obtained in the embodiments of the present invention; Figure 12This is a schematic diagram of the tenth structure obtained in the embodiments of the present invention; Figure 13 This is a schematic diagram of the eleventh structure obtained in the embodiments of the present invention; Figure 14 This is a schematic diagram of the twelfth structure obtained in the embodiments of the present invention; Figure 15 This is a schematic diagram of the thirteenth structure obtained in the embodiments of the present invention; Figure 16 This is a schematic diagram of the integrated structure of gallium nitride HEMTs and silicon-terminated diamond MOSFETs prepared in the embodiments of the present invention.

[0012] Explanation of reference numerals in the attached figures: 1-Single-crystal silicon substrate; 2-Polycrystalline diamond layer; 3-Gallium nitride layer; 4-Aluminum gallium nitride layer; 41-First trench; 5-First silicon dioxide layer; 51-Second trench; 6-Second silicon dioxide layer; 71-First source; 72-First drain; 73-First gate; 81-Second source; 82-Second drain; 83-Second gate; 9-P + Diamond layer; 10-isolation layer. Detailed Implementation

[0013] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following, in conjunction with the accompanying drawings and specific embodiments, provides a detailed description of the integrated structure of gallium nitride HEMTs and silicon-terminated diamond MOSFETs and its fabrication method proposed according to the present invention.

[0014] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0015] It should be noted that, in this document, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not explicitly listed.

[0016] Example 1 This embodiment provides a method for fabricating an integrated structure of gallium nitride HEMTs and silicon-terminated diamond MOSFETs. See also Figure 1 This includes the following steps S1 to S11.

[0017] S1, see also Figure 2 A monocrystalline silicon substrate 1 is obtained, and a polycrystalline diamond layer 2 is formed on one side of the monocrystalline silicon substrate 1 to obtain the first structure.

[0018] In one example, the monocrystalline silicon substrate 1 may be a monocrystalline silicon wafer.

[0019] S2. In the first structure, one side of the monocrystalline silicon substrate 1 and the polycrystalline diamond layer 2 is thinned to a predetermined thickness, see [reference]. Figure 3 , thus obtaining the second structure.

[0020] In one example, step S2 includes: first, thinning the single-crystal silicon substrate 1 by mechanical polishing to a first thickness; the first thickness is 80-120 μm. Then, dry etching is performed in a fluorine-based gas (CF4, NF3 or C2F6) atmosphere to thin the thickness of the single-crystal silicon substrate 1 to a preset thickness; the preset thickness is 0.2-1.0 μm.

[0021] S3. In the second structure, a gallium nitride layer 3 and an aluminum gallium nitride layer 4 are sequentially grown on the side of the thinned single-crystal silicon substrate 1 away from the polycrystalline diamond layer 2. See [reference needed]. Figure 4 and Figure 5 , thus obtaining the third structure.

[0022] In another embodiment, prior to step S3, the surface of the monocrystalline silicon substrate 1 away from the polycrystalline diamond layer 2 is polished using chemical mechanical polishing (CMP) until the surface roughness is less than 0.2 nm. The polished second structure is then placed in a metal-organic chemical vapor deposition (MOCVD) apparatus and baked at 1000-1200°C in an atmosphere of H2 gas or a mixture of H2 and N2 gas. After cooling, an aluminum nitride nucleation layer is formed on the side of the monocrystalline silicon substrate 1 away from the polycrystalline diamond layer 2. Thus, step S3 includes sequentially growing a gallium nitride layer 3 and an aluminum gallium nitride layer 4 on the side of the aluminum nitride nucleation layer away from the polycrystalline diamond layer 2.

[0023] S4. In the third structure, the aluminum gallium nitride layer 4 and the gallium nitride layer 3 are etched in the regions corresponding to the diamond MOSFETs to expose the single-crystal silicon substrate 1. (See [reference]). Figure 6 , thus obtaining the fourth structure.

[0024] In one example, step S4 includes: In the third structure, photoresist is spin-coated onto the surface of the aluminum gallium nitride layer 4, and the pattern of the corresponding region of the diamond MOSFETs is photolithographically formed using a photomask. Using an inductively coupled plasma etching process with chlorine-based (Cl2 and BCl3) gases, the aluminum gallium nitride layer 4 and the gallium nitride layer 3 of the corresponding region of the diamond MOSFETs are sequentially etched away until the single-crystal silicon substrate 1 is fully exposed.

[0025] S5, in the fourth structure, the single-crystal silicon substrate 1 exposed in the region corresponding to the diamond MOSFETs is oxidized to form a first silicon dioxide layer 5, see [link]. Figure 7 Thus, the fifth structure is obtained.

[0026] For example, the oxidation process in step S5 can be dry oxidation or wet oxidation.

[0027] S6. In the fifth structure, the aluminum gallium nitride layer 4 is etched in the region corresponding to the gallium nitride HEMTs to form a first groove 41. The first groove 41 exposes the gallium nitride layer 3. See [link / reference] Figure 8 Thus, the sixth structure is obtained.

[0028] For example, the formation of the first groove 41 may be achieved using an inductively coupled plasma (ICP) process or an atomic layer etching (ALE) process.

[0029] In structure S7, a second silicon dioxide layer 6 is grown on the surface of the corresponding region of gallium nitride HEMTs. (See below) Figure 9 Thus, the seventh structure is obtained.

[0030] For example, the method for growing the second silicon dioxide layer 6 may be plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), or sputtering.

[0031] In structure S8, the first silicon dioxide layer 5 is etched in the region corresponding to the diamond MOSFETs to form two second grooves 51, which expose the polycrystalline diamond layer 2; and then annealed in a hydrogen atmosphere at a temperature range of 300-500°C. (See [link to relevant documentation]). Figure 10 Obtain the eighth structure.

[0032] For example, in step S8, the equipment used for annealing can be a microwave plasma chemical vapor deposition equipment, a metal-organic chemical vapor deposition equipment, a tube furnace, or a rapid thermal annealing furnace.

[0033] S9. P is grown in the two second grooves 51. + Diamond, forming P + Diamond layer 9, see Figure 11 Thus, the ninth structure is obtained.

[0034] For example, P + Diamond layer 9 is a heavily doped p-type diamond layer. For example, in-situ doping can be achieved by introducing boron atoms during diamond growth using microwave plasma CVD (MPCVD) technology.

[0035] In S10, the ninth structure, a first source 71, a first drain 72, and a first gate 73 are formed in the corresponding regions of gallium nitride HEMTs; a second source 81, a second drain 82, and a second gate 83 are formed in the corresponding regions of diamond MOSFETs. (See also...) Figures 12-16 .

[0036] In one example, step S10 includes: S101, see Figure 12 The first source region and the first drain region of the gallium nitride HEMTs are etched using an inductively coupled plasma process. Fluorine gas is used to etch the second silicon dioxide layer 6, and chlorine gas is used to etch the aluminum gallium nitride layer 4. The first source window and the first drain window exposed the gallium nitride layer 3 to obtain the tenth structure.

[0037] S102, see also Figure 13 The first source 71 and the first drain 72 are deposited in the first source window and the first drain window respectively by electron beam evaporation process; then the first gate 73 is deposited on the surface of the second silicon dioxide layer 6 in the first groove 41 by electron beam evaporation process to obtain the eleventh structure.

[0038] Furthermore, the first source 71 and the first drain 72 are made of a metal stack structure consisting of Ti, Al, X and Au in sequence, wherein X is Ni, Mo, Pt or Ti; the first gate 73 is made of a metal stack structure consisting of Ni and Au in sequence or a metal stack structure consisting of Pt and Au in sequence.

[0039] S103, see also Figure 14 An isolation layer 10 is formed in the corresponding region of the diamond MOSFETs; the isolation layer 10 covers the first silicon dioxide layer 5 and P + Diamond layer 9, obtaining the twelfth structure.

[0040] S104, see also Figure 15 Using inductively coupled plasma (ICP) etching, the pre-defined second source region, pre-defined second drain region, and pre-defined second gate region of the diamond MOSFETs are etched to form the second source window, second drain window, and second gate window. The second source window and second drain window are then connected to the P... + Diamond layer 9 corresponds to, and P is exposed. +Diamond layer 9. The second gate window corresponds to the first silicon dioxide layer 5 and a third groove is formed on the isolation layer 10. The depth of the third groove is less than the thickness of the isolation layer 10, thus obtaining the thirteenth structure.

[0041] For example, the material of the isolation layer may be, but is not limited to, silicon oxide, silicon nitride, or aluminum oxide.

[0042] S105, see also Figure 16 The second source 81 and the second drain 82 are deposited in the preset second source region and the preset second drain region respectively by electron beam evaporation process; then the second gate 83 is deposited in the third groove by electron beam evaporation process.

[0043] Furthermore, the materials of the second source 81 and the second drain 82 are metal stacked structures composed of Ti, Pt and Au in sequence or metal stacked structures composed of Ti and Au in sequence; the materials of the second gate 83 are metal stacked structures composed of Pt and Au in sequence, metal stacked structures composed of Pd and Au in sequence or metal stacked structures composed of Ni and Au in sequence.

[0044] S11, see also Figure 16 The first gate 73 and the second gate 83 are connected by a first lead, and the first drain 72 and the second drain 82 are connected by a second lead, thus obtaining an integrated structure of gallium nitride HEMTs and silicon-terminated diamond MOSFETs.

[0045] With the continuous advancement of bonding technology, interface engineering, and thermal characterization techniques, the integration process of silicon-terminated diamond and GaN devices will become increasingly mature. For diamond, surface silicon termination is one of the key technologies for constructing a high-quality diamond MOSFET gate oxide interface, which helps to reduce interface state density and improve channel mobility and gate reliability. Secondly, in terms of integration, the silicon termination layer can serve as an "intermediate layer" or "buffer layer" between the two heteromaterials, gallium nitride and diamond.

[0046] The fabrication method provided by this invention involves growing a polycrystalline diamond layer on the other side of a silicon substrate, then oxidizing the silicon substrate in the region corresponding to the diamond MOSFETs to form silicon oxide. Silicon-terminated diamond is then formed at the corresponding position in the gate region of the diamond MOSFETs. Since silicon-terminated diamond lacks a natural conductive channel at zero gate voltage, it easily achieves "normally off" characteristics, making it more suitable for enhancement-mode PMOS transistors. Thus, the fabrication method of the integrated structure of gallium nitride (HEMTs) and silicon-terminated diamond MOSFETs provided by this invention utilizes silicon as a bridge between diamond-based and gallium nitride-based devices, enabling the fabrication of both diamond-enhanced and gallium nitride-enhanced devices, thereby achieving the integrated use of these two types of enhanced devices. The fabrication method provided by this invention is expected to solve the thermal failure problem of high-frequency, high-power GaN devices, driving technological changes in fields such as communications, radar, and energy. It also provides a bridge channel for ultra-efficient, high-power-density electronic systems, representing a cutting-edge direction in power electronics technology development.

[0047] Example 2 This embodiment provides an integrated structure of gallium nitride HEMTs and silicon-terminated diamond MOSFETs, which can be prepared using the preparation method provided in any of the above embodiments.

[0048] Example 3 The following is a specific embodiment of the fabrication of an integrated structure of gallium nitride HEMTs and silicon-terminated diamond MOSFETs.

[0049] Step S1: Select a clean 4-inch (111) crystal orientation monocrystalline silicon wafer with a thickness of 1 mm as the monocrystalline silicon substrate 1. Use microwave plasma chemical vapor deposition (MPCVD) to grow a polycrystalline diamond layer 2 with a thickness of about 300 μm on one side of the monocrystalline silicon substrate 1.

[0050] The specific process for growing the polycrystalline diamond layer 2 includes: firstly, pretreating the single-crystal silicon substrate 1 using a nanodiamond suspension (particle size 5-10 nm). Then, the pretreated single-crystal silicon substrate 1 is placed on the stage of the MPCVD reaction chamber, and H2 is introduced as the reaction gas to perform in-situ hydrogen plasma cleaning of the single-crystal silicon substrate 1 to remove any trace oxides and contaminants that may remain on the surface of the single-crystal silicon substrate 1, and to activate the surface. Next, the polycrystalline diamond layer is grown; the growth process parameters are: reaction gases CH4 and H2, CH4 concentration 1.5%, chamber pressure 10 kPa, microwave power 2500 W, and substrate temperature 900 °C. The resulting structure is as follows: Figure 2 The first structure shown.

[0051] Step S2: The back side (the surface away from the polycrystalline diamond layer 2) of the single-crystal silicon substrate 1 in the first structure is mechanically ground to reduce the thickness of the single-crystal silicon substrate 1 from the initial 1 mm to approximately 100 μm. Then, the remaining 100 μm of the single-crystal silicon substrate 1 is dry-etched in a fluorine-based gas atmosphere to further reduce its thickness from 100 μm. Etching to 1 The following results are obtained: Figure 3 The second structure shown.

[0052] Step S3: Perform fine chemical mechanical polishing (CMP) on the surface of the thinned single-crystal silicon substrate 1 in the second structure to reduce its surface roughness (RMS) to below 0.2 nm, so as to obtain an atomically flat surface and prepare for the subsequent high-quality epitaxial growth of gallium nitride layer and aluminum gallium nitride layer.

[0053] The thinned and polished second structure is placed on the substrate of the MOCVD reaction chamber, and H2 or an H2 / N2 mixed gas is introduced. It is then baked at 1000℃ to clean the initial substrate surface and remove the native oxide layer. AlN nucleation layer growth is then performed to provide a lattice-matched starting point for subsequent gallium nitride (GaN) growth. Next, a high-quality GaN layer is grown with the following process parameters: growth temperature 1050℃, pressure 40 kPa, precursors TMGa and NH3, and a V / III ratio (flow ratio of nitrogen source NH3 to gallium source TMGa) of 500-2000. Finally, an aluminum gallium nitride (AlGaN) layer is grown as a barrier layer with the following process parameters: growth temperature 1000℃, pressure 40 kPa, precursors TMAl, TMGa, and NH3, and a V / III ratio of 500-1500. Pulsed atomic layer epitaxy or a low growth rate mode is typically used during AlGaN layer growth to obtain an atomically flat interface. The resulting structure is as follows: Figure 4 The third structure is shown. An aluminum gallium nitride layer forms a heterojunction with the underlying gallium nitride layer. High-mobility two-dimensional electron gas (2DEG) is induced at the interface through piezoelectric polarization and spontaneous polarization effects, as shown in the diagram. Figure 5 As shown.

[0054] Step S4: Spin-coat photoresist onto the surface of the aluminum gallium nitride layer of the third structure, and then photolithographically pattern the corresponding area of ​​the diamond MOSFET using a photomask (e.g., ...). Figure 6 (Illustrated with one or more rectangular regions), then inductively coupled plasma (ICP) etching was performed using chlorine-based (Cl2 / BCl3) gas to sequentially etch away the aluminum gallium nitride layer and gallium nitride layer in the exposed areas until the underlying single-crystal silicon substrate 1 was completely exposed. The resulting structure is as follows: Figure 6 The fourth structure shown.

[0055] Step S5: Place the fourth structure in a horizontal tubular oxidation furnace under normal pressure. Heat to the target temperature of 1000℃ at a rate of 10℃ per minute under a N2 atmosphere, then stabilize for 10 minutes to ensure uniform silicon wafer temperature. Turn off the N2 atmosphere and introduce high-purity oxygen to oxidize the exposed single-crystal silicon substrate 1 into a first silicon dioxide layer 5 (this silicon dioxide layer can later be used as the gate dielectric of diamond MOSFETs and also serves as electrical isolation). Simultaneously, use a dielectric mask to shield the aluminum gallium nitride layer 4 and the gallium nitride layer 3 to prevent oxidation. The resulting structure is as follows: Figure 7 The fifth structure shown.

[0056] Step S6: Place the fifth structure into the ICP device and etch the first groove 41. Remove the aluminum gallium nitride layer 4 to eliminate the two-dimensional electron gas in the corresponding area of ​​the first groove 41, resulting in... Figure 8 The sixth structure shown.

[0057] Step S7: Place the sixth structure into a plasma-enhanced chemical vapor deposition (PECVD) apparatus, and introduce SiH4 and N2O as reactant gases to grow a second silicon dioxide layer 6 on the surface of the corresponding region of gallium nitride HEMTs. This second silicon dioxide layer 6 covers the aluminum gallium nitride layer 4 and the sidewalls and bottom of the first groove 41, resulting in the structure shown below. Figure 9 The seventh structure shown.

[0058] Step S8: In the corresponding region of the diamond MOSFETs, part of the first silicon dioxide layer 5 is etched away using ICP to prepare P. + A window (second groove 51) is created in the diamond region, extending to the interface between the first silicon dioxide layer 5 and the polycrystalline diamond layer 2, exposing the polycrystalline diamond layer 2 at the bottom of the second groove 51. The sample is then placed on the substrate of the MPCVD reaction chamber and annealed at 300-500°C by introducing H2. During annealing, the remaining first silicon dioxide layer 5 and polycrystalline diamond layer 2 form C-Si-O bonds, becoming silicon-terminated. This also repairs the interface defects of the aluminum gallium nitride layer 4 / second silicon dioxide layer 6, reducing the interface state density and improving the mobility and concentration of the two-dimensional electron gas. The resulting structure is as follows: Figure 10 The eighth structure shown.

[0059] Step S9: Grow P in the second groove 51 using MPCVD technology. + Diamond, forming P + The diamond layer results in a structure as follows: Figure 11 The ninth structure shown.

[0060] Step S10: A predetermined first source region and a predetermined first drain region of gallium nitride (GaN) HEMTs are fabricated using inductively coupled plasma (ICP). Specifically, fluorine-based and chlorine-based gases are used sequentially to etch away the second silicon dioxide layer 6 and the aluminum gallium nitride layer 4 of the predetermined first source and first drain regions, forming a first source window and a first drain window that expose the gallium nitride layer 3; that is, the depth of the first source window and the first drain window should reach the interface between the aluminum gallium nitride layer and the gallium nitride layer. The resulting structure is as follows: Figure 12 The tenth structure shown.

[0061] Step S11: Ti / Al / Ni / Au is deposited at the first source window and the first drain window of the gallium nitride HEMTs using electron beam evaporation. Ni / Au is deposited on the upper surface of the second silicon dioxide layer 6 in the first trench 41 using electron beam evaporation as the first gate 73 of the gallium nitride HEMTs. The resulting structure is as follows: Figure 13 The eleventh structure shown.

[0062] Step S12: Deposit alumina material as an isolation layer 10 for the diamond MOSFETs region using an ALD device. The isolation layer 10 covers the first silicon dioxide layer 5 and P in the corresponding region of the diamond MOSFETs. + Diamond layer 9, the resulting structure is as follows Figure 14 The twelfth structure shown.

[0063] Step S13: Fabricate the second source window, second drain window, and second gate window of the diamond MOSFET using inductively coupled plasma (ICP). The second source window and second drain window are connected to P... + Diamond layer 9 corresponds to, and P is exposed. + Diamond layer 9; that is, the depth of the second source window and the second drain window must reach the isolation layer and P. + At the interface of diamond layer 9, a third groove is formed on the isolation layer 10 by the second gate window. The depth of the third groove is less than the thickness of the isolation layer 10, resulting in the following structure: Figure 15 The thirteenth structure shown.

[0064] Step S14: Using electron beam evaporation, deposit Ti / Pt / Au at the second source and second drain windows as the second source and second drain of the diamond MOSFETs. Deposit Ni / Au at the second gate window using electron beam evaporation as the second gate of the diamond MOSFETs. Then, using wire bonding, connect the gates of the gallium nitride HEMTs and the diamond MOSFETs together as inputs, and connect the drains of the gallium nitride HEMTs and the diamond devices together as outputs. Connect the source of the gallium nitride HEMTs to GND and the source of the diamond MOSFETs to VDD. The resulting structure is as follows: Figure 16 The structure shown.

[0065] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0066] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating an integrated structure of gallium nitride HEMTs and silicon-terminated diamond MOSFETs, characterized in that, Includes the following steps: S1. Obtain a single-crystal silicon substrate (1) and form a polycrystalline diamond layer (2) on one side of the single-crystal silicon substrate (1) to obtain a first structure; S2. In the first structure, the side of the monocrystalline silicon substrate (1) away from the polycrystalline diamond layer (2) is thinned to a preset thickness to obtain the second structure; S3. In the second structure, a gallium nitride layer (3) and an aluminum gallium nitride layer (4) are sequentially grown on the side of the thinned single-crystal silicon substrate (1) away from the polycrystalline diamond layer (2) to obtain the third structure. S4. In the third structure, the aluminum gallium nitride layer (4) and the gallium nitride layer (3) are etched in the region corresponding to the diamond MOSFETs to expose the single crystal silicon substrate (1) and obtain the fourth structure. S5. In the fourth structure, the single-crystal silicon substrate (1) exposed in the corresponding area of ​​the diamond MOSFETs is oxidized to form a first silicon dioxide layer (5) to obtain the fifth structure. S6. In the fifth structure, an aluminum gallium nitride layer (4) is etched in the region corresponding to gallium nitride HEMTs to form a first groove (41), and the first groove (41) exposes the gallium nitride layer (3) to obtain the sixth structure. S7. In the sixth structure, a second silicon dioxide layer (6) is grown on the surface of the region corresponding to gallium nitride HEMTs to obtain the seventh structure; S8. In the seventh structure, the first silicon dioxide layer (5) is etched in the region corresponding to the diamond MOSFETs to form two second grooves (51), the second grooves (51) expose the polycrystalline diamond layer (2); and it is placed in a hydrogen atmosphere and annealed at a temperature range of 300-500℃ to obtain the eighth structure. S9. Grow P in the two second grooves (51) + Diamond, forming P + Diamond layer (9), thus obtaining the ninth structure; S10. In the ninth structure, a first source (71), a first drain (72), and a first gate (73) are formed in the corresponding regions of gallium nitride HEMTs; a second source (81), a second drain (82), and a second gate (83) are formed in the corresponding regions of diamond MOSFETs. S11. The first gate (73) and the second gate (83) are connected by a first lead, and the first drain (72) and the second drain (82) are connected by a second lead to obtain an integrated structure of gallium nitride HEMTs and silicon-terminated diamond MOSFETs.

2. The method for fabricating the integrated structure of gallium nitride HEMTs and silicon-terminated diamond MOSFETs according to claim 1, characterized in that, Step S2 includes: thinning the single-crystal silicon substrate (1) by mechanical polishing to a first thickness; the first thickness is 80-120 μm; Then, dry etching is performed in a fluorine-based gas atmosphere to reduce the thickness of the single-crystal silicon substrate (1) to a preset thickness of 0.2-1.0 μm.

3. The method for fabricating the integrated structure of gallium nitride HEMTs and silicon-terminated diamond MOSFETs according to claim 1, characterized in that, Before step S3, the following is also included: Chemical mechanical polishing was used to polish the surface of the single-crystal silicon substrate (1) in the second structure away from the polycrystalline diamond layer (2); the surface roughness was polished to less than 0.2 nm. The polished second structure was placed in a metal-organic chemical vapor deposition apparatus and baked at a temperature of 1000-1200℃ in an atmosphere of H2 gas or a mixture of H2 and N2 gas. After cooling, an aluminum nitride nucleation layer is formed on the side of the monocrystalline silicon substrate (1) away from the polycrystalline diamond layer (2); Step S3 includes: sequentially growing a gallium nitride layer (3) and an aluminum gallium nitride layer (4) on the side of the aluminum nitride nucleation layer away from the polycrystalline diamond layer (2).

4. The method for fabricating the integrated structure of gallium nitride HEMTs and silicon-terminated diamond MOSFETs according to claim 1, characterized in that, Step S4 includes: In the third structure, photoresist is spin-coated on the surface of the aluminum gallium nitride layer (4), and the pattern of the corresponding area of ​​the diamond MOSFET is photolithographically formed by photolithography using a photomask. Using an inductively coupled plasma etching process, chlorine-based gas is used to sequentially etch away the aluminum gallium nitride layer (4) and gallium nitride layer (3) in the corresponding area of ​​the diamond MOSFETs until the single-crystal silicon substrate (1) is completely exposed.

5. The method for fabricating the integrated structure of gallium nitride HEMTs and silicon-terminated diamond MOSFETs according to claim 1, characterized in that, In step S5, the oxidation treatment includes dry oxidation or wet oxidation.

6. The method for fabricating the integrated structure of gallium nitride HEMTs and silicon-terminated diamond MOSFETs according to claim 1, characterized in that, In step S7, the method for growing the second silicon dioxide layer (6) includes plasma-enhanced chemical vapor deposition, atomic layer deposition, low-pressure chemical vapor deposition, or sputtering.

7. The method for fabricating the integrated structure of gallium nitride HEMTs and silicon-terminated diamond MOSFETs according to claim 1, characterized in that, In step S8, the equipment used for annealing includes microwave plasma chemical vapor deposition equipment, metal-organic chemical vapor deposition equipment, tube furnace, or rapid thermal annealing furnace.

8. The method for fabricating an integrated structure of gallium nitride HEMTs and silicon-terminated diamond MOSFETs according to any one of claims 1-7, characterized in that, Step S10 includes: S101. Using inductively coupled plasma technology, the preset first source region and preset first drain region of the corresponding area of ​​gallium nitride HEMTs are etched; wherein, fluorine-based gas is used to etch the second silicon dioxide layer (6), and chlorine-based gas is used to etch the aluminum gallium nitride layer (4), and the first source window and first drain window formed expose the gallium nitride layer (3) to obtain the tenth structure. S102, A first source (71) and a first drain (72) are deposited in the first source window and the first drain window respectively using an electron beam evaporation process; then a first gate (73) is deposited on the surface of the second silicon dioxide layer (6) in the first groove using an electron beam evaporation process to obtain the eleventh structure; S103, An isolation layer (10) is formed in the corresponding region of the diamond MOSFETs; the isolation layer (10) covers the first silicon dioxide layer (5) and P + Diamond layer (9), obtaining the twelfth structure; S104. Using inductively coupled plasma (ICP) etching, the preset second source region, preset second drain region, and preset second gate region of the corresponding area of ​​the diamond MOSFETs are etched to form a second source window, a second drain window, and a second gate window; the second source window and the second drain window are connected to the P... + The diamond layer (9) corresponds to and exposes the P. + Diamond layer (9); the second gate window corresponds to the first silicon dioxide layer (5) and forms a third groove on the isolation layer (10), the depth of the third groove being less than the thickness of the isolation layer (10), thus obtaining the thirteenth structure; S105, a second source (81) and a second drain (82) are deposited in the preset second source region and the preset second drain region respectively using an electron beam evaporation process; then a second gate (83) is deposited in the third groove using an electron beam evaporation process.

9. The method for fabricating the integrated structure of gallium nitride HEMTs and silicon-terminated diamond MOSFETs according to claim 8, characterized in that, The first source (71) and the first drain (72) are made of a metal stack structure consisting of Ti, Al, X and Au in sequence, wherein X is Ni, Mo, Pt or Ti; the first gate (73) is made of a metal stack structure consisting of Ni and Au in sequence or a metal stack structure consisting of Pt and Au in sequence. The second source (81) and the second drain (82) are made of a metal stack structure consisting of Ti, Pt and Au in sequence or a metal stack structure consisting of Ti and Au in sequence; the second gate (83) is made of a metal stack structure consisting of Pt and Au in sequence, a metal stack structure consisting of Pd and Au in sequence or a metal stack structure consisting of Ni and Au in sequence.

10. An integrated structure of gallium nitride HEMTs and silicon-terminated diamond MOSFETs, characterized in that, The integrated structure of gallium nitride HEMTs and silicon-terminated diamond MOSFETs is prepared using the fabrication method provided in any one of claims 1-9.

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