Semiconductor device and forming method thereof

Abstract

In an embodiment, a method includes forming an upper gate structure adjacent to a first source / drain region and a second source / drain region and a lower gate structure adjacent to a third source / drain region; patterning the first opening and the second opening through the first dielectric layer to expose the first source / drain region and the second source / drain region; patterning to extend a second opening through the second dielectric layer to expose a third source / drain region; forming a protective layer over the exposed surface of the first dielectric layer; forming a first epitaxial regrowth layer over the first source / drain region and a second epitaxial regrowth layer over the second source / drain region; removing the protective layer; forming a first source / drain contact to the first epitaxial regrowth layer; and forming a second source / drain contact to the second epitaxial regrowth layer and the third source / drain region. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor layer on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum part size, allowing more components to be integrated into a given area. As the semiconductor industry further moves towards increased device density, higher performance, and lower cost, challenges from manufacturing and design have led to stacked device configurations, such as stacked transistors, including complementary field-effect transistors (CFETs). However, as the minimum part size decreases, additional components are introduced. Summary of the Invention

[0004] Some embodiments of this application provide a method for forming a semiconductor device, including: forming an upper gate structure adjacent to a first source / drain region and a second source / drain region, and a lower gate structure adjacent to a third source / drain region; patterning a first opening and a second opening through a first dielectric layer to expose the first source / drain region and the second source / drain region; patterning to extend the second opening through a second dielectric layer to expose the third source / drain region; forming a protective layer above the exposed surface of the first dielectric layer; forming a first epitaxial regrown layer above the first source / drain region and a second epitaxial regrown layer above the second source / drain region; removing the protective layer; forming a first source / drain contact to the first epitaxial regrown layer; and forming a second source / drain contact to the second epitaxial regrown layer and the third source / drain region.

[0005] Other embodiments of this application provide a method of forming a semiconductor device, comprising: forming an opening through a first plurality of dielectric layers to expose a first source / drain region; extending the opening through a second plurality of dielectric layers to expose a second source / drain region; forming a first protective layer along the exposed surfaces of the second plurality of dielectric layers and the second source / drain region; forming a second protective layer along the exposed surfaces of the first plurality of dielectric layers; forming an epitaxial regeneration layer on the first source / drain region; removing the second protective layer; removing the first protective layer; and forming a source / drain contact in the opening, the source / drain contact being coupled to the first source / drain region and coupled to the second source / drain region.

[0006] Some embodiments of this application provide a semiconductor device, including: a first epitaxial region comprising a first epitaxial material; a first silicide region located on the first epitaxial region; a first nanostructure adjacent to the first epitaxial region; a second epitaxial region overlapping the first epitaxial region, the second epitaxial region comprising a second epitaxial material different from the first epitaxial material; a second silicide region located on the second epitaxial region; an interlayer dielectric layer disposed above the first epitaxial region and below the second epitaxial region; and a contact plug extending through the second epitaxial region and the interlayer dielectric layer to be electrically coupled to the first epitaxial region, wherein the contact plug... The electrical conductivity of the plug is greater than that of the first epitaxial region; a third epitaxial region is laterally adjacent to the second epitaxial region, the third epitaxial region comprising the second epitaxial material and a third epitaxial material, the third epitaxial material being different from the first epitaxial material and the second epitaxial material; a third silicide region is located on the third epitaxial region, the third silicide region being in contact with the third epitaxial material of the third epitaxial region; a second nanostructure extends from the second epitaxial region to the third epitaxial region; a first gate structure is located around the first nanostructure; and a second gate structure overlaps with the first gate structure and is located around the second nanostructure. Attached Figure Description

[0007] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 A perspective view of an exemplary stacked transistor according to some embodiments is shown.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 and Figure 13 This is a view of an intermediate stage in the fabrication of stacked transistors according to some embodiments.

[0010] Figure 14 , Figure 15 and Figure 16 This is a view of an intermediate stage in the fabrication of stacked transistors according to some additional embodiments.

[0011] Figure 17 and Figure 18 The chemical structure and reaction mechanism of an intermediate stage in the fabrication of a stacked transistor according to some embodiments are shown.

[0012] Figure 19 , Figure 20 and Figure 21 The process flow of an intermediate stage in the fabrication of stacked transistors according to some embodiments is shown. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or instances for implementing various features of the embodiments of this disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0015] Stacked transistor structures and methods for forming them are provided. Stacked transistor structures, such as complementary field-effect transistors (CFETs), and methods for forming them are provided. The stacked transistor structure comprises two transistors vertically stacked and having opposite types (e.g., vertically stacked n-type and p-type transistors). Therefore, the source / drain regions of the vertically stacked transistors can also be vertically stacked. Furthermore, source / drain region contacts to the upper and / or lower source / drain regions can be formed. A patterning step can be used to form contact openings to the upper source / drain regions, and some of these contact openings can extend to the lower source / drain regions. Forming contact openings to the lower source / drain regions can include etching through the upper source / drain regions. Embodiments herein include forming one or more protective layers over the structure while the upper source / drain regions remain exposed. An epitaxial regeneration process can then be performed on the upper source / drain regions (e.g., etched-through upper source / drain regions). For example, the protective layer may include a self-assembled monolayer (SAM) selectively formed along certain dielectric surfaces while certain epitaxial surfaces remain exposed for subsequent epitaxial regrowth. After the epitaxial regrowth process, the protective layer is removed, and contact plugs are formed in the contact openings. The resulting upper source / drain regions are implemented at a higher level and with greater reliability, resulting in improved yield, performance, and reliability of the corresponding transistor.

[0016] Figure 1 Examples of stacked transistors 10 (including FETs 10U and 10L) according to some embodiments are shown. Figure 1 It is a 3D view, and for clarity, some components of the stacked transistors have been omitted.

[0017] The stacked transistor includes multiple vertically stacked FETs. For example, the stacked transistor may include a lower nanostructure FET 10L of a first device type (e.g., n-type / p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type / n-type). When the stacked transistor is a CFET, the second device type of the upper nanostructure FET 10U is opposite to the first device type of the lower nanostructure FET 10L. The nanostructure FETs 10U and 10L include a semiconductor nanostructure 26 (including a lower semiconductor nanostructure 26L and an upper semiconductor nanostructure 26U), wherein the semiconductor nanostructure 26 serves as a channel region for the nanostructure FET. The lower semiconductor nanostructure 26L is used for the lower nanostructure FET 10L, and the upper semiconductor nanostructure 26U is used for the upper nanostructure FET 10U. In other embodiments, the stacked transistor may also be adapted to other types of transistors (e.g., finFETs, etc.).

[0018] A gate dielectric 78 surrounds the corresponding semiconductor nanostructure 26. Gate electrodes 80 (including a lower gate electrode 80L and an upper gate electrode 80U) are located above the gate dielectric 78. Source / drain regions 62 (including a lower source / drain region 62L and an upper source / drain region 62U) are disposed on opposite sides of the gate dielectric 78 and the corresponding gate electrode 80. Each of the source / drain regions 62 can refer to either a source or a drain, individually or collectively, depending on the context. Isolation components (not shown) may be formed to separate the desired source / drain regions 62 and / or the desired gate electrode 80. It should be noted that the upper source / drain region 62U and the lower source / drain region 62L can be referred to by the conductivity type (e.g., p-type or n-type) of the corresponding nanostructure FET.

[0019] Figure 1 A reference cross section, used in later figures, is also shown. Section A-A' is a vertical cross section parallel to the longitudinal axis of the semiconductor nanostructure 26 of the stacked transistor and in the direction of current, for example, between the source / drain regions 62 of the stacked transistor. For clarity, subsequent figures may refer to this reference cross section.

[0020] Figure 2 A 3D view is shown, and Figures 3 to 16 Various stacked transistors (e.g., according to some embodiments) are shown. Figure 1 A cross-sectional view of an intermediate stage in the formation of a structure (illustrated schematically). Unless otherwise stated in the following discussion, Figures 3 to 16 It shows the line and Figure 1 A vertical cross-sectional view of a section similar to the vertical reference section A-A' in the diagram.

[0021] exist Figure 2 The wafer is provided, and the wafer includes a substrate 20. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, which may be doped (e.g., having p-type or n-type dopants) or undoped. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 20 may include silicon, germanium, carbon-doped silicon, III-V compound semiconductors; or combinations thereof.

[0022] Semiconductor strips 28 are formed extending upward from semiconductor substrate 20. Each semiconductor strip 28 includes a semiconductor strip 20' (a patterned portion of semiconductor substrate 20, also referred to as semiconductor fin 20') and a multilayer stack 22. The stacked components of the multilayer stack 22 are referred to hereinafter as nanostructures. Specifically, the multilayer stack 22 includes a pseudo-nanostructure 24A, one or more pseudo-nanostructures 24B, a lower semiconductor nanostructure 26L, and an upper semiconductor nanostructure 26U. Pseudo-nanostructures 24A and 24B can be further collectively referred to as pseudo-nanostructure 24, and the lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U can be further collectively referred to as semiconductor nanostructure 26.

[0023] The pseudo-nanostructure 24A is formed of a first semiconductor material, and the pseudo-nanostructure 24B is formed of a second semiconductor material different from the first semiconductor material. The first and second semiconductor materials can be selected from candidate semiconductor materials of the substrate 20. The first and second semiconductor materials have high etch selectivity towards each other. Therefore, in subsequent processes, the pseudo-semiconductor layer 24B can be removed at a faster rate than the pseudo-semiconductor layer 24A.

[0024] Semiconductor nanostructure 26 (including lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U) is formed of one or more third semiconductor materials. The third semiconductor material can be selected from candidate semiconductor materials of the substrate 20. The lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U can be formed of the same semiconductor material or different semiconductor materials. Furthermore, the first and second semiconductor materials of the pseudo-nanostructure 24 exhibit high etch selectivity towards the third semiconductor material of the semiconductor nanostructure 26. Therefore, the pseudo-nanostructure 24 can be selectively removed in subsequent process steps without significantly removing the semiconductor nanostructure 26. In some embodiments, the pseudo-nanostructure 24A is formed of or includes silicon-germanium, the semiconductor nanostructure 26 is formed of silicon, and the pseudo-nanostructure 24B can be formed of germanium or silicon-germanium having a higher percentage of germanium atoms than the pseudo-nanostructure 24A.

[0025] The lower semiconductor nanostructure 26L will provide the channel region for the lower nanostructure FET used in the CFET. The upper semiconductor nanostructure 26U will provide the channel region for the upper nanostructure FET used in the CFET. The semiconductor nanostructure 26, located directly above / below (e.g., in contact with) the pseudo-nanostructure 24B, can be used for isolation and may or may not be used as the channel region for the CFET. The pseudo-nanostructure 24B will then be replaced by an isolation structure defining the boundary between the lower and upper nanostructure FETs.

[0026] To form the semiconductor strip 28, layers of a first semiconductor material, a second semiconductor material, and a third semiconductor material (arranged as shown and described above) can be deposited over the semiconductor substrate 20. These layers can be grown using processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited using processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). A patterning process can then be applied to the layers of the first, second, and third semiconductor materials and the semiconductor substrate 20 to define the semiconductor strip 28, which includes a semiconductor strip 20', a pseudo-nanostructure 24, and a semiconductor nanostructure 26.

[0027] Semiconductor fins and nanostructures can be patterned using any suitable method. For example, the patterning process can include one or more photolithography processes, including dual patterning or multi-patterning processes. Typically, dual or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a smaller spacing than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed and patterned using a photolithography process over a substrate. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as an etch mask for the patterning process to etch layers of a first semiconductor material, a second semiconductor material, and a third semiconductor material, and the semiconductor substrate 20. Etching can be performed using any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic.

[0028] Similarly, Figure 2 As shown, an isolation region 32, such as a shallow trench isolation (STI) region 32, is formed over the substrate 20 and between adjacent semiconductor strips 28. The STI region 32 may include a dielectric pad and a dielectric material above the dielectric pad. Each of the dielectric pad and the dielectric material may include an oxide such as silicon oxide, a nitride such as silicon nitride, or a combination thereof. Forming the STI region 32 may include: depositing a dielectric layer; and performing a planarization process such as a chemical mechanical polishing (CMP) process, a mechanical polishing process, etc., to remove excess portions of the dielectric material. The deposition process may include ALD, high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc., or a combination thereof. In some embodiments, the STI region 32 includes silicon oxide formed by an FCVD process, followed by an annealing process. The dielectric layer is then recessed to define the STI region 32. The dielectric layer may be recessed such that the upper portion of the semiconductor strip 28 (including the multilayer stack 22) protrudes above the remaining STI region 32.

[0029] After forming the STI region 32, a dummy gate stack 42 can be formed over the upper portion of the semiconductor strip 28 (the portion protruding above the STI region 32) and along the sidewalls of the upper portion of the semiconductor strip 28. Forming the dummy gate stack 42 may include forming a dummy dielectric layer 36 on the semiconductor strip 28. The dummy dielectric layer 36 may be formed or include, for example, silicon oxide, silicon nitride, combinations thereof, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 38 is formed over the dummy dielectric layer 36. The dummy gate layer 38 may be deposited, for example, by physical vapor deposition (PVD), CVD, or other techniques, and then planarized, for example, by a CMP process. The material of the dummy gate layer 38 may be conductive or non-conductive and may be selected from the group including amorphous silicon, polycrystalline silicon, poly-SiGe, etc. A mask layer 40, including, for example, silicon nitride, silicon oxynitride, etc., is formed over the planarized dummy gate layer 38. Next, the mask layer 40 can be patterned using photolithography and etching processes to form a mask, which is then used to etch and pattern the dummy gate layer 38, and possibly etch and pattern the dummy dielectric layer 36. The remaining portions of the mask layer 40, the dummy gate layer 38, and the dummy dielectric layer 36 form the dummy gate stack 42.

[0030] exist Figure 3 In this process, a gate spacer 44 and a source / drain recess 46 are formed. First, the gate spacer 44 is formed over the multilayer stack 22 and on the exposed sidewalls of the dummy gate stack 42. The gate spacer 44 can be formed by conformally forming one or more dielectric layers and then anisotropically etching the dielectric layers. Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., which can be formed by deposition processes such as CVD, ALD, etc. Fin spacers (not specifically shown) may also be formed as part of the formation of the gate spacer 44.

[0031] Subsequently, source / drain recesses 46 are formed in semiconductor strip 28. The source / drain recesses 46 are formed by etching and can extend through the multilayer stack 22 and into semiconductor strip 20'. The bottom surface of the source / drain recesses 46 can be located above, below, or flush with the top surface of isolation region 32. During the etching process, gate spacers 44 and dummy gate stacks 42 mask portions of semiconductor strip 28. Etching can include a single etching process or multiple etching processes. When the source / drain recesses 46 reach the desired depth, a timing etching process can be used to stop the etching of the source / drain recesses 46.

[0032] Figure 4The various subsequent processing steps are illustrated. Specifically, internal spacers 54 and dielectric isolation layers 56 are formed. Forming the internal spacers 54 and dielectric isolation layers 56 may include an etching process that laterally etches the pseudo-nanostructure 24A and removes the pseudo-nanostructure 24B. The etching process may be isotropic and selective for the material of the pseudo-nanostructure 24, such that the pseudo-nanostructure 24 is etched at a faster rate than the semiconductor nanostructure 26. The etching process may also be selective for the material of the pseudo-nanostructure 24B, such that the pseudo-nanostructure 24B is etched at a faster rate than the pseudo-nanostructure 24A. In this way, the pseudo-nanostructure 24B can be completely removed from between the lower semiconductor nanostructure 26L (collectively referred to as the lower semiconductor nanostructure 26L) and the upper semiconductor nanostructure 26U (collectively referred to as the upper semiconductor nanostructure 26U), without completely removing the pseudo-nanostructure 24A.

[0033] In some embodiments, where the pseudo-nanostructure 24B is formed of germanium or silicon-germanium with a high percentage of germanium atoms, the pseudo-nanostructure 24A is formed of silicon-germanium with a low percentage of germanium atoms, and the semiconductor nanostructure 26 is formed of germanium-free silicon, the etching process may include a dry etching process using chlorine gas, with or without plasma. Because the pseudo-gate stack 42 surrounds the sidewalls of the semiconductor nanostructure 26 (see...), Figure 2 Therefore, the dummy gate stack 42 can support the upper semiconductor nanostructure 26U, preventing it from collapsing when the dummy nanostructure 24B is removed. Furthermore, although the sidewalls of the dummy nanostructure 24A are shown as straight after etching, the sidewalls can be concave or convex.

[0034] An internal spacer 54 is formed on the sidewall of the recessed pseudo-nanostructure 24A, and a dielectric isolation layer 56 is formed between the upper semiconductor nanostructure 26U (collectively referred to as the upper semiconductor nanostructure 26U) and the lower semiconductor nanostructure 26L (collectively referred to as the lower semiconductor nanostructure 26L). As will be described in more detail later, source / drain regions will subsequently be formed in the source / drain recess 46, and the pseudo-nanostructure 24A will be replaced with the corresponding gate structure. The internal spacer 54 serves as an isolation component between the subsequently formed source / drain regions and the subsequently formed gate structure. Furthermore, the internal spacer 54 can be used to prevent damage to the subsequently formed source / drain regions by subsequent etching processes (such as etching processes for forming the gate structure). On the other hand, the dielectric isolation layer 56 is used to isolate the upper semiconductor nanostructure 26U (collectively referred to as the upper semiconductor nanostructure 26L) from the lower semiconductor nanostructure 26L (collectively referred to as the lower semiconductor nanostructure 26L). In addition, the intermediate semiconductor nanostructure (the semiconductor nanostructure 26 in contact with the dielectric isolation layer 56) and the dielectric isolation layer 56 can define the boundary between the lower nanostructure FET and the upper nanostructure FET.

[0035] The internal spacer 54 and dielectric isolation layer 56 can be formed by conformally depositing an insulating material in the source / drain trench 46, on the sidewalls of the pseudo-nanostructure 24, and between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L, and then etching the insulating material. The insulating material can be a hard dielectric material, such as a carbon-containing dielectric material, such as silicon oxycarbonate, silicon oxycarbonate, silicon oxynitride, etc. Other low dielectric constant (low k) materials with a k value of less than about 3.5 can be used. The insulating material can be formed by a deposition process, such as ALD, CVD, etc. The etching of the insulating material can be anisotropic or isotropic. The insulating material (when etched) has a portion retained in the sidewalls of the pseudo-nanostructure 26A (thus forming the internal spacer 54) and a portion retained between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L (thus forming the dielectric isolation layer 56).

[0036] like Figure 4 As further shown, a lower epitaxial source / drain region 62L and an upper epitaxial source / drain region 62U are formed. The lower epitaxial source / drain region 62L is formed in the lower portion of the source / drain recess 46. The lower epitaxial source / drain region 62L is in contact with the lower semiconductor nanostructure 26L, but not with the upper semiconductor nanostructure 26U. An internal spacer 54 electrically insulates the lower epitaxial source / drain region 62L from the pseudo-nanostructure 24A, which will be replaced with a replacement gate in a subsequent process.

[0037] The lower epitaxial source / drain region 62L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain region 62L is an n-type source / drain region, the corresponding material may include silicon or carbon-doped silicon doped with n-type dopants such as phosphorus or arsenic. When the lower epitaxial source / drain region 62L is a p-type source / drain region, the corresponding material may include silicon or silicon-germanium doped with p-type dopants such as boron or indium. The lower epitaxial source / drain region 62L may be in-situ doped and may or may not be implanted with the corresponding p-type or n-type dopants. During the epitaxy of the lower epitaxial source / drain region 62L, the exposed surfaces (e.g., sidewalls) of the upper semiconductor nanostructure 26U may be masked to prevent undesirable epitaxial growth on the upper semiconductor nanostructure 26U. After growing the lower epitaxial source / drain region 62L, the mask on the upper semiconductor nanostructure 26U can then be removed.

[0038] Due to the epitaxial process used to form the lower epitaxial source / drain regions 62L, the upper surface of the lower epitaxial source / drain regions 62L has small planes that extend laterally outward beyond the sidewalls of the multilayer stack 22. In some embodiments, adjacent lower epitaxial source / drain regions 62L remain separated after the epitaxial process is completed. In other embodiments, these small planes cause adjacent lower epitaxial source / drain regions 62L of the same FET to merge.

[0039] A first contact etch stop layer (CESL) 66 and a first ILD 68 are formed above the lower epitaxial source / drain region 62L. The first CESL 66 can be formed from a dielectric material with high etch selectivity relative to the etching of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and can be formed by any suitable deposition process, such as CVD, ALD, etc. The first ILD 68 can be formed from a dielectric material, which can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Suitable dielectric materials for the first ILD 68 may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, etc.

[0040] The formation process may include: depositing a conformal CESL layer; depositing material for the first ILD 68; and a subsequent planarization process and then an etch-back process. In some embodiments, the first ILD 68 is first etched, leaving the first CESL 66 unetched. An anisotropic etching process is then performed to remove the portion of the first CESL 66 above the recessed first ILD 68. After recessing, the sidewalls of the upper semiconductor nanostructure 26U are exposed.

[0041] Then, an upper epitaxial source / drain region 62U is formed in the upper portion of the source / drain recess 46. The upper epitaxial source / drain region 62U can be epitaxially grown from the exposed surface of the upper semiconductor nanostructure 26U. The material of the upper epitaxial source / drain region 62U can be selected from the same group of candidate materials used to form the lower source / drain region 62L, depending on the desired conductivity type of the upper epitaxial source / drain region 62U. In embodiments where the stacked transistor is a CFET, the conductivity type of the upper epitaxial source / drain region 62U can be opposite to that of the lower epitaxial source / drain region 62L. For example, the upper epitaxial source / drain region 62U can be doped in opposite directions to the lower epitaxial source / drain region 62L. Alternatively, the upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L can have the same conductivity type. The upper epitaxial source / drain region 62U may be in-situ doped with n-type or p-type dopants and / or implanted with n-type or p-type dopants. Adjacent upper source / drain regions 62U may remain separated after the epitaxial process, or they may be merged.

[0042] After forming the epitaxial source / drain region 62U, a second CESL 70 and a second ILD 72 are formed. The materials and formation methods can be similar to those of the first CESL 66 and the first ILD 68, respectively, and will not be discussed in detail here. The formation process may include: depositing layers for CESL 70 and ILD 72; and performing a planarization process to remove excess portions of the corresponding layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacer 44, and the mask 40 (if present) or the dummy gate 38 are substantially coplanar (within process variations). Therefore, the top surface of the mask 40 (if present) or the dummy gate 38 is exposed through the second ILD 124. In the illustrated embodiment, the mask 40 is retained after the removal process. In other embodiments, the mask 40 is removed, thereby exposing the top surface of the dummy gate 38 through the second ILD 72.

[0043] exist Figure 5In this process, a gate replacement process is performed to replace the dummy gate stack 42 and the dummy nanostructure 24A with a gate stack 90. ​​The gate replacement process includes first removing the remaining portions of the dummy gate stack 42 and the dummy nanostructure 24A. The dummy gate stack 42 is removed in one or more etching processes, thereby defining a trench between the gate spacers 44 and exposing the upper portion of the semiconductor strip 28. The remaining portions of the dummy nanostructure 24A are then removed by etching, such that the trench extends between the semiconductor nanostructures 26. In the etching process, the material of the dummy nanostructure 24A is etched at a rate faster than the material of the semiconductor nanostructure 26, the dielectric isolation layer 56, and the internal spacers 54. The etching can be isotropic. For example, when the dummy nanostructure 24A is formed of silicon germanium and the semiconductor nanostructure 26 is formed of silicon, the etching process can include a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc.

[0044] Then, a gate dielectric 78 is deposited in the recesses between the gate spacers 44 and on the exposed semiconductor nanostructure 26. The gate dielectric 78 is conformally formed on the exposed surface of the recesses (removed gate stack 42 and pseudo nanostructure 24A) including the semiconductor nanostructure 26 and the gate spacers 44. In some embodiments, the gate dielectric 78 encapsulates all (e.g., four) sides of the semiconductor nanostructure 26. Specifically, the gate dielectric 78 may be formed on the top surface of the fin 20'; the top, sidewalls, and bottom surfaces of the semiconductor nanostructure 26; and the sidewalls of the gate spacers 44. The gate dielectric 78 may include oxides such as silicon oxide or metal oxides, silicates such as metal silicates, combinations thereof, multilayers thereof, etc. The gate dielectric 78 may include high dielectric constant (high k) materials having a k value greater than about 7.0, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods for forming the gate dielectric 78 may include molecular beam deposition (MBD), ALD, PECVD, etc., followed by a planarization process (e.g., CMP) to remove the portion of the gate dielectric 78 located above the second ILD 72. Although a single-layer gate dielectric 78 is shown, the gate dielectric 78 may include multiple layers, such as an interface layer and an upper high-k dielectric layer.

[0045] A lower gate electrode 80L is formed on a gate dielectric 78 surrounding the lower semiconductor nanostructure 26L. For example, the lower gate electrode 80L encapsulates the lower semiconductor nanostructure 26L. The lower gate electrode 80L can be formed of a metallic material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, or multilayers thereof. Although a single-layer gate electrode is shown, the lower gate electrode 80L may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0046] The lower gate electrode 80L is formed of a material suitable for the device type of the lower nanostructure FET. For example, the lower gate electrode 80L may include one or more work function adjustment layers formed of a material suitable for the device type of the lower nanostructure FET. In some embodiments, the lower gate electrode 80L includes an n-type work function adjustment layer, which may be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, etc. In some embodiments, the lower gate electrode 80L includes a p-type work function adjustment layer, which may be formed of titanium nitride, tantalum nitride, combinations thereof, etc. Additionally or optionally, the lower gate electrode 80L may include a dipole inducing element suitable for the device type of the lower nanostructure FET. Acceptable dipole inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0047] The lower gate electrode 80L can be formed by: conformally depositing one or more gate electrode layers; or by recessing the gate electrode layers. Any acceptable etching process, such as dry etching, wet etching, or combinations thereof, can be performed to recess the gate electrode layers. The etching can be isotropic. Etching the lower gate electrode 80L can expose the upper semiconductor nanostructure 26U.

[0048] In some embodiments, an isolation layer (not explicitly shown) may optionally be formed on the lower gate electrode 80L. The isolation layer serves as an isolation component between the lower gate electrode 80L and the subsequently formed upper gate electrode 80U. The isolation layer may be formed by conformally depositing a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, etc.) and subsequently recessing the dielectric material to expose the upper semiconductor nanostructure 26U.

[0049] Then, an upper gate electrode 80U is formed on the isolation layer (if present) or lower gate electrode 80L described above. The upper gate electrode 80U is disposed between the upper semiconductor nanostructures 26U. In some embodiments, the upper gate electrode 80U encapsulates the upper semiconductor nanostructures 26U. The upper gate electrode 80U may be formed from the same candidate materials and candidate processes used to form the lower gate electrode 80L. The upper gate electrode 80U is formed from a material suitable for the device type of the upper nanostructure FET. For example, the upper gate electrode 80U may include one or more work function adjustment layers (e.g., n-type work function adjustment layers and / or p-type work function adjustment layers) formed from a material suitable for the device type of the upper nanostructure FET. Although a single-layer gate electrode 80U is shown, the upper gate electrode 80U may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0050] Furthermore, a removal process is performed to make the top surfaces of the upper gate electrode 80U and the second ILD 72 flush. The removal process used to form the gate dielectric 78 can be the same as the removal process used to form the upper gate electrode 80U. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, etc., can be utilized. After the planarization process, the top surfaces of the upper gate electrode 80U, the gate dielectric 78, the second ILD 72, and the gate spacer 44 are substantially coplanar (within process variations). Each corresponding pair of gate dielectric 78 and gate electrode 80 (including the upper gate electrode 80U and / or the lower gate electrode 80L) can be collectively referred to as a “gate structure” 90 (including the upper gate structure 90U and the lower gate structure 90L). Each gate structure 90 extends along three sides (e.g., the top surface, sidewalls, and bottom surface) of the channel region of the semiconductor nanostructure 26 (see Figure 1 The lower gate structure 90L may also extend along the sidewalls and / or top surface of the semiconductor fin 20'.

[0051] like Figure 5 As further shown, a gate mask 92 is formed over the gate stack 90. ​​The formation process may include: recessing the gate stack 90; filling the resulting recess with a dielectric material such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbonitride, or combinations thereof; and performing a planarization process to remove excess portions of the dielectric material over the second ILD 72.

[0052] Figures 6 to 12 The diagram illustrates the formation of source / drain contacts 96 (e.g., contact plugs) according to some embodiments for electrical coupling to an upper epitaxial source / drain region 62U and / or a lower epitaxial source / drain region 62L. As described in more detail below, source / drain contact openings 82 are formed to the source / drain regions 62. One or more protective layers 84, 86 are formed above certain surfaces of the structure (e.g., within the source / drain contact openings 82). An epitaxial regeneration process is performed to remove one or more protective layers, and the source / drain contact openings 82 are filled with a conductive material 94 to form the source / drain contacts 96.

[0053] exist Figure 6In this process, an upper source / drain contact opening 82U is formed, extending through the second ILD 72 to the upper epitaxial source / drain region 62U. For example, the upper source / drain contact opening 82U is formed to expose (and optionally extend into) the upper epitaxial source / drain region 62U. Specifically, the upper source / drain contact opening 82U extends through the second ILD 72 and the second CESL 70 to expose the upper epitaxial source / drain region 62U and partially extends into it. According to some embodiments, the upper source / drain contact opening 82U can be formed using photolithography and etching steps. Etching can be performed by any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be isotropic or anisotropic.

[0054] exist Figure 7 In this configuration, a lower source / drain contact opening 82L is formed extending to the lower epitaxial source / drain region 62L. For example, some of the upper source / drain openings 82U extend through the corresponding upper epitaxial source / drain region 62U to expose the lower epitaxial source / drain region 62L below. Thus, the upper source / drain contact opening 82U exposes the upper surface of the first upper epitaxial source / drain region 62U-1, and the lower source / drain contact opening 82L extends through the second upper epitaxial source / drain region 62U-2. Specifically, the lower source / drain contact opening 82L may extend through the second ILD 72, the second CESL 70, the second upper epitaxial source / drain region 62U-2, the first ILD 68, and / or the first CESL 66 to expose the lower epitaxial source / drain region 62L and partially extend into it. Each of the upper source / drain contact openings 82U may or may not be connected to one of the lower source / drain contact openings 82L. In the region where the upper source / drain contact openings 82U and the lower source / drain contact openings 82L are connected, the exposed upper epitaxial source / drain region 62U-2 and the lower epitaxial source / drain region 62L may be electrically connected together by source / drain contacts subsequently formed in the connected upper source / drain contact openings 82U and lower source / drain contact openings 82L (see [link to relevant documentation]). Figure 12 ).

[0055] For example, the upper source / drain contact opening 82U and the lower source / drain contact opening 82L can be formed by a combination of sequential photolithography and etching processes. In some embodiments, the lower source / drain contact opening 82L can be formed before the upper source / drain contact opening 82U. Optionally, this order can be reversed, and the upper source / drain contact opening 82U can be formed before the lower source / drain contact opening 82L.

[0056] According to various embodiments, the source / drain contact opening 82 can have a high aspect ratio. For example, the aspect ratio of the lower source / drain contact opening 82L can be as high as about 8 to about 15. Nevertheless, after the upper source / drain contact opening 82U extends through the second upper epitaxial source / drain region 62U-2, the continued extension of the source / drain contact opening 82 (e.g., the lower source / drain contact opening 82L) through the first ILD 68 includes additional lateral etching of the second upper epitaxial source / drain region 62U-2. In some embodiments, during the formation of the source / drain contact opening 82, a large portion of the material in some of the second upper epitaxial source / drain regions 62U-2 is removed. For example, the process can remove up to between about 50% and about 75% of the corresponding upper epitaxial source / drain region 62U-2.

[0057] exist Figure 8 In this embodiment, a first protective layer 84 is formed in the lower source / drain opening 82L above the lower epitaxial source / drain region 62L. In some embodiments, the first protective layer 84 may also be formed over some or all of the exposed surfaces (e.g., sidewall surfaces) of the first CESL 66 and the first ILD 68. For example, the first protective layer 84 may comprise alumina and is formed by a deposition process such as CVD, ALD, etc.

[0058] In some embodiments, a first protective layer 84 is conformally deposited on the exposed surface of the structure, including within the lower source / drain contact opening 82L. A sacrificial material (not specifically shown) can then be deposited to fill the remaining portion of the lower source / drain contact opening 82L. The sacrificial material can include any suitable dielectric material. A first etching process is then performed on the sacrificial material to completely remove it from the surface of the structure and the upper source / drain contact opening 82L. Specifically, the etching process (e.g., anisotropic etching) can be stopped when the sacrificial material is substantially flush with the upper surface of the first ILD 68. A second etching process can then be performed to remove the exposed portion of the first protective layer 84. Thus, the remaining portion of the first protective layer 84 extends along the sidewall surfaces of the first ILD 68 and the first CESL 66, and the upper surface of the lower epitaxial source / drain region 62L. Finally, a third etching process can be performed to remove the remaining portion of the sacrificial material to expose the remaining portion of the first protective layer 84.

[0059] It should be understood that any suitable process can be used to form the first protective layer 84 as described. In some embodiments (not specifically shown), the remainder of the first protective layer 84 may expose some of the sidewall surfaces of the first ILD 68 and / or the first CESL 66. In other embodiments (not specifically shown), the first protective layer 84 may extend along the upper surface of the lower epitaxial source / drain region 62L, while substantially all of the sidewall surfaces of the first ILD 68 and the first CESL 66 remain exposed.

[0060] exist Figure 9 In this configuration, a second protective layer 86 is formed above the dielectric surfaces of the upper source / drain opening 82U and the lower source / drain opening 82L. Specifically, the second protective layer 86 is formed above the exposed dielectric surfaces of the second ILD 72, the second CESL 70, the gate spacer 44, and the gate mask 92. In some embodiments (not specifically shown), the protective layer 86 may be formed above and along some or all of the sidewall surfaces of the first ILD 68 and the first ILD 66 not covered by the first protective layer 84. Therefore, the second protective layer 86 selectively passivates nitrides (e.g., Si3N4) and oxides (e.g., SiO2). x ) surface. In some embodiments (not specifically shown), a protective layer 86 may be formed over and along the first protective layer 84.

[0061] According to some embodiments, the second protective layer 86 is a self-assembled monolayer (SAM). Formation of the second protective layer 86 involves flowing precursor molecules over the structure to attach (e.g., physically adsorb thereon and / or bind thereto) -OH groups along exposed surfaces (e.g., oxide surfaces). For example, the precursor molecules may include reactive head groups and protective tail groups attached to each other by atoms such as silicon or carbon.

[0062] According to various embodiments, the precursor molecules include amines (e.g., silylamines), silanes (e.g., alkylsilanes), sulfides (e.g., alkylsulfides), etc. The head group of the precursor molecule may include one, two, or three reactive groups (e.g., leaving groups), wherein one of the reactive groups leaves to provide a point for attachment of the precursor molecule to a dielectric surface (e.g., an oxide surface). In embodiments where the head group includes two or three reactive groups, adjacent attachments of the precursor molecules may bond together to form the second protective layer 86 as discrete temporary connections or substantially continuous (e.g., substantially smooth or mesh network). In other embodiments (e.g., the head group has any number of reactive groups, such as one reactive group), each adjacent attachment of the precursor molecule may remain discrete to form the second protective layer 86 as discontinuous (e.g., hair-like).

[0063] In some embodiments, the precursor molecule may have (R1) for silicon-containing chemicals (e.g., silylamines or alkylsilanes). x -Si-(R2) [4-x] Alternatively, the chemical formula CH3-S-R2 can be used for sulfur-containing chemicals (e.g., alkyl sulfides), where R1 represents a reactive head group and R2 represents a protective tail group. For silicon-containing precursor molecules, the head group includes x reactive groups (e.g., leaving groups), x can be one, two, or three, and the tail group includes 4-x non-reactive groups (e.g., protecting groups). For sulfur-containing precursor molecules, the head group includes one reactive group, and the tail group includes one non-reactive group. For example, R1 can be a hydroxyl group, an alkoxy group (e.g., methoxy, ethoxy, etc.), an amino group, or a halogen group (e.g., chlorine, fluorine, etc.). Furthermore, R2 can be an alkyl group comprising a backbone of 1 to 21 carbons with or without alkyl side chains (optionally including isomers), or an aryl group comprising phenyl, benzyl, naphthyl, anthracene, etc. Some examples of precursor molecules may include silylamines such as (dimethylamino)-trimethylsilane (DMATMS), alkylsilanes such as trimethyl(propyl)silane, or alkyl sulfides such as diethyl sulfide. However, any suitable chemical substance suited to the above description may be used as a precursor molecule.

[0064] Alternatively, as discussed in more detail below (see Figures 19 to 21Prior to the formation of the second protective layer 86, surface treatments may be performed on the structure to remove native oxides (if any), and / or surface oxidation treatments may be performed on the dielectric surfaces listed above. For example, native oxide removal is performed to remove any native oxide layers that may have formed along non-oxide surfaces. Furthermore, surface oxidation treatments can transform nitride surfaces (e.g., those of the second CESL 70, gate spacer 44, and / or gate mask 92) into oxide surfaces. Thus, silicon nitride regions on these surfaces can be transformed into silicon oxide regions. Additionally, surface oxidation treatments can increase the concentration of -OH groups along oxide surfaces (e.g., those of the second ILD 68). It should be noted that surface oxidation treatments can have similar effects on the surfaces of the first protective layer 84 (e.g., oxides and / or nitrides).

[0065] exist Figure 10 In this process, a regeneration process is performed on the upper epitaxial source / drain region 62U to form a first epitaxial regeneration layer 63-1 and a second epitaxial regeneration layer 63-2. As shown, the first epitaxial regeneration layer 63-1 is formed above the upper surface of the first upper epitaxial source / drain region 62U-1 exposed by the upper source / drain contact opening 82U. Furthermore, the second epitaxial regeneration layer 63-2 is formed along the surface of the second upper epitaxial source / drain region 62U-2.

[0066] According to some embodiments, the regeneration process includes a low-temperature epitaxial growth process. In embodiments where the upper epitaxial source / drain region 62U includes an n-type epitaxial layer, the epitaxial regeneration layer 63 can be deposited at a temperature between 350°C and 400°C and may include SiP, SiAs, or combinations thereof. In embodiments where the upper epitaxial source / drain region 62U includes a p-type epitaxial layer, the epitaxial regeneration layer 63 can be deposited at a temperature between 350°C and 400°C and may include SiB, SiGe, SiGeB, or combinations thereof. Deposition temperatures below 400°C are used to reduce the thermal budget while protecting other portions of the stacked transistor structure. In any case, in some embodiments, the epitaxial regeneration layer 63 may have a different composition than the portion of the upper epitaxial source / drain region 62U it replaces. Furthermore, the epitaxial regeneration layer 63 may have a different composition than the immediately adjacent portion of the upper epitaxial source / drain region 62U (e.g., directly below or directly laterally adjacent). For example, the epitaxial regenerated layer 63 may have a lower concentration of the corresponding impurities (e.g., phosphorus, arsenic, boron, etc.) than the counterparts described above.

[0067] It should be understood that the epitaxial regeneration process benefits from selective epitaxial growth due to the presence of the second protective layer 86. Specifically, the low-temperature epitaxy of the epitaxial regeneration layer 63 exhibits high selectivity for semiconductor materials (e.g., the material of the upper epitaxial source / drain region 62U) compared to the second protective layer 86. In fact, this selectivity is greater than the relatively low selectivity for semiconductor materials compared to dielectric materials (e.g., nitrides such as silicon nitride and oxides such as silicon oxide). Therefore, the epitaxial regeneration layer 63 can follow the crystal structure of the lower epitaxial source / drain region 62U. Furthermore, little to no amorphous epitaxial material will be formed over other surfaces of the structure (e.g., including the second protective layer 86).

[0068] Furthermore, the second protective layer 86 is chemically inert due to the non-reactive tail groups extending outward from the dielectric surface. Additionally, the second protective layer 86 is thermally stable. These properties further ensure that the epitaxial regrowth process can be performed with higher yields, without undesirable deposition of epitaxial material, and without undesirable side reactions between the second protective layer 86 and other nearby molecules.

[0069] exist Figure 11 In the process, the second protective layer 86 and the first protective layer 84 are removed. In various embodiments, the second protective layer 86 may be removed first, as it may have already formed over the first protective layer 84. The first protective layer 84 can then be removed. For example, the second protective layer 86 can be removed using chemical dry etching with ammonia and / or hydrogen fluoride. Alternatively, plasma treatment (e.g., hydrogen radical plasma treatment) can be performed for thorough cleaning, such as removal of carbon residues (if present). The removal of the first protective layer 84 can be carried out using any suitable method, such as etching processes, for example, for patterning during the formation of the first protective layer 84 (see...). Figure 8 ).

[0070] exist Figure 12 In this embodiment, a source / drain contact 96 is formed in the source / drain contact opening 82. In some embodiments, prior to forming the source / drain contact 96, a metal-semiconductor alloy region 88 is formed above the exposed surface of the source / drain region (e.g., above the first and second epitaxial regeneration layers 63). The metal-semiconductor alloy region 88 is formed at the interface between the source / drain region 62 and the source / drain contact 96.

[0071] For example, the metal-semiconductor alloy region 88 can be a silicide region formed from metal silicides (e.g., nickel silicide (NiSi), titanium silicide (TiSi), tungsten silicide (WSi), molybdenum silicide (MoSi), ruthenium silicide (RuSi), zirconium silicide (ZrSi), antimony silicide (SbSi), cobalt silicide (CoSi), etc.), a germanide region formed from metal germanides (e.g., nickel germanide (NiGe), titanium germanide (TiGe), tungsten germanide (WGe), molybdenum germanide (MoGe), ruthenium germanide (RuGe), zirconium germanide (ZrGe), antimony germanide (SbGe), cobalt germanide (CoGe), etc.), or a silicon-germanide region formed from both metal silicides and metal germanides. The metal-semiconductor alloy region 88 can be formed by depositing metal in the opening for the source / drain contact 96 before the material of the source / drain contact 96 and then performing a thermal annealing process. The metal can be any metal capable of reacting with the semiconductor material of the source / drain region 62 (e.g., silicon, silicon germanium, germanium, etc.) to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof.

[0072] Furthermore, the metal can be deposited using deposition processes such as ALD, CVD, PVD, etc. Following the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from the openings for the source / drain contacts 96 (such as from the surface of the metal-semiconductor alloy region 88). The metal-semiconductor alloy region 88 may include an upper metal-semiconductor alloy region 88U along the exposed surface of the upper source / drain region 62U and a lower metal-semiconductor alloy region 88L along the exposed surface of the lower source / drain region 62L. In some embodiments, a portion (which may or may not be all) of the first epitaxial regrown layer 63-1 and the second epitaxial regrown layer 63-2 is converted into the upper metal-semiconductor alloy region 88U. For example, in the illustrated cross-section, a portion (but not all) of the first epitaxial regrown layer 63-1 is converted into the upper metal-semiconductor alloy region 88U-1, while the entire second epitaxial regrown layer 63-2 is converted into the upper metal-semiconductor alloy region 88U-2. In some embodiments (not specifically shown), only a portion (e.g., less than all) of the two epitaxial regeneration layers 63 is converted into the corresponding upper metal-semiconductor alloy region 88U.

[0073] Still referencing Figure 12Conductive material 94 is formed in the source / drain contact opening 82 and above the metal-semiconductor alloy region 88 to electrically couple to the upper epitaxial source / drain region 62U and / or the lower epitaxial source / drain region 62L. The conductive material 94 can be a metal, such as ruthenium, tungsten, molybdenum, cobalt, copper, copper alloys, silver, gold, aluminum, nickel, combinations thereof, etc., and can be formed by plating processes, PVD, CVD, ALD, etc. A removal process can be implemented to remove excess conductive material 94 from the top surface of the gate spacer 44 and the second ILD 72. The remaining conductive material 94 forms source / drain contacts 96 in the source / drain contact opening 82. In some embodiments, a planarization process, such as CMP, etch-back process, combinations thereof, is utilized. After the planarization process, the top surfaces of the gate spacer 44, the second ILD 72, and the source / drain contacts 96 are substantially coplanar (within process variations). It should be understood that the conductivity of the source / drain contact 96 (e.g., conductive material) can be greater than the conductivity of the epitaxial source / drain region 62.

[0074] exist Figure 13 In the process, ESL 104 and third ILD 106 are then formed. In some embodiments, ESL 104 may comprise a dielectric material with high etch selectivity relative to the etching of third ILD 106, such as alumina, aluminum nitride, silicon carbide, etc. The third ILD 106 may be formed using flowable CVD, ALD, etc., and the material may include PSG, BSG, BPSG, USG, etc., which may be deposited by any suitable method, such as CVD, PECVD, etc.

[0075] Subsequently, a gate contact 108 and a source / drain via 110 are formed to contact the upper gate electrode 80U and the source / drain contact 96, respectively. As an example of forming the gate contact 108 and the source / drain via 110, openings for the gate contact 108 and the source / drain via 110 are formed through the third ILD 106 and ESL 104. The openings can be formed using acceptable photolithography and etching techniques. Pads (not shown separately) (such as diffusion barrier layers, adhesive layers, etc.) and conductive material are formed within the openings. The pads may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc. A planarization process, such as CMP, can be performed to remove excess material from the top surface of the third ILD 106. The remaining pads and conductive material form the gate contact 108 and the source / drain via 110 within the openings. The gate contact 108 and the source / drain via 110 can be formed in different processes or in the same process. Although shown as being formed in the same cross section, it should be understood that each of the gate contact 108 and the source / drain via 110 can be formed in a different cross section, which can avoid short circuits in the contacts.

[0076] A front-side interconnect structure 114 is formed on device layer 112. The front-side interconnect structure 114 includes a dielectric layer 116 and a layer of conductive components 118 within the dielectric layer 116. The dielectric layer 116 may include a low-k dielectric layer formed of a low-k dielectric material. The dielectric layer 116 may also include a passivation layer formed of a non-low-k and dense dielectric material above the low-k dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon nitride, or combinations thereof. The dielectric layer 116 may also include a polymer layer.

[0077] Conductive components 118 may include wires and vias, which can be formed using a damascene process. Conductive components 118 may include metal wires and metal vias, which include diffusion barriers and copper-containing material above the diffusion barriers. Aluminum pads may also be present above the metal wires and vias and electrically connected to them. In some embodiments, contacts to the lower gate stack 90L and the lower source / drain region 62L may be fabricated via the back side of device layer 112 (e.g., the side opposite the front interconnect structure 114).

[0078] Although not specifically shown, according to various embodiments, contacts to the lower gate stack 90L and the lower epitaxial source / drain region 62L can be fabricated through the back side of device layer 112 (e.g., the side opposite to the front interconnect structure 114). For example, device layer 112 is located between the front interconnect structure 114 and the back interconnect structure. The back interconnect structure can be substantially similar to the front interconnect structure 114 as described above.

[0079] Contact vias with contact spacers disposed on their sidewalls are formed to extend through at least partially through device layer 112. The contact vias and contact spacers can be formed from the same materials and using the same processes as the upper and lower source / drain vias 110. For example, the openings can be formed by a combination of photolithography and etching processes. The contact spacers can include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, etc., and can be formed by conformally depositing an insulating material layer (not explicitly shown) such as CVD, ALD, etc. Lateral portions of the insulating material layer can then be etched away using an anisotropic etching process (such as plasma-based dry etching) to form the contact spacers. A conductive material, including cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc., is then formed in the openings. A planarization process, such as CMP, can be implemented to remove excess material from the top surface of the second ILD 72.

[0080] Furthermore, before forming ESL 104 and the third ILD 106, contact vias and contact spacers can be formed through the first CESL 66, the first ILD 68, the second CESL 70, and the second ILD 72. The contact vias can be electrically connected to the back-side interconnect structure, and can also be electrically connected to the front-side interconnect structure 114 (e.g., via the upper source / drain contact 96). In this way, an interconnection between the front-side interconnect structure 114 and the back-side interconnect structure can be achieved.

[0081] Furthermore, some of the source / drain contacts 96 can be coupled to contact vias. The source / drain contacts 96 can be formed similarly to those described above. Figures 6 to 12 Implemented as described. In some embodiments, the third ILD 106 is formed prior to the formation of the source / drain contact 96 or as part of the formation of the source / drain contact 96. Furthermore, the third ILD 106 may include multiple layers to facilitate multiple patterning and etching steps for coupling the source / drain contact 96 to the contact via and / or the source / drain region 62. Therefore, the third ILD 106 and the etch stop layer 104 may together comprise multiple ESL and ILD layers.

[0082] Figures 14 to 16 Additional embodiments for forming stacked transistors with some variations from those described above are shown. It should be noted that the processes and components used for the stacked transistors described below can be the same as or similar to those described above, unless otherwise stated.

[0083] Figure 14 The above combination is shown. Figure 11The described steps include an embodiment of removing the second protective layer 86, wherein some or all of the first protective layer 84 remains in the lower source / drain contact opening 82L. Optionally, an etching process may be performed to remove a portion of the first protective layer 84 from the upper surface of the lower epitaxial source / drain region 62L before forming the lower metal-semiconductor alloy region 88L. The remaining portion of the first protective layer 84 along the sidewalls of the first ILD 68 and CESL 66 may be, for example, deposited thinner (see...). Figure 8 As shown, the source / drain contact 96 can then be formed along with the metal-semiconductor alloy region 88 and the conductive material 94, similarly as described above.

[0084] Figure 15 The above combination is shown. Figure 12 The described steps include an embodiment in which at least some of the second epitaxial regrown layers 63-2 are retained after the formation of the upper metal-semiconductor alloy region 88U-2. Some of the second epitaxial regrown layers 63-2 can be converted into the upper metal-semiconductor alloy region 88U-2, while the remainder of the second epitaxial regrown layers 63-2 along the sidewalls of the upper epitaxial source / drain region 62U-2 can be, for example, thinner (see embodiment 1). Figure 10 As shown, the source / drain contact 96 can then be completed along with the formation of the conductive filler material 94, similarly as described above.

[0085] Figure 16 This shows that at least some of the first protective layers 84 are retained after the second protective layer 86 is removed (see...). Figure 11 and Figure 14 And after the formation of the upper metal-semiconductor alloy region 88U-2, at least some of the second epitaxial regeneration layers 63-2 are retained (see...). Figure 12 and Figure 15 Examples of implementations. For example, Figure 16 Indicates combination Figure 14 and Figure 15 The combination of components described. Similarly, the source / drain contact 96 can then be completed along with the formation of the conductive filler material 94, similarly as described above.

[0086] Figure 17 and Figure 18 The chemical structure and reaction mechanism in the formation of the second protective layer 86 are shown. Figure 17 The overall structure of the precursor molecule is shown, and Figure 18 An exemplary chemical reaction mechanism for the surface treatment and formation of the second protective layer 86 is shown.

[0087] Figure 17A precursor molecule 202 having a head group 204 and a tail group 206 is depicted. As discussed above, and as shown along the top row, the head group 204 may include one or more (e.g., up to three) reactive groups 204A, 204B, 204C (e.g., leaving groups), and the tail group 206 may include one or more (e.g., up to three) non-reactive groups 206A, 206B, 206C (e.g., protecting groups). It should be noted that any suitable combination of them can be used, such as a head group 204 having a reactive group and a tail group 206 having a non-reactive group 206A.

[0088] Further along the bottom row are shown some exemplary head groups 204 (and corresponding reactive groups) and some exemplary tail groups 206 (and corresponding non-reactive groups). For example, head groups 204 may include silanes containing hydroxyl groups, methoxy groups, ethoxy groups, halogens (e.g., fluorine, chlorine, iodine), or alkyl sulfides such as methyl sulfides, ethyl sulfides, etc. It should be noted that silicon atoms may be considered as part of head groups 204, wherein each of the attached functional groups is a reactive group 204A, 204B, 204C. Furthermore, tail groups 206 may include a backbone of 1 to 21 carbons (e.g., a backbone of 20 carbons) having or not having alkyl side chains (optionally, including their isomers) or aryl groups such as phenyl groups, benzyl groups, naphthyl groups, anthracene groups, etc. It should be noted that each alkyl side chain may or may not be branched and may be of any suitable length, such as methyl, ethyl, propyl, butyl, etc.

[0089] Figure 18 Surface treatment (e.g., surface oxidation treatment) of exemplary nitride layers (e.g., second CESL 70) and exemplary oxide layers (e.g., second ILD 72) is illustrated, along with the reaction of precursor molecules with the treated surface to form a second protective layer 86. The surface oxidation treatment may include: cleaning, including deionized water, ozone, hydrogen peroxide, or combinations thereof. In some embodiments, a first cleaning includes ozone and / or hydrogen peroxide, and a second cleaning includes deionized water. After the surface treatment, the precursor molecules are processed using a suitable method (such as those described below). Figures 19 to 21 The exemplary method described is applied to the structure.

[0090] As shown, surface treatment can convert -NH2 groups along nitride surfaces (e.g., Si3N4) into -OH groups. Furthermore, surface treatment can increase the number of -NH2 groups along oxide surfaces (e.g., SiO2). xThe surface concentration (e.g., surface density) of the -OH groups. Upon application of the precursor molecules, the precursor molecules will be physically adsorbed along the -OH surface. Furthermore, the precursor molecules can undergo hydrolysis with water molecules in the environment or along the -OH surface. The hydrolysis reaction causes the -OH head groups to replace some of the reactive groups in the head groups. Additionally, the precursor molecules (e.g., some of which have already been hydrolyzed) will bind to the dielectric surface via mechanisms such as covalent grafting. Finally, in some embodiments, some of the head groups of adjacent covalently bound precursor molecules (e.g., the original reactive groups or new -OH head groups) can react with each other to bind the precursor molecules together. This mechanism can also be referred to as in-plane networking. As discussed above, in-plane networking can produce a second protective layer 86 comprising discrete temporary connections, mesh networks, smooth contours, or combinations thereof.

[0091] Figures 19 to 21 An exemplary method for forming the second protective layer 86 is shown (see Figure 9 Each of the exemplary methods includes the same surface treatment steps (e.g., native oxide removal and surface oxidation treatment), different SAM treatment steps to form the second protective layer 86, and the same post-treatment steps (e.g., rinsing and observation). In the first step 301, diluted hydrogen fluoride (e.g., 1:100 dHF) is applied to the structure (e.g., at the wafer level) using a suitable method (e.g., immersing the structure in dHF for up to about 1 minute). In the second step 302, the structure is rinsed with deionized water (DIW) and dried by blowing nitrogen (N2) over it. In the third step 303, a SAM treatment is performed to form the second protective layer 86. In the fourth step 304, the structure may be rinsed with an alcohol such as isopropanol, rinsed with deionized water, and dried by blowing nitrogen over it. In the fifth step 305, SAM coverage observation may be performed to confirm adequate coverage of the second protective layer 86. SAM coverage observation can include measuring the contact angle of a few drops of water (e.g., about 5 points at various locations on the wafer) or using a tribometer to analyze changes in the coefficient of friction.

[0092] Figure 19 The diagram illustrates the formation of a second protective layer 86 by immersing a structure in a SAM solution containing precursor molecules using a first SAM processing process 303A. For example, the SAM solution may contain precursor molecules dissolved in an alcohol or acetate solvent, such as methanol, ethanol, isopropanol, propylene glycol methyl ether acetate (PGMEA), etc. The first SAM processing process involves immersing the wafer in a container or tank of the SAM solution for 1 to 5 minutes at ambient pressure and a temperature ranging from 5°C to 60°C for precursor molecule reaction and formation of the second protective layer 86 over the structure.

[0093] Figure 20The second protective layer 86 is shown to be formed using a second SAM processing process 303B by spin-coating a SAM solution. For example, the SAM solution can be as described above in conjunction with the first SAM processing process. The second SAM processing process includes: depositing 5 mL to 20 mL of SAM solution over a wafer fixed to a rotating platform; rotating the wafer at a rotational speed of 50 rpm to 300 rpm for 5 to 30 seconds to fully spread and coat the SAM solution over the wafer; and allowing the precursor molecules to react at a temperature ranging from 5°C to 60°C, under ambient pressure, and for 1 to 5 minutes to form the second protective layer 86.

[0094] Figure 21 The method of forming a second protective layer 86 using a third SAM process 303C is illustrated by flowing precursor molecules (as discussed above) over a structure in a deposition chamber. For example, the precursor molecules flow over the wafer for 1 to 5 minutes at a temperature ranging from 50°C to 300°C and a pressure ranging from 5 Torr to 300 Torr to facilitate the precursor molecule reaction and form the second protective layer 86 over the structure.

[0095] This achieves various advantages. For example, after the lower source / drain contact opening 82L is formed to the lower epitaxial source / drain region 62L, an epitaxial regeneration process can be performed on the upper epitaxial source / drain region 62U. The upper epitaxial source / drain regions 62U, which are etched through to form the lower source / drain contact opening 82L, may have lost a significant portion of their epitaxial material during the process. Therefore, those upper epitaxial source / drain regions 62U can particularly benefit from the epitaxial regeneration process to replenish a large amount of epitaxial material. The step of forming one or more protective layers on the dielectric surface and above the lower epitaxial source / drain region 62L ensures that the epitaxial regeneration process is selective for the upper epitaxial source / drain region 62U. In particular, a second protective layer 86 can be selectively formed above certain dielectric surfaces, and then the epitaxial regeneration layer 63 can be selectively formed above the upper epitaxial source / drain region 62U. The resulting stacked transistors (and semiconductor devices utilizing these transistors) can be manufactured with higher yields and operate with improved performance and reliability.

[0096] In one embodiment, the method includes: forming an upper gate structure adjacent to a first source / drain region and a second source / drain region, and a lower gate structure adjacent to a third source / drain region; patterning a first opening and a second opening through a first dielectric layer to expose the first source / drain region and the second source / drain region; patterning to extend a second opening through a second dielectric layer to expose the third source / drain region; forming a protective layer above the exposed surface of the first dielectric layer; forming a first epitaxial regrown layer above the first source / drain region, and forming a second epitaxial regrown layer above the second source / drain region; removing the protective layer; forming a first source / drain contact to the first epitaxial regrown layer; and forming a second source / drain contact to the second epitaxial regrown layer and the third source / drain region. In another embodiment, the formation of the first epitaxial regrown layer and the formation of the second epitaxial regrown layer are performed simultaneously. In another embodiment, the formation of the first epitaxial regrown layer and the second epitaxial regrown layer includes an epitaxial process at a temperature less than about 400°C. In another embodiment, forming the protective layer includes flowing precursor molecules above the exposed surface of the first dielectric layer, wherein the precursor molecules include silylamine, alkylsilane, or alkyl sulfide. In another embodiment, removing the protective layer includes a chemical dry etching process, wherein the etchant in the chemical dry etching process includes at least one of ammonia or hydrogen fluoride. In another embodiment, removing the protective layer further includes performing a hydrogen plasma treatment. In another embodiment, the method further includes forming an aluminum oxide layer above the third source / drain region and the second dielectric layer prior to forming the protective layer. In another embodiment, the protective layer is chemically bonded to the aluminum oxide layer.

[0097] In one embodiment, the method includes: forming an opening through a first plurality of dielectric layers to expose a first source / drain region; extending the opening through a second plurality of dielectric layers to expose a second source / drain region; forming a first protective layer along the exposed surfaces of the second plurality of dielectric layers and the second source / drain region; forming a second protective layer along the exposed surfaces of the first plurality of dielectric layers; forming an epitaxial regrown layer on the first source / drain region; removing the second protective layer; removing the first protective layer; and forming a source / drain contact in the opening, the source / drain contact being coupled to both the first and second source / drain regions. In another embodiment, extending the opening through the second plurality of dielectric layers includes extending the opening through the first source / drain region. In another embodiment, the first protective layer comprises aluminum oxide. In another embodiment, forming the second protective layer comprises a precursor molecule reacting with and attaching to the first plurality of dielectric layers, wherein the precursor molecule comprises at least one of an alkyl group or an aryl group. In another embodiment, forming the second protective layer comprises impregnation in a solution comprising a precursor molecule dissolved in a solvent. In another embodiment, forming the second protective layer includes spin-coating precursor molecules over the first plurality of dielectric layers. In another embodiment, forming the second protective layer includes flowing precursor molecules over the first plurality of dielectric layers in a deposition chamber.

[0098] In an embodiment, the semiconductor device includes: a first epitaxial region comprising a first epitaxial material; a first silicide region located on the first epitaxial region; a first nanostructure adjacent to the first epitaxial region; a second epitaxial region overlapping the first epitaxial region, the second epitaxial region comprising a second epitaxial material different from the first epitaxial material; a second silicide region located on the second epitaxial region; an interlayer dielectric layer disposed above the first epitaxial region and below the second epitaxial region; and a contact plug extending through the second epitaxial region and the interlayer dielectric layer to be electrically coupled to the first epitaxial region, wherein the contact plug... The conductivity of the plug is greater than that of the first epitaxial region; a third epitaxial region, laterally adjacent to the second epitaxial region, the third epitaxial region comprising a second epitaxial material and a third epitaxial material, the third epitaxial material being different from the first and second epitaxial materials; a third silicide region located on the third epitaxial region, the third silicide region contacting the third epitaxial material of the third epitaxial region; a second nanostructure extending from the second epitaxial region to the third epitaxial region; a first gate structure located around the first nanostructure; and a second gate structure overlapping the first gate structure and located around the second nanostructure. In another embodiment, the second epitaxial region comprises a third epitaxial material, and wherein the second silicide region contacts the third epitaxial material of the second epitaxial region. In another embodiment, the semiconductor device further includes a metal oxide layer extending from the first silicide region to the second silicide region. In another embodiment, the metal oxide layer comprises aluminum oxide. In another embodiment, the second epitaxial region does not have a third epitaxial material.

[0099] Some embodiments of this application provide a method for forming a semiconductor device, including: forming an upper gate structure adjacent to a first source / drain region and a second source / drain region, and a lower gate structure adjacent to a third source / drain region; patterning a first opening and a second opening through a first dielectric layer to expose the first source / drain region and the second source / drain region; patterning to extend the second opening through a second dielectric layer to expose the third source / drain region; forming a protective layer above the exposed surface of the first dielectric layer; forming a first epitaxial regrown layer above the first source / drain region and a second epitaxial regrown layer above the second source / drain region; removing the protective layer; forming a first source / drain contact to the first epitaxial regrown layer; and forming a second source / drain contact to the second epitaxial regrown layer and the third source / drain region.

[0100] In some embodiments, the formation of the first epitaxial regrown layer and the formation of the second epitaxial regrown layer are performed simultaneously. In some embodiments, the formation of the first and second epitaxial regrown layers includes an epitaxial process at a temperature below 400°C. In some embodiments, forming the protective layer includes flowing precursor molecules above the exposed surface of the first dielectric layer, wherein the precursor molecules include silylamine, alkylsilane, or alkyl sulfide. In some embodiments, removing the protective layer includes a chemical dry etching process, wherein the etchant in the chemical dry etching process includes at least one of ammonia or hydrogen fluoride. In some embodiments, removing the protective layer further includes performing a hydrogen plasma treatment. In some embodiments, the method further includes forming an aluminum oxide layer above the third source / drain region and the second dielectric layer prior to forming the protective layer. In some embodiments, the protective layer is chemically bonded to the aluminum oxide layer.

[0101] Other embodiments of this application provide a method of forming a semiconductor device, comprising: forming an opening through a first plurality of dielectric layers to expose a first source / drain region; extending the opening through a second plurality of dielectric layers to expose a second source / drain region; forming a first protective layer along the exposed surfaces of the second plurality of dielectric layers and the second source / drain region; forming a second protective layer along the exposed surfaces of the first plurality of dielectric layers; forming an epitaxial regeneration layer on the first source / drain region; removing the second protective layer; removing the first protective layer; and forming a source / drain contact in the opening, the source / drain contact being coupled to the first source / drain region and coupled to the second source / drain region.

[0102] In some embodiments, extending the opening through the second plurality of dielectric layers includes extending the opening through the first source / drain region. In some embodiments, the first protective layer comprises aluminum oxide. In some embodiments, forming the second protective layer comprises a precursor molecule reacting with and attaching to the first plurality of dielectric layers, wherein the precursor molecule comprises at least one of an alkyl group or an aryl group. In some embodiments, forming the second protective layer comprises impregnating the precursor molecule in a solution comprising the precursor molecule dissolved in a solvent. In some embodiments, forming the second protective layer comprises spin-coating the precursor molecule over the first plurality of dielectric layers. In some embodiments, forming the second protective layer comprises flowing the precursor molecule over the first plurality of dielectric layers in a deposition chamber.

[0103] Some embodiments of this application provide a semiconductor device, including: a first epitaxial region comprising a first epitaxial material; a first silicide region located on the first epitaxial region; a first nanostructure adjacent to the first epitaxial region; a second epitaxial region overlapping the first epitaxial region, the second epitaxial region comprising a second epitaxial material different from the first epitaxial material; a second silicide region located on the second epitaxial region; an interlayer dielectric layer disposed above the first epitaxial region and below the second epitaxial region; and a contact plug extending through the second epitaxial region and the interlayer dielectric layer to be electrically coupled to the first epitaxial region, wherein the contact plug... The electrical conductivity of the plug is greater than that of the first epitaxial region; a third epitaxial region is laterally adjacent to the second epitaxial region, the third epitaxial region comprising the second epitaxial material and a third epitaxial material, the third epitaxial material being different from the first epitaxial material and the second epitaxial material; a third silicide region is located on the third epitaxial region, the third silicide region being in contact with the third epitaxial material of the third epitaxial region; a second nanostructure extends from the second epitaxial region to the third epitaxial region; a first gate structure is located around the first nanostructure; and a second gate structure overlaps with the first gate structure and is located around the second nanostructure.

[0104] In some embodiments, the second epitaxial region includes the third epitaxial material, and wherein the second silicide region is in contact with the third epitaxial material of the second epitaxial region. In some embodiments, the semiconductor device further includes a metal oxide layer extending from the first silicide region to the second silicide region. In some embodiments, the metal oxide layer includes aluminum oxide. In some embodiments, the second epitaxial region does not have the third epitaxial material.

[0105] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A method for forming a semiconductor device, comprising: An upper gate structure adjacent to the first source / drain region and the second source / drain region and a lower gate structure adjacent to the third source / drain region are formed. Pattern the first opening and the second opening through the first dielectric layer to expose the first source / drain region and the second source / drain region; Patterning is used to extend the second opening through the second dielectric layer to expose the third source / drain region; A protective layer is formed above the exposed surface of the first dielectric layer; A first epitaxial regeneration layer is formed above the first source / drain region, and a second epitaxial regeneration layer is formed above the second source / drain region; Remove the protective layer; A first source / drain contact is formed to the first epitaxial regenerated layer; as well as A second source / drain contact is formed in the second epitaxial regeneration layer and the third source / drain region.

2. The method according to claim 1, wherein, The formation of the first epitaxial regeneration layer and the formation of the second epitaxial regeneration layer are carried out simultaneously.

3. The method according to claim 1, wherein, The formation of the first epitaxial regenerated layer and the second epitaxial regenerated layer includes an epitaxial process at a temperature of less than 400°C.

4. The method according to claim 1, wherein, Forming the protective layer includes flowing precursor molecules above the exposed surface of the first dielectric layer, wherein the precursor molecules include silylamine, alkylsilane, or alkylsulfide.

5. The method according to claim 1, wherein, Removing the protective layer includes a chemical dry etching process, wherein the etchant used in the chemical dry etching process includes at least one of ammonia or hydrogen fluoride.

6. The method according to claim 5, wherein, Removing the protective layer also includes performing hydrogen plasma treatment.

7. The method of claim 1, further comprising forming an aluminum oxide layer over the third source / drain region and the second dielectric layer prior to forming the protective layer.

8. The method according to claim 7, wherein, The protective layer is chemically bonded to the alumina layer.

9. A method for forming a semiconductor device, comprising: An opening is formed through the first plurality of dielectric layers to expose the first source / drain region; The opening extends through a second plurality of dielectric layers to expose a second source / drain region; A first protective layer is formed along the exposed surfaces of the second plurality of dielectric layers and the second source / drain regions; A second protective layer is formed along the exposed surfaces of the first plurality of dielectric layers; An epitaxial regeneration layer is formed on the first source / drain region; Remove the second protective layer; Remove the first protective layer; as well as A source / drain contact is formed in the opening, the source / drain contact being coupled to the first source / drain region and to the second source / drain region.

10. A semiconductor device, comprising: A first epitaxial region, the first epitaxial region comprising a first epitaxial material; The first silicide region is located on the first epitaxial region; The first nanostructure is adjacent to the first epitaxial region; The second epitaxial region overlaps with the first epitaxial region, and the second epitaxial region includes a second epitaxial material that is different from the first epitaxial material; The second silicide region is located on the second epitaxial region; An interlayer dielectric layer is disposed above the first epitaxial region and below the second epitaxial region; A contact plug extends through the second epitaxial region and the interlayer dielectric layer to be electrically coupled to the first epitaxial region, wherein the conductivity of the contact plug is greater than the conductivity of the first epitaxial region; The third epitaxial region is laterally adjacent to the second epitaxial region. The third epitaxial region includes the second epitaxial material and the third epitaxial material, and the third epitaxial material is different from the first epitaxial material and the second epitaxial material. A third silicide region is located on the third epitaxial region, and the third silicide region is in contact with the third epitaxial material of the third epitaxial region; The second nanostructure extends from the second epitaxial region to the third epitaxial region; A first gate structure is located around the first nanostructure; and A second gate structure overlaps with the first gate structure and is located around the second nanostructure.

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