Monolithic integrated CMOS (complementary metal oxide semiconductor) driven GaN vertical device and preparation method thereof

Abstract

The invention discloses a monolithic integrated CMOS (complementary metal oxide semiconductor) driving GaN vertical device and a preparation method thereof. The monolithic integrated CMOS driving GaN vertical device comprises a p-channel FET (field effect transistor), an n-channel p-GaN gate GaN HEMT (high electron mobility transistor) and a vertical groove MOSFET, wherein the n-channel p-GaN gate GaN HEMT is positioned on one side of the p-channel FET; the n channel p-GaN gate GaN HEMT, the p channel FET and the vertical groove MOSFET share a drift layer; the drift layer is superposed on the substrate; epitaxial structures in the n-channel p-GaN gate GaN HEMT, the p-channel FET and the vertical groove MOSFET are formed by deposition at the same time; a first isolation region is arranged between the n channel p-GaN gate GaN HEMT and the p channel FET; and a second isolation region is arranged between the vertical trench MOSFET and the p-channel FET, so that a monolithic integrated CMOS driving GaN vertical device scheme with high efficiency and low cost is provided.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a monolithically integrated CMOS (complementary metal-oxide-semiconductor) driven GaN (gallium nitride) vertical device and its fabrication method. Background Technology

[0002] Gallium nitride (GaN) power devices have attracted much attention due to their excellent material properties. However, existing technologies mainly focus on lateral HEMT (high electron mobility transistor) devices, lacking effective integration of vertical devices. In particular, the lagging development of p-type GaN devices has constrained the realization of all-GaN complementary logic.

[0003] Existing monolithic integration solutions for horizontal and vertical devices typically employ complex processes such as secondary epitaxy on pre-etched epitaxial structures to form horizontal and vertical transistors separately, or hybrid integration solutions using discrete packaging or external driving via silicon-based CMOS chips. Neither of these solutions achieves true monolithic integration of horizontal and vertical devices and on-chip CMOS driving. Currently, no monolithic integration solution exists that allows for direct and efficient control of vertical power transistors by a CMOS driving circuit within the same process flow.

[0004] While lateral transistors are easy to integrate, their breakdown voltage and on-resistance are determined by their lateral dimensions. To achieve high breakdown voltage, the gate-drain spacing needs to be significantly increased, leading to a sharp decrease in chip area utilization. Although vertical transistors have superior power handling capabilities and area efficiency, they are difficult to integrate with lateral drive circuits to achieve high efficiency and low parasitic parameters.

[0005] Therefore, how to efficiently and cost-effectively integrate GaN lateral and vertical devices on a single chip has become an important issue. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides a monolithically integrated CMOS-driven GaN vertical device and its fabrication method.

[0007] The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a monolithically integrated CMOS driving GaN vertical device, comprising: An n-channel p-GaN gate GaN HEMT, a p-channel FET, and a vertical trench MOSFET; the n-channel p-GaN gate GaN HEMT is located on one side of the p-channel FET, and the vertical trench MOSFET is located on the other side of the p-channel FET; The n-channel p-GaN gate GaN HEMT, the p-channel FET, and the vertical trench MOSFET share a drift layer; the drift layer is stacked on the substrate; The epitaxial structures in the n-channel p-GaN gate GaN HEMT, the p-channel FET, and the vertical trench MOSFET are deposited simultaneously. A first isolation region is provided between the n-channel p-GaN gate GaN HEMT and the p-channel FET; a second isolation region is provided between the vertical trench MOSFET and the p-channel FET.

[0008] Optionally, the n-channel p-GaN gate GaN HEMT includes the substrate, the drift layer, the first vertical channel layer, the first heavily doped layer, the first lateral channel layer, the first barrier layer, the first cap layer, the first gate, the first source, the first drain, and a first passivation layer covering the surface of the n-channel p-GaN gate GaN HEMT and avoiding the first gate, the first source, and the first drain; The first vertical channel layer, the first heavily doped layer, the first lateral channel layer, and the first barrier layer are stacked sequentially on the drift layer from bottom to top. The first cap layer is superimposed on the upper surface of the first barrier layer; The first source and the first drain are both superimposed on the upper surface of the first barrier layer and are located on both sides of the first cap layer, respectively. The first gate is superimposed on the first cap layer.

[0009] Optionally, the materials of the first vertical channel layer, the first heavily doped layer, the first lateral channel layer, and the first cap layer are all GaN; the material of the first barrier layer is AlGaN or InGaN; the material of the first gate is a metal combination based on Ni / Au, TiN, or Ti / Al; the materials of the first source and the first drain are Ti / Al / Ni / Au, Ti / Al / Pt / Au, Ti / Al / Ti / TiN, or a metal combination based on Ti / Al; and the material of the first passivation layer is at least one of Al2O3, AlTiO, SiO2, Si3N4, and HfO2.

[0010] Optionally, the p-channel FET includes the substrate, the drift layer, the second vertical channel layer, the second heavily doped layer, the second lateral channel layer, the second barrier layer, the second cap layer, the second gate, the second source, the second drain, and a second passivation layer covering the surface of the p-channel FET and avoiding the second source and the second drain. The second vertical channel layer, the second heavily doped layer, the second lateral channel layer, the second barrier layer, and the second cap layer are stacked sequentially on the drift layer from bottom to top. The second drain and the second source are respectively disposed on both sides of the upper surface of the second cap layer; the upper surface region of the second cap layer is provided with a first trench structure; the second gate is located on the second passivation layer within the trench structure.

[0011] Optionally, the materials of the second vertical channel layer, the second heavily doped layer, the second lateral channel layer, and the second cap layer are all GaN; the material of the second barrier layer is AlGaN or InGaN; the material of the second gate is a metal combination based on Ni / Au, TiN, or Ti / Al; the materials of the second source and the second drain are Ti / Al / Ni / Au, Ti / Al / Pt / Au, Ti / Al / Ti / TiN, or a metal combination based on Ti / Al; and the material of the second passivation layer is at least one of Al2O3, AlTiO, SiO2, Si3N4, and HfO2.

[0012] Optionally, the vertical trench MOSFET includes the substrate, the drift layer, the third vertical channel layer, the third heavily doped layer, the third gate, the third source, the third drain, and a third passivation layer covering the surface of the vertical trench MOSFET and avoiding the third source and the third drain. The third vertical channel layer and the third heavily doped layer are stacked on the drift layer from bottom to top. The third source electrode is disposed on both sides of the upper surface of the third heavily doped layer; the third drain electrode is superimposed on the lower surface of the substrate; the middle region of the upper surface of the third heavily doped layer is provided with a second trench structure extending to the drift layer; the third gate electrode is located on the third passivation layer within the second trench structure.

[0013] Optionally, the third vertical channel layer and the third heavily doped layer are both GaN; the material of the third gate is a metal combination based on Ni / Au, TiN, or Ti / Al; the materials of the third source and the third drain are both Ti / Al / Ni / Au, Ti / Al / Pt / Au, Ti / Al / Ti / TiN, or a metal combination based on Ti / Al; and the material of the third passivation layer is at least one of Al2O3, AlTiO, SiO2, Si3N4, and HfO2.

[0014] Optionally, the first isolation region and the second isolation region are formed by nitrogen ion or fluorine ion implantation.

[0015] Optionally, the substrate is made of GaN, Si, sapphire, AlN, SOI, or a composite material; the drift layer is made of GaN.

[0016] Secondly, the present invention provides a method for fabricating a monolithically integrated CMOS-driven GaN vertical device, comprising: A substrate is selected and an epitaxial structure is deposited on the substrate; the epitaxial structure includes, from bottom to top: a drift layer, a vertical channel layer, a heavily doped layer, a lateral channel layer, a barrier layer, and a cap layer; A first region is formed by etching downwards from a portion of one side of the upper surface of the epitaxial structure; wherein the etching depth extends to the upper part of the drift layer; A second region is formed by etching downwards from a portion of the upper surface of the epitaxial structure; wherein the etching depth extends to the upper surface of the barrier layer; A portion of the cap layer in the unetched middle region on the upper surface of the epitaxial structure is etched to form a third region; A first isolation region is formed between the second region and the third region by ion implantation, and a second isolation region is formed between the first region and the third region; A vertical trench MOSFET is fabricated in the first region by sequentially depositing a passivation layer, a gate, a source, and a drain; an n-channel p-GaN gate GaN HEMT is fabricated in the second region; and a p-channel FET is fabricated in the third region.

[0017] This invention provides a monolithically integrated CMOS driver GaN vertical device in which an n-channel p-GaN gate GaN HEMT, a p-channel FET, and a vertical trench MOSFET are co-fabricated on the same substrate, solving the incompatibility problem between monolithic integration processes of GaN lateral and vertical devices. Furthermore, the epitaxial structures in the n-channel p-GaN gate GaN HEMT, p-channel FET, and vertical trench MOSFET are simultaneously deposited, eliminating the complexity of secondary epitaxy required in existing structures, resulting in higher efficiency and lower cost. Moreover, the zero-distance connection between the driver circuit and the power transistor achieves a leap in switching speed and energy efficiency. Simultaneously, the shared heat sink design ensures thermal management and reliability by allowing heat sources to share a single heat dissipation substrate.

[0018] The present invention will now be described in further detail with reference to the accompanying drawings. Attached Figure Description

[0019] Figure 1 This is a cross-sectional view of a monolithically integrated CMOS driving GaN vertical device provided in an embodiment of the present invention; Figure 2 This is an equivalent circuit diagram of a monolithically integrated CMOS driving GaN vertical device provided in an embodiment of the present invention; Figure 3 This is a schematic flowchart of a method for fabricating a monolithically integrated CMOS driving GaN vertical device according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the device structure after the epitaxial structure is fabricated, as provided in the embodiments of the present invention; Figure 5 This is a schematic diagram of the device structure after etching the mesa, provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the device structure obtained by etching the first region according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the device structure obtained by etching the second region according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the device structure obtained by etching the third region according to an embodiment of the present invention; Figure 9 This is a schematic diagram of the device structure after the injection isolation region is provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of the device structure after the passivation layer is deposited, as provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of the device structure after gate metal deposition provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of the device structure after the deposition of source and drain metals provided in an embodiment of the present invention.

[0020] Reference numerals: 10, substrate; 11, drift layer; 20, first vertical channel layer; 21, first heavily doped layer; 22, first lateral channel layer; 23, first barrier layer; 24, first cap layer; 25, first source; 26, first drain; 27, first gate; 30, second vertical channel layer; 31, second heavily doped layer; 32, second lateral channel layer; 33, second barrier layer; 34, second cap layer; 35, second drain; 36, second source; 37, second gate; 40, third vertical channel layer; 41, third heavily doped layer; 42, third source; 43, third drain; 44, third gate. Detailed Implementation

[0021] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0022] To address the issues of low compatibility, high complexity, and high cost associated with existing monolithic integration solutions for horizontal and vertical devices, this invention provides a monolithically integrated CMOS-driven GaN vertical device. (See also...) Figure 1 , Figure 1 This is a cross-sectional view of a monolithically integrated CMOS driving GaN vertical device provided in an embodiment of the present invention. The monolithically integrated CMOS driving GaN vertical device includes an n-channel p-GaN gate GaN HEMT, a p-channel FET, and a vertical trench MOSFET. In this embodiment of the invention, the n-channel p-GaN gate GaN HEMT is located on one side of the p-channel FET, and the vertical trench MOSFET is located on the other side of the p-channel FET.

[0023] n-channel p-GaN gate GaN HEMTs, p-channel FETs, and vertical trench MOSFETs share a drift layer 11 and a substrate 10; the drift layer 11 is stacked on the substrate 10. The substrate 10 can be made of GaN, Si (silicon), sapphire, AlN (aluminum nitride), SOI (silicon-on-insulator), or a composite material. The drift layer 11 is made of n-GaN and its thickness can range from 500 to 100,000 nm.

[0024] In this embodiment of the invention, epitaxial structures in an n-channel p-GaN gate GaN HEMT, a p-channel FET, and a vertical trench MOSFET are simultaneously deposited.

[0025] In one implementation, the n-channel p-GaN gate GaN HEMT includes a substrate 10, a drift layer 11, a first vertical channel layer 20, a first heavily doped layer 21, a first lateral channel layer 22, a first barrier layer 23, a first cap layer 24, a first gate 27, a first source 25, a first drain 26, and a first passivation layer covering the surface of the n-channel p-GaN gate GaN HEMT and avoiding the first gate 27, the first source 25, and the first drain 26.

[0026] The first vertical channel layer 20, the first heavily doped layer 21, the first lateral channel layer 22, the first barrier layer 23, and the first cap layer 24 are epitaxial structures in an n-channel p-GaN gate GaN HEMT; the first vertical channel layer 20, the first heavily doped layer 21, the first lateral channel layer 22, and the first barrier layer 23 are stacked sequentially on the drift layer 11 from bottom to top.

[0027] The first cap layer 24 is superimposed on the upper surface region of the first barrier layer 23; The first source 25 and the first drain 26 are both superimposed on the upper surface of the first barrier layer 23 and are located on opposite sides of the first cap layer 24. Specifically, the first source 25 is disposed on the side of the first cap layer 24 away from the p-channel FET, and the first drain 26 is disposed on the side of the first cap layer 24 closer to the p-channel FET.

[0028] The first gate 27 is superimposed on the first cap layer 24.

[0029] In this embodiment of the invention, the materials of the first vertical channel layer 20, the first heavily doped layer 21, the first lateral channel layer 22, and the first cap layer 24 are all GaN; the material of the first barrier layer 23 is AlGaN (aluminum gallium nitride) or InGaN (indium gallium nitride); the material of the first gate 27 is a metal combination based on Ni (nickel) / Au (gold), TiN (titanium nitride), or Ti (titanium) / Al (aluminum); the materials of the first source 25 and the first drain 26 are all Ti / Al / Ni / Au, Ti / Al / Pt / Au, Ti / Al / Ti / TiN, or a metal combination based on Ti / Al; the material of the first passivation layer is at least one of Al2O3 (aluminum oxide), AlTiO (aluminum titanate), SiO2 (silicon dioxide), Si3N4 (silicon nitride), and HfO2 (hafnium dioxide).

[0030] Furthermore, the material of the first vertical channel layer 20 can be p-GaN, with a thickness ranging from 50 to 3000 nm and a p-type doping concentration ranging from [missing value]. The first heavily doped layer 21 can be made of n+GaN, with a thickness ranging from 10 to 1000 nm. The first lateral channel layer 22 can be made of GaN, with a thickness ranging from 10 to 3000 nm. The first barrier layer 23 can be made of AlGaN or InGaN, with a thickness less than 100 nm. The first cap layer 24 can be made of GaN doped with p-type impurities, including Mg, with a doping concentration ranging from [missing value]. The material of the first passivation layer may include at least one of Al2O3, AlTiO, SiO2, Si3N4 and HfO2, and the thickness of the first passivation layer ranges from 5 to 10000 nm.

[0031] In this embodiment of the invention, the materials of the first source 25 and the first drain 26 can be Ti / Al / Ni / Au, Ti / Al / Pt / Au, Ti / Al / Ti / TiN, or a Ti / Al-based metal combination. The material of the first gate 27 can be Ni / Au-based, TiN-based, or a Ti / Al-based metal combination.

[0032] In one implementation, the p-channel FET includes a substrate 10, a drift layer 11, a second vertical channel layer 30, a second heavily doped layer 31, a second lateral channel layer 32, a second barrier layer 33, a second cap layer 34, a second gate 37, a second source 36, a second drain 35, and a second passivation layer covering the surface of the p-channel FET and avoiding the second source 36 and the second drain 35. The second vertical channel layer 30, the second heavily doped layer 31, the second lateral channel layer 32, the second barrier layer 33, and the second cap layer 34 are epitaxial structures in a p-channel FET. The second vertical channel layer 30, the second heavily doped layer 31, the second lateral channel layer 32, the second barrier layer 33, and the second cap layer 34 are stacked sequentially on the drift layer 11 from bottom to top. The second drain 35 and the second source 36 are respectively disposed on both sides of the upper surface of the second cap layer 34; the upper surface region of the second cap layer 34 is provided with a first trench structure; the second gate 37 is located on the second passivation layer within the first trench structure.

[0033] Specifically, the first trench structure is located on the upper surface region of the second cap layer 34 between the second drain 35 and the second source 36; the second source 36 is disposed on the side of the second cap layer 34 near the n-channel p-GaN gate GaN HEMT, and the second drain 36 is disposed on the side of the second cap layer 34 near the vertical trench MOSFET.

[0034] In this embodiment of the invention, the second vertical channel layer 30, the second heavily doped layer 31, the second lateral channel layer 32, and the second cap layer 34 are all made of GaN; the second barrier layer 33 is made of AlGaN or InGaN; the second gate 37 is made of a metal combination based on Ni / Au, TiN, or Ti / Al; the second source 36 and the second drain 35 are made of Ti / Al / Ni / Au, Ti / Al / Pt / Au, Ti / Al / Ti / TiN, or a metal combination based on Ti / Al; and the second passivation layer is made of at least one of Al2O3, AlTiO, SiO2, Si3N4, and HfO2.

[0035] Specifically, the material of the second vertical channel layer 30 can be p-GaN, with a thickness ranging from 50 to 3000 nm and a p-type doping concentration ranging from [missing value]. The second heavily doped layer 31 can be made of n+GaN, with a thickness ranging from 10 to 1000 nm. The second lateral channel layer 32 can be made of GaN, with a thickness ranging from 10 to 3000 nm. The second barrier layer 33 can be made of AlGaN or InGaN, with a thickness less than 100 nm. The second cap layer 34 can be made of GaN doped with p-type impurities, including Mg, with a doping concentration ranging from [missing value]. The material of the second passivation layer may include at least one of Al2O3, AlTiO, SiO2, Si3N4 and HfO2, and the thickness of the first passivation layer ranges from 5 to 10000 nm.

[0036] In this embodiment of the invention, the materials of the second source 36 and the second drain 35 can be Ti / Al / Ni / Au, Ti / Al / Pt / Au, Ti / Al / Ti / TiN, or a Ti / Al-based metal combination. The material of the second gate 37 can be a Ni / Au-based metal, a TiN-based metal, or a Ti / Al-based metal combination.

[0037] In one implementation, the vertical trench MOSFET includes a substrate 10, a drift layer 11, a third vertical channel layer 40, a third heavily doped layer 41, a third gate 44, a third source 42, a third drain 43, and a third passivation layer covering the n-channel p-GaN gate GaN HEMT surface and avoiding the third source 42 and the third drain 43. The third vertical channel layer 40 and the third heavily doped layer 41 are epitaxial structures in the vertical trench MOSFET. The third vertical channel layer 40 and the third heavily doped layer 41 are stacked sequentially on the drift layer 11 from bottom to top. The third source electrode 42 is disposed on both sides of the upper surface of the third heavily doped layer 41; the third drain electrode 43 is superimposed on the lower surface of the substrate 10; the middle region of the upper surface of the third heavily doped layer 41 is provided with a second trench structure extending to the bottom of the drift layer 11; the third gate electrode 44 is located on the third passivation layer within the second trench structure.

[0038] In this embodiment of the invention, the third vertical channel layer 40 and the third heavily doped layer 41 are both GaN; the material of the third gate 44 is a metal combination based on Ni / Au, TiN, or Ti / Al; the materials of the third source 42 and the third drain 43 are both Ti / Al / Ni / Au, Ti / Al / Pt / Au, Ti / Al / Ti / TiN, or a metal combination based on Ti / Al; and the material of the third passivation layer is at least one of Al2O3, AlTiO, SiO2, Si3N4, and HfO2.

[0039] Specifically, the material of the third vertical channel layer 40 can be p-GaN, with a thickness ranging from 10 to 3000 nm and a p-type doping concentration ranging from [missing value]. The material of the third doped layer 41 can be n+GaN, and the thickness can range from 10 to 1000 nm. The material of the third passivation layer can include at least one of Al2O3, AlTiO, SiO2, Si3N4 and HfO2, and the thickness of the first passivation layer ranges from 5 to 10000 nm.

[0040] In this embodiment of the invention, the materials of the third source 42 and the third drain 43 can be Ti / Al / Ni / Au, Ti / Al / Pt / Au, Ti / Al / Ti / TiN, or a Ti / Al-based metal combination. The material of the third gate 44 can be a Ni / Au-based metal, a TiN-based metal, or a Ti / Al-based metal combination.

[0041] In one implementation, the components of the first barrier layer 23 and the second barrier layer 33 are both... ,exist The Al composition in the barrier layer is 0.1~0.7, and the deposition thickness is 5~100 nm. The formation of the two-dimensional electron gas (2DEG) in GaN HEMT mainly depends on the spontaneous polarization and piezoelectric polarization at the AlGaN / GaN interface. If the Al composition is too low, the polarization intensity is too weak to induce a sufficiently high concentration and high mobility of 2DEG. If the Al composition is too high, the lattice mismatch between the AlGaN layer and the underlying GaN layer becomes more severe, resulting in high-density dislocations and defects, reducing crystal quality, and increasing stress, which may cause cracks, especially during thick-layer growth. Based on this, in this embodiment of the invention, the Al composition is set to 0.1~0.7.

[0042] See Figure 2 , Figure 2 This is an equivalent circuit diagram of a monolithically integrated CMOS-driven GaN vertical device provided in an embodiment of the present invention, wherein M1 is nmos, i.e., n-channel p-GaN gate GaN HEMT, M2 is pmos, i.e., p-channel FET, and M3 is a vertical transistor, i.e., vertical trench MOSFET.

[0043] In this embodiment of the invention, a first isolation region is provided between the n-channel p-GaN gate GaN HEMT and the p-channel FET; a second isolation region is provided between the vertical trench MOSFET and the p-channel FET. The isolation regions can separate the various devices.

[0044] Specifically, the bottoms of both the first and second isolation regions extend into the drift layer 11. Both the first and second isolation regions are also covered with an isolation passivation layer. The implanted ions are nitrogen ions or fluoride ions.

[0045] In one implementation, mesa regions are etched on both sides of the epitaxial structure of the entire integrated structure to separate the active regions of each monolithic integrated device, wherein the etching depth of the mesa structure stops at the drift layer 11 or deeper.

[0046] In this embodiment of the invention, it can be clearly understood from the above content that the first vertical channel layer 20, the second vertical channel layer 30, and the third vertical channel layer 40 are integrally formed into a vertical channel layer structure through a simultaneous deposition process; the first heavily doped layer 21, the second heavily doped layer 31, and the third heavily doped layer 41 are integrally formed into a heavily doped layer structure through a simultaneous deposition process; the first lateral channel layer 22 and the second lateral channel layer 32 are integrally formed into a lateral channel layer structure through a simultaneous deposition process; the first barrier layer 23 and the second barrier layer 33 are integrally formed into a barrier layer structure through a simultaneous deposition process; and the first cap layer 24 and the second cap layer 34 are integrally formed into a cap layer structure through a simultaneous deposition process.

[0047] In this embodiment of the invention, the n-channel p-GaN gate GaN HEMT, p-channel FET, and vertical trench MOSFET are co-fabricated on the same substrate, solving the incompatibility problem of monolithic integration of GaN lateral and vertical devices. Furthermore, the epitaxial structures in the n-channel p-GaN gate GaN HEMT, p-channel FET, and vertical trench MOSFET are deposited simultaneously, eliminating the complexity of secondary epitaxy required in existing structure fabrication, resulting in higher efficiency and lower cost. Moreover, the zero-distance connection between the drive circuit and the power transistor achieves a leap in switching speed and energy efficiency. At the same time, thanks to the shared heat sink design, thermal management and reliability are ensured by allowing the heat source to share a single heat dissipation substrate.

[0048] In this embodiment of the invention, an all-GaN power system is constructed by integrating an n-channel p-GaN gate GaN HEMT, a p-channel FET, and a vertical trench MOSFET on a single substrate. This overcomes the problems of high system complexity, large parasitic parameters, and high cost associated with multi-chip solutions in existing technologies. It provides core support for the evolution of next-generation power electronic devices towards higher efficiency, higher power density, and higher reliability. Its innovative architecture is particularly suitable for applications with stringent requirements on system size and energy efficiency, including but not limited to high-end power conversion fields such as electric vehicle drive systems and on-board chargers, industrial servo drives and inverters, high-efficiency power supplies for data centers, renewable energy inverters, and fast charging equipment for consumer electronics.

[0049] Based on the same inventive concept, embodiments of the present invention also provide a method for fabricating a monolithically integrated CMOS-driven GaN vertical device, see [link to relevant documentation]. Figure 3 , Figure 3 This is a schematic flowchart of a method for fabricating a monolithically integrated CMOS-driven GaN vertical device according to an embodiment of the present invention, which specifically includes the following steps: Step S301: Select substrate 10 and deposit an epitaxial structure on substrate 10; the epitaxial structure includes, from bottom to top: drift layer 11, vertical channel layer, heavily doped layer, lateral channel layer, barrier layer, and cap layer.

[0050] The following is an example of a process for preparing an epitaxial structure: A substrate 10 made of GaN or Si is selected, and an n-GaN drift layer 11 of 500-100000 nm is deposited and grown on the substrate 10 using MOCVD (metal-organic chemical vapor deposition) process. On the drift layer 11, a vertical channel layer of p-GaN material with a thickness of 50-3000 nm is deposited and grown using MOCVD process; On the vertical channel layer, a heavily doped layer of n+GaN material is grown using MOCVD process, with a thickness of 10~1000nm. On the heavily doped layers, a lateral channel layer of GaN material is grown using MOCVD process, with a thickness of 10~3000 nm. On the lateral channel layer, a barrier layer made of AlGaN is grown using MOCVD process, wherein the composition of the barrier layer is [missing information]. ,exist The Al composition in the barrier layer is 0.1~0.7, and the deposition thickness is 5~100 nm; On the barrier layer, a p-GaN cap layer with a thickness of 30–500 nm is deposited and grown using MOCVD technology. (See [link to documentation]). Figure 4 , Figure 4 This is a schematic diagram of the device structure after the epitaxial structure is fabricated, as provided in an embodiment of the present invention.

[0051] In step S302, a portion of one side of the upper surface of the epitaxial structure is etched downwards to form a first region; wherein the etching depth extends to the upper part of the drift layer 11.

[0052] In one implementation, ICP etching is first used to etch the cap layer, barrier layer, and lateral trench layer on both sides of the entire epitaxial structure to facilitate subsequent mesa isolation and fabrication of vertical trench devices. (See [link to documentation]). Figure 5 , Figure 5 This is a schematic diagram of the device structure after etching the mesa, as provided in an embodiment of the present invention.

[0053] Then, ICP etching is used to etch the heavily doped layer, vertical channel layer, and drift layer 11 in the mesa isolation and vertical device trench gate regions to obtain the final mesa isolation region and the first region. See [link to relevant documentation]. Figure 6 , Figure 6 This is a schematic diagram of the device structure obtained by etching the first region according to an embodiment of the present invention.

[0054] Step S303: Etch downwards from a portion of the upper surface of the epitaxial structure on the other side to form a second region; wherein the etching depth extends to the upper surface of the barrier layer.

[0055] The cap layer is etched using an ICP etching process until it penetrates to the upper surface of the barrier layer, forming a second region. See [link to relevant documentation]. Figure 7 , Figure 7 This is a schematic diagram of the device structure obtained by etching the second region according to an embodiment of the present invention.

[0056] Step S304: Etch part of the cap layer in the unetched middle region on the upper surface of the epitaxial structure to form the third region.

[0057] The third region is obtained by etching a portion of the cap layer in the unetched middle region on the upper surface of the epitaxial structure using ICP etching. Figure 8 As shown, Figure 8 This is a schematic diagram of the device structure obtained by etching the third region according to an embodiment of the present invention.

[0058] Step S305: A first isolation region is formed between the second and third regions by ion implantation, and a second isolation region is formed between the first and third regions.

[0059] In this embodiment of the invention, ion implantation is performed on the device, implanting nitrogen ions or fluorine ions to isolate the device. Specifically, the implantation site extends from the barrier layer into the drift layer 11, such as... Figure 9 As shown, Figure 9 This is a schematic diagram of the device structure after the implantation of the isolation region provided in the embodiment of the present invention, which shows that a first isolation region is located between the second region and the third region, and a second isolation region is located between the first region and the third region.

[0060] In step S306, a vertical trench MOSFET is fabricated in the first region by sequentially depositing a passivation layer, a gate, a source, and a drain; an n-channel p-GaN gate GaN HEMT is fabricated in the second region; and a p-channel FET is fabricated in the third region.

[0061] In this embodiment of the invention, the sample after the above steps is placed in a plasma chemical vapor deposition (PECVD) reaction chamber. The PECVD process deposits a 1-500 nm thick Si3N4, Al2O3, or SiO2 passivation layer on the monolithic integrated device. Figure 10 As shown, Figure 10 This is a schematic diagram of the device structure after the passivation layer is deposited, as provided in an embodiment of the present invention.

[0062] The passivation layer of the gate region in the second region, i.e., the passivation layer above the cap layer in the second region, is etched. The material is then placed in an E-Beam electron beam evaporation apparatus, where an electron beam evaporation process is used to deposit gate metal simultaneously above the cap layer in the second region, above the passivation layer in the second trench in the first region, and above the passivation layer in the first trench in the third region. The gate metal is a Ni / Au-based or Ti / Al-based metal combination, such as... Figure 11As shown, Figure 11 This is a schematic diagram of the device structure after the gate metal is deposited, as provided in an embodiment of the present invention.

[0063] The passivation layers of the source and drain regions in the second and third regions, as well as the passivation layer of the source region in the first region, are etched. Source and drain metals are deposited in the source and drain regions of the second and third regions using electron beam evaporation. Source metal is deposited in the source region of the first region, and drain metal is deposited on the substrate 10. Ti / Al / Ni / Au, Ti / Al / Pt / Au, Ti / Al / Ti / TiN, or a Ti / Al-based metal combination are used as the source and drain electrodes. Annealing is performed at 850°C for 30 seconds to form high-temperature ohmic contacts. Finally, a vertical trench MOSFET is fabricated in the first region, an n-channel p-GaN gate GaN HEMT is fabricated in the second region, and a p-channel FET is fabricated in the third region. (See [link to documentation]). Figure 12 , Figure 12 This is a schematic diagram of the device structure after the deposition of source and drain metals provided in an embodiment of the present invention.

[0064] In this embodiment of the invention, electrodes are led out above the source, drain, and gate and interconnected accordingly, thus obtaining a monolithic integrated device, such as... Figure 1 As shown. In the n-channel p-GaN gate GaN HEMT, the vertical channel layer is called the first vertical channel layer 20, the heavily doped layer is called the first heavily doped layer 21, the lateral channel layer is called the first lateral channel layer 22, the barrier layer is called the first barrier layer 23, the cap layer is called the first cap layer 24, the source is called the first source 25, the drain is called the first drain 26, and the gate is called the first gate 27. In the p-channel FET, the vertical channel layer is called the second vertical channel layer 30, the heavily doped layer is called the second heavily doped layer 31, the lateral channel layer is called the second lateral channel layer 32, the barrier layer is called the second barrier layer 33, the cap layer is called the second cap layer 34, the drain is called the second drain 35, the source is called the second source 36, and the gate is called the second gate 37. The vertical channel layer in the vertical trench MOSFET is called the third vertical channel layer 40, the heavily doped layer is called the third heavily doped layer 41, the source is called the third source 42, the drain is called the third drain 43, and the gate is called the third gate 44.

[0065] In this embodiment of the invention, an all-GaN power system is constructed by integrating an n-channel p-GaN gate GaN HEMT, a p-channel FET, and a vertical trench MOSFET on a single substrate. This overcomes the problems of high system complexity, large parasitic parameters, and high cost associated with multi-chip solutions in existing technologies. It provides core support for the evolution of next-generation power electronic devices towards higher efficiency, higher power density, and higher reliability. Its innovative architecture is particularly suitable for applications with stringent requirements on system size and energy efficiency, including but not limited to high-end power conversion fields such as electric vehicle drive systems and on-board chargers, industrial servo drives and inverters, high-efficiency power supplies for data centers, renewable energy inverters, and fast charging equipment for consumer electronics.

[0066] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.

[0067] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0068] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.

[0069] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0070] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0071] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0072] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A monolithically integrated CMOS driving GaN vertical device, characterized in that, include: An n-channel p-GaN gate GaN HEMT, a p-channel FET, and a vertical trench MOSFET; the n-channel p-GaN gate GaN HEMT is located on one side of the p-channel FET, and the vertical trench MOSFET is located on the other side of the p-channel FET; The n-channel p-GaN gate GaN HEMT, the p-channel FET, and the vertical trench MOSFET share a drift layer; the drift layer is stacked on the substrate; The epitaxial structures in the n-channel p-GaN gate GaN HEMT, the p-channel FET, and the vertical trench MOSFET are deposited simultaneously. A first isolation region is provided between the n-channel p-GaN gate GaN HEMT and the p-channel FET; a second isolation region is provided between the vertical trench MOSFET and the p-channel FET.

2. The monolithically integrated CMOS driving GaN vertical device according to claim 1, characterized in that, The n-channel p-GaN gate GaN HEMT includes the substrate, the drift layer, the first vertical channel layer, the first heavily doped layer, the first lateral channel layer, the first barrier layer, the first cap layer, the first gate, the first source, the first drain, and a first passivation layer covering the surface of the n-channel p-GaN gate GaN HEMT and avoiding the first gate, the first source, and the first drain. The first vertical channel layer, the first heavily doped layer, the first lateral channel layer, and the first barrier layer are stacked sequentially on the drift layer from bottom to top. The first cap layer is superimposed on the upper surface of the first barrier layer; The first source and the first drain are both superimposed on the upper surface of the first barrier layer and are located on both sides of the first cap layer, respectively. The first gate is superimposed on the first cap layer.

3. The monolithically integrated CMOS driving GaN vertical device according to claim 2, characterized in that, The materials of the first vertical channel layer, the first heavily doped layer, the first lateral channel layer, and the first cap layer are all GaN; the material of the first barrier layer is AlGaN or InGaN; the material of the first gate is a metal combination based on Ni / Au, TiN, or Ti / Al; the materials of the first source and the first drain are Ti / Al / Ni / Au, Ti / Al / Pt / Au, Ti / Al / Ti / TiN, or a metal combination based on Ti / Al; the material of the first passivation layer is at least one of Al2O3, AlTiO, SiO2, Si3N4, and HfO2.

4. The monolithically integrated CMOS driving GaN vertical device according to claim 1, characterized in that, The p-channel FET includes the substrate, the drift layer, the second vertical channel layer, the second heavily doped layer, the second lateral channel layer, the second barrier layer, the second cap layer, the second gate, the second source, the second drain, and a second passivation layer covering the surface of the p-channel FET and avoiding the second source and the second drain; The second vertical channel layer, the second heavily doped layer, the second lateral channel layer, the second barrier layer, and the second cap layer are stacked sequentially on the drift layer from bottom to top. The second drain and the second source are respectively disposed on both sides of the upper surface of the second cap layer; the upper surface region of the second cap layer is provided with a first trench structure; the second gate is located on the second passivation layer within the trench structure.

5. The monolithically integrated CMOS driving GaN vertical device according to claim 4, characterized in that, The second vertical channel layer, the second heavily doped layer, the second lateral channel layer, and the second cap layer are all made of GaN; the second barrier layer is made of AlGaN or InGaN; the second gate is made of a metal combination based on Ni / Au, TiN, or Ti / Al; the second source and the second drain are made of Ti / Al / Ni / Au, Ti / Al / Pt / Au, Ti / Al / Ti / TiN, or a metal combination based on Ti / Al; and the second passivation layer is made of at least one of Al2O3, AlTiO, SiO2, Si3N4, and HfO2.

6. The monolithically integrated CMOS driving GaN vertical device according to claim 1, characterized in that, The vertical trench MOSFET includes the substrate, the drift layer, the third vertical channel layer, the third heavily doped layer, the third gate, the third source, the third drain, and a third passivation layer covering the surface of the vertical trench MOSFET and avoiding the third source and the third drain. The third vertical channel layer and the third heavily doped layer are stacked on the drift layer from bottom to top. The third source electrode is disposed on both sides of the upper surface of the third heavily doped layer; the third drain electrode is superimposed on the lower surface of the substrate; the middle region of the upper surface of the third heavily doped layer is provided with a second trench structure extending to the drift layer; the third gate electrode is located on the third passivation layer within the second trench structure.

7. The monolithically integrated CMOS driving GaN vertical device according to claim 6, characterized in that, The third vertical channel layer and the third heavily doped layer are both GaN; the material of the third gate is a metal combination based on Ni / Au, TiN, or Ti / Al; the materials of the third source and the third drain are both Ti / Al / Ni / Au, Ti / Al / Pt / Au, Ti / Al / Ti / TiN, or a metal combination based on Ti / Al; the material of the third passivation layer is at least one of Al2O3, AlTiO, SiO2, Si3N4, and HfO2.

8. The monolithically integrated CMOS driving GaN vertical device according to claim 1, characterized in that, The first isolation region and the second isolation region are formed by nitrogen ion or fluorine ion implantation.

9. The monolithically integrated CMOS driving GaN vertical device according to claim 1, characterized in that, The substrate is made of GaN, Si, sapphire, AlN, SOI, or a composite material; the drift layer is made of GaN.

10. A method for fabricating a monolithically integrated CMOS-driven GaN vertical device, characterized in that, include: Select a substrate and deposit an epitaxial structure on the substrate; The epitaxial structure, from bottom to top, includes: a drift layer, a vertical channel layer, a heavily doped layer, a lateral channel layer, a barrier layer, and a cap layer; A first region is formed by etching downwards from a portion of one side of the upper surface of the epitaxial structure; wherein the etching depth extends to the upper part of the drift layer; A second region is formed by etching downwards from a portion of the upper surface of the epitaxial structure; wherein the etching depth extends to the upper surface of the barrier layer; A portion of the cap layer in the unetched middle region on the upper surface of the epitaxial structure is etched to form a third region; A first isolation region is formed between the second region and the third region by ion implantation, and a second isolation region is formed between the first region and the third region; A vertical trench MOSFET is fabricated in the first region by sequentially depositing a passivation layer, a gate, a source, and a drain; an n-channel p-GaN gate GaN HEMT is fabricated in the second region; and a p-channel FET is fabricated in the third region.

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