Semiconductor structure and forming method thereof

Abstract

One aspect of the present disclosure relates to a structure. The structure includes: a first interlayer dielectric (ILD) layer; a conductive feature disposed in the first ILD layer; an etch stop layer (ESL) disposed on the first ILD layer; a second ILD layer disposed on the ESL; and a metal feature disposed in the second ILD layer and in contact with the conductive feature, where the metal feature is laterally separated from the ESL by an air gap. The embodiment of the invention also relates to a semiconductor structure and a forming method thereof.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods of forming the same. Background Technology

[0002] The electronics industry has a growing demand for smaller and faster electronic devices capable of supporting increasingly complex and sophisticated functions. To meet these demands, the integrated circuit (IC) industry has a sustained trend towards manufacturing low-cost, high-performance, and low-power ICs. To date, these goals have been largely achieved by reducing IC size (e.g., the smallest possible IC component size), thereby increasing production efficiency and reducing associated costs. However, this scaling also increases the complexity of IC manufacturing processes. Therefore, continued advancements in IC devices and their performance require similar progress in IC manufacturing processes and technologies.

[0003] As component sizes continue to shrink, metal vias and contacts need to fit into smaller spaces while minimizing contact resistance. Fitting metal material into smaller spaces often creates gaps or voids, reducing electrical connectivity. One way to address this is bottom-up metal growth. However, during bottom-up metal growth, impurities in the etch stop layer (ESL) that the etcher passes through can come into contact with the deposited metal, causing a loss of selectivity during the growth process. Additionally, the portion of the ESL sandwiched between metal contacts / vias can also lead to unwanted parasitic capacitance.

[0004] Therefore, while existing methods for forming semiconductor metal vias / contacts are generally sufficient for their intended purpose, they are not entirely satisfactory in every respect. Summary of the Invention

[0005] One embodiment of this application provides a semiconductor structure, including: a first interlayer dielectric (ILD) layer; a conductive component disposed in the first interlayer dielectric layer; an etch stop layer (ESL) disposed on the first interlayer dielectric layer; a second interlayer dielectric layer disposed on the etch stop layer; and a metal component disposed in the second interlayer dielectric layer and in contact with the conductive component, wherein the metal component is laterally separated from the etch stop layer by an air gap.

[0006] Another embodiment of this application provides a semiconductor structure, including: a source / drain (S / D) contact located above a source / drain component; a gate structure located above a channel region, wherein the channel region is adjacent to the source / drain component; a first interlayer dielectric (ILD) layer located above the gate structure and surrounding the source / drain contact; an etch stop layer located above the first interlayer dielectric layer and the source / drain contact; a second interlayer dielectric layer located above the etch stop layer; and a source / drain via resting on the source / drain contact, wherein the source / drain via is embedded in the second interlayer dielectric layer and separated from the etch stop layer.

[0007] In another aspect, this application provides a method for forming a semiconductor structure, comprising: forming a metal contact in a first dielectric layer; depositing an etch stop layer (ESL) over the metal contact and the first dielectric layer; depositing a second dielectric layer over the etch stop layer; forming a trench through the second dielectric layer and the etch stop layer to expose the metal contact; forming a sacrificial liner along the sidewalls of the trench; forming a protective liner along the sidewalls of the sacrificial liner; depositing metal in the trench and between the protective liners; selectively removing the sacrificial liner to form an air gap; and sealing the air gap by performing ion implantation on the second dielectric layer.

[0008] Embodiments of this application provide an etch stop layer that isolates the metal vias and contacts. Attached Figure Description

[0009] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion. It should also be emphasized that the drawings illustrate only typical embodiments of this disclosure and should therefore not be considered limiting, as this disclosure is equally well applicable to other embodiments. Furthermore, the drawings may implicitly describe components not explicitly described in the detailed description.

[0010] Figure 1 A flowchart illustrating a method for forming part or all of a semiconductor device having gate contacts and source / drain vias according to embodiments of the present disclosure is shown.

[0011] Figure 2 A three-dimensional view of a semiconductor IC structure according to an embodiment of the present disclosure is shown, wherein line A-A' cross-cuts the IC structure.

[0012] Figures 3 to 8 The illustration shows an intermediate stage of manufacturing according to an embodiment of the present disclosure and according to... Figure 1The method processes along Figure 2 A cross-sectional view of a semiconductor device cut by line A-A'.

[0013] Figure 9 A flowchart illustrating part or all of a method for forming a metal via or contact isolated from an etch stop layer according to an embodiment of the present disclosure is shown.

[0014] Figures 10A to 10B It was shown as Figure 9 The methods of forming sacrificial linings and protective linings are different.

[0015] Figures 11 to 19 The illustration shows an intermediate stage of manufacturing according to an embodiment of the present disclosure and according to... Figure 9 and Figure 10A A cross-sectional view of the membrane stack processed by the method.

[0016] Figures 20A to 20B A metal via or contact isolated from an etch stop layer is shown according to a further embodiment of this disclosure.

[0017] Figures 21 to 28 The illustration shows an intermediate stage of manufacturing according to an embodiment of the present disclosure and according to... Figure 9 and Figure 10B A cross-sectional view of the membrane stack processed by the method.

[0018] Figures 29A to 29B A metal via or contact isolated from an etch stop layer is shown according to a further embodiment of this disclosure. Detailed Implementation

[0019] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0020] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “below,” “lower,” “above,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Besides the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0021] Furthermore, when terms such as "about," "approximately," or "substantially" are used to describe numerical values ​​or ranges, the term is intended to cover values ​​within a reasonable range that includes the described value, such as within + / - 10% of the described value, or other values ​​understood by those skilled in the art. For example, the term "about 5 nm" could cover a size range from 4.5 nm to 5.5 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / - 10%. And when comparing the size or dimensions of a component with another component, phrases such as "substantially the same," "essentially the same," or "similar in size" can be understood as within + / - 10% of the compared components. Additionally, the disclosed dimensions of different components may implicitly disclose the size ratios between the different components.

[0022] In semiconductor manufacturing, metal vias (or contacts) are formed to penetrate various interlayer dielectrics (ILDs) and etch stop layers (ESLs). However, direct contact between the metal via and the ESL can impair device performance. Direct contact can introduce greater parasitic coupling (especially if the ESL is a high-k dielectric, such as silicon nitride (SiN)). Specifically, sandwiching a portion of the ESL between the metal via can lead to unwanted capacitive coupling, which degrades overall device performance. Furthermore, direct contact with the ESL can cause selective metal loss due to impurities in the ESL reacting with the deposited metal (e.g., during bottom-up metal growth). For example, the ESL can include low-k dielectrics such as silicon carbonitride (SiCN), and carbon impurities react with the deposited bottom-up metal, resulting in a tapered landing on the underlying components, reducing surface contact and electrical connectivity. Therefore, there is a need to improve effective capacitance when using high-k ESLs while preventing selective metal loss when using low-k ESLs.

[0023] For this and other reasons, this disclosure provides a method for forming metal vias (or contacts) isolated from an etch stop layer (ESL). A pseudo-sacrificial liner (e.g., a silicon liner) and a protective liner (e.g., a SiOx liner) are used to form a separation between the ESL and the metal via. The sacrificial liner is selectively removed to form an air wall, and the air wall is sealed by ion implantation to form an air spacer (or air gap). Simultaneously, the protective liner layer remains on the sidewalls of the metal via and can be considered part of the interlayer dielectric after sealing the air wall. In this embodiment, the metal via (or contact) is laterally spaced from the ESL by the protective liner portion of the interlayer dielectric and the air spacer. The air spacer reduces the capacitance of the ESL (e.g., the capacitance decreases from 3.8 to 1 when the ESL includes SiCN), and the protective liner enables bottom-up growth without impurities. In this embodiment, the metal via (or contact) is formed by bottom-up deposition to form a via (or contact) without voids and with reduced resistance.

[0024] To illustrate various aspects of this disclosure, methods for forming semiconductor devices (or structures) are discussed below. The embodiments shown in this disclosure are implemented using gate-all-around (GAA) field-effect transistors (FETs), but this disclosure is not limited thereto. A GAA-FET refers to a transistor having a gate stack (gate electrode and gate dielectric layer) surrounding a transistor channel, such as a vertically stacked gate-all-around horizontal nanowire or nanosheet MOSFET device. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other structures to achieve the same purposes and / or advantages as the embodiments described herein. For example, the embodiments herein can also be implemented using planar MOSFETs, FinFETs, forked-plate FETs, complementary FETs (CFETs), vertically stacked FETs, and / or combinations thereof.

[0025] Figure 1 A flowchart illustrating part or all of a method 1000 for forming a semiconductor device 100 having a gate contact and a source / drain via according to an embodiment of the present disclosure is shown. Reference is made below. Figures 2 to 8 Method 1000 is described. For clarity, these figures are simplified to better understand the inventive concept of this disclosure. Additional components may be added to the semiconductor device 100, and some of the components described below may be replaced, modified, or eliminated in other embodiments of the semiconductor device 100.

[0026] refer to Figures 2 to 3In method 1000, a semiconductor IC structure 150 is received at operation 1002. As described below, the semiconductor IC structure 150 includes a gate structure 108 located above a channel region CR, a source / drain (S / D) component 106b adjacent to the channel region CR (e.g., located in the S / D region SDR), and a first interlayer dielectric (ILD) layer 110 adjacent to the gate structure 108 and located above the S / D component 106b.

[0027] Figure 2 A three-dimensional view of a semiconductor IC structure 150 is shown. The semiconductor IC structure 150 corresponds to a semiconductor device 100 in the initial or intermediate stages of manufacturing. The semiconductor device 100 may be part of an integrated circuit (IC) chip, a system-on-a-chip (SoC), or a portion thereof, and includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), FinFETs, nanosheet FETs, nanowire FETs, other types of multi-gate FETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof. In some embodiments, the device includes non-volatile memory, such as non-volatile random access memory (NVRAM), flash memory, electrically erasable programmable read-only memory (EEPROM), electrically programmable read-only memory (EPROM), other suitable memory types, or combinations thereof.

[0028] Semiconductor device 100 includes a substrate 101 and one or more semiconductor stacks 106 protruding from the substrate 101 over an isolation structure 103. The isolation structure 103 is disposed over the substrate 101 and provides isolation between adjacent semiconductor stacks 106, and may be a shallow trench isolation (STI) layer. In an example process, a dielectric material for the isolation structure 103 is deposited over an IC structure 150 using CVD, subatmospheric pressure CVD (SACVD), flowable CVD, physical vapor deposition (PVD), spin coating, and / or other suitable processes. The deposited dielectric material is then planarized and recessed until the semiconductor stacks 106 rise over the isolation structure 103. The dielectric material for the isolation structure 103 may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials.

[0029] The semiconductor device 100 also includes one or more gate structures 108 (or gate stacks) disposed above the channel region CR of the semiconductor stack 106. The semiconductor stack 106 may also be referred to as a semiconductor fin 106 or a fin active region 106. The semiconductor stack 106 extends longitudinally along the X direction, and the gate structures 108 extend longitudinally along the Y direction. As shown, the semiconductor stack 106 includes a channel region CR located between the source / drain regions SDR. The channel region CR refers to the region of the semiconductor stack 106 directly below and enclosed by the gate structures 108.

[0030] Figure 2 A line A-A' is shown, cut along the semiconductor stack 106 in the X direction (the longitudinal direction of the semiconductor stack 106). The line A-A' passes through the two source / drain regions SDR and the channel region CR between the two source / drain regions SDR. Figures 3 to 8 It shows cutting along line A-A' and according to Figure 1 A cross-sectional view of a semiconductor IC structure 150 processed by method 1000.

[0031] Figure 3 Additional details of the initial IC structure 150 are shown. As illustrated, the channel region CR may include vertically stacked channels 106a, the S / D region SDR may include S / D epitaxial components 106b, and the channel 106a extends laterally between the S / D epitaxial components 106b along the X direction. The S / D epitaxial components 106b may include n-type S / D components corresponding to n-type GAA transistor regions or p-type source / drain components corresponding to p-type GAA transistor regions. The S / D epitaxial components 106b may be formed by epitaxial processes using CVD deposition techniques (e.g., VPE and / or UHV-CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The S / D epitaxial components 106b are doped with n-type dopants and / or p-type dopants. In some embodiments, for an n-type GAA transistor, the S / D epitaxial component 106b comprises silicon and may be doped with carbon, phosphorus, arsenic, other n-type dopants, or combinations thereof (e.g., forming a Si:C epitaxial source / drain component, a Si:P epitaxial source / drain component, or a Si:C:P epitaxial source / drain component). In some embodiments, for a p-type GAA transistor, the S / D epitaxial component 106b comprises silicon-germanium or germanium and may be doped with boron, other p-type dopants, or combinations thereof (e.g., forming a Si:Ge:B epitaxial source / drain component).

[0032] Still referencing Figure 3Gate structure 108 is bonded to and encloses each channel 106a. Gate structure 108 includes a gate dielectric layer (not explicitly shown) and a gate electrode (not explicitly shown) disposed on the gate dielectric layer. In some embodiments, the gate dielectric layer includes an interface layer and a high-k dielectric layer disposed on the interface layer. The gate electrode may include one or more conductive materials, such as a capping layer, a work function metal layer, a barrier layer, a metal fill layer, and / or other suitable conductive material layers. The work function layers (if present) may be the same or different and may be n-type or p-type work function layers, depending on the type of the corresponding GAA transistor. The gate dielectric layer includes a high-k dielectric material, such as a material with a dielectric constant greater than silicon oxide (k≈3.9). The metal fill layer includes a suitable conductive material, such as Al, W, and / or Cu. The metal fill layer may additionally or collectively include other metals, metal oxides, metal nitrides, other suitable materials, or combinations thereof.

[0033] Still referencing Figure 3 The gate structure 108 includes a bottom portion 108a disposed below the topmost channel 106a and a top portion 108b disposed above the topmost channel 106a. An inner spacer 105 is disposed along the sidewall of the bottom portion 108a of the gate structure 108, and a gate spacer 109 is disposed along the sidewall of the top portion 108b of the gate structure 108. The inner spacer 105 is vertically disposed between the channels 106a and laterally disposed between the S / D epitaxial member 106b and the gate structure 108. The gate spacer 109 rests on the topmost channel 106a and can be directly disposed above the inner spacer 105. In some embodiments, the internal spacer 105 includes a dielectric material comprising silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (e.g., silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), or silicon carbonitride (SiOCN). In some embodiments, the internal spacer 105 includes a low-k dielectric material. In some embodiments, the gate spacer 109 may be made of silicon oxide (SiO2), silicon nitride (SiN), silicon carbonitride (SiOC), silicon carbonitride (SiOCN), silicon carbonitride (SiCN), metal nitride, or a suitable dielectric material. In some embodiments, the internal spacer 105 may include a material different from that of the gate spacer 109 to achieve desired etch selectivity or different isolation effects.

[0034] Still referencing Figure 3The semiconductor device 100 includes a first interlayer dielectric (ILD) layer 110 adjacent to a gate structure 108 and located above an S / D epitaxial member 106b. The first ILD layer 110 laterally surrounds the top portion 108b of the gate structure 108. As shown, a gate spacer 109 is laterally disposed between the first ILD layer 110 and the top portion 108b of the gate structure 108. In this embodiment, the first ILD layer 110 comprises an oxide-based dielectric material, such as silicon oxide (SiO2). However, the first ILD layer 110 may comprise a multilayer structure having multiple dielectric layers. In some embodiments, an etch stop layer (ESL) 111 is vertically disposed between the S / D epitaxial member 106b and the first ILD layer 110, and laterally disposed between the gate spacer 109 and the first ILD layer 110. The ESL 111 comprises a material different from that of the first ILD layer 110, such as a dielectric material different from the dielectric material of the first ILD layer 110. For example, in the case where the first ILD layer 110 comprises an oxide-based dielectric material, the ESL 111 comprises silicon and nitrogen, such as silicon nitride (SiN), silicon carbonitride (SiCN), or silicon oxynitride (SiON).

[0035] Now for reference Figure 4 In method 1000, at operation 1004, a second ILD layer 120 is formed over the first ILD layer 110 and the gate structure 108. In this embodiment, operation 1004 includes depositing an etch stop layer (ESL) 115 over the first ILD layer 110, and then depositing the second ILD layer 120 over the ESL 115. Although described separately, the ESL 115 may also be referred to as a portion of the second ILD layer 120 (i.e., the second ILD layer 120 is a multilayer structure having multiple dielectric layers including the ESL 115).

[0036] ESL 115 can be formed by any suitable deposition process, such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or combinations thereof. In this embodiment, ESL 115 is a nitride-based dielectric layer, such as a silicon nitride (SiN) layer or a silicon carbonitride (SiCN) layer. ESL 115 is deposited directly on the top surface of the first ILD layer 110, the gate spacer 109, and the top portion 108b of the gate structure 108.

[0037] The second ILD layer 120 can be formed by any suitable deposition process (such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or combinations thereof). The second ILD layer 120 comprises a material similar to that of the first ILD layer 110 (e.g., both ILD layers comprise silicon oxide).

[0038] Now for reference Figure 5 In method 1000, at operation 1006, an S / D contact 116 is formed through the first ILD layer 110 and the second ILD layer 120 to land on the S / D component 106b. As shown, the S / D contact 116 also penetrates the ESL 115. Operation 1006 may include first forming an S / D contact trench (not shown) by a patterning process to expose one or more S / D epitaxial components 106b. The patterning process may include photolithography and etching, wherein a patterned mask layer is formed over the IC structure 150, and the S / D contact trench is formed by etching through an opening defined by the patterned mask layer. The etching may be a multi-etching process that individually and sequentially etches the material through the second ILD layer 120, the ESL 115, the first ILD layer 110, and the ESL 111. For example, each of the first ILD layer and the second ILD layer 120 may be etched by dry etching, and the ESL 115 and 111 may be etched by wet etching. The etchant applied to the first ILD layer and the second ILD layer 120 can be selective in etching the oxide dielectric, and the etchant applied to ESL 115 and 111 can be selective in etching the nitride dielectric. After forming the S / D contact trench, operation 1006 can deposit one or more conductive materials into the S / D contact trench. Thereafter, chemical mechanical planarization (CMP) can be performed to form the S / D contact 116. The deposited conductive material can include silicide components and a metal filler layer above the silicide components. The silicide components can include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel platinum silicide (NiPtSi), nickel platinum germanium silicide (NiPtGeSi), nickel germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds. The metal filler layer above the silicide component may include titanium (Ti), titanium nitride (TiN), ruthenium (Ru), copper (Cu), nickel (Ni), cobalt (Co), tungsten (W), tantalum (Ta), or molybdenum (Mo).

[0039] Optionally, method 1000 at operation 1006 may further include forming a barrier layer 113 in the S / D trench prior to forming the S / D contact 116. For example, a barrier liner may be conformally deposited into the S / D trench, followed by a dry etching process (e.g., anisotropic plasma etching) to etch away the horizontal portion of the barrier liner, thereby forming the barrier layer 113. The barrier layer 113 linings the sidewalls of the S / D contact 116 to prevent metal diffusion into the surrounding environment. The barrier layer 113 may comprise Ti / TiN, SiN, or W. In this embodiment, the barrier layer 113 comprises SiN.

[0040] Now for reference Figure 6 In method 1000, at operation 1008, a third ILD layer 130 is formed over the second ILD layer 120 and the S / D contact 116. In this embodiment, operation 1008 includes depositing an etch stop layer (ESL) 125 over the second ILD layer 120, and then depositing the third ILD layer 130 over the ESL 125. Although described separately, the ESL 125 may also be referred to as a portion of the third ILD layer 130 (i.e., the third ILD layer 130 is a multilayer structure having multiple dielectric layers including the ESL 125).

[0041] ESL 125 can be formed by any suitable deposition process, such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or combinations thereof. In this embodiment, ESL 125 is a nitride-based dielectric layer, such as a silicon nitride (SiN) layer or a silicon carbonitride (SiCN) layer. ESL 125 is deposited directly on the top surface of the second ILD layer 120, the barrier layer 113 (if present), and the S / D contact 116.

[0042] The third ILD layer 130 can be formed by any suitable deposition process (such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or combinations thereof). The third ILD layer 130 comprises a material similar to that of the first ILD layer 110 (e.g., both ILD layers comprise silicon oxide).

[0043] Now for reference Figure 7In method 1000, at operation 1010, a gate contact 118 is formed through a second ILD layer 120 and a third ILD layer 130 to rest on a gate structure 108. The gate contact 118 is isolated from one or more etch stop layers (ESLs) (e.g., ESLs 115 and / or 125) by one or more air gaps 141. As shown, the gate contact 118 also penetrates ESLs 115 and 125. Operation 1010 may include first forming a gate contact trench (not shown) by a patterning process to expose one or more gate structures 108. The patterning process may include photolithography and etching, wherein a patterned mask layer is formed over an IC structure 150, and the gate contact trench is formed by etching through an opening defined by the patterned mask layer. After forming the gate contact trench, operation 1010 may deposit one or more conductive materials into the gate contact trench. The deposition may be a bottom-up metal growth process with excellent gap-filling capabilities to avoid forming voids in the gate contact 118. Figure 9 Method 1100 further describes a bottom-up metal growth process. After depositing one or more conductive materials, chemical mechanical planarization (CMP) can be performed to form gate contact 118. The deposited conductive material may include W, Ti / TiN, Ru, Mo, or combinations thereof. In one embodiment, gate contact 118 comprises a polycrystalline metal with impurities. In another embodiment, gate contact 118 is made of a single-grain pure metal such as pure Mo.

[0044] Operation 1010 forms gate contacts 118 that are isolated from and separated from ESLs (e.g., ESL 115 and / or 125). This relates to Figure 9 Method 1100 is further described in the figure. As shown, the gate contact 118 can be laterally separated from the ESL (e.g., ESL 115 and / or 125) by portions of the respective ILD layers 120 and 130 and by air gap 141. The portions of the respective ILD layers 120 and 130 are protective liner portions that are directly in contact with the sidewalls of the gate contact 118.

[0045] Now for reference Figure 8In method 1000, at operation 1012, an S / D via 126 is formed through a third ILD layer 130 to fall on an S / D contact 116. The S / D via 126 is isolated from one or more etch stop layers (ESLs) (e.g., ESL 125) by one or more air gaps 141. As shown, the S / D via 126 also penetrates the ESL 125. Operation 1012 may include first forming an S / D via trench (not shown) by a patterning process to expose one or more S / D contacts 116. The patterning process may include photolithography and etching, wherein a patterned mask layer is formed over an IC structure 150, and the S / D via trench is formed by etching through an opening defined by the patterned mask layer. After forming the S / D via trench, operation 1012 may deposit one or more conductive materials into the S / D via trench. Deposition can be a bottom-up metal growth process with excellent gap-filling capabilities to avoid voids in the S / D vias 126. About Figure 9 Method 1100 further describes a bottom-up metal growth process. After depositing one or more conductive materials, chemical mechanical planarization (CMP) can be performed to form an S / D via 126. The deposited conductive material may include W, Ti / TiN, Ru, Mo, or combinations thereof. In one embodiment, the S / D via 126 comprises a polycrystalline metal with impurities. In another embodiment, the S / D via 126 is made of a single-grain pure metal (such as pure Mo).

[0046] Operation 1012 forms an S / D via 126 that is isolated and separated from the ESL (e.g., ESL 125). This is about Figure 9 Method 1100 is further described in the figure. As shown, the S / D via 126 can be laterally separated from the ESL 125 by a portion of the corresponding ILD layer 130 and by an air gap 141. The portion of the corresponding ILD layer 130 is a protective liner portion that is directly in contact with the sidewall of the S / D via 126.

[0047] In this embodiment, ILD layers 110, 120, and 130 comprise dielectric materials different from ESL layers 111, 115, and 125. For example, ILD layers 110, 120, and 130 are made of oxide-based dielectrics such as silicon oxide, and ESL layers 115 and 125 are made of nitride-based dielectrics such as silicon nitride or silicon carbonitride. This allows for etchant selectivity when forming various conductive plugs (i.e., vias and contacts) through the different ILD and ESL layers. Additionally, ESL layers 111, 115, and 125 are thinner along the z-direction than the corresponding ILD layers 110, 120, and 130. In this embodiment, ILD layer 110 is thicker along the z-direction than ILD layer 120.

[0048] Additional operations may be provided before, during, and after method 1000, and some of the described operations may be moved, replaced, or eliminated for additional embodiments of method 1000. For example, method 1000 may also include forming an interconnect structure over the third ILD layer 130. The interconnect structure may include components electrically coupled to various devices (e.g., p-type GAA transistors and / or n-type GAA transistors of device 100, resistors, capacitors, and / or inductors) and / or components (e.g., gate structures 108 of p-type GAA transistors and / or n-type GAA transistors and / or epitaxial source / drain components 106b) such that the various devices and / or components can operate according to the design requirements of device 100.

[0049] The interconnect structure includes a combination of dielectric layers (i.e., inter-metal dielectric layers and ESLs) and conductive layers (e.g., metal layers) configured to form various interconnect layers. The conductive layers are configured to form vertical interconnect components (such as vias) and / or horizontal interconnect components (such as wires). Vertical interconnect components typically connect horizontal interconnect components in different layers (or different planes) of the interconnect structure. Various horizontal and vertical interconnect components may be electrically connected to device-level contacts (e.g., S / D vias 126 and gate contacts 118) formed in a third ILD layer 130. Note that, according to the methods described herein, the interconnect structure may include inter-metal vias that are also laterally separated from the ESL. During operation, the interconnect structure is configured to route signals between devices and / or components of device 100, and / or distribute signals (e.g., clock signals, voltage signals, and / or ground signals) to devices and / or components of device 100.

[0050] Figure 9 A flowchart of part or all of a method 1100 for forming metal vias or contacts (e.g., S / D via 126 and gate contact 118) isolated from etch stop layers (e.g., ESL 115 and 125) according to embodiments of the present disclosure is shown. Figures 10A to 10B It was shown as Figure 9 Method 1100 partially forms sacrificial and protective liners in different method embodiments 1200a and 1200b. See below for reference. Figures 11 to 19 , Figures 20A to 20B , Figures 21 to 28 and Figures 29A to 29B Method 1100 is described. These figures illustrate a film stack of device 100, the film stack including an ILD and an ESL located above conductive components. In this embodiment, these figures correspond to... Figure 8 The area shown is 500 (i.e., around the S / D via 126). However, note that these diagrams can also correspond to... Figure 8 Other areas shown (e.g., around gate contact 118) or Figure 8Other areas not shown (e.g., inter-metal vias surrounding the front interconnect structure).

[0051] Figures 11 to 19 The embodiments according to this disclosure are shown. Figure 9 and Figure 10A A cross-sectional view of the film stack of the semiconductor device 100 processed by the method.

[0052] Now for reference Figure 11 In method 1100, at operation 1102, a metal contact (e.g., S / D contact 116) is formed in a first dielectric layer (e.g., ILD layer 120). The metal contact may be lined with a barrier layer (e.g., barrier layer 113) along its sidewalls. Operation 1102 may correspond to operation 1006 previously described.

[0053] Still referencing Figure 11 In method 1100, at operation 1104, an etch stop layer (ESL) (e.g., ESL 125) is deposited over a metal contact (e.g., S / D contact 116) and a first dielectric layer (e.g., ILD layer 120). In an embodiment, the ESL is a nitride-based dielectric, such as silicon nitride (SiN). In an embodiment, the ESL is a low-k ESL (e.g., SiCN) to minimize stray capacitive coupling. Operation 1104 may correspond to operation 1008 previously described.

[0054] Still referencing Figure 11 In method 1100, at operation 1106, a second dielectric layer (e.g., ILD layer 130) is deposited over an ESL (e.g., ESL 125). As a result, a film stack is formed, wherein the ESL is vertically disposed between the first and second dielectric layers (e.g., ILD layers 120 and 130). In embodiments, the first and second dielectric layers comprise oxide-based dielectrics, such as silicon oxide (SiOx). Operation 1106 may correspond to the previously described operation 1008.

[0055] Now for reference Figure 12In method 1100, at operation 1108, a trench 210 is formed through a second dielectric layer (e.g., ILD layer 130) and an ESL (e.g., ESL 125) to expose a metal contact (e.g., an S / D contact 116). The trench 210 can be formed by photolithography and etching processes. For example, a photolithography process can form a masking element that covers an unetched area of ​​device 100 and exposes the area to be etched. An etching process is then performed to etch through the exposed area. In this embodiment, the trench 210 is formed wider in the x-direction than the metal contact (e.g., S / D contact 116). This creates the necessary spacing to form air spacers and a protective liner that isolates the metal vias (or contacts) subsequently formed in the trench 210 from the adjacent ESL (e.g., ESL 125).

[0056] Now for reference Figures 13 to 16 In method 1100, a sacrificial liner 213 is formed along the sidewall of the groove 210 at operations 1110 and 1112, and a protective liner 230 is formed along the sidewall of the sacrificial liner 213. Operations 1110 and 1112 are collectively referred to as method 1200, according to the first embodiment 1200a. Figure 10A Further description is provided below. Figures 13 to 16 The first embodiment 1200a is described.

[0057] refer to Figure 13 In method 1200, at operation 1202, a sacrificial liner 213 is conformally deposited in trench 210 (e.g., by CVD). The sacrificial liner 213 rests on the top and sides of a second dielectric layer (e.g., ILD layer 130), the sides of an ESL (e.g., ESL 125), the top surface of a metal contact (e.g., S / D contact 116), and a barrier layer 113 (if present). The sacrificial liner 213 has a different material from its surrounding components (e.g., ILD layer 130 and ESL 125). This is so that it can be selectively etched away later without damaging the surrounding components. In this embodiment, the sacrificial liner 213 is a pseudo-silicon liner. The silicon liner may comprise amorphous silicon or polycrystalline silicon.

[0058] refer to Figure 14Method 1200 removes the horizontal portion of the sacrificial liner 213 at operation 1204, thereby forming the sacrificial liner 213 along the sidewalls of the trench 210. Operation 1204 includes anisotropic etching (e.g., plasma etching) that selectively etches portions of the sacrificial liner 213 that fall on the top surface of the second dielectric layer (e.g., ILD layer 130) and the top surface of the metal contacts (e.g., S / D contacts 116). In embodiments, the thickness of the sacrificial liner 213 along the x-direction is in the range of about 2 nm to about 4 nm. If the thickness is too thin, the air gap formed later will be too small to achieve a significant effective capacitance improvement. If the thickness is too thick, the ILD sealing performed later may fail.

[0059] refer to Figure 15 In method 1200, at operation 1206, a protective liner 230 is conformally deposited (e.g., by CVD) in trench 210 and along the sidewalls of sacrificial liner 213. The protective liner 230 rests on the top surface of the second dielectric layer (e.g., ILD layer 130), the sides of the sacrificial liner 213, and the top surface of the metal contacts (e.g., S / D contacts 116). The protective liner 230 serves as a barrier layer for metals deposited later. The protective liner 230 reduces bottom-up metal selectivity loss by preventing later-deposited metals from reacting with impurities in ESL 125 and / or surrounding components. For example, the protective liner 230 prevents any carbon exposed in trench 210 from affecting the bottom-up metal growth process. In this embodiment, the protective liner 230 comprises silicon oxide (SiOx). After ILD sealing, the protective liner 230 later becomes part of the second dielectric layer (e.g., ILD layer 130).

[0060] refer to Figure 16 In method 1200, at operation 1208, a horizontal portion of the protective liner 230 is removed, thereby forming the protective liner 230 along the sidewall of the sacrificial liner 213. Operation 1208 includes anisotropic etching (e.g., plasma etching) that selectively etches portions of the protective liner 230 that fall on the top surface of the second dielectric layer (e.g., ILD layer 130) and the top surface of the metal contacts (e.g., S / D contacts 116). In embodiments, the thickness of the protective liner 230 along the x-direction is in the range of about 2 nm to about 4 nm. If the thickness is too thin, the protective liner 230 cannot provide sufficient protection against selective metal loss. If the thickness is too thick, there is less surface contact between the metal contacts (e.g., S / D contacts 116) and the subsequently formed metal vias or contacts (e.g., S / D vias 126).

[0061] As a result of operation 1208, and according to the first embodiment 1200a, a double-layer liner structure is formed along the sidewall of trench 210, wherein the bottom surfaces of sacrificial liner 213 and protective liner 230 are coplanar (or substantially coplanar), and the sacrificial liner 213 and protective liner 230 have the same (or substantially the same) vertical height. The first embodiment 1200a relates to an etching step following each deposition of a corresponding liner, resulting in… Figure 16 The structure is shown. After operation 1208, method 1100 continues to operation 1114.

[0062] refer to Figure 17 In method 1100, metal (e.g., S / D via 126) is deposited between trench 210 and protective liner 230 at operation 1114. The metal is deposited via bottom-up metal growth. Bottom-up metal growth, also known as bottom-up anisotropic deposition, involves depositing metal layers sublayer by layer by applying a metal precursor and promoting vertical metal growth. In some embodiments, bottom-up metal growth includes applying a halogen composition to promote simultaneous deposition and etching. Bottom-up metal growth can be advantageous over isotropic metal deposition by achieving greater metal density and avoiding metal gaps. However, in bottom-up metal growth, selective metal loss can occur when the deposited metal directly contacts and reacts with impurities, such as carbon impurities in low-k SiCN ESL. The protective liner 230 does not contain impurities and also prevents impurities from contacting the deposited metal, thereby eliminating or reducing the risk of selective metal loss.

[0063] refer to Figure 18 Method 1100 selectively removes the sacrificial liner 213 at operation 1116 to form an air gap 141 (also referred to as an air spacer or air wall). Operation 1116 includes applying an etchant that targets the sacrificial liner 213 while substantially not etching surrounding components (e.g., by having an etch selectivity greater than 10 compared to surrounding components such as the protective liner 230, the second dielectric layer (e.g., ILD layer 130), and the ESL (e.g., ESL 125)). The etching process can be a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. The air gap reduces stray capacitive coupling by reducing the capacitance of the ESL (e.g., from 3.8 to 1 when the ESL includes SiCN).

[0064] refer to Figure 19In method 1100, at operation 1118, the gas gap 141 is sealed by performing ion implantation on a second dielectric layer (e.g., ILD layer 130). Ion implantation causes the second dielectric layer to expand, causing the second dielectric layer to laterally merge with the protective liner 230. As a result, the protective liner 230 becomes part of the second dielectric layer. Note that the composition of the second dielectric layer (e.g., ILD layer 130) is selected for expansion that effectively achieves gas gap sealing via the ion implantation process. Ion implantation introduces one or more dopants into the second dielectric layer, thereby transforming the second dielectric layer into an implanted second dielectric layer that laterally seals the gas gap 141. For example, ion implantation may include energies in the range of 10 keV to 20 keV and doses in the range of 1E1 to 3E14 atoms / cm². 2 Germanium (Ge) implantation is performed within a certain range. In optional (or further) embodiments, ion implantation may include arsenic (As) or tin (Sn) implantation with similar energy and dosage. In an embodiment, each of the first and second dielectric layers (e.g., ILD layers 120 and 130) comprises silicon oxide, wherein the second ILD layer (e.g., ILD layer 130) further comprises germanium (and / or arsenic), and the top portion of the second ILD layer has a higher germanium (and / or arsenic) concentration than the bottom portion of the second ILD layer. In an embodiment, the top portion of the second ILD layer seals an air gap. As a result of sealing, the sealed air gap 141 results in a reduced height. Figure 19 In one embodiment, the second dielectric layer (e.g., ILD layer 130) is fully laterally expanded, and the height of the sealed air gap 141 is substantially similar to the height of the ESL (e.g., ESL 125). In another embodiment, the top surface of the air gap 141 is substantially coplanar with the top surface of the ESL.

[0065] Figures 20A to 20B A metal via or contact (e.g., S / D via 126) isolated from an etch stop layer (e.g., ESL125) is shown according to a further embodiment of this disclosure. Note that in Figures 20A to 20B In the embodiments, according to Figure 10A The first embodiment 1200a processing device 100 is described in the text.

[0066] refer to Figure 20A Operation 1118 can be adjusted so that the sealed air gap 141 has a height above or below the ESL. For example, injecting with lower energy and / or dose can cause only the top portion of the second dielectric layer (e.g., ILD layer 130) to expand laterally, while the bottom portion remains uninjected. As a result, only the top portion of the second dielectric layer (e.g., ILD layer 130) expands laterally to engage with the protective liner 230. In this case, as... Figure 20AAs shown, the sealed air gap 141 has a height greater than the ESL. Alternatively, injecting with higher energy and / or dosage can further advance a second dielectric layer (e.g., ILD layer 130) that has already been fully laterally expanded to the bottom portion of the air gap 141. In this case, the sealed air gap 141 has a height less than the ESL (not shown).

[0067] refer to Figure 20B In a further embodiment, multiple air gaps 141 may be formed between the metal via or contact (e.g., S / D via 126) and the ESL (e.g., ESL 125). For example, instead of a two-layer structure forming a sacrificial liner 213 and a protective liner 230, a four-layer structure of alternating sacrificial liner 213, protective liner 230, sacrificial liner 213, and protective liner 230 is formed. Furthermore, two of the four sacrificial liners 213 are selectively removed, while two protective liners 230 are retained after ion implantation and become part of the second dielectric layer (e.g., ILD layer 130). In these embodiments, a greater reduction in parasitic capacitance can be achieved. Although not shown, but related to... Figure 20A As in the previous embodiment, the multiple air gaps 141 may also have a height located above or below the ESL.

[0068] Figures 21 to 28 Another embodiment according to this disclosure is shown. Figure 9 and Figure 10B A cross-sectional view of the film stack of the semiconductor device 100 processed by the method. Figure 9 and Figure 10B The method is similar to that about Figures 11 to 19 Description Figure 9 and Figure 10A The method. For the sake of brevity, similar features will not be repeated.

[0069] refer to Figure 21 In method 1100, at operations 1102-1106, an ESL (e.g., ESL 125) is formed over a metal contact (e.g., S / D contact 116) and a first dielectric layer (e.g., ILD layer 120). Operations 1102-1106 also form a second dielectric layer (e.g., ILD layer 130) over the ESL.

[0070] refer to Figure 22 Method 1100 forms a trench 210 at operation 1108 through the second dielectric layer (e.g., ILD layer 130) and ESL (e.g., ESL 125) to expose the metal contact (e.g., S / D contact 116).

[0071] Now for reference Figures 23 to 25In method 1100, a sacrificial liner 213 is formed along the sidewall of the groove 210 at operations 1110 and 1112, and a protective liner 230 is formed along the sidewall of the sacrificial liner 213. Operations 1110 and 1112 are collectively referred to as method 1200, according to the second embodiment 1200b. Figure 10B Further description is provided below. Figures 23 to 25 The second embodiment 1200b is described.

[0072] refer to Figure 23 In method 1200, at operation 1202, a sacrificial liner 213 is conformally deposited in trench 210 (e.g., by CVD). The sacrificial liner 213 rests on the top and sides of a second dielectric layer (e.g., ILD layer 130), the sides of an ESL (e.g., ESL 125), the top surface of a metal contact (e.g., S / D contact 116), and a barrier layer 113 (if present). The sacrificial liner 213 has a different material from its surrounding components (e.g., ILD layer 130 and ESL 125). This is so that it can be selectively etched away later without damaging the surrounding components. In this embodiment, the sacrificial liner 213 is a pseudo-silicon liner. The silicon liner may comprise amorphous silicon or polycrystalline silicon.

[0073] refer to Figure 24 In method 1200, at operation 1205, a protective liner 230 is conformally deposited in trench 210 (e.g., by CVD) and on sacrificial liner 213. The protective liner 230 rests on the top, bottom, and side surfaces of sacrificial liner 213. The protective liner 230 serves as a barrier layer for metals deposited later. The protective liner 230 reduces bottom-up metal selectivity loss by preventing later-deposited metals from reacting with impurities in ESL 125 and / or surrounding components. For example, the protective liner 230 prevents any carbon exposed in trench 210 from affecting the bottom-up metal growth process. In this embodiment, the protective liner 230 comprises silicon oxide (SiOx). After ILD sealing, the protective liner 230 later becomes part of a second dielectric layer (e.g., ILD layer 130).

[0074] refer to Figure 25 In method 1200, at operation 1207, horizontal portions of the sacrificial liner 213 and the protective liner 230 are removed, thereby forming the sacrificial liner along the sidewalls of the trench 210 and the protective liner 230 along the sidewalls of the sacrificial liner 213. Operation 1207 includes anisotropic etching (e.g., plasma etching) that selectively etches portions of the sacrificial liner 213 and the protective liner 230 above the top surface of the second dielectric layer (e.g., ILD layer 130) and the top surface of the metal contacts (e.g., S / D contacts 116).

[0075] As a result of operation 1207, and according to the second embodiment 1200b, a double-layer liner structure is formed along the sidewall of trench 210. However, unlike the first embodiment 1200a, the sacrificial liner 213 and the protective liner 230 do not have the same or substantially the same vertical height. The sacrificial liner 213 has a greater height than the protective liner 230, and the protective liner 230 may rest on a small horizontal portion of the sacrificial liner 213. This small horizontal portion has the same or similar width as the protective liner 230. This is because the second embodiment involves only one etching step after depositing the two corresponding liners, resulting in a sacrificial liner 213 with an "L" shape, as shown below. Figure 25 The structure is shown below. After operation 1207, method 1100 continues to operation 1114.

[0076] refer to Figure 26 In method 1100, metal (e.g., S / D via 126) is deposited between trench 210 and protective liner 230 at operation 1114. The metal is deposited via bottom-up metal growth. Bottom-up metal growth, also known as bottom-up anisotropic deposition, involves depositing metal layers sublayer by layer by applying a metal precursor and promoting vertical metal growth. In some embodiments, bottom-up metal growth includes applying a halogen component to promote simultaneous deposition and etching. Bottom-up metal growth can be advantageous over isotropic metal deposition by achieving greater metal density and avoiding metal gaps. However, in bottom-up metal growth, selective metal loss can occur when the deposited metal directly contacts and reacts with impurities (such as carbon impurities) in the low-k ESL of SiCN. The protective liner 230 does not contain impurities and also prevents impurities from contacting the deposited metal, thereby eliminating or reducing the risk of metal selective loss. Figure 26 In this embodiment, the deposited metal may partially contact a small, exposed horizontal portion of the sacrificial liner 213. This contact is minimal and does not pose a risk of loss of metal selectivity.

[0077] refer to Figure 27Method 1100 selectively removes the sacrificial liner 213 at operation 1116 to form an air gap 141 (also referred to as an air spacer or air wall). Operation 1116 involves applying an etchant that targets the sacrificial liner 213 while substantially not etching surrounding components (e.g., having an etch selectivity greater than 10 when compared to surrounding components such as the protective liner 230, the second dielectric layer (e.g., ILD layer 130), and the ESL (e.g., ESL 125)). The etching process can be a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. The air gap reduces stray capacitive coupling by reducing the capacitance of the ESL (e.g., from 3.8 to 1 when the ESL includes SiCN). Note that in this embodiment, the air gap 141 has an "L" shape, with the horizontal portion partially exposing the sidewalls of the deposited metal. Therefore, there is greater air separation for the additional stray capacitance reduction.

[0078] refer to Figure 28 In method 1100, at operation 1118, the gas gap 141 is sealed by performing ion implantation on a second dielectric layer (e.g., ILD layer 130). Ion implantation causes the second dielectric layer to expand, causing the second dielectric layer to laterally merge with the protective liner 230. As a result, the protective liner 230 becomes part of the second dielectric layer. Note that the composition of the second dielectric layer (e.g., ILD layer 130) is selected for expansion that effectively achieves gas gap sealing via the ion implantation process. Ion implantation introduces one or more dopants into the second dielectric layer, thereby transforming the second dielectric layer into an implanted second dielectric layer that laterally seals the gas gap 141. For example, ion implantation may include energies in the range of 10 keV to 20 keV and doses in the range of 1E14 to 3E14 atoms / cm². 2 Germanium (Ge) is implanted within a certain range. As a result of sealing, the sealed air gap 141 leads to a reduction in height. Figure 19 In one embodiment, the second dielectric layer (e.g., ILD layer 130) is fully laterally expanded, and the height of the sealed air gap 141 is substantially similar to the height of the ESL (e.g., ESL 125). In another embodiment, the top surface of the air gap 141 is substantially coplanar with the top surface of the ESL.

[0079] Figures 29A to 29B A metal via or contact (e.g., S / D via 126) isolated from an etch stop layer (e.g., ESL125) is shown according to a further embodiment of this disclosure. Note that in Figures 29A to 29B In the embodiments, according to Figure 10B The second embodiment 1200b processing device 100 is described in the text.

[0080] refer to Figure 29AOperation 1118 can be adjusted so that the sealed air gap 141 has a height above or below the ESL. For example, injecting with lower energy and / or dose can cause only the top portion of the second dielectric layer (e.g., ILD layer 130) to expand laterally, while the bottom portion remains uninjected. As a result, only the top portion of the second dielectric layer (e.g., ILD layer 130) expands laterally to engage with the protective liner 230. In this case, as... Figure 29A As shown, the sealed air gap 141 has a height greater than the ESL. Alternatively, injecting with higher energy and / or dosage can further advance a second dielectric layer (e.g., ILD layer 130) that has already been fully laterally expanded to the bottom portion of the air gap 141. In this case, the sealed air gap 141 has a height less than the ESL (not shown).

[0081] refer to Figure 29B In a further embodiment, multiple air gaps 141 may be formed between the metal via or contact (e.g., S / D via 126) and the ESL (e.g., ESL 125). For example, instead of a two-layer structure forming a sacrificial liner 213 and a protective liner 230, a four-layer structure of alternating sacrificial liner 213, protective liner 230, sacrificial liner 213, and protective liner 230 is formed. Furthermore, two of the four sacrificial liners 213 are selectively removed, while two protective liners 230 are retained after ion implantation and become part of the second dielectric layer (e.g., ILD layer 130). In these embodiments, a greater reduction in parasitic capacitance can be achieved. Although not shown, but related to... Figure 29A As in the previous embodiment, the multiple air gaps 141 may also have a height located above or below the ESL.

[0082] While not limiting, this disclosure provides advantages for forming metal contacts / vias. One example advantage is forming a transversely located air gap between the metal contact / via and the etch stop layer to reduce stray capacitance coupling. Another example advantage is forming a protective liner that facilitates bottom-up metal growth. Another example advantage is sealing the air gap by ion implantation, preparing it for further processing. Yet another example advantage is forming multiple air gaps and / or air gaps at different heights according to design requirements.

[0083] One aspect of this disclosure relates to a structure. The structure includes: a first interlayer dielectric (ILD) layer; a conductive component disposed in the first ILD layer; an etch stop layer (ESL) disposed on the first ILD layer; a second ILD layer disposed on the ESL; and a metal component disposed in the second ILD layer and in contact with the conductive component, wherein the metal component is laterally separated from the ESL by an air gap.

[0084] In one embodiment, the metal component is also laterally separated from the ESL by a portion of the second ILD layer. In another embodiment, a portion of the second ILD layer rests on the conductive component. In yet another embodiment, a portion of the second ILD layer is isolated from the conductive component by a lateral portion of an air gap.

[0085] In one embodiment, the first ILD layer and the second ILD layer comprise silicon oxide, wherein the second ILD layer further comprises germanium, and the top portion of the second ILD layer has a higher germanium concentration than the bottom portion of the second ILD layer. In another embodiment, the top portion of the second ILD layer seals the air gap.

[0086] In one embodiment, the top surface of the air gap is located above the top surface of the etch stop layer. In another embodiment, the metal component is also laterally separated from the ESL by a second air gap embedded in the second ILD layer.

[0087] In one embodiment, the ESL is a low-k dielectric. In another embodiment, the ESL comprises silicon nitride. In a further embodiment, the ESL also comprises carbon.

[0088] Another aspect of this disclosure relates to a structure. The structure includes: a source / drain (S / D) contact located above an S / D component; a gate structure located above a channel region, wherein the channel region is adjacent to the S / D component; a first interlayer dielectric (ILD) layer located above the gate structure and surrounding the S / D contact; an etch stop layer located above the first ILD layer and the S / D contact; a second ILD layer located above the etch stop layer; and an S / D via resting on the S / D contact, wherein the S / D via is embedded in the second ILD layer and separated from the etch stop layer.

[0089] In one embodiment, a portion of the second ILD layer is laterally located between the S / D via and the etch stop layer. In another embodiment, the S / D via is isolated from the etch stop layer by an air gap, wherein the air gap is laterally disposed between the S / D via and the etch stop layer. In another embodiment, the first and second ILD layers comprise oxide-based dielectrics, and the etch stop layer comprises a nitride-based dielectric. In another embodiment, the etch stop layer comprises silicon carbonitride. In another embodiment, the second ILD layer has a bottom portion that descends below the top surface of the etch stop layer.

[0090] Another aspect of this disclosure relates to a method. The method includes: forming a metal contact in a first dielectric layer; depositing an etch stop layer (ESL) over the metal contact and the first dielectric layer; depositing a second dielectric layer over the ESL; forming a trench through the second dielectric layer and the ESL to expose the metal contact; forming a sacrificial liner along the sidewalls of the trench; forming a protective liner along the sidewalls of the sacrificial liner; depositing metal between the trench and the protective liner; selectively removing the sacrificial liner to form an air gap; and sealing the air gap by performing ion implantation on the second dielectric layer.

[0091] In the embodiments, the sacrificial liner and the protective liner comprise different materials.

[0092] In an embodiment, the protective liner and the second dielectric layer comprise the same dielectric material.

[0093] The accompanying drawings illustrate details of the methods and systems of this disclosure. Features of several embodiments have been summarized above to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, comprising: First interlayer dielectric (ILD) layer; A conductive component is disposed in the first interlayer dielectric layer; An etch stop layer (ESL) is disposed on the first interlayer dielectric layer; A second interlayer dielectric layer is disposed on the etch stop layer; as well as A metal component is disposed in the second interlayer dielectric layer and in contact with the conductive component, wherein the metal component is laterally separated from the etch stop layer by an air gap.

2. The semiconductor structure according to claim 1, wherein, The metal component is also laterally separated from the etch stop layer by a portion of the second interlayer dielectric layer.

3. The semiconductor structure according to claim 2, wherein, The portion of the second interlayer dielectric layer rests on the conductive component.

4. The semiconductor structure according to claim 2, wherein, The portion of the second interlayer dielectric layer is isolated from the conductive component by the lateral portion of the air gap.

5. The semiconductor structure according to claim 1, wherein, The first interlayer dielectric layer and the second interlayer dielectric layer comprise silicon oxide, wherein the second interlayer dielectric layer further comprises germanium, and the top portion of the second interlayer dielectric layer has a higher germanium concentration than the bottom portion of the second interlayer dielectric layer.

6. The semiconductor structure according to claim 5, wherein, The top portion of the second interlayer dielectric layer seals the air gap.

7. The semiconductor structure according to claim 1, wherein, The top surface of the air gap is located above the top surface of the etch stop layer.

8. The semiconductor structure according to claim 1, wherein, The metal component is also laterally separated from the etch stop layer by a second air gap embedded in the second interlayer dielectric layer.

9. A semiconductor structure, comprising: Source / drain (S / D) contacts are located above the source / drain components; A gate structure is located above a channel region, wherein the channel region is adjacent to the source / drain components; The first interlayer dielectric (ILD) layer is located above the gate structure and surrounds the source / drain contacts; An etch stop layer is located above the first interlayer dielectric layer and the source / drain contact. A second interlayer dielectric layer is located above the etch stop layer; and A source / drain via is located on the source / drain contact, wherein the source / drain via is embedded in the second interlayer dielectric layer and separated from the etch stop layer.

10. A method for forming a semiconductor structure, comprising: Metal contacts are formed in the first dielectric layer; An etch stop layer (ESL) is deposited over the metal contacts and the first dielectric layer; A second dielectric layer is deposited above the etch stop layer; A trench is formed through the second dielectric layer and the etch stop layer to expose the metal contacts; A sacrificial liner is formed along the sidewalls of the trench; A protective liner is formed along the sidewalls of the sacrificial liner; Metal is deposited in the trench and between the protective linings; The sacrificial liner is selectively removed to form an air gap; as well as The air gap is sealed by performing ion implantation on the second dielectric layer.

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