High-voltage bidirectional silicon-controlled electrostatic protection device and manufacturing method thereof

Abstract

The invention discloses a high-voltage bidirectional silicon controlled rectifier electrostatic protection device and a manufacturing method. The high-voltage bidirectional silicon controlled rectifier electrostatic protection device comprises a P-type substrate, a P-type well and a high-voltage N well, the emitter P + injection of a parasitic PNP triode and the emitter N + injection of a parasitic NPN triode in the P-type well are arranged alternately, so that the length of a transverse discharge path of the silicon controlled rectifier is reduced to the greatest extent, the square resistance of a PNPN positive feedback conduction path is greatly reduced, and the key problem that a symmetrical bidirectional silicon controlled rectifier structure cannot be effectively opened in a high-voltage window of more than 70V is solved; in addition, the layout can provide an additional parasitic NPN triode path for a silicon controlled rectifier path, the effective area of an emitter of the parasitic NPN triode and the proportion of the emitter in a silicon controlled rectifier loop are increased, and the current discharge capacity of the device is further improved. Therefore, reference can be provided for the structural design of the high-voltage symmetrical bidirectional silicon controlled rectifier electrostatic protection device, and the silicon controlled rectifier can be effectively applied to ESD protection of a high-voltage bidirectional port.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge (ESD) protection, and in particular to a high-voltage bidirectional thyristor ESD protection device and its manufacturing method. Background Technology

[0002] With advancements in semiconductor manufacturing processes, ESD-induced failures of integrated circuit chips and electronic products have become increasingly severe. ESD protection for electronic products and integrated circuit chips has become one of the major challenges faced by product engineers.

[0003] Compared to other ESD devices, traditional silicon controlled rectifiers (SCRs) have advantages such as a dual-conductance modulation mechanism, high discharge efficiency per unit area, small parasitic capacitance per unit area, and the best robustness. However, traditional SCRs have drawbacks such as excessively high trigger voltage and excessively low sustaining voltage after hysteresis. Excessively high trigger voltage can cause the protection device to fail to protect the core circuit in time, while excessively low sustaining voltage can cause latch-up, making it impossible to guarantee the integrity of the signals transmitted through the I / O ports.

[0004] Bidirectional thyristor devices are an improvement on traditional thyristors. They can be considered as an integration of several ordinary thyristors connected in anti-parallel. Their working principle is the same as that of traditional unidirectional thyristors, clamping voltage in both forward and reverse directions. A cross-sectional diagram of a traditional bidirectional thyristor electrostatic discharge (ESD) device is shown below. Figure 1 Its equivalent circuit diagram is shown in Figure 2 When an ESD pulse is applied to the anode of a bidirectional SCR, avalanche breakdown occurs in the reverse-biased PN junction between the N-type well and the P-type well of the cathode. The resulting avalanche current flows through the parasitic resistance Rpw2 of the P-type well of the cathode, forming a voltage drop across it to turn on the NPN2 transistor. After the NPN2 transistor turns on, it provides base current to the lateral PNP transistor, turning it on. Conversely, after the PNP transistor turns on, it provides base current to the NPN2 transistor. The two quickly form a positive feedback loop, causing the device to enter a low-resistance conduction state to discharge static electricity. The working principle of the reverse ESD pulse is completely symmetrical to this. However, in high-voltage ports, as the trigger voltage of traditional bidirectional SCRs rises to 70V or 80V or higher, traditional bidirectional SCRs often fail to turn on properly, i.e., the device fails as soon as it is triggered. This is because the thyristor needs to increase the DC breakdown voltage and trigger voltage to 70V or 80V or higher. The traditional bidirectional SCR structure often cannot avoid increasing the distance between the cathode and anode, ultimately causing the high-voltage bidirectional SCR to frequently fail to turn on properly.

[0005] Therefore, how to provide a bidirectional ESD protection device with high trigger voltage, reliable turn-on capability, and sufficiently high sustaining voltage has become one of the problems that urgently need to be solved by those skilled in the art.

[0006] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a high-voltage bidirectional thyristor electrostatic discharge (ESD) protection device and its manufacturing method, so as to solve the contradiction between high trigger voltage, reliable turn-on capability and sufficiently high sustaining voltage in the prior art bidirectional ESD protection device.

[0008] To achieve the above and other related objectives, the present invention provides a high-voltage bidirectional thyristor electrostatic discharge (ESD) protection device, wherein the high-voltage bidirectional thyristor ESD protection device comprises at least:

[0009] A P-type substrate, an N-type buried layer disposed in the P-type substrate, and a PNP device structure disposed on the N-type buried layer;

[0010] The PNP device structure includes a first P-type epitaxial layer, a first high-voltage N-well, and a second P-type epitaxial layer sequentially disposed on the N-type buried layer; a first P-type well disposed in the first P-type epitaxial layer; a first N-type well disposed on the first high-voltage N-well; and a second P-type well disposed in the second P-type epitaxial layer. A first direction is defined as a direction parallel to the device surface and pointing from the first P-type well to the second P-type well; and a second direction is defined as a direction parallel to the device surface and perpendicular to the first direction.

[0011] The first P-type well contains a first fixed N+ injection region, M first segmented P+ injection regions, and M first segmented N+ injection regions. The first fixed N+ injection region is located on the first side of the first P-type well near the device edge. The M first segmented P+ injection regions and the M first segmented N+ injection regions are arranged alternately along a direction parallel to the second direction, forming a first alternating sequence. The second P-type well contains a second fixed N+ injection region, M second segmented N+ injection regions, and M second segmented P+ injection regions. The second fixed N+ injection region is located on the second side of the second P-type well near the device edge. The M second segmented N+ injection regions and the M second segmented P+ injection regions are arranged alternately along the second direction, forming a second alternating sequence.

[0012] In a top-view projection perpendicular to the second direction, at least one of the first segment N+ injection regions in the first alternating sequence is positioned opposite to one of the second segment P+ injection regions in the second alternating sequence; and / or, at least one of the first segment P+ injection regions in the first alternating sequence is positioned opposite to one of the second segment N+ injection regions in the second alternating sequence.

[0013] The first fixed N+ injection region, M first segmented P+ injection regions, and M first segmented N+ injection regions are electrically connected through a first metal interconnect structure to form the anode of the high-voltage bidirectional thyristor electrostatic discharge (ESD) device; the second fixed N+ injection region, M second segmented P+ injection regions, and M second segmented N+ injection regions are electrically connected through a second metal interconnect structure to form the cathode of the high-voltage bidirectional thyristor ESD device; M is a natural number greater than or equal to 2.

[0014] Optionally, the high-voltage bidirectional thyristor electrostatic discharge (ESD) device further includes: a first field oxygen isolation region disposed outside the first fixed N+ injection region in the first P-type well; a second field oxygen isolation region disposed outside the second fixed N+ injection region in the second P-type well; a third field oxygen isolation region disposed between the first alternating sequence in the first P-type well and the second alternating sequence in the second P-type well; a fourth field oxygen isolation region disposed between the first fixed N+ injection region and the first alternating sequence in the first P-type well; a fifth field oxygen isolation region disposed between the second fixed N+ injection region and the second alternating sequence in the second P-type well; 2M-1 field oxygen isolation regions disposed between M first segmented P+ injection regions and M first segmented N+ injection regions in the first alternating sequence; and 2M-1 field oxygen isolation regions disposed between M second segmented N+ injection regions and M second segmented P+ injection regions in the second alternating sequence.

[0015] Optionally, the high-voltage bidirectional thyristor electrostatic discharge (ESD) device further includes an isolation structure disposed around the periphery of the high-voltage bidirectional thyristor ESD device structure.

[0016] Optionally, the isolation structure includes: a second high-voltage N-well disposed outside the first P-type epitaxial layer, a second N-type well disposed on the second high-voltage N-well; a third high-voltage N-well disposed outside the second P-type epitaxial layer, and a third N-type well disposed on the third high-voltage N-well.

[0017] Optionally, the M first segment P+ injection regions and the M first segment N+ injection regions have the same size along the second direction within the first P-type well, and the first spacing between adjacent injection regions is equal; the M second segment N+ injection regions and the M second segment P+ injection regions have the same size along the second direction within the second P-type well, and the second spacing between adjacent injection regions is equal, and the first spacing is equal to the second spacing.

[0018] This application also proposes a method for manufacturing the above-mentioned high-voltage bidirectional thyristor electrostatic discharge (ESD) device, the method comprising:

[0019] Step 1) An N-type buried layer is formed in a P-type substrate, and a P-type epitaxial layer is formed on the surface of the N-type buried layer;

[0020] Step 2) A first high-voltage N-well is formed in the P-type epitaxial layer, wherein the first high-voltage N-well divides the P-type epitaxial layer into a first P-type epitaxial layer and a second P-type epitaxial layer in the lateral direction.

[0021] Step 3) A first P-type well is formed in the first P-type epitaxial layer, and a second P-type well is formed in the second P-type epitaxial layer;

[0022] Step 4) A first N-type well is formed above the first high-pressure N-well. The first N-type well is spaced between the first P-type well and the second P-type well, and is flush with the first high-pressure N-well in the vertical direction.

[0023] Step 5) Define a direction parallel to the device surface and pointing from the first P-type well to the second P-type well as a first direction, and define a direction parallel to the device surface and perpendicular to the first direction as a second direction; form a first fixed N+ injection region near the first edge of the device and a first alternating sequence near the center of the device in the first P-type well, the first alternating sequence consisting of M first segmented P+ injection regions and M first segmented N+ injection regions, alternating along the second direction; form a second fixed N+ injection region near the second edge of the device and a second alternating sequence near the center of the device in the second P-type well, the second alternating sequence consisting of M second segmented N+ injection regions and M second segmented P+ injection regions, alternating along the second direction; wherein, in a top view perpendicular to the second direction, at least one first segmented N+ injection region in the first alternating sequence is positioned opposite to one second segmented P+ injection region in the second alternating sequence; and / or, at least one first segmented P+ injection region in the first alternating sequence is positioned opposite to one second segmented N+ injection region in the second alternating sequence; M is a natural number greater than or equal to 2;

[0024] Step 6) Anneal each injection zone to eliminate the migration of impurities in the injection zone;

[0025] Step 7) Connect the first fixed N+ injection region, M first segmented P+ injection regions, and M first segmented N+ injection regions in the first P-type well together and use them as the anode of the high-voltage bidirectional thyristor electrostatic discharge (ESD) device. Connect the second fixed N+ injection region, M second segmented P+ injection regions, and M second segmented N+ injection regions in the second P-type well together and use them as the cathode of the high-voltage bidirectional thyristor ESD device.

[0026] Optionally, after step 4), the method further includes: forming a first field oxygen isolation region outside the first fixed N+ injection region in the first P-type well; forming a second field oxygen isolation region outside the second fixed N+ injection region in the second P-type well; forming a third field oxygen isolation region between the first alternating sequence and the second alternating sequence; forming a fourth field oxygen isolation region between the first fixed N+ injection region and the first alternating sequence in the first P-type well; forming a fifth field oxygen isolation region between the second fixed N+ injection region and the second alternating sequence in the second P-type well; forming 2M-1 field oxygen isolation regions between the M first segmented P+ injection regions and the M first segmented N+ injection regions in the first alternating sequence; and forming 2M-1 field oxygen isolation regions between the M second segmented P+ injection regions and the M second segmented N+ injection regions in the second alternating sequence.

[0027] Optionally, the method further includes the step of forming an isolation structure around the high-voltage bidirectional thyristor electrostatic discharge (ESD) device structure:

[0028] Step 2) further includes: forming a second high-voltage N-well on the outside of the first P-type epitaxial layer, and forming a third high-voltage N-well on the outside of the second P-type epitaxial layer.

[0029] Optionally, step 3) further includes forming a second N-type well above the second high-pressure N-well and forming a third N-type well above the third high-pressure N-well.

[0030] Optionally, the M first segment P+ injection regions and the M first segment N+ injection regions have the same size along the second direction within the first P-type well, and the first spacing between adjacent injection regions is equal; the M second segment N+ injection regions and the M second segment P+ injection regions have the same size along the second direction within the second P-type well, and the second spacing between adjacent injection regions is equal, and the first spacing is equal to the second spacing.

[0031] As described above, the beneficial effects of the high-voltage bidirectional thyristor electrostatic discharge (ESD) protection device and its manufacturing method provided by the embodiments of the present invention are as follows:

[0032] 1) This invention, without altering the layout area of ​​the thyristor device, segments the P+ emitter injection of the parasitic PNP transistor and the N+ emitter injection of the parasitic NPN transistor within the P-well of the thyristor device. Furthermore, it employs an alternating layout for the P+ and N+ emitter injections of the parasitic PNP and NPN transistors, designating the outermost injection regions of the two P-wells as N+ injection areas. This approach minimizes the length of the lateral discharge current path of the thyristor device, reducing the sheet resistance of the PNPN positive feedback conduction path. In port applications requiring a thyristor trigger voltage higher than 70V or 80V, this invention solves the critical problem of symmetrical bidirectional thyristor structures failing to effectively turn on due to excessively long lateral discharge current paths.

[0033] 2) This invention segments and alternates the P+ emitter injection of the parasitic PNP transistor and the N+ emitter injection of the parasitic NPN transistor in the P-well, so that the P-well resistance and the emitter (P+ injection) of the thyristor on the forward and reverse paths are on the same straight line as the emitter (N+ injection) of the parasitic NPN transistor, greatly shortening the PNPN positive feedback conduction path length. Simultaneously, the outermost injection points of the two P-wells are designated as N+ injection regions, providing an additional parasitic NPN transistor path for the thyristor. This increases the effective area of ​​the parasitic NPN transistor emitter and its proportion in the thyristor circuit, significantly improving the current amplification factor of the parasitic NPN transistor, thereby further increasing the device's failure current and improving the discharge efficiency per unit area. Attached Figure Description

[0034] Figure 1 This is a cross-sectional view of a currently known bidirectional SCR electrostatic discharge protection device.

[0035] Figure 2 This is the equivalent circuit diagram of the currently known bidirectional SCR electrostatic discharge protection device.

[0036] Figure 3 A three-dimensional cross-sectional view of the high-voltage bidirectional thyristor electrostatic discharge protection device provided in an embodiment of the present invention.

[0037] Figure 4 A cross-sectional view of AA' and an equivalent circuit diagram of the high-voltage bidirectional thyristor electrostatic discharge protection device provided in the embodiments of the present invention.

[0038] Figure 5 A cross-sectional view of BB' and an equivalent circuit diagram of the high-voltage bidirectional thyristor electrostatic discharge protection device provided in the embodiments of the present invention.

[0039] Figure 6aThis is a schematic diagram of the structure after forming an N-type buried layer in a P-type substrate and then forming a P-type epitaxial layer, according to an embodiment of the present invention.

[0040] Figure 6b This is a schematic diagram of the structure after each high-voltage N-well is formed according to an embodiment of the present invention.

[0041] Figure 6c This is a schematic diagram of the structure after forming the first P-type well and the second P-type well according to an embodiment of the present invention.

[0042] Figure 6d This is a schematic diagram of the structure after each N-type well is formed according to an embodiment of the present invention.

[0043] Figure 6e This is a schematic diagram of the structure after forming the oxygen isolation zones in each field according to an embodiment of the present invention.

[0044] Component designation explanation

[0045] 1 High-voltage bidirectional thyristor electrostatic protection device 101 P-type substrate 201 N-type buried layer 11 PNP device structure 301~302 First and second P-type epitaxial layers 401~403 First, second, and third high-pressure N-wells 501~503 First, second, and third N-type traps 601~602 First and second P-type wells 701~705 First, second, third, fourth, and fifth oxygen isolation zones 706a~706c Oxygen isolation zones 6, 7, and 8 707a~707c Oxygen isolation zones 9, 10, and 11 801 First fixed N+ injection area 802a, 802c First segment P+ injection region_Ⅰ, First segment P+ injection region_Ⅱ 802b, 802d First Segment N+ Injection Region_Ⅰ, First Segment N+ Injection Region_Ⅱ 803a, 803c Second Segment N+ Injection Region_Ⅰ, Second Segment N+ Injection Region_Ⅱ 803b, 803d Second segment P+ injection region_Ⅰ, Second segment P+ injection region_Ⅱ 804 Second fixed N+ injection region Detailed Implementation

[0046] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] Please see Figures 3-6e As shown. It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0048] Example 1

[0049] like Figures 3-5 As shown, the present invention provides a high-voltage bidirectional thyristor electrostatic discharge (ESD) protection device 1 with high trigger voltage, reliable turn-on capability, and sufficiently high sustaining voltage. The high-voltage bidirectional thyristor ESD protection device 1 includes:

[0050] A P-type substrate 101, an N-type buried layer 201 disposed in the P-type substrate 101, and a PNP device structure 11 disposed on the N-type buried layer 201.

[0051] like Figure 3 and Figure 4As shown, a P-type substrate 101 is disposed on the bottom layer of the device, an N-type buried layer 201 is located on the top layer of the P-type substrate 101, and a PNP device structure 11 is located on the N-type buried layer 201. The N-type buried layer 201 separates the PNP device structure 11 from the P-type substrate 101, thus avoiding the influence of the substrate potential on the PNP device structure 11.

[0052] like Figure 3 and Figure 4 As shown, the PNP device structure 11 includes a first P-type epitaxial layer 301, a first high-voltage N-well 401, a second P-type epitaxial layer 302, a first P-type well 601, a first N-type well 501, a second P-type well 602, a first fixed N+ injection region 801, a second fixed N+ injection region 804, a first alternating sequence, and a second alternating sequence. The first direction is defined as parallel to the device surface and pointing from the first P-type well 601 to the second P-type well 602, and the second direction is defined as parallel to the device surface and perpendicular to the first direction. The first alternating sequence includes M first segmented P+ injection regions and M first segmented N+ injection regions, arranged alternately along the second direction. The second alternating sequence includes M second segmented N+ injection regions and M second segmented P+ injection regions, arranged alternately along the second direction. M is a natural number greater than or equal to 2.

[0053] Specifically, the first P-type epitaxial layer 301, the first high-voltage N-well 401 and the second P-type epitaxial layer 302 are sequentially laid (flattened) on the N-type buried layer 201. The first high-voltage N-well 401 is located in the central region of the device, and the first P-type epitaxial layer 301 and the second P-type epitaxial layer 302 are located on both sides of the first high-voltage N-well 401.

[0054] Specifically, the first P-type well 601 is disposed in the first P-type epitaxial layer 301, the second P-type well 602 is disposed in the second P-type epitaxial layer 302, the first N-type well 501 is located in the central region of the device and on the first high-voltage N-well 401, and is flush with both sides of the first high-voltage N-well 401; the first P-type well 601 and the second P-type well 602 are respectively located on both sides of the first N-type well 501, and the first P-type well 601 and the first N-type well 501 are isolated by the first P-type epitaxial layer 301, and the second P-type well 602 and the first N-type well 501 are isolated by the second P-type epitaxial layer 302.

[0055] Specifically, in this embodiment, M is set to 2. The first alternating sequence includes a first segmented P+ injection region_Ⅰ802a, a first segmented N+ injection region_Ⅰ802b, a first segmented P+ injection region_Ⅱ802c, and a first segmented N+ injection region_Ⅱ802d disposed in the first P-type well 601, and arranged alternately along the second direction; the first alternating sequence is located on the left side of the device and forms a straight line. The second alternating sequence includes a second segmented N+ injection region_Ⅰ803a, a second segmented P+ injection region_Ⅰ803b, a second segmented N+ injection region_Ⅱ803c, and a second segmented P+ injection region_Ⅱ803d disposed in the second P-type well 602, and arranged alternately along the second direction; the second alternating sequence is located on the right side of the device and forms a straight line.

[0056] In another embodiment, the M first segment P+ injection regions and the M first segment N+ injection regions have equal dimensions along the second direction within the first P-type well 601, and the first spacing between adjacent injection regions is equal; the M second segment N+ injection regions and the M second segment P+ injection regions have equal dimensions along the second direction within the second P-type well 602, and the second spacing between adjacent injection regions is equal, with the first spacing and the second spacing being equal. By setting a symmetrical layout of "equal dimensions and equal spacing," the high consistency of the device's bidirectional protection performance is fundamentally ensured, while achieving uniform distribution of current and heat. It not only eliminates the directional weakness of electrostatic discharge protection, ensuring complete matching of the device's forward and reverse triggering characteristics, but also improves current discharge capability by optimizing on-resistance and significantly enhances reliability by avoiding localized hot spots.

[0057] like Figure 4 As shown, the first fixed N+ injection region 801, M first segmented P+ injection regions, and M first segmented N+ injection regions are electrically connected through a first metal interconnect structure to form the anode of the high-voltage bidirectional thyristor electrostatic discharge (ESD) device; the second fixed N+ injection region 804, M second segmented P+ injection regions, and M second segmented N+ injection regions are electrically connected through a second metal interconnect structure to form the cathode of the high-voltage bidirectional thyristor ESD device.

[0058] As another implementation of the present invention, such as Figure 3 and Figure 4As shown, the high-voltage bidirectional thyristor electrostatic discharge (ESD) device 1 further includes: a first field oxygen isolation region 701, a second field oxygen isolation region 702, a third field oxygen isolation region 703, a fourth field oxygen isolation region 704, and a fifth field oxygen isolation region 705. The first field oxygen isolation region 701 is located outside the first fixed N+ injection region 801; in this embodiment, the first field oxygen isolation region 701 is located at the interface surface between the first P-type epitaxial layer 301 and the first P-type well 601. The second field oxygen isolation region 702 is located outside the second fixed N+ injection region 804; in this embodiment, the second field oxygen isolation region 702 is located at the interface surface between the second P-type epitaxial layer 302 and the second P-type well 602. The third field oxygen isolation region 703 is located between the first alternating sequence (the innermost first segment P+ injection region or the first segment N+ injection region in the first P-type well 601) and the second alternating sequence (the innermost second segment N+ injection region or the second segment P+ injection region in the second P-type well 602); that is, it is located on the surface of the first P-type well 601, the first P-type epitaxial layer 301, the first N-type well 501, the second P-type epitaxial layer 302, and the second P-type well 602. In this example, one field oxygen isolation region is provided in the first P-type well 601, denoted as the fourth field oxygen isolation region 704; one field oxygen isolation region is provided in the second P-type well 602, denoted as the fifth field oxygen isolation region 705. Among them, the fourth field oxygen isolation region 704 is located on the surface of the first P-type well 601 between the first fixed N+ injection region 801 and the first alternating sequence; the fifth field oxygen isolation region 705 is located on the surface of the second P-type well 602 between the second fixed N+ injection region 804 and the second alternating sequence. The first alternation sequence has 2M-1 oxygen isolation zones, which are located between the M first segment P+ injection zones and the M first segment N+ injection zones in the first alternation sequence; the second alternation sequence has 2M-1 oxygen isolation zones, which are located between the M second segment N+ injection zones and the M second segment P+ injection zones in the second alternation sequence.

[0059] In this embodiment, the first alternating sequence includes three field oxygen isolation regions: a sixth field oxygen isolation region 706a, a seventh field oxygen isolation region 706b, and an eighth field oxygen isolation region 706c. The sixth field oxygen isolation region 706a is located between the first segment P+ injection region_Ⅰ802a and the first segment N+ injection region_Ⅰ802b; the seventh field oxygen isolation region 706b is located between the first segment N+ injection region_Ⅰ802b and the first segment P+ injection region_Ⅱ802c; and the eighth field oxygen isolation region 706c is located between the first segment P+ injection region_Ⅱ802c and the first segment N+ injection region_Ⅱ802d. Between; the second alternating sequence has three field oxygen isolation zones, namely the ninth field oxygen isolation zone 707a, the tenth field oxygen isolation zone 707b, and the eleventh field oxygen isolation zone 707c; the ninth field oxygen isolation zone 707a is located between the second segment N+ injection zone_Ⅰ803a and the second segment P+ injection zone_Ⅰ803b; the tenth field oxygen isolation zone 707b is located between the second segment P+ injection zone_Ⅰ803b and the second segment N+ injection zone_Ⅱ803c; the eleventh field oxygen isolation zone 707c is located between the second segment N+ injection zone_Ⅱ803c and the second segment P+ injection zone_Ⅱ803d.

[0060] As another implementation of the present invention, such as Figure 3 and Figure 4 As shown, the high-voltage bidirectional thyristor electrostatic discharge (ESD) device 1 also includes an isolation structure disposed around the PNP device structure 11. As an example, the isolation structure includes: a second high-voltage N-well 402, a second N-type well 502, a third high-voltage N-well 403, and a third N-type well 503. The second high-voltage N-well 402 is located outside the first P-type epitaxial layer 301, the second N-type well 502 is located on the second high-voltage N-well 402, the third high-voltage N-well 403 is located outside the second P-type epitaxial layer 302, and the third N-type well 503 is located on the third high-voltage N-well 403.

[0061] In this embodiment, refer to Figure 3 Screenshot of section AA, as shown Figure 4As shown, the injection region in the first alternating sequence on the first cross-section is the first segmented P+ injection region 802a, and the corresponding injection region in the second alternating sequence is the second segmented N+ injection region 803a. The first segmented P+ injection region 802a, the first N-type well 501, the first high-voltage N-type well 401, the second P-type epitaxial layer 302, and the second P-type well 602 constitute a lateral parasitic PNP transistor; wherein, the second segmented P+ injection region _Ⅰ803b is located adjacent to the second segmented N+ injection region _Ⅰ803a in the second direction, and as part of the cathode contact, it provides a low-resistance metal contact for the second P-type well 602. The second segmented N+ injection region _Ⅰ803a, the second P-type well 602, and the first high-voltage N-well 401 (whose surface achieves low-resistance ohmic contact through the first N-type well 501) constitute a longitudinal parasitic NPN1 transistor. The second fixed N+ injection region 804, the second P-type well 602, and the first high-voltage N-well 401 (whose surface achieves low-resistance ohmic contact through the first N-type well 501) constitute a longitudinal parasitic NPN2 type transistor.

[0062] The isolation structure consisting of the second N-type well 502, the second high-voltage N-well 402, the N-type buried layer 201, the third high-voltage N-well 403, and the third N-type well 503 completely isolates the device from the P-type substrate 101.

[0063] like Figure 3 and Figure 4 As shown, when the ESD high voltage pulse reaches the anode of the device, the first fixed N+ injection region 801 and the first segmented P+ injection region _Ⅰ802a are at high potential, while the second fixed N+ injection region 804 and the second segmented N+ injection region _Ⅰ803a at the other end are at low potential cathode. The PN junction formed by the first N-type well 501, the first high-voltage N-well 401, the second P-type epitaxial layer 302, and the second P-type well 602 is reverse-biased. When the pulse voltage exceeds the avalanche breakdown voltage of this reverse-biased PN junction, a large avalanche current is generated inside the device. The avalanche current flows through the second P-type well 602 and the second segmented P+ injection region_I803b into the cathode. Since the first segmented P+ injection region_I802a and the second segmented N-injection region_I803a are spatially opposite each other, the coupling path between their respective parasitic transistors (PNP and NPN1) is minimized, resulting in the highest efficiency of the carrier injection-collection pair. Therefore, the shortest and most efficient initial triggering path is formed, ensuring that the avalanche current preferentially and strongly forward-biases the emitter junction of NPN1, enabling it to turn on reliably first. The turn-on of NPN1 provides a decisive initial gain for the entire positive feedback loop. Subsequently, during the establishment of the positive feedback, NPN2 is also fully driven, further enhancing the overall current discharge capability of the device.

[0064] Similarly, in this embodiment, refer to Figure 3 See the screenshot of section BB, such as Figure 5 As shown, the first segment N+ injection region_Ⅱ802d in the first alternating sequence on the first directional section is set opposite to the second segment P+ injection region_Ⅱ803d in the second alternating sequence.

[0065] The second segment P+ injection region_Ⅱ803d, the first N-type well 501, the first high-voltage N-well 401, the first P-type epitaxial layer 301, and the first P-type well 601 constitute a lateral parasitic PNP transistor. The first segment N+ injection region_Ⅰ802c is located adjacent to the current first segment N+ injection region_Ⅰ802d in the second direction in the first alternating sequence, serving as part of the anode contact and providing a low-resistance metal contact for the first P-type well 601. The first segment N+ injection region_Ⅱ802d, the first P-type well 601, and the first high-voltage N-well 401 (whose surface achieves low-resistance ohmic contact through the first N-type well 501) constitute a longitudinal parasitic NPN1 transistor. The first fixed N+ injection region 801, the first P-type well 601, and the first high-voltage N-well 401 constitute a longitudinal parasitic NPN2 transistor.

[0066] The isolation structure consisting of the second N-type well 502, the second high-voltage N-well 402, the N-type buried layer 201, the third high-voltage N-well 403, and the third N-type well 503 completely isolates the device from the P-type substrate 101.

[0067] Similarly, such as Figure 3 and Figure 5 As shown, when the ESD high voltage pulse reaches the cathode of the device, the second fixed N+ injection region 804 and the second segmented P+ injection region _Ⅱ803d are at high potential, while the first fixed N+ injection region 801 and the first segmented N+ injection region _Ⅱ802d at the other end are at low potential cathode. The PN junction formed by the first N-type well 501, the first high-voltage N-well 401, the first P-type epitaxial layer 301, and the first P-type well 601 is reverse-biased. When the pulse voltage exceeds the avalanche breakdown voltage of this reverse-biased PN junction, a large avalanche current is generated inside the device. The avalanche current flows through the first P-type well 601 and the first segmented P+ injection region_I802c into the cathode. Since the second segmented P+ injection region_Ⅱ803d and the first segmented N-injection region_Ⅱ802d are spatially opposite each other, the coupling path between their respective parasitic transistors (PNP and NPN1) is minimized, resulting in the highest efficiency of the carrier injection-collection pair. Therefore, the shortest and most efficient initial triggering path is formed, ensuring that the avalanche current preferentially and strongly forward-biases the emitter junction of NPN1, enabling it to turn on reliably first. The turn-on of NPN1 provides a decisive initial gain for the entire positive feedback loop. Subsequently, during the establishment of the positive feedback, NPN2 is also fully driven, further enhancing the overall current discharge capability of the device.

[0068] Example 2

[0069] The present invention also provides a method for manufacturing the above-mentioned high-voltage bidirectional thyristor electrostatic discharge (ESD) device 1, so as to... Figure 3 Section AA Figure 4 The structure is shown in the example, and includes the following steps:

[0070] See Figure 4 and Figure 6a (Execute step 1) to form an N-type buried layer 201 in a P-type substrate 101 and a P-type epitaxial layer on the surface of the N-type buried layer 201.

[0071] Specifically, as an example, before forming the N-type buried layer 201, step 1) further includes a step of pre-processing the P-type substrate 101; including: forming a growth inhibition layer on the P-type substrate 101 (e.g., the growth inhibition layer includes, but is not limited to, stacked silicon dioxide and silicon nitride layers), spin-coating a photoresist layer on the growth inhibition layer and performing exposure and development based on a mask to form an isolation pattern to delineate the device fabrication area, removing the growth inhibition layer in the device fabrication area and removing the isolation pattern.

[0072] See Figure 4 and Figure 6b (Execute step 2) to form a first high-voltage N-well 401 in the P-type epitaxial layer. The first high-voltage N-well 401 divides the P-type epitaxial layer laterally into a first P-type epitaxial layer 301 and a second P-type epitaxial layer 302.

[0073] Specifically, when the high-voltage bidirectional thyristor electrostatic discharge protection device 1 includes an isolation structure, step 2) further includes forming a second high-voltage N-well 402 on the outside of the first P-type epitaxial layer 301 and forming a third high-voltage N-well 403 on the outside of the second P-type epitaxial layer 302.

[0074] See Figure 4 and Figure 6c (Execute step 3) to form a first P-type well 601 in the first P-type epitaxial layer 301 and a second P-type well 602 in the second P-type epitaxial layer 302.

[0075] Specifically, when the high-voltage bidirectional thyristor electrostatic discharge protection device 1 includes an isolation structure, step 3) further includes: forming a second N-type well 502 above the second high-voltage N-well 402, and forming a third N-well 503 above the third high-voltage N-well 403.

[0076] See Figure 4 and Figure 6d (Execute step 4) to form a first N-type well 501 above the first high-pressure N-well 401. The first N-type well 501 is spaced between the first P-type well 601 and the second P-type well 602, and the first N-type well 501 and the first high-pressure N-well 401 are flush in the vertical direction.

[0077] Specifically, see Figure 6e In this embodiment, a first oxygen isolation region 701, a fourth oxygen isolation region 704, a third oxygen isolation region 703, a fifth oxygen isolation region 705, and a second oxygen isolation region 702 are formed sequentially at intervals. The first oxygen isolation region 701 spans the second N-type well 502, the second P-type epitaxial layer 302, and the first P-type well 601. The fourth oxygen isolation region 704 is located in the first P-type well 601. The third oxygen isolation region 703 spans the first P-type well 601, the first P-type epitaxial layer 301, the first N-type well 501, the second P-type epitaxial layer 302, and the second P-type well 602. The fifth oxygen isolation region 705 is located in the second P-type well 602. The second oxygen isolation region 702 spans the second P-type well 602, the second P-type epitaxial layer 302, and the third N-type well 503.

[0078] A first direction is defined as the direction parallel to the device surface and pointing from the first P-type well 601 to the second P-type well 602. A second direction is defined as the direction parallel to the device surface and perpendicular to the first direction. In the first P-type well 601, near the third field oxygen isolation region 703, 2M-1 field oxygen isolation regions are sequentially spaced at intervals along the second direction, forming a straight line. In the second P-type well 602, near the third field oxygen isolation region 703, 2M-1 field oxygen isolation regions are sequentially spaced at intervals along the second direction, forming a straight line. The 2M-1 field oxygen isolation regions in the first P-type well 601 correspond to the 2M-1 field oxygen isolation regions in the second P-type well 602. In this embodiment, M is set to 2. In the first P-type trap 601, a sixth oxygen isolation region 706a, a seventh oxygen isolation region 706b, and an eighth oxygen isolation region 706c are sequentially formed on the side near the third oxygen isolation region 703. In the second P-type trap 602, a ninth oxygen isolation region 707a, a tenth oxygen isolation region 707b, and an eleventh oxygen isolation region 707c are sequentially formed on the side near the third oxygen isolation region 703. Of course, in other embodiments, M can be set according to actual design requirements, such as 10, 20, 30, 40, etc., and no specific limitation is made here.

[0079] See Figures 4-5Step 5) Define a direction parallel to the device surface and pointing from the first P-type well 601 to the second P-type well 602 as a first direction, and define a direction parallel to the device surface and perpendicular to the first direction as a second direction; form a first fixed N+ injection region 801 near the first edge of the device and a first alternating sequence near the center of the device in the first P-type well 601, the first alternating sequence consisting of M first segmented P+ injection regions and M first segmented N+ injection regions, alternating along the second direction; form a second fixed N+ injection region 804 near the second edge of the device and a second alternating sequence near the center of the device in the second P-type well 602, the second alternating sequence consisting of M second segmented N+ injection regions and M second segmented P+ injection regions, alternating along the second direction; wherein, in a top view projection perpendicular to the second direction, at least one first segmented N+ injection region in the first alternating sequence is positioned opposite to one second segmented P+ injection region in the second alternating sequence; and / or, at least one first segmented P+ injection region in the first alternating sequence is positioned opposite to one second segmented N+ injection region in the second alternating sequence.

[0080] Specifically, in this embodiment, M is set to 2. A first fixed N+ injection region 801 and a first alternating sequence are formed in the first P-type well 601. The first fixed N+ injection region 801 is located on the first side of the first P-type well 601 near the device edge. The first alternating sequence includes a first segmented P+ injection region_Ⅰ802a, a first segmented N+ injection region_Ⅰ802b, a first segmented P+ injection region_Ⅱ802c, and a first segmented N+ injection region_Ⅱ802d, which are arranged alternately along a direction parallel to the second direction. A second fixed N+ injection region 804 and a second alternating sequence are formed in the second P-type well 602. The second fixed N+ injection region 804 is located on the second side of the second P-type well 602 near the device edge. The second alternating sequence includes a second segmented N+ injection region_Ⅰ803a, a second segmented P+ injection region_Ⅰ803b, a second segmented N+ injection region_Ⅱ803c, and a second segmented P+ injection region_Ⅱ803d, which are arranged alternately along a direction. See Figure 4 The first segment P+ injection region in the first alternation sequence is positioned opposite to the second segment N+ injection region in the second alternation sequence. (See also...) Figure 5 The first segment N+ injection region in the first alternation sequence is positioned opposite to the second segment P+ injection region in the second alternation sequence. Of course, in other embodiments, M can be set according to actual design requirements, such as 10, 20, 30, 40, etc., and no specific limitation is made here.

[0081] In another embodiment, the M first segment P+ injection regions and the M first segment N+ injection regions have equal dimensions along the second direction within the first P-type well 601, and the first spacing between adjacent injection regions is equal; the M second segment N+ injection regions and the M second segment P+ injection regions have equal dimensions along the second direction within the second P-type well 602, and the second spacing between adjacent injection regions is equal, with the first spacing and the second spacing being equal. By setting a symmetrical layout of "equal dimensions and equal spacing," the high consistency of the device's bidirectional protection performance is fundamentally ensured, while achieving uniform distribution of current and heat. It not only eliminates the directional weakness of electrostatic discharge protection, ensuring complete matching of the device's forward and reverse triggering characteristics, but also improves current discharge capability by optimizing on-resistance and significantly enhances reliability by avoiding localized hot spots.

[0082] Step 6) Anneal each injection zone to eliminate the migration of impurities in the injection zone.

[0083] Step 7) Connect the first fixed N+ injection region 801, M first segmented P+ injection regions, and M first segmented N+ injection regions in the first P-type well 601 together and use them as the anode of the high-voltage bidirectional thyristor electrostatic discharge (ESD) device. Connect the second fixed N+ injection region 804, M second segmented P+ injection regions, and M second segmented N+ injection regions in the second P-type well 602 together and use them as the cathode of the high-voltage bidirectional thyristor ESD device.

[0084] Specifically, in this embodiment, the first fixed N+ injection region 801, the first segmented P+ injection region_Ⅰ802a, the first segmented N+ injection region_Ⅰ802b, the first segmented P+ injection region_Ⅱ802c, and the first segmented N+ injection region_Ⅱ802d are connected together and serve as the anode of the high-voltage bidirectional thyristor electrostatic discharge (ESD) device. The second fixed N+ injection region 804, the second segmented N+ injection region_Ⅰ803a, the second segmented P+ injection region_Ⅰ803b, the second segmented N+ injection region_Ⅱ803c, and the second segmented P+ injection region_Ⅱ803d are connected together and serve as the cathode of the high-voltage bidirectional thyristor ESD device. Of course, in other embodiments, M can be set according to actual design requirements, such as 10, 20, 30, 40, etc., and no specific limitation is made here.

[0085] It should be noted that this article is based on Figure 3 Section AA Figure 4 The structure shown is illustrated as an example, but the manufacturing method of the present invention is not limited to this example. Those skilled in the art will understand that this method is equally applicable to other structural variations covered by the present invention.

[0086] In summary, this invention provides a high-voltage bidirectional thyristor electrostatic discharge (ESD) device and its fabrication method, comprising: a P-type substrate, an N-type buried layer, and a PNP structure formed by sequentially stacking a first P-type epitaxial layer and a second P-type epitaxial layer; wherein, a first P-type well is provided in the first P-type epitaxial layer, a second P-type well is provided in the second P-type epitaxial layer, and a first N-type well longitudinally penetrates the epitaxial layer and the N-well to form isolation. The core innovation of this invention lies in the injection region layout within the first and second P-type wells: within each P-type well, along a direction parallel to the electrode, the emitter (P+ injection region) of the parasitic PNP transistor and the emitter (N+ injection region) of the parasitic NPN transistor are segmented and arranged alternately to form M pairs (M≥2) of segmented injection sequences, thereby forming a high-voltage symmetrical bidirectional thyristor ESD device with an alternating emitter layout; simultaneously, a fixed N+ injection region is provided on the side of each P-type well near the device edge. The segmented sequences within the two P-type wells are staggered in a top-view projection. All injection regions located in the first P-type well are connected in parallel as anodes through a first metal interconnect, and all injection regions located in the second P-type well are connected in parallel as cathodes through a second metal interconnect, thus forming a symmetrical bidirectional structure.

[0087] The fabrication method of this invention for a high-voltage bidirectional thyristor electrostatic discharge (ESD) device is simple and easy to operate. This novel bidirectional SSD ESD device structure, without changing the layout area of ​​the SSD, is achieved by segmenting the P+ and N+ emitter injection regions of the parasitic PNP transistor and NPN transistor within the P-type well of the SSD, respectively, and innovatively employing an alternating layout for the P+ and N+ injection regions. This approach minimizes the length of the lateral discharge current path of the SSD, significantly reducing the sheet resistance of the PNPN positive feedback conduction path. In port applications requiring a SSD trigger voltage higher than 70V or 80V, it solves the critical problem of symmetrical bidirectional SSD structures failing to effectively turn on due to excessively long lateral discharge current paths. Furthermore, the outermost N+ injection regions of the two P-type wells in this novel SCR electrostatic discharge (ESD) structure provide an additional parasitic NPN transistor path for the SCR. This increases the effective emitter area of ​​the parasitic NPN transistor and its proportion in the SCR circuit, significantly improving the β (current amplification factor) of the parasitic NPN transistor and further enhancing the device's discharge current capability. The device in this invention example utilizes a 0.18μm BCDMOS process. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and possesses high industrial applicability.

[0088] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A high-voltage bidirectional thyristor electrostatic discharge (ESD) protection device, characterized in that, The high-voltage bidirectional thyristor electrostatic discharge protection device includes at least: A P-type substrate, an N-type buried layer disposed in the P-type substrate, and a PNP device structure disposed on the N-type buried layer; The PNP device structure includes a first P-type epitaxial layer, a first high-voltage N-well, and a second P-type epitaxial layer sequentially disposed on the N-type buried layer; a first P-type well disposed in the first P-type epitaxial layer; a first N-type well disposed on the first high-voltage N-well; and a second P-type well disposed in the second P-type epitaxial layer. A first direction is defined as a direction parallel to the device surface and pointing from the first P-type well to the second P-type well; and a second direction is defined as a direction parallel to the device surface and perpendicular to the first direction. The first P-type well contains a first fixed N+ injection region, M first segmented P+ injection regions, and M first segmented N+ injection regions. The first fixed N+ injection region is located on the first side of the first P-type well near the device edge. The M first segmented P+ injection regions and the M first segmented N+ injection regions are arranged alternately along a direction parallel to the second direction to form a first alternating sequence. The second P-type well contains a second fixed N+ injection region, M second segmented N+ injection regions, and M second segmented P+ injection regions. The second fixed N+ injection region is located on the second side of the second P-type well near the device edge. The M second segmented N+ injection regions and the M second segmented P+ injection regions are arranged alternately along a direction to form a second alternating sequence. In a top-view projection perpendicular to the second direction, at least one of the first segment N+ injection regions in the first alternating sequence is positioned opposite to one of the second segment P+ injection regions in the second alternating sequence; and / or, at least one of the first segment P+ injection regions in the first alternating sequence is positioned opposite to one of the second segment N+ injection regions in the second alternating sequence. The first fixed N+ injection region, M first segmented P+ injection regions, and M first segmented N+ injection regions are electrically connected through a first metal interconnect structure to form the anode of the high-voltage bidirectional thyristor electrostatic discharge (ESD) device; the second fixed N+ injection region, M second segmented P+ injection regions, and M second segmented N+ injection regions are electrically connected through a second metal interconnect structure to form the cathode of the high-voltage bidirectional thyristor ESD device; M is a natural number greater than or equal to 2.

2. The high-voltage bidirectional thyristor electrostatic discharge protection device according to claim 1, characterized in that: The high-voltage bidirectional thyristor electrostatic discharge (ESD) device further includes: a first field oxygen isolation region disposed outside the first fixed N+ injection region in the first P-type well; a second field oxygen isolation region disposed outside the second fixed N+ injection region in the second P-type well; a third field oxygen isolation region disposed between the first alternating sequence in the first P-type well and the second alternating sequence in the second P-type well; a fourth field oxygen isolation region disposed between the first fixed N+ injection region and the first alternating sequence in the first P-type well; a fifth field oxygen isolation region disposed between the second fixed N+ injection region and the second alternating sequence in the second P-type well; 2M-1 field oxygen isolation regions disposed between M first segmented P+ injection regions and M first segmented N+ injection regions in the first alternating sequence; and 2M-1 field oxygen isolation regions disposed between M second segmented N+ injection regions and M second segmented P+ injection regions in the second alternating sequence.

3. The high-voltage bidirectional thyristor electrostatic discharge protection device according to claim 1 or 2, characterized in that: The high-voltage bidirectional thyristor electrostatic discharge protection device also includes an isolation structure disposed on the periphery of the high-voltage bidirectional thyristor electrostatic discharge protection device structure.

4. The high-voltage bidirectional thyristor electrostatic discharge protection device according to claim 3, characterized in that: The isolation structure includes: a second high-voltage N-well disposed outside the first P-type epitaxial layer, a second N-type well disposed on the second high-voltage N-well; a third high-voltage N-well disposed outside the second P-type epitaxial layer, and a third N-type well disposed on the third high-voltage N-well.

5. The method for manufacturing the high-voltage bidirectional thyristor electrostatic discharge (ESD) protection device according to claim 1, characterized in that: The M first segment P+ injection regions and the M first segment N+ injection regions have the same size along the second direction within the first P-type well, and the first spacing between adjacent injection regions is equal; the M second segment N+ injection regions and the M second segment P+ injection regions have the same size along the second direction within the second P-type well, and the second spacing between adjacent injection regions is equal, and the first spacing is equal to the second spacing.

6. A method for manufacturing a high-voltage bidirectional thyristor electrostatic discharge (ESD) device as described in any one of claims 1-5, characterized in that, The method for manufacturing the high-voltage bidirectional thyristor electrostatic discharge protection device includes: Step 1) An N-type buried layer is formed in a P-type substrate, and a P-type epitaxial layer is formed on the surface of the N-type buried layer; Step 2) A first high-voltage N-well is formed in the P-type epitaxial layer, wherein the first high-voltage N-well divides the P-type epitaxial layer laterally into a first P-type epitaxial layer and a second P-type epitaxial layer. Step 3) A first P-type well is formed in the first P-type epitaxial layer, and a second P-type well is formed in the second P-type epitaxial layer; Step 4) A first N-type well is formed above the first high-pressure N-well. The first N-type well is spaced between the first P-type well and the second P-type well, and is flush with the first high-pressure N-well in the vertical direction. Step 5) Define a direction parallel to the device surface and pointing from the first P-type well to the second P-type well as a first direction, and define a direction parallel to the device surface and perpendicular to the first direction as a second direction; form a first fixed N+ injection region near the first edge of the device and a first alternating sequence near the center of the device in the first P-type well, the first alternating sequence consisting of M first segmented P+ injection regions and M first segmented N+ injection regions, alternating along the second direction; form a second fixed N+ injection region near the second edge of the device and a second alternating sequence near the center of the device in the second P-type well, the second alternating sequence consisting of M second segmented N+ injection regions and M second segmented P+ injection regions, alternating along the second direction; wherein, in a top view perpendicular to the second direction, at least one first segmented N+ injection region in the first alternating sequence is positioned opposite to one second segmented P+ injection region in the second alternating sequence; and / or, at least one first segmented P+ injection region in the first alternating sequence is positioned opposite to one second segmented N+ injection region in the second alternating sequence, where M is a natural number greater than or equal to 2; Step 6) Anneal each injection zone to eliminate the migration of impurities in the injection zone; Step 7) Connect the first fixed N+ injection region, M first segmented P+ injection regions, and M first segmented N+ injection regions in the first P-type well together and use them as the anode of the high-voltage bidirectional thyristor electrostatic discharge (ESD) device. Connect the second fixed N+ injection region, M second segmented P+ injection regions, and M second segmented N+ injection regions in the second P-type well together and use them as the cathode of the high-voltage bidirectional thyristor ESD device.

7. The method for manufacturing the high-voltage bidirectional thyristor electrostatic discharge (ESD) protection device according to claim 6, characterized in that: Step 4) further includes: forming a first field oxygen isolation region outside the first fixed N+ injection region in the first P-type well; forming a second field oxygen isolation region outside the second fixed N+ injection region in the second P-type well; forming a third field oxygen isolation region between the first alternating sequence and the second alternating sequence; forming a fourth field oxygen isolation region between the first fixed N+ injection region and the first alternating sequence in the first P-type well; forming a fifth field oxygen isolation region between the second fixed N+ injection region and the second alternating sequence in the second P-type well; forming 2M-1 field oxygen isolation regions between M first segmented P+ injection regions and M first segmented N+ injection regions in the first alternating sequence; and forming 2M-1 field oxygen isolation regions between M second segmented P+ injection regions and M second segmented N+ injection regions in the second alternating sequence.

8. The method for manufacturing a high-voltage bidirectional thyristor electrostatic discharge (ESD) device according to claim 6 or 7, characterized in that: It also includes the step of forming an isolation structure around the structure of the high-voltage bidirectional thyristor electrostatic discharge (ESD) device: Step 2) further includes: forming a second high-voltage N-well on the outside of the first P-type epitaxial layer, and forming a third high-voltage N-well on the outside of the second P-type epitaxial layer.

9. The method for manufacturing the high-voltage bidirectional thyristor electrostatic discharge protection device according to claim 8, characterized in that: It also includes step 3), in which a second N-type well is formed above the second high-pressure N-well, and a third N-type well is formed above the third high-pressure N-well.

10. The method for manufacturing the high-voltage bidirectional thyristor electrostatic discharge (ESD) protection device according to claim 6, characterized in that: In step 5), the M first segment P+ injection regions and the M first segment N+ injection regions have the same size along the second direction within the first P-type well, and the first spacing between adjacent injection regions is equal; the M second segment P+ injection regions and the M second segment N+ injection regions have the same size along the second direction within the second P-type well, and the second spacing between adjacent injection regions is equal, and the first spacing is equal to the second spacing.

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