Laminated component and manufacturing method thereof

Abstract

The invention discloses a laminated assembly and a manufacturing method thereof, the laminated assembly comprises a thin-film battery layer and a crystalline silicon battery layer, the thin-film battery layer is provided with a short-circuit current I1, a total output voltage V1 and a first electrode lead-out wire; the crystalline silicon cell layer is provided with a short-circuit current I2, a total output voltage V2 and a second electrode outgoing line; wherein 0.975 I2 < = I1 < = 1.025 I2, and 0.95 V2 < = V1 < = 1.05 V2; the first electrode lead-out wire and the second electrode lead-out wire are respectively connected in parallel to a shared positive bus bar and a shared negative bus bar, and the electrodes are matched with each other. The thin film battery layer and the crystalline silicon battery layer are connected in parallel and integrated according to a specific current and voltage matching relation, so that a battery framework with optical series connection and circuit parallel connection is creatively realized, and the problem of current mismatching caused by spectral change of a traditional series laminated assembly is effectively avoided.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic cells, and in particular to a tandem module and its manufacturing method. Background Technology

[0002] As is well known, traditional tandem photovoltaic (TPM) modules typically employ a series structure, where the top and bottom cells are connected in series in the circuit. The output performance of this structure is limited by the cell with the lowest current. In actual outdoor operation, the solar spectrum dynamically changes with weather and time, leading to current mismatch between the series-connected cells. This results in significant efficiency loss and potential hot spot risks, affecting the module's reliability and lifespan. Furthermore, the series structure causes output voltage superposition, posing a higher risk of electric arcing, and requires complex interconnect structures or additional terminals, increasing manufacturing costs and process complexity. Summary of the Invention

[0003] The present invention aims to at least solve one of the technical problems existing in the prior art. To this end, the present invention proposes a stacked assembly capable of reliably integrating batteries.

[0004] The present invention also proposes a method for manufacturing the above-described stacked assembly.

[0005] According to a first aspect of the present invention, a stacked assembly includes: a thin-film battery layer and a crystalline silicon battery layer. The thin-film battery layer includes a plurality of thin-film sub-cells connected in series to form the thin-film battery layer. The thin-film battery layer has a short-circuit current I1, a total output voltage V1, and a first electrode lead. The crystalline silicon battery layer includes a plurality of crystalline silicon sub-cells connected in series to form the crystalline silicon battery layer. The crystalline silicon battery layer has a short-circuit current I2, a total output voltage V2, and a second electrode lead. Wherein, 0.975I2≤I1≤1.025I2, 0.95V2≤V1≤1.05V2. The first electrode lead and the second electrode lead are respectively connected in parallel to a common positive busbar and a negative busbar, and the electrodes are matched to each other.

[0006] The stacked module according to embodiments of the present invention has at least the following beneficial effects: by integrating the thin-film battery layer and the crystalline silicon battery layer in parallel with a specific current and voltage matching relationship, a battery architecture of optical series connection and circuit parallel connection is creatively realized. This architecture effectively avoids the current mismatch problem caused by spectral changes in traditional series stacked modules through voltage matching, fundamentally eliminating the resulting efficiency loss and hot spot risk. The parallel output characteristics make the module's operating voltage comparable to that of conventional single-junction modules, significantly reducing the high-voltage arc safety hazard during system applications and improving the intrinsic safety level of the system. Simultaneously, the dynamic voltage matching characteristics of the single parallel circuit make the module insensitive to spectral and temperature changes, resulting in more stable and higher power generation output in actual outdoor environments.

[0007] According to some embodiments of the present invention, a front encapsulation plate and a rear encapsulation plate are also included, wherein the thin-film battery layer and the crystalline silicon battery layer are both located between the front encapsulation plate and the rear encapsulation plate, and the front encapsulation plate and the rear encapsulation plate can cooperate to shield and encapsulate the thin-film battery layer and the crystalline silicon battery layer.

[0008] According to some embodiments of the present invention, at least one of the front encapsulation plate and the rear encapsulation plate is configured as semi-tempered / tempered glass, and the thickness of both the front encapsulation plate and the rear encapsulation plate is configured as 2mm-6mm.

[0009] According to some embodiments of the present invention, at least one of the front encapsulation plate and the rear encapsulation plate is coated with an anti-reflective film.

[0010] According to some embodiments of the present invention, a protective film is provided between the front packaging plate and the thin-film battery layer, between the thin-film battery layer and the crystalline silicon battery layer, and between the crystalline silicon battery layer and the rear packaging plate.

[0011] According to some embodiments of the present invention, the protective film between the front encapsulation plate and the thin-film battery layer is set as a UV light-converting adhesive film; the protective film between the thin-film battery layer and the crystalline silicon battery layer, and between the crystalline silicon battery layer and the rear encapsulation plate, is set as a POE adhesive film or a high-transparency EVA adhesive film.

[0012] A manufacturing method according to a second aspect embodiment of the present invention, for manufacturing a stacked assembly according to the first aspect embodiment of the present invention, includes the following steps:

[0013] S1: A transparent conductive layer and a thin-film photovoltaic structure are deposited on a glass substrate to form a thin-film battery. The thin-film battery is divided into multiple thin-film sub-cells with consistent section width by laser scribing and then integrated in series to prepare a thin-film battery layer. S2: Cut a standard crystalline silicon cell into multiple crystalline silicon sub-cells, and then arrange the multiple crystalline silicon sub-cells in series with conductive adhesive or solder ribbon to form a crystalline silicon cell layer; S3: Stack the layers in the following order: front encapsulation board, first protective film, thin film battery layer obtained in step S1, second protective film, crystalline silicon battery layer obtained in step S2, third protective film, and rear encapsulation board. S4: Vacuum lamination is performed on the stacked components to ensure a strong bond between the layers; S5: Connect the output terminals of the thin-film battery layer and the crystalline silicon battery layer of the laminated module in parallel, and connect them to the positive and negative busbars of a single junction box. In steps S1 and S2, the following current matching steps are performed: A1: Based on the area ratio 'a' of the etched region of the thin-film battery layer, the spectral response curve of the bottom crystalline silicon battery, and the AM1.5 standard spectrum, calculate E: E = a × K1 + (1-a) × K2 + (1-a) × K3; A2: Calculate the expected short-circuit current of the crystalline silicon cell layer according to the formula I = I0 × K(m) × E, where I0 is the current of the complete crystalline silicon cell and K(m) is the area loss factor after slab division. A3: By adjusting the section width of the thin-film sub-cell and the number of crystalline silicon sub-cells m, the difference between the expected short-circuit current of the crystalline silicon cell layer and the short-circuit current of the thin-film cell layer can be controlled within ±5%. in: a represents the area percentage of the etched region in the thin-film battery layer; K1 is the relative current coefficient of the crystalline silicon cell layer in the etched region of the thin-film cell layer; K2 is the relative current coefficient of the crystalline silicon solar cell layer in the light transmission band (λg to 1200nm) of the thin-film solar cell layer, and its value is determined based on the AM1.5 spectrum and the spectral response curve of the crystalline silicon solar cell layer. K3 is the relative current coefficient of the crystalline silicon solar cell layer in the remaining short-wavelength band (300nm to λg) that is not fully absorbed by the thin-film solar cell layer. Its value is determined by the quantum efficiency curve of the thin-film solar cell layer and the transmittance of its transparent electrode.

[0014] The manufacturing method according to embodiments of the present invention has at least the following beneficial effects: By performing precise optical and electrical calculations before cell layer fabrication and stacking, a quantitative current matching design process based on a physical model can be deeply integrated into specific manufacturing steps, thereby transforming the traditional trial-and-error cycle of fabrication, testing, and adjustment into a highly efficient model-prediction-precision manufacturing mode. This pre-design capability ensures a high degree of current matching between the thin-film cell branch and the crystalline silicon cell branch when connected in parallel, significantly reducing internal energy loss and potential hot spot risks caused by current mismatch from the manufacturing source, and greatly improving product reliability, performance consistency, and yield. Therefore, it can effectively make the manufacturing process no longer blind, but a scientifically guided, predictable, and highly controllable intelligent production.

[0015] According to some embodiments of the present invention, the thin-film battery layer is configured as a cadmium telluride thin-film battery with an absorption edge λg of 855 nm, and the crystalline silicon battery layer is a heterojunction battery, wherein K2=0.353 and K3=0.207.

[0016] According to some embodiments of the present invention, the thin-film battery layer is configured as a perovskite thin-film battery with an absorption edge λg of 780 nm, and the crystalline silicon battery layer is a heterojunction battery, wherein K2=0.441 and K3=0.224.

[0017] According to some embodiments of the present invention, in the parallel connection of step S5, if the calculated difference between the currents of the two branches is greater than 2.5%, a low-dropout Schottky anti-reverse current diode is connected in series at the positive output terminal of the thin-film battery layer.

[0018] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0019] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of a stacked component according to an embodiment of the present invention; Figure 2 for Figure 1 A schematic diagram of a cross-section of the stacked assembly is shown; Figure 3 The spectral curves of CdTe, PK, and Si cells are shown. Figure 4 The transmittance of the CdTe transparent electrode is given.

[0020] Reference numerals: Front encapsulation plate 100; Protective film 400; Thin-film battery layer 500; Thin-film sub-cell 550; Crystalline silicon battery layer 700; Crystalline silicon sub-cell 750; Rear encapsulation plate 900; Detailed Implementation Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0021] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0022] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0023] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0024] Reference Figure 1A stacked assembly includes: a thin-film battery layer 500 and a crystalline silicon battery layer 700. The thin-film battery layer 500 includes multiple thin-film sub-cells 550, which are connected in series to form the thin-film battery layer 500. The thin-film battery layer 500 has a short-circuit current I1, a total output voltage V1, and a first electrode lead. The crystalline silicon battery layer 700 includes multiple crystalline silicon sub-cells 750, which are connected in series to form the crystalline silicon battery layer 700. The crystalline silicon battery layer 700 has a short-circuit current I2, a total output voltage V2, and a second electrode lead. Wherein, 0.975I2≤I1≤1.025I2, 0.95V2≤V1≤1.05V2. The first electrode lead and the second electrode lead are respectively connected in parallel to a common positive electrode busbar and a negative electrode busbar, and the electrodes are matched with each other. By integrating the thin-film battery layer 500 and the crystalline silicon battery layer 700 in parallel with a specific current and voltage matching relationship, a battery architecture combining optical series connection and circuit parallel connection has been creatively achieved. This architecture effectively avoids the current mismatch problem caused by spectral changes in traditional series-connected multilayer modules through voltage matching, fundamentally eliminating the resulting efficiency loss and hot spot risk. The parallel output characteristics make the module's operating voltage comparable to that of conventional single-junction modules, significantly reducing the high-voltage arc safety hazard during system applications and improving the system's intrinsic safety level. Simultaneously, the dynamic voltage matching characteristics of the single parallel circuit make the module insensitive to spectral and temperature changes, resulting in more stable and higher power generation in actual outdoor environments.

[0025] Furthermore, this stacked architecture can be extended to more types of battery combinations. For example, the top thin-film layer can be a CIGS (copper indium gallium selenide) thin-film battery with an adjustable absorption edge, allowing for optical and electrical matching with different types of crystalline silicon batteries (such as PERC, TOPCon, etc.). In addition, intelligent power electronic devices, such as micro-inverters or optimizers, can be integrated at the parallel nodes to further refine the output of the two branches, achieving independent optimization of maximum power point tracking, thereby maintaining extremely high energy output even under extremely complex lighting conditions.

[0026] In some embodiments, reference is made to Figure 2The thin-film battery layer 500 is configured as either a cadmium telluride (CdT) thin-film battery or a perovskite thin-film battery, and is divided into multiple independent thin-film sub-cells 550 with consistent section widths. Using CdT or perovskite as the top-cell thin-film layer fully utilizes the high voltage, good low-light response, and suitable bandgap of these two materials for top-cell applications. Dividing it into sub-cells with consistent section widths using laser scribing allows for precise control of the total output voltage of the series-connected thin-film battery string, providing a crucial technological means to achieve voltage matching with the bottom silicon layer. Thus, the top-cell layer not only absorbs high-energy photons but also becomes a precisely controllable electrical unit, laying a solid foundation for the stability of the entire parallel system. The inherent stability of CdT film and the high efficiency potential of perovskite film together endow this stacked module with the dual advantages of high reliability and high performance.

[0027] In the implementation of cadmium telluride thin-film batteries, the transparent conductive layer can be made of cadmium-free or low-cadmium materials such as zinc oxide doped with aluminum to improve environmental friendliness. For perovskite thin-film batteries, a two-dimensional / three-dimensional perovskite hybrid structure or the introduction of an interface passivation layer can be used to significantly improve their long-term environmental stability. The laser scribing process can be further optimized, for example, by using ultrafast lasers to reduce the heat-affected zone, thereby reducing the dead zone width and improving the fill factor and final efficiency of the thin-film battery string. It is also possible to explore combining thin-film sub-cells with different section widths to achieve better current matching under non-standard spectra.

[0028] In some embodiments, reference is made to Figure 1 The crystalline silicon cell layer 700 is configured as a standard crystalline silicon cell, which is then cut into half-cells or multiple smaller cells to form multiple crystalline silicon sub-cells 750. Cutting the standard crystalline silicon cell into multiple segments has the primary benefit of significantly reducing the internal current resistance loss within the cell, thereby improving the fill factor and output power of the cell string. Secondly, the segmented design effectively reduces the risk of hot spot effects caused by localized shading, improving the module's anti-shading capability and reliability. More importantly, by adjusting the number of segments, the total output current of the crystalline silicon cell string can be flexibly adjusted, which is one of the core control dimensions for achieving precise matching with the current of the top-cell thin-film string. The smaller segmented layout also provides greater flexibility for the internal layout of the module, helping to optimize the arrangement within a limited area and improve energy density.

[0029] In practical implementation, the crystalline silicon sub-cell 750 can be cut using non-destructive or low-destructive cutting techniques, such as thermal laser separation or stealth cutting, to maximize the mechanical strength of the cut edges, reduce the fragmentation rate, and minimize efficiency loss due to cutting damage. The interconnection method after slab formation can surpass traditional solder ribbon interconnection, employing technologies such as conductive adhesive, flexible circuit boards, or dispensing interconnection to reduce welding stress and the risk of microcracks. Furthermore, the slab shape is not limited to rectangles; hexagonal or other shapes more conducive to optical management and current collection can be explored.

[0030] In some embodiments, reference is made to Figure 2 The system also includes a front encapsulation plate 100 and a rear encapsulation plate 900. The thin-film battery layer 500 and the crystalline silicon battery layer 700 are both located between the front encapsulation plate 100 and the rear encapsulation plate 900. The front encapsulation plate 100 and the rear encapsulation plate 900 work together to shield and encapsulate the thin-film battery layer 500 and the crystalline silicon battery layer 700. Together, the front encapsulation plate 100 and the rear encapsulation plate 900 form a robust sealed protective body, providing a physical barrier against external environmental erosion such as moisture, oxygen, and ultraviolet radiation for the internally fragile battery layers, ensuring the module has long-term weather resistance and reliability. This encapsulation structure protects the thin-film battery layer 500 and the crystalline silicon battery layer 700 as a whole, simplifying the encapsulation process and avoiding the complex process of separate encapsulation and reassembly. At the same time, the choice of encapsulation plate directly affects the optical and mechanical properties of the module and is the foundation for achieving integrated structural and functional design of the module.

[0031] Furthermore, the encapsulation can be extended to a frameless double-glass sandwich structure, where the edges of the two glass panes are bonded together with sealant to achieve a complete seal, further enhancing resistance to potential-induced degradation and moisture barrier properties. Another embodiment uses a polymer composite backsheet combined with the front glass to reduce the overall weight of the module. Additionally, microstructured optical films, such as prism films or diffraction gratings, can be designed on the inner or outer surface of the front encapsulation plate 100 to guide more light into the cell active layer, improving light capture efficiency.

[0032] In some embodiments, reference is made to Figure 1 At least one of the front encapsulation panel 100 and the rear encapsulation panel 900 is made of semi-tempered / tempered glass, with a thickness of 2mm-6mm for both panels. Using semi-tempered or fully tempered glass as the encapsulation panel significantly enhances the mechanical strength of the module, enabling it to withstand severe mechanical stresses such as wind pressure, snow load, and hail impact. This makes it particularly suitable for applications requiring high structural strength, such as building-integrated photovoltaics (BIPV). The 2mm to 6mm thickness range achieves a good balance between weight and strength while ensuring structural rigidity and impact resistance. Tempered glass has a low spontaneous breakage rate and high safety; even if it breaks, it will shatter into small, blunt-angled particles, reducing safety hazards. The double-glass structure also gives the module excellent water resistance and corrosion resistance.

[0033] Furthermore, ultra-clear tempered glass can be used to maximize incident light transmittance. For scenarios requiring lightweight design, thin chemically tempered glass or transparent ceramic plates can be used. Another expansion is the use of self-cleaning glass, with a surface coated with photocatalytic materials or superhydrophobic coatings, which can decompose and remove surface dirt through rainwater washing or ultraviolet irradiation, maintaining high light transmittance over a long period and reducing maintenance costs.

[0034] In some embodiments, reference is made to Figure 2 At least one of the front encapsulation panel 100 and the rear encapsulation panel 900 is coated with an anti-reflective film. Coating the surface of the encapsulation panel with an anti-reflective film effectively reduces Fresnel reflection loss at the air-glass interface, increases the number of photons incident on the cell's active layer, and particularly improves transmittance in the visible to near-infrared band, directly increasing the module's short-circuit current and power output. This optical anti-reflection effect is particularly pronounced when the incident light angle is large, helping to extend the module's effective power generation time and increase average daily power generation.

[0035] Furthermore, the antireflective film can be a multilayer interference film system. By precisely controlling the thickness and refractive index of each layer, excellent antireflection effects can be achieved over a wider spectral range and a broader incident angle range. Nanostructured biomimetic antireflective layers, such as moth-eye structures, can also be used. By forming a subwavelength-sized conical array on the surface to gradient-change the refractive index, ultra-wide spectral and wide-angle antireflection can be achieved. In addition, the antireflective function can be integrated with the aforementioned self-cleaning function into a single coating, achieving multifunctionality.

[0036] In some embodiments, reference is made to Figure 1 Protective films 400 are provided between the front encapsulation plate 100 and the thin-film battery layer 500, between the thin-film battery layer 500 and the crystalline silicon battery layer 700, and between the crystalline silicon battery layer 700 and the rear encapsulation plate 900. The core function of these multiple protective films 400, placed between the battery layers and the encapsulation plate, and between the two battery layers, is to firmly bond each layer into a whole and provide excellent electrical insulation performance, ensuring that there is no leakage or breakdown between the top and bottom batteries. These film layers can buffer the mechanical stress brought about by the lamination process and the external environment, preventing microcracks in the battery cells. The high light transmittance of the films ensures efficient light energy transmission.

[0037] In practical implementation, the protective film 400 can employ a functional gradient design. For example, passivated nanoparticles can be incorporated into the portion near the battery layer to improve interfacial properties, the middle portion ensures high light transmittance and high adhesive strength, and the outer layer emphasizes UV resistance and moisture barrier properties. The use of UV conversion adhesive films can be explored to convert harmful ultraviolet light into visible light useful for the battery, thus protecting the polymer materials and improving light utilization. Another embodiment is to use thermoplastic polyolefin elastomers instead of traditional EVA to achieve faster lamination cycles and better weather resistance.

[0038] In some embodiments, reference is made to Figure 1The protective film 400 between the front encapsulation plate 100 and the thin-film battery layer 500 is set as a UV light-converting adhesive film. The specific use of this UV light-converting adhesive film between the front encapsulation plate 100 and the thin-film battery layer 500 converts high-energy ultraviolet light from the solar spectrum—ultraviolet light that degrades polymer materials and battery interfaces—into visible light through a light conversion mechanism. This process not only reduces UV radiation damage to the encapsulation materials and battery passivation layer, significantly slowing down the aging rate of the module and extending its lifespan, but also transforms previously unusable or harmful ultraviolet light into effective photons that can be absorbed and utilized by the battery, thereby increasing the effective photocurrent of the module and achieving a functional upgrade from protection to gain.

[0039] In practical implementation, UV light-conversion films can be customized to the spectral response of the top-cell film. For example, for perovskite cells, ultraviolet light can be converted into blue-green light near its absorption peak to obtain maximum current gain. The light-conversion material can be an organic rare-earth complex or quantum dots, which are uniformly dispersed in the film matrix.

[0040] In some embodiments, reference is made to Figure 2 The protective film 400 between the thin-film battery layer 500 and the crystalline silicon battery layer 700, and between the crystalline silicon battery layer 700 and the backplate 900, is set as a POE film or a high-transparency EVA film. The use of POE or high-transparency EVA films between the thin-film battery layer 500 and the crystalline silicon battery layer 700, and between the crystalline silicon battery layer 700 and the backplate, primarily utilizes the extremely high volume resistivity of these materials to ensure reliable electrical insulation between the two independent circuit systems, preventing interlayer leakage or short circuits under high voltage. This is the cornerstone of the safe operation of the parallel structure. Their high light transmittance ensures that the bottom crystalline silicon battery can maximize the use of residual light transmitted through the top battery. Because POE films do not contain vinyl acetate, they have better hydrolytic stability and can better suppress PID phenomena, making them particularly suitable for high-efficiency battery structures sensitive to moisture.

[0041] Reference Figure 2 and Figure 3 The second aspect of the present invention provides an embodiment of a manufacturing method for manufacturing the above-described stacked assembly, comprising the following steps: S1: A transparent conductive layer and a thin-film photovoltaic structure are deposited on a glass substrate to form a thin-film battery. The thin-film battery is divided into multiple thin-film sub-cells 550 with consistent section width by laser scribing and then integrated in series to prepare a thin-film battery layer 500. S2: Cut the standard crystalline silicon solar cell into multiple crystalline silicon sub-cells 750, and then arrange the multiple crystalline silicon sub-cells 750 in series with conductive adhesive or solder ribbon to form a crystalline silicon solar cell layer 700. S3: The layers are stacked in the following order: front encapsulation plate 100, first protective film 400, thin film battery layer 500 obtained in step S1, second protective film 400, crystalline silicon battery layer 700 obtained in step S2, third protective film 400, and rear encapsulation plate 900. S4: Vacuum lamination is performed on the stacked components to ensure a strong bond between the layers; S5: Connect the output terminal of the thin-film battery layer 500 of the laminated module in parallel with the output terminal of the crystalline silicon battery layer 700, and connect them to the positive and negative busbars of a single junction box. In steps S1 and S2, the following current matching steps are performed: A1: Based on the area ratio a of the etched region of the thin-film battery layer 500, the spectral response curve of the bottom crystalline silicon battery and the AM1.5 standard spectrum, calculate E, E= a×K1 + (1-a) × K2 + (1-a)× K3; A2: Calculate the expected short-circuit current of the crystalline silicon cell layer 700 according to the formula I = I0 × K(m) × E, where I0 is the current of the complete crystalline silicon cell and K(m) is the area loss factor after slicing. A3: By adjusting the section width of the thin-film sub-cell 550 and the number of slabs m of the crystalline silicon sub-cell 750, the difference between the expected short-circuit current of the crystalline silicon cell layer 700 and the short-circuit current of the thin-film cell layer 500 is controlled within ±5%. in: a represents the area percentage of the 500-line region in the thin-film battery layer; K1 is the relative current coefficient of the crystalline silicon cell layer 700 in the etched area of ​​the thin-film cell layer 500; K2 is the relative current coefficient of the crystalline silicon cell layer 700 in the light transmission band (λg to 1200nm) of the thin film cell layer 500, and its value is determined based on the AM1.5 spectrum and the spectral response curve of the crystalline silicon cell layer 700. K3 is the relative current coefficient of the crystalline silicon cell layer 700 in the remaining short-wavelength band (300nm to λg) that is not fully absorbed by the thin-film cell layer 500. Its value is determined by the quantum efficiency curve of the thin-film cell layer 500 and the transmittance of its transparent electrode.

[0042] By performing precise optical and electrical calculations before cell layer fabrication and stacking, a quantitative current matching design process based on physical models can be deeply integrated into specific manufacturing steps. This transforms the traditional trial-and-error cycle of fabrication, testing, and adjustment into a highly efficient model of model prediction and precision manufacturing. This pre-design capability ensures a high degree of current matching between thin-film and crystalline silicon cell branches when connected in parallel, significantly reducing internal energy loss and potential hot spot risks caused by current mismatch from the manufacturing source, and greatly improving product reliability, performance consistency, and yield. Therefore, it effectively makes the manufacturing process no longer blind, but a scientifically guided, predictable, and highly controllable intelligent production.

[0043] In some embodiments, reference is made to Figure 2 and Figure 3 The thin-film battery layer 500 is a cadmium telluride (CdTe) thin-film battery with an absorption edge λg of 855 nm, while the crystalline silicon battery layer 700 is a heterojunction battery with K2=0.353 and K3=0.207. For this specific combination of CdTe thin film and heterojunction crystalline silicon, a unique, experimentally verified optical coefficient of K2=0.353 and K3=0.207 was applied, enabling extremely high precision and targeting in the current matching design. This precisely guides the thinning process and laser scribing scheme of the CdTe absorber layer, optimizing the utilization of the high voltage and good low-light performance of CdTe cells and the low temperature coefficient and high bifaciality of heterojunction cells. This quantitative manufacturing guidance ensures that the stacked modules manufactured using this mature technology combination achieve theoretically maximum spectral complementarity, obtaining stable and efficient power output, while inheriting the inherent high reliability and long lifespan advantages of both technologies.

[0044] When implementing this manufacturing method, subsequent processing steps for the CdTe thin film can be specifically optimized. For example, the temperature and time window of the CdCl2 annealing activation process can be precisely controlled to achieve grain growth while avoiding adverse effects on the already precisely controlled film thickness and interface properties. For heterojunction bottom cells, sputtering process parameters can be optimized in the transparent conductive oxide (TCO) deposition process to obtain higher near-infrared transmittance and better lateral conductivity, which helps to further improve the current collection efficiency under specific spectra after CdTe filtering. The use of encapsulating films with specific refractive indices between CdTe and HJT can also be explored to minimize interfacial optical losses.

[0045] In some embodiments, reference is made to Figure 2 and Figure 3The thin-film battery layer 500 is configured as a perovskite thin-film battery with an absorption edge λg of 780 nm, while the crystalline silicon battery layer 700 is a heterojunction battery with K2=0.441 and K3=0.224. For this combination of perovskite and heterojunction, experimentally verified optical coefficients K2=0.441 and K3=0.224 are used to provide a precise process roadmap for manufacturing tandem modules with extremely high efficiency potential. This roadmap accurately guides the composition engineering and nanoscale thickness control of the perovskite layer, ensuring its high efficiency while transmitting optimal near-infrared light to the bottom heterojunction battery. This physical model-based design, manufacturing, and integration approach effectively overcomes the challenges of perovskite materials, such as their narrow processing window and performance sensitivity to preparation parameters. Through quantitative control, the material advantages are transformed into stable and repeatable product performance, laying a solid technological foundation for the mass production of next-generation ultra-high-efficiency photovoltaic products.

[0046] During the wet coating or vacuum deposition process of the perovskite layer, an in-situ optical monitoring system can be integrated to monitor the film quality and optical constants in real time, ensuring that they remain consistent with the quantum efficiency curve on which the K3 parameter set in the model depends.

[0047] In some embodiments, in the parallel connection of step S5, if the calculated difference between the currents of the two branches is greater than 2.5%, a low-dropout Schottky anti-reverse current diode is connected in series at the positive output terminal of the thin-film battery layer 500. By identifying a small but not entirely ideal current difference greater than 2.5% in the current matching calculation, the Schottky anti-reverse current diode is forcibly integrated into the thin-film battery branch, adding extra safety assurance for the long-term stable operation of the module under complex and variable real-world conditions. The diode can effectively prevent reverse current from the crystalline silicon branch with a larger current to the thin-film branch that may occur under specific transient conditions such as local shading or spectral changes caused by rapid cloud cover, avoiding power consumption, heat generation, and performance degradation of the thin-film battery under such abnormal conditions, thereby improving the resilience and lifespan of the entire module system.

[0048] Furthermore, Schottky diodes can be integrally molded with busbars, or integrated onto a miniaturized printed circuit board using surface mount technology, and then soldered to the battery string leads, improving integration and reliability. Simple diodes can also be replaced with self-resetting intelligent switching devices that monitor inter-branch voltage differences and only disconnect the circuit when conditions that may cause harmful circulating currents are detected, while remaining conductive during normal operation to reduce path losses. Additionally, mounting positions and heat dissipation designs for the diode can be pre-defined within the junction box, allowing for manufacturing flexibility by determining whether to install it based on the final tested current difference.

[0049] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0050] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A stacked assembly, characterized in that, include: The thin-film battery layer (500) includes a plurality of thin-film sub-cells (550), each of the thin-film sub-cells (550) being connected in series to form the thin-film battery layer (500), and the thin-film battery layer (500) having a short-circuit current I1, a total output voltage V1, and a first electrode lead. A crystalline silicon solar cell layer (700) includes multiple crystalline silicon sub-cells (750), each of which is connected in series to form the crystalline silicon solar cell layer (700). The crystalline silicon solar cell layer (700) has a short-circuit current I2, a total output voltage V2, and a second electrode lead. 0.975I2≤I1≤1.025I2, 0.95V2≤V1≤1.05V2; The first electrode lead and the second electrode lead are connected in parallel to a common positive busbar and a negative busbar, respectively, and the electrodes are matched with each other.

2. The stacked assembly as claimed in claim 1, characterized in that: It also includes a front encapsulation plate (100) and a rear encapsulation plate (900), wherein the thin-film battery layer (500) and the crystalline silicon battery layer (700) are both located between the front encapsulation plate (100) and the rear encapsulation plate (900), and the front encapsulation plate (100) and the rear encapsulation plate (900) can cooperate to shield and encapsulate the thin-film battery layer (500) and the crystalline silicon battery layer (700).

3. The stacked assembly as described in claim 2, characterized in that: At least one of the front encapsulation plate (100) and the rear encapsulation plate (900) is made of semi-tempered / tempered glass, and the thickness of the front encapsulation plate (100) and the rear encapsulation plate (900) is both set to 2mm-6mm.

4. The stacked assembly as claimed in claim 2, characterized in that: At least one of the front encapsulation plate (100) and the rear encapsulation plate (900) is coated with an anti-reflective film.

5. The stacked assembly as claimed in claim 2, characterized in that: A protective film (400) is provided between the front encapsulation plate (100) and the thin film battery layer (500), between the thin film battery layer (500) and the crystalline silicon battery layer (700), and between the crystalline silicon battery layer (700) and the rear encapsulation plate (900).

6. The stacked assembly as claimed in claim 5, characterized in that: Protective films (400) are provided between the front encapsulation plate (100) and the thin-film battery layer (500), between the thin-film battery layer (500) and the crystalline silicon battery layer (700), and between the crystalline silicon battery layer (700) and the rear encapsulation plate (900). The protective film (400) between the front encapsulation plate (100) and the thin-film battery layer (500) is configured as a UV light-converting adhesive film.

7. A manufacturing method for manufacturing a laminated assembly as described in any one of claims 1-6, characterized in that, Includes the following steps: S1: A transparent conductive layer and a thin-film photovoltaic structure are deposited on a glass substrate to form a thin-film battery. The thin-film battery is divided into multiple thin-film sub-cells (550) with consistent segment width by laser scribing and then integrated in series to form a thin-film battery layer (500). S2: Cut a standard crystalline silicon cell into multiple crystalline silicon sub-cells (750), and then arrange the multiple crystalline silicon sub-cells (750) in series with conductive adhesive or solder ribbon to form a crystalline silicon cell layer (700). S3: The layers are stacked in the following order: front encapsulation plate (100), first protective film (400), thin film battery layer (500) obtained in step S1, second protective film (400), crystalline silicon battery layer (700) obtained in step S2, third protective film (400), and rear encapsulation plate (900). S4: Vacuum lamination is performed on the stacked components to ensure a strong bond between the layers; S5: Connect the output terminal of the thin-film battery layer (500) of the laminated module in parallel with the output terminal of the crystalline silicon battery layer (700), and connect them to the positive and negative busbars of a single junction box; In steps S1 and S2, the following current matching steps are performed: A1: Based on the area ratio a of the etched region of the thin-film battery layer (500), the spectral response curve of the bottom crystalline silicon battery and the AM1.5 standard spectrum, calculate E, E= a×K1 + (1-a) × K2 + (1-a)× K3; A2: Calculate the expected short-circuit current of the crystalline silicon cell layer (700) according to the formula I = I0 × K(m) × E, where I0 is the current of the complete crystalline silicon cell and K(m) is the area loss factor after slicing. A3: By adjusting the section width of the thin-film sub-cell (550) and the number of slabs m of the crystalline silicon sub-cell (750), the difference between the expected short-circuit current of the crystalline silicon cell layer (700) and the short-circuit current of the thin-film cell layer (500) is controlled within ±5%. in: a represents the area percentage of the (500) etched region in the thin-film battery layer; K1 is the relative current coefficient of the crystalline silicon cell layer (700) under the scribed region of the thin-film cell layer (500); K2 is the relative current coefficient of the crystalline silicon cell layer (700) in the light transmission band (λg to 1200nm) of the thin film cell layer (500), and its value is determined based on the AM1.5 spectrum and the spectral response curve of the crystalline silicon cell layer (700). K3 is the relative current coefficient of the remaining short-wavelength band (300nm to λg) of the crystalline silicon cell layer (700) that is not fully absorbed by the thin-film cell layer (500). Its value is determined by the quantum efficiency curve of the thin-film cell layer (500) and the transmittance of its transparent electrode.

8. The manufacturing method as described in claim 7, characterized in that: The thin-film battery layer (500) is configured as a cadmium telluride thin-film battery with an absorption edge λg of 855 nm. The crystalline silicon battery layer (700) is a heterojunction battery with K2=0.353 and K3=0.

207.

9. The manufacturing method as described in claim 7, characterized in that: The thin-film battery layer (500) is configured as a perovskite thin-film battery with an absorption edge λg of 780 nm, and the crystalline silicon battery layer (700) is a heterojunction battery with K2=0.441 and K3=0.

224.

10. The manufacturing method as described in claim 7, characterized in that: In the parallel connection of step S5, if the difference between the calculated currents of the two branches is greater than 2.5%, a low-dropout Schottky anti-reverse current diode is connected in series at the positive output terminal of the thin-film battery layer (500).

Images