Preparation method of semiconductor structure and semiconductor device

Abstract

The invention provides a semiconductor structure and a preparation method of a semiconductor device, and belongs to the field of semiconductors. The method comprises the following steps: firstly, forming a pre-etched wide groove and a pre-etched narrow groove which are different in depth, then filling the grooves with barrier layers, and converting the depth difference of the pre-etched wide groove and the pre-etched narrow groove into the thickness difference of the barrier layers. Due to the fact that the thickness difference exists in the barrier layer, when the barrier layer in the pre-etching narrow groove is removed, a part of the barrier layer in the pre-etching wide groove is reserved, the reserved part of the barrier layer protects the pre-etching wide groove, and when the pre-etching narrow groove is deepened, the depth of the pre-etching wide groove does not change. And after the depth of the pre-etched narrow groove is deepened to a certain degree, removing the barrier layer filled in the pre-etched wide groove, and synchronously etching the pre-etched wide groove and the pre-etched narrow groove to a target depth to obtain a narrow deep groove and a wide shallow groove. The method can save the use frequency of the photomask.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more particularly to a method for fabricating a semiconductor structure and a semiconductor device. Background Technology

[0002] Back-illuminated CMOS (BSI) image sensors are widely used in consumer electronics, automotive electronics, medical and scientific imaging, security monitoring, and professional imaging technologies due to their high sensitivity and low noise characteristics.

[0003] In the manufacturing process of back-illuminated image sensors (BSI), forming narrow and deep trenches and wide and shallow trenches are two key structures. They each perform important, interrelated but different functions, and together improve the sensor's performance (mainly photosensitivity and crosstalk suppression).

[0004] The primary purpose of narrow, deep trenches is to suppress optical crosstalk. When light enters a silicon substrate from the back, not all photons enter their target pixel's photodiode (PD) perpendicularly. Photons may be scattered or refracted within the silicon, entering obliquely into the regions of adjacent pixels. Narrow, deep trenches (typically filled with a high-refractive-index medium or metal) act as a physical barrier, absorbing or reflecting these "lost" photons and preventing them from entering the photosensitive areas of neighboring pixels, thus significantly reducing optical crosstalk between pixels. This directly improves image quality, particularly color purity and signal-to-noise ratio in low light. Deep trenches also enhance electrical isolation between pixels to some extent, helping to reduce leakage current spreading from one pixel to another (electrical crosstalk).

[0005] The wide, shallow trenches primarily serve to house the metal interconnect layers. In a BSI (Block Component Interconnect) structure, the metal wiring layer used to connect the transistors within a pixel (transmission gate TX, reset transistor RST, source follower SF, row select transistor RS, etc.) and the readout circuitry is located on the front side of the silicon wafer (i.e., the side opposite to the photosensitive surface). These wide, shallow trenches (often called front-end interconnect trenches or wiring trenches) are etched into the front side of the silicon to deposit metal wires (such as copper), enabling electrical connections within the pixel unit and from the pixel to peripheral circuitry.

[0006] Currently, simultaneously fabricating narrow and deep trenches and wide and shallow trenches typically requires two photomasks (two photolithography processes), which not only increases production costs but also complicates the process and extends the production cycle. Its high manufacturing cost may limit the popularity and application of back-illuminated image sensors in the market. Summary of the Invention

[0007] In view of this, on the one hand, this application provides a method for fabricating a semiconductor structure, aiming to simultaneously fabricate narrow deep trenches and wide shallow trenches using only a single photomask. On the other hand, this application provides a method for fabricating a semiconductor device using the above-described semiconductor structure fabrication method, aiming to fabricate semiconductor devices at low cost.

[0008] In a first aspect, this application provides a method for fabricating a semiconductor structure, comprising: A substrate is provided, and a buffer layer and a hard mask are sequentially formed on the substrate; The hard mask and buffer layer are patterned to form pre-etched narrow trenches and pre-etched wide trenches within the hard mask and buffer layer; the bottom of the pre-etched wide trenches extends to the substrate surface, and the bottom of the pre-etched narrow trenches remains within the buffer layer. A barrier layer is formed within the pre-etched narrow trench and the pre-etched wide trench; The barrier layer and hard mask located above the surface of the buffer layer are removed by planarization or thinning processes. The barrier layer in the pre-etched narrow trench is removed by etching process, and at least a portion of the barrier layer thickness is retained in the pre-etched wide trench; The buffer layer is etched using a selective etching process until the bottom of the pre-etched narrow trench is pushed to the substrate surface. By selecting the etching ratio, a portion of the barrier layer is retained in the pre-etched wide trench. Using the remaining buffer and barrier layers as a mask, the substrate at the bottom of the pre-etched narrow trench is etched until the target depth is reached; The barrier layer in the pre-etched wide trench is removed, and the remaining buffer layer is used as a mask to etch the substrate, resulting in both wide shallow trenches and narrow deep trenches.

[0009] Optionally, the step of patterning the hard mask and buffer layer to form pre-etched narrow trenches and pre-etched wide trenches on the hard mask and buffer layer includes: A patterned photoresist layer is formed on the surface of a hard mask, wherein a large first etching window and a small second etching window are formed in the patterned photoresist layer; Utilizing the etching load effect, a hard mask is etched through a first etching window and a second etching window to form a pre-etched wide trench and a pre-etched narrow trench in the hard mask; the depth of the pre-etched wide trench is greater than that of the pre-etched narrow trench. Using a first selectivity etching process, the pre-etched middle wide trench and the pre-etched middle narrow trench are deepened, thereby obtaining the pre-etched wide trench and the pre-etched narrow trench located in the hard mask and the buffer layer.

[0010] Optionally, by utilizing the etching load effect, when etching a hard mask through a first etching window and a second etching window, the etching rate at the first etching window is higher than the etching rate at the second etching window.

[0011] Optionally, when using a first selectivity etching process to deepen the pre-etched middle wide trench and the pre-etched middle narrow trench, the etching rate of the buffer layer is higher than the etching rate of the hard mask.

[0012] Optionally, the buffer layer is made of a different material than the rigid mask.

[0013] Optionally, the buffer layer is made of a different material than the barrier layer.

[0014] Optionally, the buffer layer may be made of materials including SiN and SiO. x Any one of TiN.

[0015] Optionally, the material used for the hard mask includes SiO2. x Any one of TiN and Al2O3.

[0016] Optionally, the barrier layer may be made of a material including SiO2. x Any one of TiN and Al2O3.

[0017] Optionally, the process used to remove the barrier layer in the pre-etched narrow trench includes a wet etching process.

[0018] Optionally, the buffer layer is etched using a selective etching process until the bottom of the pre-etched narrow trench is pushed to the substrate surface. The step of retaining a portion of the barrier layer in the pre-etched wide trench by selecting the etching ratio includes: A second selectivity etching process is used to etch the buffer layer at the bottom of the pre-etched narrow trench by adjusting the selectivity ratio of the buffer layer and the barrier layer; so that after etching, the bottom of the pre-etched narrow trench is exposed to the substrate, while a barrier layer of a certain thickness is still retained in the pre-etched wide trench.

[0019] Optionally, when using the second selective etching process, the etching rate of the buffer layer is higher than that of the barrier layer.

[0020] Secondly, this application provides a method for fabricating a semiconductor device, the method comprising the method for fabricating a semiconductor structure as described in any of the preceding claims.

[0021] The unexpected technical effects of the technical solution provided in this application include: This application provides a method for fabricating a semiconductor structure, the purpose of which is to fabricate wide-shallow trenches and narrow-deep trenches using only a single photomask. An unexpected technical advantage is that this application first forms pre-etched wide trenches and pre-etched narrow trenches of different depths, and then fills the trenches with a barrier layer. The difference in depth between the pre-etched wide trenches and pre-etched narrow trenches translates into a difference in the thickness of the barrier layer filling them. Due to the thickness difference of the barrier layer, when the barrier layer in the pre-etched narrow trench is removed, the barrier layer in the pre-etched wide trench is not completely removed, but a portion remains, and this retained portion protects the pre-etched wide trench. Thus, when the depth of the pre-etched narrow trench is increased, the depth of the pre-etched wide trench remains unchanged because it is filled with a barrier layer. Once the depth of the pre-etched narrow trench is increased to a certain extent, the blocking layer filling the pre-etched wide trench is removed. Then, the pre-etched wide trench and the pre-etched narrow trench are simultaneously etched to the target depth, resulting in a deep narrow trench and a shallow wide trench. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application. Figure 2 A flowchart illustrating the preparation method of pre-etched wide trenches and pre-etched narrow trenches according to an embodiment of this application; Figure 3 A schematic diagram of the prepared buffer layer and hard mask provided in an embodiment of this application; Figure 4 A schematic diagram of a patterned photoresist layer prepared according to an embodiment of this application; Figure 5 This is a schematic diagram of a pre-etched wide trench and a pre-etched narrow trench prepared according to an embodiment of this application; Figure 6 This is a schematic diagram of a pre-etched wide trench and a pre-etched narrow trench prepared according to an embodiment of this application; Figure 7 This is a schematic diagram of the barrier layer prepared according to an embodiment of this application; Figure 8 This is a schematic diagram of a polished barrier layer provided in an embodiment of this application; Figure 9 This is a schematic diagram of the process after removing the barrier layer in the pre-etched narrow trench, according to an embodiment of this application. Figure 10 This is a schematic diagram showing the result of performing a second selective ratio etching process according to an embodiment of this application; Figure 11 This is a schematic diagram of a pre-etched narrow trench provided in an embodiment of this application; Figure 12 This is a schematic diagram of the process after removing the barrier layer in a pre-etched wide trench, according to an embodiment of this application. Figure 13 This is a schematic diagram of a wide shallow trench and a narrow deep trench prepared according to an embodiment of this application.

[0024] The attached figures are labeled as follows: 1: Substrate; 11: Wide shallow trench; 12: Narrow deep trench; 2: Buffer layer; 21: Pre-etched wide trench; 22: Pre-etched narrow trench; 3: Hard mask; 31: Pre-etched middle wide trench; 32: Pre-etched middle narrow trench; 4: Photoresist layer; 41: First etching window; 42: Second etching window; 5: Barrier layer. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0026] Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application. See also... Figure 1 ,include: S101. Provide a substrate, and sequentially form a buffer layer and a hard mask on the substrate.

[0027] S102. The hard mask and the buffer layer are patterned to form pre-etched narrow trenches and pre-etched wide trenches within the hard mask and the buffer layer; the bottom of the pre-etched wide trenches extends to the substrate surface, and the bottom of the pre-etched narrow trenches remains within the buffer layer.

[0028] S103, forming a barrier layer within the pre-etched narrow trench and the pre-etched wide trench.

[0029] S104. Use planarization or thinning processes to remove the barrier layer and hard mask located above the surface of the buffer layer.

[0030] S105. Use an etching process to remove the barrier layer in the pre-etched narrow trench, and retain at least a portion of the barrier layer thickness in the pre-etched wide trench.

[0031] S106. The buffer layer is etched using a selective etching process until the bottom of the pre-etched narrow trench is pushed to the substrate surface. By selecting the etching ratio, a portion of the barrier layer is retained in the pre-etched wide trench.

[0032] S107. Using the remaining buffer layer and barrier layer as a mask, etch the substrate at the bottom of the pre-etched narrow trench until the target depth is reached.

[0033] S108. Remove the barrier layer in the pre-etched wide trench, and use the remaining buffer layer as a mask to etch the substrate, thereby obtaining both wide shallow trenches and narrow deep trenches.

[0034] This application provides a method for fabricating a semiconductor structure, the purpose of which is to fabricate wide-shallow trenches and narrow-deep trenches using only a single photomask. An unexpected technical advantage is that this application first forms pre-etched wide trenches and pre-etched narrow trenches of different depths, and then fills the trenches with a barrier layer. The difference in depth between the pre-etched wide trenches and pre-etched narrow trenches translates into a difference in the thickness of the barrier layers filling them. Due to the thickness difference of the barrier layers, when the barrier layer in the pre-etched narrow trench is removed, the barrier layer in the pre-etched wide trench is not completely removed, but a portion remains, and this retained portion of the barrier layer protects the pre-etched wide trench. Thus, when the depth of the pre-etched narrow trench is increased, the depth of the pre-etched wide trench remains unchanged because it is filled with a barrier layer. Once the depth of the pre-etched narrow trench is increased to a certain extent, the blocking layer filling the pre-etched wide trench is removed. Then, the pre-etched wide trench and the pre-etched narrow trench are simultaneously etched to the target depth, resulting in a deep narrow trench and a shallow wide trench.

[0035] In some examples, step S101 includes: S1011. Provide a substrate 1 and form a buffer layer 2 on the surface of the substrate.

[0036] In some examples, substrate 1 may be a semiconductor substrate, such as a single-element semiconductor substrate, a compound semiconductor substrate, and / or an alloy semiconductor substrate. Single-element semiconductor substrates may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Compound semiconductor substrates may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor substrates may include, but are not limited to, germanium silicon (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium arsenide phosphide (GaInAsP).

[0037] In some embodiments, substrate 1 is a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.

[0038] For example, substrate 1 in this application is a silicon (Si) substrate.

[0039] In some examples, buffer layer 2 includes a SiN layer and a SiO layer. x Either the TiN layer or the TiN layer.

[0040] As some examples provided in this application, the buffer layer 2 can be prepared using any one of the following processes: Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Atomic Layer Deposition (ALD), High-Density Plasma Chemical Vapor Deposition (HDP-CVD).

[0041] In some examples, if the buffer layer 2 is a SiN layer, it can be prepared by low-pressure chemical vapor deposition (LPCVD).

[0042] In some examples, SiO x In the layer, x represents the ratio of element Si to element O.

[0043] In some examples, SiO x In the layer, x can be 1 or 2. If x is 1, then SiO x The layer represents a SiO layer. If x is 2, then SiO x The layer represents a SiO2 layer.

[0044] S1012. A hard mask 3 is formed on the surface of the buffer layer 2.

[0045] In some examples, the rigid mask 3 is made of a different material than the buffer layer 2.

[0046] It should be noted that the hard mask 3 and the buffer layer 2 are made of different materials. The purpose is to utilize the different etching selectivity of the materials, which will facilitate the subsequent etching of trenches using the selectivity etching process.

[0047] In some examples, the hard mask is made of materials including SiO2. x Any one of TiN and Al2O3.

[0048] In some examples, the hard mask 3 includes SiO2. x The layer, x, represents the ratio of Si to O. If x is 2, the hard mask includes a SiO2 layer. If x is 1, the hard mask includes a SiO layer.

[0049] As some examples provided in this application, the hard mask 3 can be prepared using any one of the following processes: Low Pressure Chemical Vapor Deposition (LPCVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Atomic Layer Deposition (ALD), High-Density Plasma Chemical Vapor Deposition (HDP-CVD), etc.

[0050] See Figure 3 Specifically, a buffer layer 2 and a hard mask 3 are sequentially formed on a substrate 1.

[0051] In this application, the core objective of step S102 is to form pre-etched narrow trenches 22 and pre-etched wide trenches 21 with different depths in the hard mask 3 and buffer layer 2 by etching the hard mask 3 and buffer layer 2. Furthermore, the depth of the pre-etched wide trenches 21 must be greater than that of the pre-etched narrow trenches 22.

[0052] The depth difference between the pre-etched wide trench 21 and the pre-etched narrow trench 22 is beneficial to control the thickness of the barrier layer 5 formed in the pre-etched narrow trench 22 to be lower than the thickness of the barrier layer 5 formed in the pre-etched wide trench 21 when the barrier layer 5 is formed in the pre-etched wide trench 21 and the pre-etched narrow trench 22. This allows the depth difference between the pre-etched wide trench 21 and the pre-etched narrow trench 22 to be converted into the thickness difference of the barrier layer 5.

[0053] When the thickness of the barrier layer 5 formed in the pre-etched wide trench 21 is greater than the thickness of the barrier layer 5 in the pre-etched narrow trench 22, when the barrier layers 5 in the pre-etched wide trench 21 and the pre-etched narrow trench 22 are etched simultaneously, a barrier layer 5 of a certain thickness can still be maintained in the pre-etched wide trench 21 after the barrier layer 5 in the pre-etched narrow trench 22 is completely removed.

[0054] The barrier layer 5 retained in the pre-etched wide trench 21 can protect the pre-etched wide trench 21 when the depth of the pre-etched narrow trench 22 is increased, so that the depth of the pre-etched wide trench 21 does not change. As a result, the originally shallow pre-etched narrow trench 22 is transformed into a deeper narrow deep trench 12, and the originally deep pre-etched wide trench 21 is transformed into a shallow wide shallow trench 11.

[0055] It should be noted that "deeper" does not refer to a specific numerical range, but rather to the greater depth of the two. For example, "deeper pre-etched wide trench 21" means that, compared to "deeped narrow trench 22," the pre-etched wide trench 21 is deeper. The same logic applies to "shallower depth," which will not be elaborated upon here.

[0056] Additionally, it should be noted that the pre-etched wide trench 21 needs to be etched to the surface of the substrate 1. This is because the pre-etched wide trench 21 will subsequently be filled with a barrier layer 5. If the pre-etched wide trench 21 is not etched to the surface of the substrate 1, that is, if the bottom of the pre-etched wide trench 21 is a buffer layer 2, the process difficulty will increase when removing the barrier layer 5 in the pre-etched wide trench 21 and using the buffer layer as a mask to etch and transform the pre-etched wide trench 21 into a wide and shallow trench 11.

[0057] During this transformation process, if the bottom of the pre-etched wide trench 21 does not expose the substrate 1, the buffer layer 2 needs to be etched until the bottom of the pre-etched wide trench 21 is etched to the surface of the substrate 1, and then the substrate 1 can be etched to form the wide shallow trench 11.

[0058] However, due to the multiple etching processes prior to the formation of the wide and shallow trench 11, the thickness of the buffer layer 2 has been reduced to a relatively small thickness. If the buffer layer 2 is etched again to etch the pre-etched wide trench 21 to the surface of the substrate 1, the difficulty of the etching process will increase dramatically. It is necessary to ensure that the bottom of the pre-etched wide trench 21 can be etched to the surface of the substrate 1, and also to ensure that a portion of the thickness of the buffer layer 2 is still retained on the surface of the substrate 1 as a mask for the subsequent etching process (the process of etching to form the wide and shallow trench 11). This requires extremely high process precision and is very difficult to fabricate.

[0059] Therefore, by etching the pre-etched wide trench 21 to the surface of the substrate 1 from the beginning, due to the etching load effect, the etching rate at the pre-etched wide trench 21 will inevitably be greater than the etching rate at the pre-etched narrow trench 22. Furthermore, by reasonably calculating the etching time, the depth difference between the pre-etched wide trench 21 and the pre-etched narrow trench 22 can be effectively controlled, and the pre-etched wide trench 21 can be etched to the surface of the substrate 1. The process difficulty is relatively low; it can be achieved simply by reasonably controlling the thickness of the hard mask 3 and the buffer layer 2 from the beginning, and by controlling the etching time of the hard mask 3 and the buffer layer 2.

[0060] See Figure 2 In some examples, step S102 includes: S1021. A patterned photoresist layer 4 is formed on the surface of the hard mask 3, wherein a large-sized first etching window 41 and a small-sized second etching window 42 are formed in the patterned photoresist layer 4.

[0061] In some examples, step S1021 includes: Photoresist is coated on the surface of the hard mask 3 to form a photoresist layer. The photoresist layer is then subjected to exposure, development and other steps to pattern the photoresist layer, thereby obtaining a photoresist layer 4 with a first etching window 41 and a second etching window 42.

[0062] In some examples, the process for forming the patterned photoresist layer can be a photolithography process.

[0063] It should be noted that the large-size first etching window and the small-size second etching window refer to the fact that the size of the first etching window is larger than the size of the second etching window, and the window size can be the horizontal area of ​​the window. Figure 4 (The width of the window is displayed in the text).

[0064] It should be noted that the purpose of forming the first etching window and the second etching window in step S1021 is to utilize the size difference of the etching windows, combined with the etching load effect, to make the etching rates at the first etching window and the second etching window different. As a result, the depths of the pre-etched wide trench and the pre-etched narrow trench formed by etching through the first etching window and the second etching window will be different. This is the result of the different etching rates.

[0065] See Figure 4 The structure of the patterned photoresist layer 4 prepared in this application is shown.

[0066] S1022. Utilizing the etching load effect, the hard mask 3 is etched through the first etching window 41 and the second etching window 42 to form a pre-etched middle wide trench 31 and a pre-etched middle narrow trench 32 in the hard mask 3; the depth of the pre-etched middle wide trench 31 is deeper than that of the pre-etched middle narrow trench 32.

[0067] In some examples, step S1022 includes: The hard mask 3 is etched by utilizing the etching load effect through the first etching window 41 and the second etching window 42, wherein the etching rate at the first etching window 41 is higher than the etching rate at the second etching window 42.

[0068] In some examples, the etching process used when etching the hard mask 3 can be a dry etching process.

[0069] By utilizing the etching load effect to etch windows of different sizes at different rates, the depths of the pre-etched middle wide trench 31 and the pre-etched middle narrow trench 32 obtained in the same etching process of the first etching window 41 and the second etching window 42 are different.

[0070] In some examples, the etching depth at the first etching window 41 can be etched to the surface of the buffer layer 2, and the etching depth at the second etching window 42 can be etched into the hard mask 3 (but not to the surface of the buffer layer 2).

[0071] In other examples, the etching depth at the first etching window 41 can be etched into the interior of the hard mask 3, the etching depth at the second etching window 42 can be etched into the interior of the hard mask 3, and the etching depth at the first etching window 41 is greater than the etching depth at the second etching window 42.

[0072] For this application, it is only necessary to ensure that the etching depth at the first etching window 41 is greater than the etching depth at the second etching window 42. The specific location of the first etching window 41 and the second etching window 42 within the hard mask 3 is not limited by this application.

[0073] It should be noted that the etching load effect refers to the phenomenon that the etching rate varies with the density and size of the pattern to be processed. In this application, the size of the etching window is used to create the etching load effect, thereby forming trenches of different depths.

[0074] The etch load effect can be altered by adjusting the process parameters (pressure, power, gas) of the dry etching process and improving the chamber hardware design (focusing ring, ESC, spray head).

[0075] Step S1022 primarily utilizes a first etching window with a defined large opening (large CD, where CD is the bottom size) and a second etching window with a small opening (small CD, where CD is the bottom size). The core principle is that in plasma etching (RIE), the etching rate of the small opening (high aspect ratio) region is significantly lower than that of the large opening (low aspect ratio) region. This difference in etching rate is specifically due to factors such as limited reactant diffusion, difficulty in product removal, reduced ion flux, and enhanced passivation layer effect. The aim is to create a suppressive effect in the high aspect ratio (small opening) region, making its etching rate lower than that of the low aspect ratio (large opening) region.

[0076] As some more specific implementations provided in this application, the etching load effect can be achieved using the following process parameters: The gas used in dry etching is CF4 / CF. 3（ The gas flow rate ratio is approximately 8:2, and the He mixed gas is used. The C / F ratio is optimized to control polymer generation and removal.

[0077] Small opening region: In the small opening, due to the low ion flux and the difficulty in removing reaction products (including polymer precursors), the bottom polymer passivation layer is more likely to accumulate and become thicker, thus significantly inhibiting etching.

[0078] Large opening area: Strong ion bombardment can effectively remove the polymer at the bottom, allowing etching to continue.

[0079] By reducing the F / C ratio (i.e., increasing the proportion of C or reducing the addition of O2), polymer formation can be enhanced, thereby exacerbating the etching loading effect.

[0080] The pressure used in dry etching is relatively high, 50 mTorr~80 mTorr (approximately 6.5~10.6 Pa).

[0081] Under high pressure, the mean free path of ions shortens, collisions increase, and ion directionality deteriorates. This makes it more difficult for ions to be perpendicularly incident to the bottom of the small opening, while the large opening region is relatively less affected. At the same time, high pressure helps to enhance chemical reactions (high concentration of free radicals), but it also exacerbates the diffusion restriction of reactants within the small opening and the difficulty of product removal, thereby inhibiting the etching of the small opening.

[0082] Dry etching reaction temperature: Lowering the reaction temperature, typically 50℃, to 30~40℃ is beneficial for CF. x Polymer (CF) x The adhesion and deposition of element C to element F on the wafer surface further enhances the passivation effect within the small opening and inhibits its etching.

[0083] The power used in dry etching is as follows: source power of 400W~600W to generate high-density plasma. Bias power of 100W~200W to control the ion bombardment energy.

[0084] Low bias power implies lower ion bombardment energy. In small openings, ion energy is inherently weakened, making it more difficult to effectively bombard and remove the bottom passivation layer (such as CF2) at low energies. x The polymer undergoes physical sputtering, causing etching to stop. However, in the large opening region, ion energy decays less, allowing etching to continue. This enhances the loading effect of the ion-driven etching mechanism.

[0085] See Figure 5 The two pre-etched intermediate wide trenches 31 and pre-etched intermediate narrow trenches 32 are prepared by step S1022 in this application. The bottom of the pre-etched intermediate wide trench 31 exposes the buffer layer 2, while the bottom of the pre-etched intermediate narrow trench 32 remains inside the hard mask 3, that is, the pre-etched intermediate narrow trench 32 does not penetrate the hard mask 3.

[0086] S1023. Using a first selective ratio etching process, the pre-etched middle wide trench 31 and the pre-etched middle narrow trench 32 are deepened, thereby obtaining the pre-etched wide trench 21 and the pre-etched narrow trench 22 located in the hard mask 3 and the buffer layer 2.

[0087] In some examples, when using a first selectivity etching process to deepen the pre-etched intermediate wide trench 31 and the pre-etched intermediate narrow trench 32, the etching rate of the buffer layer 2 is higher than the etching rate of the hard mask 3.

[0088] In some examples, when using a first selective ratio etching process to deepen the pre-etched intermediate wide trench 31 and the pre-etched intermediate narrow trench 32, the ratio of the etching rate of the buffer layer 2 to the etching rate of the hard mask 3 is greater than 10:1.

[0089] In some examples, the first choice etching process can be a dry etching process.

[0090] The core principle of the first selective etching process is to use fluorine-based chemistry and precisely control the process conditions to form a robust, carbon-rich fluorocarbon polymer passivation layer on the surface of a hard mask, thereby greatly inhibiting the etching of the hard mask. At the same time, by using physical bombardment or specific chemical composition ratios, this passivation layer is broken or cannot be stably formed on the surface of the buffer layer, thereby achieving highly selective etching.

[0091] Adjust the buffer layer (e.g., using SiN) and the hard mask (e.g., using SiO2). x In terms of etch selectivity, under similar process conditions (same chemical gases, power, pressure, etc.), SiN typically has a much faster etch rate than SiO2. Currently, processes can be optimized to achieve high SiN:SiO2 selectivity (e.g., 10:1, 20:1, or even higher), thereby pushing the bottom of wide, shallow trenches to the substrate surface through dry etching of a hard mask (e.g., using SiN), while the bottom of narrow, deep trenches is located on a hard mask (e.g., using SiO2). x Under high selectivity etching conditions, the bottom of the narrow, deep trench is controlled to stop at a certain depth from the upper surface of the buffer layer (such as SiN).

[0092] In some examples, the specific implementation process of the first-choice etching process is as follows: Gas composition is the most critical factor determining selectivity. Fluorine source gases such as CF4, CHF3, C4F8, and SF6, as well as added gases such as O2, Ar, He, and N2, all greatly affect the rate and selectivity. For example, CHF3 typically provides higher selectivity for buffer layers / hard masks (SiN / SiO2) than pure CF4.

[0093] The dry etching gas used is CF4 / CHF3 (approximately 1:9), a small amount of O2 (or CO), and He.

[0094] The pressure used in dry etching affects the mean free path, concentration, and energy of free radicals and ions reaching the wafer. The effects of pressure variations on rate and selectivity are complex and require specific process optimization.

[0095] The dry etching pressure used is less than 10 mT.

[0096] RF power: Increasing power typically increases ion energy and density, which in turn increases physical sputtering and free radical generation, thereby increasing the etching rate of both, but may reduce selectivity (because physical sputtering has little difference between the two materials).

[0097] The dry etching source power used is 500W to 600W (high frequency, such as 60MHz) to generate high-density plasma.

[0098] The dry etching bias power used is less than 100W (low frequency, such as 2MHz) to control the ion bombardment energy. Bias power is a key physical parameter for achieving high selectivity. Low bias power significantly reduces the physical bombardment energy of ions on the substrate. This makes it difficult to remove the robust polymer layer on the hard mask surface, while the buffer layer, due to its chemical bond energy difference, can still be etched at a slower chemical rate under the same weak bombardment. Higher bias power results in lower selectivity.

[0099] The dry etching temperature used is 10°C to 15°C. Low temperatures facilitate the adhesion and stability of fluorocarbon polymers on the hard mask surface, making them more difficult to remove and thus further improving selectivity. This is a common method for achieving ultra-high selectivity of over 20:1.

[0100] Fine optimization within the aforementioned process parameter window (especially the matching of O2 flow rate and bias power) can achieve selectivity from 15:1 to 30:1.

[0101] See Figure 6 The pre-etched wide trench 21 and pre-etched narrow trench 22 are prepared by step S1023 in this application (after removing the remaining photoresist layer 4). The bottom of the pre-etched wide trench 21 exposes the substrate 1, while the bottom of the pre-etched narrow trench 22 exposes the buffer layer 2. That is, the pre-etched narrow trench 22 is only etched into the interior of the buffer layer 2 and does not penetrate the buffer layer 2.

[0102] In some examples, the barrier layer used in step S103 is made of a different material than the buffer layer.

[0103] The buffer layer 2 and the barrier layer 5 are made of different materials. The purpose is that during the etching process of the buffer layer 2, the difference in materials between the buffer layer 2 and the barrier layer 5 will create a difference in etching rate. This will ensure that when the buffer layer 2 is etched through, the barrier layer 5 in the pre-etched wide trench 21 will still be preserved. Thus, the barrier layer 5 in the pre-etched wide trench 21 can effectively protect the depth of the pre-etched wide trench 21.

[0104] In some examples, the barrier layer 5 is made of a material including SiO2. x Any one of TiN and Al2O3 In some examples, the barrier layer 5 includes SiO2. x The barrier layer is defined as follows: x represents the ratio of element Si to element O. For example, when x is 2, the barrier layer includes a SiO2 layer, which is also known as a silicon dioxide layer.

[0105] In some examples, the barrier layer 5 can be formed using a chemical vapor deposition (CVD) process.

[0106] See Figure 7 This shows the barrier layer 5 prepared according to step S103 of this application.

[0107] In some examples, step S104 includes: Chemical mechanical polishing is used to polish the barrier layer 5 and the hard mask 3 until the upper surface of the buffer layer 2 is polished. At this time, the hard mask 3 is completely removed, and part of the thickness of the barrier layer 5 is also polished away. The remaining part of the thickness of the barrier layer 5 is retained in the pre-etched wide trench 21 and pre-etched narrow trench 22 in the buffer layer 2.

[0108] Before the chemical mechanical polishing process, the pre-etched wide trench 21 is deeper than the pre-etched narrow trench 22. The pre-etched wide trench 21 extends to the surface of the buffer layer 2, while the pre-etched narrow trench 22 remains in the buffer layer 2. Both the pre-etched wide trench 21 and the pre-etched narrow trench 22 are completely filled by the barrier layer 5.

[0109] During the chemical mechanical polishing process, the depths of the pre-etched wide trench 21 and the pre-etched narrow trench 22 decrease synchronously, and the thickness of the barrier layer 5 located in the pre-etched wide trench 21 and the pre-etched narrow trench 22 also decreases synchronously.

[0110] After the chemical mechanical polishing process is completed, the reduced depths of the pre-etched wide trenches 21 and the pre-etched narrow trenches 22 are the same, and the reduced thickness of the barrier layer 5 located within the pre-etched wide trenches 21 and the pre-etched narrow trenches 22 is the same. At this time, the depth of the pre-etched wide trenches 21 located within the buffer layer 2 is greater than the depth of the pre-etched narrow trenches 22. That is, the thickness of the barrier layer 5 filling the pre-etched wide trenches 21 within the buffer layer 2 is greater than the thickness of the barrier layer 5 filling the pre-etched narrow trenches 22, thus creating a thickness difference in the barrier layer 5.

[0111] When the thickness difference of the barrier layer 5 is formed, when the thinner barrier layer 5 in the pre-etched narrow trench 22 is removed, at least a portion of the thicker barrier layer 5 in the pre-etched wide trench 21 can be retained. This retained portion of the barrier layer 5 can protect the depth of the pre-etched wide trench 21.

[0112] See Figure 8 This is a schematic diagram of the barrier layer 5 formed after grinding according to step S104 in this application.

[0113] In some examples, step S105 employs a wet etching process to remove the barrier layer 5 within the pre-etched narrow trench 22.

[0114] In some examples, the wet etching solution used in the wet etching process may include diluted hydrofluoric acid (DHF).

[0115] During the wet etching process, the barrier layers within the pre-etched wide trenches and pre-etched narrow trenches are etched simultaneously. Etching can be stopped simply by controlling the etching time of the wet etching process to completely remove the barrier layer in the pre-etched narrow trenches. A barrier layer of a certain thickness is then retained in the pre-etched wide trenches to protect them when the depth of the pre-etched narrow trenches is subsequently increased, ensuring that the depth of the pre-etched wide trenches remains unchanged.

[0116] See Figure 9 This is a schematic diagram showing the removal of the barrier layer 5 in the pre-etched narrow trench 22 according to step S105 of this application. During the removal of the barrier layer 5 in the pre-etched narrow trench 22, the thickness of the buffer layer 2 may change or remain unchanged, depending mainly on the type of process used. As long as a buffer layer 2 of a certain thickness is retained as the etching template for subsequent etching processes, it is acceptable.

[0117] In step S106, since the bottom of the pre-etched narrow trench is exposed as a buffer layer after the barrier layer in the pre-etched narrow trench is removed, the pre-etched narrow trench must be etched to the surface of the substrate before the depth of the pre-etched narrow trench can be increased, thereby making the depth of the pre-etched narrow trench exceed the depth of the pre-etched wide trench.

[0118] In some examples, step S106 includes: The second selectivity etching process is used to etch the buffer layer 2 by adjusting the selectivity of the buffer layer and the barrier layer until the bottom of the pre-etched narrow trench 22 is pushed to the substrate surface; so that after etching, the bottom of the pre-etched narrow trench 22 is exposed to the substrate 1, and the barrier layer 5 with a certain thickness is still retained in the pre-etched wide trench 21.

[0119] In some examples, when etching is performed using the second selectivity etching process, the etching rate of buffer layer 2 is higher than that of barrier layer 5.

[0120] In some examples, when etching is performed using the second selectivity etching process, the ratio of the etching rate of the buffer layer 2 to the etching rate of the barrier layer 5 is greater than 10:1.

[0121] It should be noted that the etching deepening of the bottom of the pre-etched narrow trench 22 is achieved by directly etching the entire buffer layer, which inevitably increases the width of the pre-etched narrow trench 22. This invention employs two methods to control this. The first method is to define the width of the second etching window 42 in step S102 as smaller than the width of the subsequently prepared narrow-deep trench 12. After widening, this width is exactly equal to the pre-set width of the narrow-deep trench 12. The second method is to use a highly anisotropic etching process, advancing the etching of the pre-etched narrow trench 22 only in the vertical direction, with minimal impact on its horizontal width. In some examples, the second selective etching process may include highly anisotropic physical / ion-assisted etching.

[0122] As some more specific embodiments provided in this application, the specific implementation process of the second selective etching process is as follows: Dry etching gases: More physically-based formulations: CHF3 / Ar or (CF4 / CHF3 (gas flow rate ratio approximately 1:9)) / Ar. It's possible to try reducing the CHF3 flow rate while significantly increasing the Ar flow rate. CHF3 tends to form a polymer passivation layer on the sidewalls, contributing to anisotropy, but its chemical reactivity is also high. With existing openings, excessive chemical reactivity (such as using high concentrations of CHF3 or NF3) can lead to lateral etching. Ar is an inert gas that does not participate in chemical reactions; its high-energy ions directly "bombard" the material through physical bombardment, exhibiting strong directionality and better replicating the mask pattern.

[0123] The pressure used in dry etching is less than 10 mT.

[0124] Dry etching uses a source power of 500W to 600W (high frequency, such as 60MHz) to generate high-density plasma.

[0125] Dry etching employs a bias power of 100W–200W (low frequency, such as 2MHz) to control the ion bombardment energy. Bias power is a key physical parameter for achieving high selectivity. Low bias power significantly reduces the physical bombardment energy of ions on the substrate. This makes it difficult to remove the robust polymer layer on the surface of the barrier layer (e.g., SiO2), while the buffer layer (e.g., SiN), due to its different chemical bond energies, can still be etched at a slower chemical rate under the same weak bombardment. Higher power results in lower selectivity.

[0126] The temperature used for dry etching is 50°C to 60°C. Too low a temperature may prevent etching byproducts from evaporating from the bottom, thus affecting the etching rate and uniformity. It is typically controlled between 20°C and 60°C.

[0127] The selectivity ratio of the buffer layer to the barrier layer is controlled between 15:1 and 30:1, which optimizes the high selectivity while reducing lateral etching.

[0128] See Figure 10 The diagram shows a pre-etched narrow trench 22 and buffer layer 2 obtained after etching buffer layer 2 according to the second selective ratio etching process.

[0129] In step S107, when the bottom of the pre-etched narrow trench exposes the substrate, a barrier layer of a certain thickness is still retained in the pre-etched wide trench. At this time, the bottoms of both the pre-etched narrow trench and the pre-etched wide trench reach the substrate surface. By etching the pre-etched narrow trench, the depth of the pre-etched narrow trench is made deeper than that of the pre-etched wide trench.

[0130] In some examples, step S107 includes: After the second selective ratio etching process is completed, the buffer layer 2 and the barrier layer 5 are used as a mask to perform a dry etching process to etch the substrate 1 exposed at the bottom of the pre-etched narrow trench 22, and to further deepen the depth of the pre-etched narrow trench 22 into the substrate 1.

[0131] See Figure 11 The diagram shows a schematic of the deepened pre-etched narrow trench 22.

[0132] Once the depth of the pre-etched narrow trench is increased to the target depth, step S108 can be executed to etch the substrate at the bottom of the pre-etched narrow trench and the pre-etched wide trench, forming a wide shallow trench and a narrow deep trench.

[0133] In some examples, step S108 includes: S1081. Remove the barrier layer 5 in the pre-etched wide trench 21.

[0134] In some examples, a wet etching process can be used to remove the barrier layer 5 in the pre-etched wide trench 21.

[0135] In some examples, the wet etching process uses a wet etching solution that includes hot phosphoric acid (H3PO4).

[0136] See Figure 12 This is a schematic diagram after removing the blocking layer 5.

[0137] S1082, simultaneously etch the pre-etched narrow trench 22 and the pre-etched wide trench 21, deepen the pre-etched wide trench 21 and the pre-etched narrow trench 22 to form a wide shallow trench 11 and a narrow deep trench 12.

[0138] In some examples, a dry etching process is used to simultaneously etch the substrate 1 at the bottom of the pre-etched wide trench 21 and the substrate 1 at the bottom of the pre-etched narrow trench 22. After etching for a certain period of time, a narrow deep trench 12 and a wide shallow trench 11 are formed.

[0139] See Figure 13 These are the wide shallow trench 11 and narrow deep trench 12 prepared according to step S108 in this application.

[0140] It should be noted that the above-described method for fabricating semiconductor structures can be applied to the fabrication of back-illuminated image sensors. It can also be applied to the fabrication of other semiconductor devices, and this application does not impose any limitations on it.

[0141] Finally, it should be noted that the unexpected technical effects of the technical solution provided in this application include: This application provides a method for fabricating a semiconductor structure, the purpose of which is to fabricate wide-shallow trenches and narrow-deep trenches using only a single photomask. An unexpected technical advantage is that this application first forms pre-etched wide trenches and pre-etched narrow trenches of different depths, and then fills the trenches with a barrier layer. The difference in depth between the pre-etched wide trenches and pre-etched narrow trenches translates into a difference in the thickness of the barrier layers filling them. Due to the thickness difference of the barrier layers, when the barrier layer in the pre-etched narrow trench is removed, the barrier layer in the pre-etched wide trench is not completely removed, but a portion remains, and this retained portion of the barrier layer protects the pre-etched wide trench. Thus, when the depth of the pre-etched narrow trench is increased, the depth of the pre-etched wide trench remains unchanged because it is filled with a barrier layer. Once the depth of the pre-etched narrow trench is increased to a certain extent, the barrier layer filling the pre-etched wide trench is removed. Then, the pre-etched wide trench and the pre-etched narrow trench are simultaneously etched to the target depth to obtain the narrow deep trench and the wide shallow trench.

[0142] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, and a buffer layer and a hard mask are sequentially formed on the substrate; The hard mask and buffer layer are patterned to form pre-etched narrow trenches and pre-etched wide trenches within the hard mask and buffer layer; the bottom of the pre-etched wide trenches extends to the substrate surface, while the bottom of the pre-etched narrow trenches remains within the buffer layer. A barrier layer is formed within the pre-etched narrow trench and the pre-etched wide trench; The barrier layer and hard mask located above the surface of the buffer layer are removed by planarization or thinning processes. The barrier layer in the pre-etched narrow trench is removed by etching process, and at least a portion of the barrier layer thickness is retained in the pre-etched wide trench; The buffer layer is etched using a selective etching process until the bottom of the pre-etched narrow trench is pushed to the substrate surface. By selecting the etching ratio, a portion of the barrier layer is retained in the pre-etched wide trench. Using the remaining buffer and barrier layers as a mask, the substrate at the bottom of the pre-etched narrow trench is etched until the target depth is reached; The barrier layer in the pre-etched wide trench is removed, and the remaining buffer layer is used as a mask to etch the substrate, resulting in both wide shallow trenches and narrow deep trenches.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The steps of patterning a hard mask and a buffer layer to form pre-etched narrow trenches and pre-etched wide trenches on the hard mask and the buffer layer include: A patterned photoresist layer is formed on the surface of a hard mask, wherein a large first etch window and a small second etch window are formed in the patterned photoresist layer; Utilizing the etching load effect, a hard mask is etched through a first etching window and a second etching window to form a pre-etched wide trench and a pre-etched narrow trench in the hard mask; the depth of the pre-etched wide trench is greater than that of the pre-etched narrow trench. Using a first selectivity etching process, the pre-etched middle wide trench and the pre-etched middle narrow trench are deepened, thereby obtaining the pre-etched wide trench and the pre-etched narrow trench located in the hard mask and the buffer layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, By utilizing the etching load effect, when etching a hard mask through a first etching window and a second etching window, the etching rate at the first etching window is higher than the etching rate at the second etching window.

4. The method for preparing a semiconductor structure according to claim 2, characterized in that, When using the first selectivity etching process to deepen the pre-etched wide trench and the pre-etched narrow trench, the etching rate of the buffer layer is higher than that of the hard mask.

5. The method for preparing a semiconductor structure according to any one of claims 1 to 4, characterized in that, The buffer layer is made of a different material than the rigid mask.

6. The method for preparing a semiconductor structure according to any one of claims 1 to 4, characterized in that, The buffer layer is made of a different material than the barrier layer.

7. The method for preparing a semiconductor structure according to any one of claims 1 to 4, characterized in that, The process used to remove the barrier layer in the pre-etched narrow trench includes wet etching.

8. The method for preparing a semiconductor structure according to any one of claims 1 to 4, characterized in that, The step of selectively etching the buffer layer until the bottom of the pre-etched narrow trench is pushed to the substrate surface, and retaining a portion of the barrier layer in the pre-etched wide trench by selecting the etching ratio, includes: A second selectivity etching process is used to etch the buffer layer by adjusting the selectivity ratio of the buffer layer and the barrier layer; so that after etching, the bottom of the pre-etched narrow trench is exposed to the substrate, while a barrier layer of a certain thickness is still retained in the pre-etched wide trench.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, When etching is performed using the second selective ratio etching process, the etching rate of the buffer layer is higher than that of the barrier layer.

10. A method for fabricating a semiconductor device, characterized in that, The method for fabricating the semiconductor device includes the method for fabricating the semiconductor structure as described in any one of claims 1 to 9.

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