Preparation method of TBC battery and TBC battery

Abstract

The invention discloses a preparation method of a TBC battery and the TBC battery. The preparation method comprises the following steps: firstly, providing an N-type silicon substrate; wherein the first surface of the N-type silicon substrate comprises a first region and a second region which are alternately arranged in an interdigital manner, then an intermediate spacer layer, a first tunneling oxide layer and a boron diffusion doping layer are sequentially prepared on the first surface corresponding to the first region and the second region, and the boron diffusion doping layer is prepared on the first surface in a wet etching manner. And removing the boron diffusion doping layer, the first tunneling oxide layer and the middle spacing layer corresponding to the second region, sequentially preparing a second tunneling oxide layer and a phosphorus diffusion doping layer on the first surface corresponding to the second region, and finally preparing a first passivation film layer on one side, far away from the first surface, of the boron diffusion doping layer and the phosphorus diffusion doping layer, and carrying out silk-screen printing and sintering treatment on the first passivation film layer to prepare the TBC battery. By utilizing the method, the boron doping concentration of the first region is effectively improved, and meanwhile, residual associated products such as borosilicate glass are thoroughly removed.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and more particularly to a method for preparing a TBC cell and the TBC cell itself. Background Technology

[0002] TBC (Tunnel Oxide Passivated Contact) cells are crystalline silicon solar cells with a tunnel oxide passivated contact back contact structure. They combine TOPCon (Tunnel Oxide Passivated Contact) with BC (Back Contact) technology, forming high-quality, interdigitated P-regions and N-regions on the back of the cell. Due to their lack of front-side grid lines and full back-side field contact, TBC cells offer high conversion efficiency and an aesthetically pleasing appearance, representing an important direction for the development of photovoltaic technology.

[0003] In existing TBC battery fabrication processes, laser ablation is typically used to patternarly define the P-region (boron-doped) and N-region (phosphorus-doped) on the back of the battery. However, this method has inherent limitations. Laser ablation is extremely sensitive to the boron doping concentration in the P-region. To ensure complete removal of byproducts such as borosilicate glass after laser ablation and to avoid borosilicate glass residue, the boron doping concentration in the P-region must be controlled at a low level, typically no higher than 5.5E+19 atoms / cm². 3 Furthermore, if the boron doping concentration in the P-region is too high, the borosilicate glass will deform under the high temperature of the laser, leaving residual borosilicate glass that cannot be completely removed. This residual borosilicate glass will severely affect the PN junction isolation, passivation effect, and metal contact, leading to a decrease in battery efficiency (especially fill factor FF) and battery yield.

[0004] Therefore, under the traditional TBC battery fabrication process, it is impossible to further reduce the contact resistance between the metal and semiconductor in the P-region by increasing the boron doping concentration in the P-region, thus limiting the potential of battery efficiency. Summary of the Invention

[0005] This invention provides a method for preparing a TBC battery and a TBC battery in order to effectively increase the boron doping concentration in the first region, while thoroughly removing residual byproducts such as borosilicate glass, thereby improving the efficiency and yield of the TBC battery and avoiding affecting the PN junction isolation, passivation effect and metal contact of the TBC battery.

[0006] In a first aspect, embodiments of the present invention provide a method for preparing a TBC battery, comprising: An N-type silicon substrate is provided; wherein the N-type silicon substrate includes a first surface and a second surface that are opposite to each other, and the first surface includes a first region and a second region that are arranged alternately in an interdigitated pattern; An intermediate spacer layer, a first tunneling oxide layer, and a boron diffusion doped layer are sequentially prepared on the first surface corresponding to the first region and the second region. The boron diffusion doped layer, the first tunneling oxide layer, and the intermediate spacer layer corresponding to the second region are removed by wet etching. A second tunneling oxide layer and a phosphorus diffusion doped layer are sequentially prepared on the first surface corresponding to the second region. A first passivation film is prepared on the side of the boron diffusion doped layer and the phosphorus diffusion doped layer away from the first surface, and screen printing and sintering are performed on the first passivation film to form an electrode structure, thereby obtaining the TBC battery.

[0007] Optionally, an intermediate spacer layer, a first tunneling oxide layer, and a boron diffusion-doped layer are sequentially formed on the first surface corresponding to the first region and the second region, and the boron diffusion-doped layer, the first tunneling oxide layer, and the intermediate spacer layer corresponding to the second region are removed by wet etching, including: The intermediate spacer layer, the first tunneling oxide layer, and the first intrinsic silicon layer are sequentially prepared on the first surface corresponding to the first region and the second region. The side of the first intrinsic silicon layer away from the first tunneling oxide layer is subjected to boron diffusion doping to form the boron diffusion doped layer; A first photoresist mask layer is prepared on the side of the boron diffusion doped layer corresponding to the first region away from the first surface, and the boron diffusion doped layer, the first tunneling oxide layer and the intermediate spacer layer corresponding to the second region are removed by wet etching to expose the first surface corresponding to the second region and remove the first photoresist mask layer corresponding to the first region.

[0008] Optionally, the intermediate spacer layer includes an intermediate tunneling oxide layer and an intermediate intrinsic silicon layer stacked sequentially; The intermediate spacer layer, the first tunneling oxide layer, and the first intrinsic silicon layer are sequentially fabricated on the first surface corresponding to the first region and the second region, including: The intermediate tunneling oxide layer, the intermediate intrinsic silicon layer, the first tunneling oxide layer, and the first intrinsic silicon layer are sequentially formed on the first surface corresponding to the first region and the second region.

[0009] Optionally, the thickness of the intermediate tunneling oxide layer ranges from 0.5 to 1.2 nm, the thickness of the intermediate intrinsic silicon layer ranges from 20 to 70 nm, the thickness of the first tunneling oxide layer ranges from 0.5 to 1.5 nm, and the thickness of the first intrinsic silicon layer ranges from 200 to 380 nm.

[0010] Optionally, the side of the first intrinsic silicon layer away from the first tunneling oxide layer is subjected to boron diffusion doping to form the boron diffusion doped layer, including: Using a tubular diffusion apparatus and a boron diffusion process, the side of the first intrinsic silicon layer away from the first tunneling oxide layer is subjected to a high-temperature propulsion process and a cooling oxidation process in sequence to form the boron diffusion doped layer.

[0011] Optionally, the temperature range corresponding to the high-temperature propulsion treatment is 950-1050℃, and the temperature range corresponding to the cooling oxidation treatment is 800-950℃.

[0012] Optionally, a second tunneling oxide layer and a phosphorus diffusion doped layer are sequentially formed on the first surface corresponding to the second region, including: The second tunneling oxide layer and the second intrinsic silicon layer are prepared on the first surface corresponding to the exposed second region and on the side of the boron diffusion doped layer away from the first surface; The side of the second intrinsic silicon layer away from the second tunneling oxide layer is subjected to phosphorus diffusion doping to form the phosphorus diffusion doped layer; A second photoresist mask layer is prepared on the side of the phosphorus diffusion doped layer corresponding to the second region away from the first surface, and the phosphorus diffusion doped layer and the second tunneling oxide layer corresponding to the first region are removed by wet etching to expose the boron diffusion doped layer corresponding to the first region, and the second photoresist mask layer corresponding to the second region is removed.

[0013] Optionally, after sequentially forming a second tunneling oxide layer and a phosphorus diffusion doped layer on the first surface corresponding to the second region, the method further includes: A second passivation film is prepared on the second surface.

[0014] Optionally, the first passivation film layer includes a first anti-ultraviolet attenuation film layer and a first anti-reflection film layer stacked sequentially, and the second passivation film layer includes a second anti-ultraviolet attenuation film layer and a second anti-reflection film layer stacked sequentially.

[0015] Secondly, embodiments of the present invention also provide a TBC battery, which is prepared using the TBC battery preparation method described in any one of the first aspects.

[0016] This invention provides a method for fabricating a TBC battery and the TBC battery itself. The method first provides an N-type silicon substrate. The N-type silicon substrate includes a first surface and a second surface that are opposite to each other. The first surface includes a first region and a second region arranged alternately in an interdigitated pattern. Then, an intermediate spacer layer, a first tunneling oxide layer, and a boron diffusion doped layer are sequentially fabricated on the first surface corresponding to the first region and the second region. The boron diffusion doped layer, the first tunneling oxide layer, and the intermediate spacer layer corresponding to the second region are removed by wet etching. Then, a second tunneling oxide layer and a phosphorus diffusion doped layer are sequentially fabricated on the first surface corresponding to the second region. Finally, a first passivation film layer is fabricated on the side of the boron diffusion doped layer and the phosphorus diffusion doped layer away from the first surface. The first passivation film layer is screen printed and sintered to form an electrode structure, thus obtaining a TBC battery. Using the above method, wet etching is used instead of the existing laser ablation method. This eliminates the need for laser irradiation during the fabrication of TBC cells, overcoming the limitations of existing laser patterning processes on the boron doping concentration in the first region, and ensuring high boron doping concentration in the first region (e.g., boron doping concentration greater than or equal to 5.8E+19 atoms / cm). 3 This is significantly higher than the existing 5.5E+19 atoms / cm 3 This process can thoroughly remove residual byproducts such as borosilicate glass and / or phosphosilicate glass. The interface between the patterned first and second regions is clean and residue-free, effectively reducing the contact resistance between the metal and semiconductor, improving the efficiency and yield of TBC cells, and preventing the PN junction isolation, passivation effect, and metal contact of TBC cells from being affected. In other words, the patterning process uses photolithography, employing a wet etching technique after printing photoresist. Wet etching is an isotropic chemical etching process; its effectiveness depends only on the chemical properties of the etching solution and the material itself, and is independent of the doping concentration. For example, it does not limit the boron doping concentration in the first region. Therefore, even for boron doping concentrations higher than 6E+19 atoms / cm², the process is effective. 3 The borosilicate glass described above can also be uniformly and thoroughly removed, fundamentally eliminating borosilicate glass residue. Furthermore, the first region is sequentially prepared with an intermediate spacer layer, a first tunneling oxide layer, and a boron diffusion doping layer. The first tunneling oxide layer can effectively block the excessive diffusion of boron atoms from the boron diffusion doping layer towards the intermediate spacer layer, enabling the boron diffusion doping layer to achieve a high concentration of boron doping to optimize contact. At the same time, the intermediate spacer layer maintains a low concentration of boron doping to maintain excellent passivation. This achieves gradient doping of high-concentration boron doping in the boron diffusion doping layer and low-concentration boron doping in the intermediate spacer layer, further improving the overall boron doping concentration in the first region. The boron diffusion doping layer and the intermediate spacer layer can carry carriers through the tunneling effect of the first tunneling oxide layer, improving the photoelectric conversion efficiency of the TBC cell and ensuring the operational stability and reliability of the TBC cell.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic flowchart of a method for preparing a TBC battery according to an embodiment of the present invention; Figure 2 This is a schematic flowchart of another method for preparing a TBC battery provided in an embodiment of the present invention; Figure 3 This is a schematic flowchart of another TBC battery preparation method provided in this embodiment of the invention. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] First, it's important to clarify that TBC cells are a type of highly efficient and stable solar cell. The biggest difference between TBC cells and other crystalline silicon solar cells is that the emitter, surface field, and metal electrodes are all located on the back of the cell and arranged in an interdigitated pattern. There are no grid lines obstructing the front of the cell. In other words, TBC cells incorporate the tunneling oxide passivation contact technology of TOPCon cells and the interdigitated P- and N-region arrangement on the back of the cell. Since there are no electrodes on the front of the TBC cell, charge collection and energy transfer are achieved through ohmic contacts on the back. Because there are no electrodes obstructing the front of the TBC cell, it can maximize the utilization of incident light, minimizing optical losses. This means that TBC cells reduce shading of sunlight, resulting in a larger effective power generation area and improved photoelectric conversion efficiency.

[0023] Figure 1 This is a schematic flowchart of a TBC battery preparation method provided by an embodiment of the present invention. This TBC battery preparation method is applicable to the preparation of TBC batteries and can be used to prepare TBC batteries. Figure 1 As shown, the preparation method includes: S110, providing an N-type silicon substrate; wherein the N-type silicon substrate includes a first surface and a second surface that are opposite to each other, and the first surface includes a first region and a second region that are arranged alternately in an interdigitated pattern.

[0024] Specifically, an N-type silicon substrate is provided, comprising a first surface and a second surface that are opposite to each other. Exemplarily, the first surface can be understood as the back surface of the N-type silicon substrate, and the second surface can be understood as the front surface of the N-type silicon substrate. The first surface includes a first region and a second region arranged alternately in an interdigitated pattern. Exemplarily, the first region can be understood as a P-region, where a boron doping process can subsequently be performed, and the second region can be understood as an N-region, where a phosphorus doping process can subsequently be performed.

[0025] The first surface of the N-type silicon substrate is a polished surface. Exemplarily, the first surface of the N-type silicon substrate can be subjected to alkaline polishing to ensure it is polished, thereby forming a highly reflective polished surface. This improves the flatness and smoothness of the battery surface, increases the reflection of long-wavelength light, promotes secondary light absorption, increases short-circuit current, and reduces leakage current, meeting subsequent process requirements. Exemplarily, the weight reduction from polishing can be controlled within the range of 0.1-3g, and exemplarily, the weight reduction from polishing can be 0.4g. Exemplarily, the size of the base after polishing and weight reduction can be controlled within the diameter range of 5-40μm, and exemplarily, the diameter of the base after polishing and weight reduction can be 21μm. Exemplarily, the reflectivity of the base after polishing and weight reduction can be controlled at approximately 35%. Furthermore, it is understood that the effect of alkaline polishing is that both sides are polished; that is, alkaline polishing can be performed on both sides of the N-type silicon substrate simultaneously.

[0026] The second surface of the N-type silicon substrate is textured. Exemplarily, the second surface of the N-type silicon substrate can be textured to create a textured surface; exemplarily, the textured surface exhibits a pyramidal structure under a microscope. Textured treatment can remove organic contaminants and metallic impurities from the surface of the N-type silicon substrate, remove the mechanical damage layer generated during the wire cutting process, reduce recombination centers, and create an uneven textured surface. This facilitates the use of light-trapping effects, increasing the absorption rate of sunlight by the N-type silicon substrate, reducing reflectivity, and simultaneously increasing the surface area of ​​the N-type silicon substrate, thereby increasing the area of ​​the PN junction formed on the surface. Furthermore, exemplarily, the gap region between the first and second regions on the first surface can also be textured. In this embodiment, the order of textured treatment of the second surface and textured treatment of the gap region between the first and second regions is not specifically required or limited. Exemplarily, textured treatment of the second surface and textured treatment of the gap region between the first and second regions can be performed simultaneously, or sequentially.

[0027] Furthermore, it should be noted that this embodiment does not impose specific requirements or limitations on the order of alkaline polishing and texturing. In practice, alkaline polishing can be performed first, followed by texturing, or vice versa. This embodiment is merely an example and is not intended to limit the process. Additionally, after alkaline polishing and texturing, the N-type silicon substrate can be subjected to a chain-like acid pickling process using hydrochloric acid (HCl) solution to further ensure the cleanliness of both sides of the N-type silicon substrate.

[0028] S120. An intermediate spacer layer, a first tunneling oxide layer, and a boron diffusion doped layer are sequentially prepared on the first surface corresponding to the first region and the second region. The boron diffusion doped layer, the first tunneling oxide layer, and the intermediate spacer layer corresponding to the second region are removed by wet etching.

[0029] Specifically, the first tunneling oxide layer and the corresponding polycrystalline silicon layer allow majority carriers (electrons) to pass smoothly through the tunneling effect while preventing the recombination of minority carriers (holes), thereby achieving selective carrier collection, reducing surface recombination, increasing the open-circuit voltage and fill factor of the cell, and thus improving the overall photoelectric conversion efficiency of the TBC cell. The composite layer of the first tunneling oxide layer and the corresponding polycrystalline silicon layer together forms a passivation contact structure, which can effectively reduce surface recombination and metal contact recombination of the overall TBC cell. In other words, depositing an ultrathin first tunneling oxide layer on one side of the first surface of the N-type silicon substrate can provide good interface passivation and provide tunneling barriers for different carriers. Depositing a corresponding polycrystalline silicon layer on the first tunneling oxide layer can increase the electron migration rate while suppressing the hole migration rate. In addition, the corresponding polycrystalline silicon layer contacts the subsequent metal electrode, acting as an electron transport bridge. After forming the corresponding polycrystalline silicon layer on one side of the first surface of the N-type silicon substrate, boron diffusion doping can be performed on the side of the corresponding polycrystalline silicon layer away from the first surface to form a boron-doped polycrystalline silicon layer on one side of the first surface of the N-type silicon substrate. The boron diffusion doping treatment can form a PN junction on the first surface of the N-type silicon substrate. The junction formation process involves generating semiconductor layers with different conductivity types on a semiconductor substrate material, that is, forming a boron diffusion-doped layer. The material and thickness of the first tunneling oxide layer and the boron diffusion-doped layer can be set according to actual needs and are not specifically limited here. For example, the material of the first tunneling oxide layer can be one or more of the following materials, including but not limited to silicon oxide, aluminum oxide, titanium oxide, chromium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium carbonitride.

[0030] It should also be noted that in this embodiment, an intermediate spacer layer is formed between the first surface of the N-type silicon substrate and the first tunneling oxide layer. Specifically, after forming the intermediate spacer layer on the first surface corresponding to the first and second regions, the first tunneling oxide layer is formed on the side of the intermediate spacer layer away from the first surface, and a boron diffusion-doped layer is formed on the side of the first tunneling oxide layer away from the intermediate spacer layer. The first tunneling oxide layer effectively blocks excessive diffusion of boron atoms from the boron diffusion-doped layer towards the intermediate spacer layer, allowing the boron diffusion-doped layer to achieve a high concentration of boron doping to optimize contact. Simultaneously, the intermediate spacer layer maintains a low concentration of boron doping to preserve excellent passivation. This achieves a gradient doping effect, with high boron doping in the boron diffusion-doped layer and low boron doping in the intermediate spacer layer, further increasing the overall boron doping concentration in the first region. The boron diffusion-doped layer and the intermediate spacer layer can transport charge carriers through the tunneling effect of the first tunneling oxide layer, ensuring the excellent photoelectric performance of the TBC cell. In other words, the intermediate spacer layer also effectively prevents further diffusion of boron atoms towards the N-type silicon substrate, avoiding failure of the N-type silicon substrate. Furthermore, this embodiment employs wet etching to remove the boron diffusion doping layer, the first tunneling oxide layer, and the intermediate spacer layer corresponding to the second region. Wet etching is an isotropic chemical etching process, and its effectiveness depends only on the chemical properties of the etching solution and the material itself, and is independent of the doping concentration. For example, it does not limit the boron doping concentration in the first region. Therefore, even for ultra-high concentrations of boron doping in the first region, the corresponding byproducts, such as borosilicate glass, can be uniformly and thoroughly removed, fundamentally eliminating borosilicate glass residue. The combined application of these two methods can further increase the boron doping concentration in the first region. The wet etching method does not limit the boron doping concentration in the first region and can also ensure the complete removal of associated byproducts such as borosilicate glass. The intermediate spacer layer can also ensure that high concentrations of boron atoms do not diffuse to the first surface of the N-type silicon substrate through the boron diffusion doping layer and the first tunneling oxide layer. In other words, while ensuring the normal application of the prepared TBC battery, it not only increases the boron doping concentration in the first region and reduces the contact resistance between the metal and the semiconductor, but also completely removes associated byproducts such as borosilicate glass in the first region, as well as completely removes the boron diffusion doping layer, the first tunneling oxide layer and the intermediate spacer layer in the second region, so as to expose the first surface in the second region for subsequent doping processes in the second region.

[0031] Furthermore, by way of example, this embodiment specifically uses wet etching to delineate the first region and the second region, that is, to clearly distinguish the first region and the second region. Wet etching replaces the existing laser ablation method, eliminating the need for laser irradiation during the fabrication of the TBC battery. This overcomes the limitation of existing laser patterning processes on the boron doping concentration of the first region, which can be increased and selected according to actual needs. Moreover, this wet etching method can include, but is not limited to, acidic solution cleaning, alkaline solution cleaning, and neutral solution cleaning for etching. The etching objects corresponding to this wet etching method include, but are not limited to, byproducts such as borosilicate glass corresponding to the first region, byproducts such as borosilicate glass corresponding to the second region, the boron diffusion doped layer corresponding to the second region, the first tunneling oxide layer corresponding to the second region, and the intermediate spacer layer corresponding to the second region.

[0032] S130. A second tunneling oxide layer and a phosphorus diffusion doped layer are sequentially prepared on the first surface corresponding to the second region.

[0033] Specifically, the second tunneling oxide layer and the corresponding polycrystalline silicon layer allow majority carriers (electrons) to pass smoothly through the tunneling effect while preventing the recombination of minority carriers (holes), thereby achieving selective carrier collection, reducing surface recombination, increasing the open-circuit voltage and fill factor of the cell, and thus improving the overall photoelectric conversion efficiency of the TBC cell. The composite layer of the second tunneling oxide layer and the corresponding polycrystalline silicon layer together forms a passivation contact structure, which can effectively reduce surface recombination and metal contact recombination of the overall TBC cell. In other words, depositing an ultrathin second tunneling oxide layer on the first surface of the N-type silicon substrate can provide good interface passivation and provide tunneling barriers for different carriers. Depositing a corresponding polycrystalline silicon layer on the second tunneling oxide layer can increase the electron migration rate while suppressing the hole migration rate. In addition, the corresponding polycrystalline silicon layer contacts the subsequent metal electrode, acting as an electron transport bridge. After forming the corresponding polycrystalline silicon layer on one side of the first surface of the N-type silicon substrate, phosphorus diffusion doping can be performed on the side of the corresponding polycrystalline silicon layer away from the first surface to form a phosphorus-doped polycrystalline silicon layer on the first surface of the N-type silicon substrate. The phosphorus diffusion doping treatment enables the formation of a PN junction on the first surface of the N-type silicon substrate. The junction formation process involves generating semiconductor layers of different conductivity types on a semiconductor substrate material, i.e., forming a phosphorus diffusion-doped layer. The material and thickness of the second tunneling oxide layer and the phosphorus diffusion-doped layer can be set according to actual needs and are not specifically limited here. For example, the material of the second tunneling oxide layer can be one or more of the following materials, including but not limited to silicon oxide, aluminum oxide, titanium oxide, chromium dioxide, gallium oxide, tantalum pentoxide, niobium pentoxide, silicon nitride, silicon carbonitride, aluminum nitride, titanium nitride, and titanium carbonitride.

[0034] S140. A first passivation film layer is prepared on the side of the boron diffusion doped layer and the phosphorus diffusion doped layer away from the first surface, and screen printing and sintering are performed on the first passivation film layer to form an electrode structure, thereby obtaining a TBC battery.

[0035] Specifically, a first passivation film can be prepared on the side of the boron-diffused and phosphorus-diffused doped layers away from the N-type silicon substrate using processes such as atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), and film deposition. It is understood that the first passivation film possesses passivation and UV-fast degradation resistance properties, effectively preventing the entire TBC cell from being affected by ultraviolet and infrared radiation, further ensuring the operational reliability of the entire TBC cell. Exemplarily, the first passivation film includes a first UV-fast degradation resistance film and a first anti-reflection film layer stacked sequentially. Exemplarily, the first UV-fast degradation resistance film layer can be made of aluminum oxide, and the first anti-reflection film layer can be made of silicon nitride.

[0036] For example, the first UV-resistant film layer can be fabricated using an ALD process on the side of the boron-diffused doped layer and the phosphorus-diffused doped layer away from the first surface of the N-type silicon substrate. For example, the thickness of the first UV-resistant film layer ranges from 1 to 20 nm. For example, the thickness of the first UV-resistant film layer can be 5 nm, which can effectively resist UV decay, passivate, and protect the back side of the N-type silicon substrate.

[0037] For example, the first antireflective film can be prepared using a PECVD process on the side of the first surface of the first anti-UV degradation film away from the N-type silicon substrate. For example, the thickness of the first antireflective film ranges from 50-150 nm, and the refractive index ranges from 1.7%-2.6%. For example, the thickness of the first antireflective film can be 70 nm, and the refractive index can be 2.2%, which can further improve the overall photoelectric performance of the TBC cell, reduce sunlight reflection, increase sunlight absorption, improve the overall photoelectric conversion efficiency of the TBC cell, and simultaneously reduce surface recombination, increase carrier mobility, and improve the overall performance of the TBC cell.

[0038] Optionally, after sequentially preparing a second tunneling oxide layer and a phosphorus diffusion doped layer on the first surface corresponding to the second region, the method further includes preparing a second passivation film layer on the second surface.

[0039] Specifically, a second passivation film can be prepared on the second surface of an N-type silicon substrate using processes such as atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), and film deposition. It is understood that the second passivation film possesses passivation and UV-fast degradation resistance properties, effectively preventing the entire TBC cell from being affected by ultraviolet and infrared radiation, further ensuring the operational reliability of the entire TBC cell. Exemplarily, the second passivation film includes a second UV-fast degradation film and a second anti-reflection film stacked sequentially. Exemplarily, the material of the second UV-fast degradation film can be aluminum oxide, and the material of the second anti-reflection film can be silicon nitride.

[0040] For example, the second UV-resistant film layer can be fabricated on the second surface of an N-type silicon substrate using an ALD process. For example, the thickness of the second UV-resistant film layer ranges from 1 to 20 nm. For example, the thickness of the second UV-resistant film layer can be 5 nm, which can effectively resist UV degradation, passivate, and protect the front side of the N-type silicon substrate.

[0041] For example, the second antireflective film can be prepared using a PECVD process on the side of the second surface of the second anti-UV degradation film away from the N-type silicon substrate. For example, the thickness of the second antireflective film ranges from 50-150 nm, and the refractive index ranges from 1.5%-3%. For example, the thickness of the second antireflective film can be 80 nm, and the refractive index can be 2%, which can further improve the overall photoelectric performance of the TBC cell, reduce sunlight reflection, increase sunlight absorption, improve the overall photoelectric conversion efficiency of the TBC cell, and simultaneously reduce surface recombination, increase carrier mobility, and improve the overall performance of the TBC cell.

[0042] It should also be noted that this embodiment does not impose specific requirements or limitations on the formation order of the first passivation film and the second passivation film. In practice, the first passivation film can be formed first, followed by the second passivation film, or vice versa, or the preparation processes of the first and second passivation films can be performed simultaneously. Furthermore, by way of example, the first and second passivation films can be understood as being prepared simultaneously, with the only difference being their positions; the remaining materials and parameters can be the same.

[0043] Furthermore, screen printing is one of the core processes in the manufacturing of TBC batteries, primarily used for the formation of metal electrodes. This process utilizes the basic principle that the paste passes through the mesh openings of the screen in the patterned areas, while the paste does not pass through the mesh openings in the non-patterned areas. During the printing process, the paste is precisely extruded onto the N-type silicon substrate through the mesh openings of the screen. The paste is evenly distributed on the surface of the TBC battery in the form of conductive lines, forming the desired metal electrode pattern. Typically, the paste used for screen printing can include, but is not limited to, silver paste. The pattern formed by screen printing includes metal grid lines. High-temperature sintering is used to process the electrode material screen-printed onto the surface of the battery cell at high temperatures, drying the paste on the N-type silicon substrate, burning off the organic components of the paste, and allowing the paste to etch through the passivation film layer and connect with the PN junction. This enables the metal grid lines to form a good ohmic contact with the N-type silicon substrate, achieving the purpose of collecting and discharging current. For example, in the screen printing process, the wet weight of the main grid can be controlled within the range of 2-20g, and the linewidth of the printed main grid can be controlled within the range of 50-90μm. For example, the wet weight of the main grid can be controlled within 15g, and the linewidth of the printed main grid can be controlled within 80μm. For example, in the screen printing process, the wet weight of the fine grid can be controlled within the range of 10-60mg, and the linewidth of the printed fine grid can be controlled within the range of 10-70μm. For example, the wet weight of the fine grid can be controlled within 20mg, and the linewidth of the printed fine grid can be controlled within 40μm or 50μm. For example, the linewidth of the fine grid after printing in the first region can be the same as or different from the linewidth of the fine grid after printing in the second region; this embodiment is not limited here. Furthermore, the TBC cell after the screen printing process can undergo a light injection process and a laser-induced process, which can induce silver-silicon interdiffusion, thereby significantly reducing the contact resistance, increasing the fill factor of the cell, and effectively improving the efficiency of the cell.

[0044] The technical solution in this embodiment of the invention uses wet etching instead of the existing laser ablation method. This eliminates the need for laser irradiation during the fabrication of TBC cells, overcoming the limitations of existing laser patterning processes on the boron doping concentration in the first region, and ensuring high boron doping concentration in the first region (e.g., boron doping concentration greater than or equal to 5.8E+19 atoms / cm). 3 This is significantly higher than the existing 5.5E+19 atoms / cm 3This process can thoroughly remove residual byproducts such as borosilicate glass and / or phosphosilicate glass. The interface between the patterned first and second regions is clean and residue-free, effectively reducing the contact resistance between the metal and semiconductor, improving the efficiency and yield of TBC cells, and preventing the PN junction isolation, passivation effect, and metal contact of TBC cells from being affected. In other words, the patterning process uses photolithography, employing a wet etching technique after printing photoresist. Wet etching is an isotropic chemical etching process; its effectiveness depends only on the chemical properties of the etching solution and the material itself, and is independent of the doping concentration. For example, it does not limit the boron doping concentration in the first region. Therefore, even for boron doping concentrations higher than 6E+19 atoms / cm², the process is effective. 3 The borosilicate glass described above can also be uniformly and thoroughly removed, fundamentally eliminating borosilicate glass residue. Furthermore, the first region is sequentially prepared with an intermediate spacer layer, a first tunneling oxide layer, and a boron diffusion doping layer. The first tunneling oxide layer can effectively block the excessive diffusion of boron atoms from the boron diffusion doping layer towards the intermediate spacer layer, enabling the boron diffusion doping layer to achieve a high concentration of boron doping to optimize contact. At the same time, the intermediate spacer layer maintains a low concentration of boron doping to maintain excellent passivation. This achieves gradient doping of high-concentration boron doping in the boron diffusion doping layer and low-concentration boron doping in the intermediate spacer layer, further improving the overall boron doping concentration in the first region. The boron diffusion doping layer and the intermediate spacer layer can carry carriers through the tunneling effect of the first tunneling oxide layer, improving the photoelectric conversion efficiency of the TBC cell and ensuring the operational stability and reliability of the TBC cell.

[0045] Figure 2 This is a schematic flowchart of another TBC battery fabrication method provided by an embodiment of the present invention. This embodiment is an optimization based on the above embodiment. Optionally, an intermediate spacer layer, a first tunneling oxide layer, and a boron diffusion doped layer are sequentially fabricated on the first surfaces corresponding to the first and second regions, and the boron diffusion doped layer, the first tunneling oxide layer, and the intermediate spacer layer corresponding to the second region are removed by wet etching, including: An intermediate spacer layer, a first tunneling oxide layer, and a first intrinsic silicon layer are sequentially fabricated on the first surface corresponding to the first region and the second region. Boron diffusion doping is performed on the side of the first intrinsic silicon layer away from the first tunneling oxide layer to form a boron diffusion doped layer; A first photoresist mask layer is prepared on the side of the boron diffusion doped layer corresponding to the first region that is away from the first surface. The boron diffusion doped layer, the first tunneling oxide layer and the intermediate spacer layer corresponding to the second region are removed by wet etching to expose the first surface corresponding to the second region and remove the first photoresist mask layer corresponding to the first region.

[0046] For details not covered in this embodiment, please refer to the above embodiments. Figure 2 As shown, the preparation method includes: S210, providing an N-type silicon substrate; wherein the N-type silicon substrate includes a first surface and a second surface that are opposite to each other, and the first surface includes a first region and a second region that are arranged alternately in an interdigitated pattern.

[0047] S220. An intermediate spacer layer, a first tunneling oxide layer, and a first intrinsic silicon layer are sequentially formed on the first surface corresponding to the first region and the second region.

[0048] Optionally, the intermediate spacer layer includes an intermediate tunneling oxide layer and an intermediate intrinsic silicon layer stacked sequentially; the intermediate spacer layer, the first tunneling oxide layer and the first intrinsic silicon layer are sequentially formed on the first surface corresponding to the first region and the second region, including: the intermediate tunneling oxide layer, the intermediate intrinsic silicon layer, the first tunneling oxide layer and the first intrinsic silicon layer are sequentially formed on the first surface corresponding to the first region and the second region.

[0049] Specifically, an intermediate tunneling oxide layer, an intermediate intrinsic silicon layer, a first tunneling oxide layer, and a first intrinsic silicon layer can be sequentially deposited on the first surfaces corresponding to the first and second regions using an LPCVD process. For example, the thickness of the intermediate tunneling oxide layer ranges from 0.5 to 1.2 nm. For example, the deposition process temperature for the intermediate tunneling oxide layer can be 600°C, the deposition process time can be 20 min, and the oxygen flow rate can be 20000 sccm. Based on this deposition process, the thickness of the intermediate tunneling oxide layer formed can be 1 nm. For example, the thickness of the intermediate intrinsic silicon layer ranges from 20 to 70 nm. For example, the deposition process temperature for the intermediate intrinsic silicon layer can be 580°C, the deposition process time can be 40 min, and the silane flow rate can be 200 sccm. Based on this deposition process, the thickness of the intermediate intrinsic silicon layer formed can be 30 nm. For example, the thickness of the first tunneling oxide layer ranges from 0.5 to 1.5 nm. For example, the deposition process temperature for the first tunneling oxide layer can be 600°C, the deposition process time for the first tunneling oxide layer can be 5 min, and the oxygen flow rate for the first tunneling oxide layer can be 20000 sccm. Based on this deposition process, the thickness of the first tunneling oxide layer formed can be 0.4 nm. For example, the thickness of the first intrinsic silicon layer ranges from 200 to 380 nm. For example, the deposition process temperature for the first intrinsic silicon layer can be 580°C, the deposition process time for the first intrinsic silicon layer can be 200 min, and the silane flow rate for the first intrinsic silicon layer can be 300 sccm. Based on this deposition process, the thickness of the first intrinsic silicon layer formed can be 310 nm.

[0050] S230. Boron diffusion doping is performed on the side of the first intrinsic silicon layer away from the first tunneling oxide layer to form a boron diffusion doped layer.

[0051] Optionally, a boron diffusion doping process is performed on the side of the first intrinsic silicon layer away from the first tunneling oxide layer to form a boron diffusion doped layer, including: using a tubular diffusion device and employing a boron diffusion process, sequentially performing a high-temperature advance process and a cooling oxidation process on the side of the first intrinsic silicon layer away from the first tunneling oxide layer to form a boron diffusion doped layer.

[0052] Specifically, after forming the first intrinsic silicon layer, it needs to be doped with boron to form a boron diffusion-doped layer, simultaneously forming a first associated layer. The first intrinsic silicon layer is a silicon material layer with intrinsic semiconductor characteristics. An intrinsic semiconductor is a semiconductor material without both donor impurities (n-type dopant) and acceptor impurities (p-type dopant), and its conductivity mainly depends on the generation and recombination of electron-hole pairs within the material itself. Understandably, after the high-temperature propulsion process and cooling oxidation process form the boron diffusion-doped layer, the boron atoms in the doping process usually do not completely react into the first intrinsic silicon layer, but will generate some residual organic matter. To prevent this residual organic matter from affecting the boron diffusion-doped layer, it can be post-oxidized. By introducing a certain flow rate of oxygen into the post-oxidation reaction chamber, the residual organic matter reacts with oxygen to form a first associated layer. Typically, the first associated layer is a borosilicate glass (BSG) layer, which can be subsequently removed by wet etching.

[0053] Using tubular diffusion equipment, such as a tubular low-pressure diffusion furnace, and employing a boron diffusion process, the temperature range corresponding to the high-temperature propulsion treatment is 950-1050℃, the temperature range corresponding to the cooling oxidation treatment is 800-950℃, and the oxygen flow rate corresponding to the oxygen supply atmosphere is 5000-30000 sccm. For example, the deposition temperature for the boron diffusion process can be 880°C, the deposition flow rate can be 200 sccm, and the deposition time can be 10 min. The temperature for the high-temperature propulsion treatment can be 980°C, and the propulsion time can be 20 min. The temperature change for the cooling oxidation treatment can be a gradual decrease from 980°C to 880°C, and the cooling time can be 40 min. The oxygen flow rate for the oxygen supply atmosphere can be 20,000 sccm. The thickness of the borosilicate glass (BSG) layer formed after the boron diffusion doping treatment can be 50 nm, the sheet resistance after the boron diffusion doping treatment can be 140 Ω / sq, and the surface boron doping concentration after the boron diffusion doping treatment can be 5.9E+19 atoms / cm.3 .

[0054] It should also be noted that in this embodiment, the first intrinsic silicon layer is subjected to a high-temperature propulsion process and a cooling oxidation process in sequence to form the corresponding boron diffusion doping layer. The high-temperature propulsion process allows boron impurities to be propagated at a higher temperature, promoting the penetration and activation of boron atoms. After the high-temperature propulsion process, oxygen is introduced during the cooling oxidation process. The introduced oxygen can react with the boron and silicon on the surface to form a dense borosilicate glass (BSG) layer, "fixing" the high concentration of boron on the outermost layer, that is, in the boron diffusion doping layer. At the same time, the oxidation process changes the surface impurity segregation coefficient, inhibiting the reverse precipitation of boron during the cooling process, thereby further increasing the boron impurity doping concentration to 6E+19 atoms / cm. 3 Understandably, the first tunneling oxide layer effectively blocks the excessive diffusion of boron atoms from the boron diffusion-doped layer towards the intermediate intrinsic silicon layer. This allows the boron diffusion-doped layer to achieve a high concentration of boron doping to optimize contact, while the intermediate intrinsic silicon layer maintains a low concentration of boron doping to preserve excellent passivation. This achieves a gradient doping effect between the high-concentration boron doping in the boron diffusion-doped layer and the low-concentration boron doping in the intermediate intrinsic silicon layer, further increasing the overall boron doping concentration in the first region. Carrier transport between the boron diffusion-doped layer and the intermediate intrinsic silicon layer can be achieved through the tunneling effect of the first tunneling oxide layer, ensuring the excellent photoelectric performance of the TBC cell. Furthermore, the intermediate tunneling oxide layer, positioned between the intermediate intrinsic silicon layer and the first surface of the N-type silicon substrate, further blocks the excessive diffusion of boron atoms from the intermediate intrinsic silicon layer towards the N-type silicon substrate, preventing N-type silicon substrate failure.

[0055] S240. A first photoresist mask layer is prepared on the side of the boron diffusion doped layer corresponding to the first region that is away from the first surface. The boron diffusion doped layer, the first tunneling oxide layer and the intermediate spacer layer corresponding to the second region are removed by wet etching to expose the first surface corresponding to the second region and remove the first photoresist mask layer corresponding to the first region.

[0056] Specifically, this step essentially involves sequentially removing the first associated layer, boron diffusion doped layer, first tunneling oxide layer, and intermediate spacer layer corresponding to the second region. If the first associated layer is not actually formed during the process, then only the boron diffusion doped layer, first tunneling oxide layer, and intermediate spacer layer corresponding to the second region need to be removed sequentially until the first surface of the N-type silicon substrate corresponding to the second region is exposed. For example, a wet etching method following photoresist printing can be used to prepare a first photoresist mask layer on the side of the boron diffusion doped layer corresponding to the first region away from the first surface. This first photoresist mask layer can cover the first region and expose the second region, facilitating precise photoresist removal and etching in the second region during subsequent wet etching, forming the etched second region and the unetched first region. For example, the first photoresist mask layer can be a single-layer photoresist or a multi-layer photoresist, which can effectively avoid damage to the N-type silicon substrate during subsequent wet etching. Furthermore, the first photoresist mask layer also helps to distinguish the first region and the second region, forming the etched second region and the unetched first region. That is, when the first surface of the N-type silicon substrate is patterned, the intermediate spacer layer, the first tunneling oxide layer, and the boron diffusion doped layer corresponding to the first region are retained, while the intermediate spacer layer, the first tunneling oxide layer, and the boron diffusion doped layer corresponding to the second region are removed until the surface of the N-type silicon substrate corresponding to the second region is exposed, thus making the positional difference between the first region and the second region more obvious.

[0057] For example, the wet etching method after printing photoresist can be used, which involves printing photoresist by screen printing, curing, acid washing, removing the photoresist, and etching to form a patterned structure. For example, the printing pressure of screen printing can be 50N, the screen printing distance can be 2.5mm, the squeegee height can be 2mm, the power of curing can be 60W, the pickling time can be 70s, the solution concentration of pickling can be HF:pure water = 1:50, the time of desmearing can be 100s, the solution concentration of desmearing can be KOH:pure water = 1:20, the acid bath solution concentration of etching can be HF:pure water = 1:12.5, the corresponding processing time of the acid bath of etching can be 60s, the solution concentration of the alkaline bath of etching can be KOH:pure water = 1:10, the corresponding processing time of the alkaline bath of etching can be 200s, the weight reduction of etching in the entire process can be 0.3g, the thickness of the remaining borosilicate glass layer (BSG) can be 10nm, and then the borosilicate glass layer (BSG) can be completely removed by acidic or alkaline solutions.

[0058] S250. A second tunneling oxide layer and a phosphorus diffusion doped layer are sequentially prepared on the first surface corresponding to the second region.

[0059] S260. A first passivation film layer is prepared on the side of the boron diffusion doped layer and the phosphorus diffusion doped layer away from the first surface, and screen printing and sintering are performed on the first passivation film layer to form an electrode structure, thereby obtaining a TBC battery.

[0060] Figure 3 This is a schematic flowchart of another TBC battery fabrication method provided by an embodiment of the present invention, which is an optimization based on the above embodiment. Optionally, a second tunneling oxide layer and a phosphorus diffusion doped layer are sequentially fabricated on the first surface corresponding to the second region, including: A second tunneling oxide layer and a second intrinsic silicon layer are prepared on the first surface corresponding to the exposed second region and on the side of the boron diffusion doped layer away from the first surface; Phosphorus diffusion doping is performed on the side of the second intrinsic silicon layer away from the second tunneling oxide layer to form a phosphorus diffusion doped layer; A second photoresist mask layer is prepared on the side of the phosphorus diffusion doped layer corresponding to the second region that is away from the first surface. The phosphorus diffusion doped layer and the second tunneling oxide layer corresponding to the first region are removed by wet etching to expose the boron diffusion doped layer corresponding to the first region and remove the second photoresist mask layer corresponding to the second region.

[0061] For details not covered in this embodiment, please refer to the above embodiments. Figure 3 As shown, the preparation method includes: S310, providing an N-type silicon substrate; wherein the N-type silicon substrate includes a first surface and a second surface that are opposite to each other, and the first surface includes a first region and a second region that are arranged alternately in an interdigitated pattern.

[0062] S320. An intermediate spacer layer, a first tunneling oxide layer, and a boron diffusion doped layer are sequentially prepared on the first surface corresponding to the first region and the second region. The boron diffusion doped layer, the first tunneling oxide layer, and the intermediate spacer layer corresponding to the second region are removed by wet etching.

[0063] S330. A second tunneling oxide layer and a second intrinsic silicon layer are prepared on the first surface corresponding to the exposed second region and on the side of the boron diffusion doped layer away from the first surface.

[0064] Specifically, an LPCVD process can be used to sequentially deposit a second tunneling oxide layer and a second intrinsic silicon layer on the first surface corresponding to the exposed second region and on the side of the boron diffusion-doped layer away from the first surface. For example, the thickness of the second tunneling oxide layer ranges from 0.5 to 1.2 nm. For example, the deposition process temperature for the second tunneling oxide layer can be 600°C, the deposition time can be 20 min, and the oxygen flow rate can be 30,000 sccm. Based on this deposition process, the thickness of the formed second tunneling oxide layer can be 1.5 nm. For example, the thickness of the second intrinsic silicon layer ranges from 150 to 300 nm. For example, the deposition process temperature for the second intrinsic silicon layer can be 580°C, the deposition time can be 130 min, and the silane flow rate can be 20,000 sccm. Based on this deposition process, the thickness of the formed second intrinsic silicon layer can be 240 nm.

[0065] S340. Phosphorus diffusion doping is performed on the side of the second intrinsic silicon layer away from the second tunneling oxide layer to form a phosphorus diffusion doped layer.

[0066] Specifically, after forming the second intrinsic silicon layer, it needs to be doped with phosphorus to form a phosphorus diffusion-doped layer, simultaneously forming a second associated layer. The second intrinsic silicon layer is a silicon material layer with intrinsic semiconductor characteristics. An intrinsic semiconductor is a semiconductor material without both donor impurities (n-type dopant) and acceptor impurities (p-type dopant), and its conductivity mainly depends on the generation and recombination of electron-hole pairs within the material itself. Understandably, after high-temperature doping to form the phosphorus diffusion-doped layer, phosphorus atoms during the doping process usually do not completely react and enter the second intrinsic silicon layer, generating some residual organic matter. To prevent this residual organic matter from affecting the phosphorus diffusion-doped layer, it can be post-oxidized. By introducing a certain flow rate of oxygen into the post-oxidation reaction chamber, the residual organic matter reacts with oxygen to form a second associated layer. Typically, this second associated layer is a phosphosilicate glass (PSG) layer, which can be subsequently removed by wet etching.

[0067] Using tubular diffusion equipment, such as a tubular low-pressure diffusion furnace, and employing a phosphorus diffusion process, the temperature range corresponding to the high-temperature propulsion treatment is 900-1050℃, the temperature range corresponding to the cooling oxidation treatment is 800-900℃, the oxygen flow rate corresponding to the oxygen supply atmosphere is 5000-30000 sccm, the thickness of the phosphorus silicon glass (PSG) layer formed after phosphorus diffusion doping treatment can be controlled within the range of 25-100 nm, and the sheet resistance range after phosphorus diffusion doping treatment can be controlled within the range of 7-55 Ω / sq. For example, the deposition temperature for the phosphorus diffusion process can be 800°C, the deposition flow rate can be 1000 sccm, and the deposition time can be 30 min. The temperature for the high-temperature propulsion treatment can be 900°C, and the propulsion time can be 20 min. The temperature change for the cooling oxidation treatment can be a gradual decrease from 900°C to 880°C, and the cooling time can be 60 min. The oxygen flow rate for the oxygen supply atmosphere can be 15000 sccm. The thickness of the phosphorus silicate glass (PSG) layer formed after phosphorus diffusion doping treatment can be 60 nm, the sheet resistance after phosphorus diffusion doping treatment can be 16 Ω / sq, and the surface phosphorus doping concentration after phosphorus diffusion doping treatment can be 4.5E+20 atoms / cm. 3 .

[0068] S350. A second photoresist mask layer is prepared on the side of the phosphorus diffusion doped layer corresponding to the second region away from the first surface, and the phosphorus diffusion doped layer and the second tunneling oxide layer corresponding to the first region are removed by wet etching to expose the boron diffusion doped layer corresponding to the first region, and the second photoresist mask layer corresponding to the second region is removed.

[0069] Specifically, this step essentially involves sequentially removing the second associated layer, the phosphorus diffusion doped layer, and the second tunneling oxide layer corresponding to the first region. If no second associated layer is actually formed during the process, only the phosphorus diffusion doped layer and the second tunneling oxide layer corresponding to the first region need to be removed sequentially until the boron diffusion doped layer corresponding to the first region is exposed. For example, a wet etching method following photoresist printing can be used to prepare a second photoresist mask layer on the side of the phosphorus diffusion doped layer corresponding to the second region away from the first surface. This second photoresist mask layer can cover the second region and expose the first region, facilitating precise photoresist removal and etching in the first region during subsequent wet etching, forming the etched first region and the unetched second region. For example, the second photoresist mask layer can be a single-layer photoresist or a multi-layer photoresist, effectively avoiding damage to the N-type silicon substrate during subsequent wet etching. Furthermore, the second photoresist mask layer also helps to distinguish the first and second regions, forming the etched first region and the unetched second region. That is, the first surface of the N-type silicon substrate is then patterned, the second tunneling oxide layer and the phosphorus diffusion doping layer corresponding to the second region are retained, while the second tunneling oxide layer and the phosphorus diffusion doping layer corresponding to the first region are removed until the boron diffusion doping layer corresponding to the first region is exposed, so that the positional difference between the first region and the second region becomes more obvious.

[0070] For example, using a wet etching method after printing photoresist, the photoresist can be printed by screen printing, cured, acid-washed, stripped, and etched to form a patterned structure. For example, the screen printing pressure can be 50N, the screen printing distance can be 2.5mm, the squeegee height can be 2mm, the curing power can be 60W, the acid washing time can be 70s, the acid washing solution concentration can be HF:pure water = 1:50, the stripping time can be 100s, the stripping solution concentration can be KOH:pure water = 1:20, the etching acid bath solution concentration can be HF:pure water = 1:25, the etching acid bath treatment time can be 200s, the etching alkaline bath solution concentration can be KOH:pure water = 1:10, the etching alkaline bath treatment time can be 200s, and the weight reduction during the entire etching process can be 0.1g. Furthermore, exemplarily, a trough texturing process can be used to effectively remove impurities from one side of the first surface of the N-type silicon substrate and effectively form a textured surface in the gap region between the first and second regions, reducing the surface reflectivity of the subsequently fabricated TBC battery. Exemplarily, the trough texturing process can employ a mixed solution of concentrated potassium hydroxide (KOH) solution and texturing additives. Exemplarily, the solution concentration for texturing can be KOH:pure water = 1:8, the texturing time can be 230 s, and the overall reflectivity of one side of the first surface of the N-type silicon substrate after texturing can be 9%. Thus, the gap region between the second surface of the subsequently fabricated TBC battery and the first and second regions on the first surface has a textured structure, while the first and second regions on the first surface have a polished structure.

[0071] S360. A first passivation film layer is prepared on the side of the boron diffusion doped layer and the phosphorus diffusion doped layer away from the first surface, and screen printing and sintering are performed on the first passivation film layer to form an electrode structure, thereby obtaining a TBC battery.

[0072] Based on the same inventive concept, embodiments of the present invention also provide a TBC battery. This TBC battery is prepared using the preparation method of a TBC battery as provided in any of the embodiments of the present invention. Therefore, this TBC battery possesses the functional modules and beneficial effects corresponding to the preparation method of a TBC battery.

[0073] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0074] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for preparing a TBC battery, characterized in that, include: An N-type silicon substrate is provided; wherein the N-type silicon substrate includes a first surface and a second surface that are opposite to each other, and the first surface includes a first region and a second region that are arranged alternately in an interdigitated pattern; An intermediate spacer layer, a first tunneling oxide layer, and a boron diffusion doped layer are sequentially prepared on the first surface corresponding to the first region and the second region. The boron diffusion doped layer, the first tunneling oxide layer, and the intermediate spacer layer corresponding to the second region are removed by wet etching. A second tunneling oxide layer and a phosphorus diffusion doped layer are sequentially prepared on the first surface corresponding to the second region. A first passivation film is prepared on the side of the boron diffusion doped layer and the phosphorus diffusion doped layer away from the first surface, and screen printing and sintering are performed on the first passivation film to form an electrode structure, thereby obtaining the TBC battery.

2. The preparation method according to claim 1, characterized in that, An intermediate spacer layer, a first tunneling oxide layer, and a boron diffusion-doped layer are sequentially formed on the first surface corresponding to the first region and the second region. The boron diffusion-doped layer, the first tunneling oxide layer, and the intermediate spacer layer corresponding to the second region are then removed using a wet etching process. The intermediate spacer layer, the first tunneling oxide layer, and the first intrinsic silicon layer are sequentially prepared on the first surface corresponding to the first region and the second region. The side of the first intrinsic silicon layer away from the first tunneling oxide layer is subjected to boron diffusion doping to form the boron diffusion doped layer; A first photoresist mask layer is prepared on the side of the boron diffusion doped layer corresponding to the first region away from the first surface, and the boron diffusion doped layer, the first tunneling oxide layer and the intermediate spacer layer corresponding to the second region are removed by wet etching to expose the first surface corresponding to the second region and remove the first photoresist mask layer corresponding to the first region.

3. The preparation method according to claim 2, characterized in that, The intermediate spacer layer includes an intermediate tunneling oxide layer and an intermediate intrinsic silicon layer stacked sequentially. The intermediate spacer layer, the first tunneling oxide layer, and the first intrinsic silicon layer are sequentially fabricated on the first surface corresponding to the first region and the second region, including: The intermediate tunneling oxide layer, the intermediate intrinsic silicon layer, the first tunneling oxide layer, and the first intrinsic silicon layer are sequentially formed on the first surface corresponding to the first region and the second region.

4. The preparation method according to claim 3, characterized in that, The thickness of the intermediate tunneling oxide layer ranges from 0.5 to 1.2 nm, the thickness of the intermediate intrinsic silicon layer ranges from 20 to 70 nm, the thickness of the first tunneling oxide layer ranges from 0.5 to 1.5 nm, and the thickness of the first intrinsic silicon layer ranges from 200 to 380 nm.

5. The preparation method according to claim 2, characterized in that, Performing boron diffusion doping on the side of the first intrinsic silicon layer away from the first tunneling oxide layer to form the boron diffusion-doped layer includes: Using a tubular diffusion apparatus and a boron diffusion process, the side of the first intrinsic silicon layer away from the first tunneling oxide layer is subjected to a high-temperature propulsion process and a cooling oxidation process in sequence to form the boron diffusion doped layer.

6. The preparation method according to claim 5, characterized in that, The temperature range corresponding to the high-temperature propulsion treatment is 950-1050℃, and the temperature range corresponding to the cooling oxidation treatment is 800-950℃.

7. The preparation method according to claim 1, characterized in that, A second tunneling oxide layer and a phosphorus diffusion doped layer are sequentially prepared on the first surface corresponding to the second region, including: The second tunneling oxide layer and the second intrinsic silicon layer are prepared on the first surface corresponding to the exposed second region and on the side of the boron diffusion doped layer away from the first surface; The side of the second intrinsic silicon layer away from the second tunneling oxide layer is subjected to phosphorus diffusion doping to form the phosphorus diffusion doped layer; A second photoresist mask layer is prepared on the side of the phosphorus diffusion doped layer corresponding to the second region away from the first surface, and the phosphorus diffusion doped layer and the second tunneling oxide layer corresponding to the first region are removed by wet etching to expose the boron diffusion doped layer corresponding to the first region, and the second photoresist mask layer corresponding to the second region is removed.

8. The preparation method according to claim 1, characterized in that, After sequentially preparing a second tunneling oxide layer and a phosphorus diffusion doped layer on the first surface corresponding to the second region, the method further includes: A second passivation film is prepared on the second surface.

9. The preparation method according to claim 8, characterized in that, The first passivation film layer includes a first anti-ultraviolet attenuation film layer and a first anti-reflection film layer stacked sequentially, and the second passivation film layer includes a second anti-ultraviolet attenuation film layer and a second anti-reflection film layer stacked sequentially.

10. A TBC battery, characterized in that, The TBC battery was prepared using the method described in any one of claims 1-9.

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